CMOS/Overview

– Review
• MOSFETs I/V operation and characteristics
summary
• 2nd order effects
• Scaling theory
• Short-channel effects
– CMOS processing technology
– Latch-Up

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CMOS/Objectives
– A basic understanding of MOSFETs
• Why?
– MOSFET is the predominant VLSI device
– A basic understanding of CMOS processing
technology
• Why?
– Basic knowledge about CMOS processing technology is essential.
Understand effects like latch-up and on-chip transmission lines
– Many limitations imposed on performance of ICs are directly
related to CMOS fabrication issues

29/09/2005 EE6471 (KR) 66

CMOS/Mosfets/Mosfet as a Switch
– “MOSFET”
Metal Oxide Silicon Field Effect Transistor Gate
– Symbol
• Shown is a symbol for an n-type mosfet
Source Drain
– Operation as a switch
• Voltage at gate VG is “high”:
Source and drain connected
• Voltage at gate VG is “low”:
Source and drain isolated

– Questions:
• Threshold voltage? Resistance between S
and D for On/Off? Speed?

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CMOS/Mosfets/Basic Structure
– Basic MOSFET Structure
• Shown is a simplified structure of an n-type MOSFET (NMOS, NFET)
• Fabricated on p-type substrate (“bulk”, “body”)
• Device consists of
– two heavily-doped n-regions forming Source (S) and Drain (D)
– a heavily-doped piece of polysilicon (“poly”, amorphous Si)
– a thin layer of silicon oxide (SiO2) insulating the gate from the substrate.
Poly
Gate oxide thickness tox.
• Useful action of the device occurs G Oxide
B S D
in the substrate region under
the gate oxide W
• Symmetrie (S and D) p+ n+ n+
• Mosfet idea was patented Leff
1930 (Lilienfeld)
well before BJT (Shockley, 1947, see above) p-substrate
Ldrawn

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 CMOS/Mosfets/Mosfet IV Characteristics
• Threshold voltage:
– Gate voltage Vg increases from zero. Gate and substrate form a capacitor. Holes in substrate
are repelled from the gate area leaving negative ions behind. A negative space-charge region
is created. The negative charge in the induced depletion region corresponds to the negative
charge on the bottom plate of the gate-oxide capacitor. No current flows from D to S
because no free charge carriers are available.
– As Vg increases so does the width of the depletion region and the potential at the oxide-
silicon interface. The structure resembles two capacitors in series: the gate-oxide capacitor,
and the depletion region capacitor.
– When the interface potential reaches
a sufficiently positive value, Vg
electrons flow from the S to the Vd (0.1V)
interface and on to the D. A “channel”
of charge carriers is formed between S
and D, the transistor is “on”. The + + +
interface is “inverted”. Vg has reached p n n
the threshold voltage Vth.
– If Vg rises further the channel charge
density increases further p-substrate
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 CMOS/Mosfets/Mosfet IV Characteristics
• Threshold voltage:
– In practice the turn-on phenomenon is a gradual function of Vg making it difficult to define
the threshold voltage Vth unambiguously
– Threshold voltage Vth in semiconductor physics:
The interface is “as much n-type as the substrate is p-type”
– “Native” threshold values may not be suitable
Threshold-adjust implant into the channel area during device fabrication. Essentially alters Nsub near
the oxide interface.

Qdep
Vth0 = φ MS + 2φ F +
Cox
kT  Nsub  φF: Bulk potential
φF = ln  φMS: Contact potential between poly and bulk
q  ni 
Nsub: Substrate carrier concentration
ni: Carrier concentration in undoped Si
Qdep = 4q ⋅ ε Si ⋅ Nsub ⋅ φ F
Qdep: Charge in depletion region
Cox: Gate-oxide capacitance per unit area
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 CMOS/Mosfets/Mosfet IV Characteristics
• What happens if Vd is increased?
– As the drain voltage increases, the voltage drop across the oxide near the drain terminal
decreases. The induced inversion charge density near the drain decreases. As Vd increases to
the point where the potential difference across the oxide at the drain terminal is equal to Vth
the induced inversion charge density at the drain terminal is zero. For this condition the
incremental channel conductance at the drain is zero, which means that the slope of Id vs Vd
is zero (in theory…)
3
2.722

Vdssat = Vgs − Vth 2.5

Id( Vds , 4 ⋅V) 2

• If Vds<Vdssat m ⋅A

Id( Vds , 3 ⋅V)

– Triode region, linear region m ⋅A
1.5

Id( Vds , 2 ⋅V)

• If Vds>Vdssat m ⋅A 1

– Saturation region
0.5

0
0 1 2 3 4 5 6
0 Vds 6

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 CMOS/Mosfets/Mosfet IV Characteristics
• Mosfet I/V Characteristics in the triode region (linear region)

 2
(Vgs − Vth )Vds − 2 Vds 
W 1
Id = µn ⋅ Cox ⋅
L  

• Deep triode region Vds<<Vgs-Vth

W
Id = µn ⋅ Cox ⋅ (Vgs − Vth)Vds
L
1 In the deep triode region mosfet can operate as a
Ron = resistor whose value is controlled by the overdrive
µn ⋅ Cox ⋅ (Vgs − Vth )
W
L voltage
µn: Mobility of electrons
L: Effective channel length
W: Channel width

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 CMOS/Mosfets/Mosfet IV Characteristics
• Mosfet I/V Characteristics in the saturation region
Vgs

Id = µn ⋅ Cox ⋅ (Vgs − Vth )

1 W 2
Vds

2 L'
p+ n+ n+
L’: Channel length to pinch-off point

p-substrate L'
• Transconductance gm
A Mosfet in saturation produces a current in
response to its gate-source voltage
gm = µn ⋅ Cox ⋅
W
(Vgs − Vth)
L
δId
gm = gm = 2 µn ⋅ Cox ⋅
W
Id
δVgs Vds =const L
2 Id
gm =
Vgs − Vth
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 CMOS/Mosfets/Mosfet IV Characteristics
• P-channel devices

µp = 25..50% of µn
• Mobility of holes is less than mobility of electrons. PMOS devices suffer from lower
“current drive”. Use NMOS wherever possible.
• NMOS and PMOS devices must be fabricated on the same wafer, i.e. the same
substrate. One device must be placed in a “local substrate” or “well”. Typically the
PMOS device is fabricated in an n-well. The n-well must be connected to a potential
such that the S/D junction diodes of the PMOS transistor remain reverse-biased under
all conditions. In most circuits the n-well is tied to the most positive supply voltage
using a well-tie.
p+ n+ n+ p+ p+ n+
n-well
p-substrate

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CMOS/Mosfets/2nd order effects
– Body effect:
So far it was assumed that the substrate and the source were tied together (to
ground). If the substrate voltage drops below the source voltage the threshold
voltage Vth increases.

Vth = Vth0 + γ ( 2φ F + Vsb − 2φ F )

Qdep
Vth0 = φ MS + 2φ F +
Vg
Vb<0 Vd
Cox
p+ n+ n+
γ: body-effect parameter

p-substrate

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CMOS/Mosfets/2nd order effects Vgs
Vds

– Channel-Length Modulation p+ n+ n+
The length of the inverted channel gradually
decreases as the potential difference between
p-substrate L'
gate and drain increases.

Id = µn ⋅ Cox ⋅ (Vgs − Vth )

1 W 2

2 L'
∆L
1+
1 L ∆L
L ' = L − ∆L ≈ = λ ⋅Vds
L' L L

Id ≈ µn ⋅ Cox ⋅ (Vgs − Vth ) (1 + λVds )

1 W 2

2 L λ: channel-length modulation coefficient

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CMOS/Mosfets/2nd order effects
– Sub-threshold Conduction
So far it was assumed that mosfets turn off abruptly as Vgs drops below Vth. In
reality a weak inversion layer still exists even for Vgs<Vth, and some current flows
from D to S.

Vgs
Id ≈ Id 0 ⋅ exp Valid for Vds>200mV
ζ ⋅Vt
ζ: nonideality factor

With typical values for ζ, at room temperature Vgs must decrease by about 80mV for Id
to decrease by one decade. Sub-threshold conduction is a serious challenge for further
lowering operating voltages of ICs.
Assume: Vcc=1V. Vth=0.32V. When Vgs is reduced from 0.32V to 0V the drain current decreases
only my a factor of 104

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 CMOS/Short-Channel Effects
• Comments
– Equations covered so far provide acceptable accuracies for devices
with L>4um
– Status Quo (2002): L=0.13um and falling…
– Understanding of short-channel effects and improved models
required so as to attain enough accuracy in simulations

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 CMOS/Short-Channel Effects
• (Incomplete) List of short-channel effects:
– Threshold voltage variation with channel length
Depletion regions associated with S/D junctions protrude into the channel yielding a
lower Vth.
– Drain-induced barrier lowering (DIBL)
Drain voltage affects Vth
– Mobility degradation with vertical field
Large Vgs leads to more carrier scattering and reduced mobility
– Velocity saturation
Mobility of carriers begins to drop as electric fields increase above 1V/um
– Hot carrier effects
High lateral electric fields cause “hot” carriers which may hit Si atoms near drain at high
speeds creating impact ionisation (causing substrate and gate currents).

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CMOS/Short-Channel Effects/Scaling Theory
– Scaling Theory, discussed by Dennard et al, 1974
Dennard et al recognised the tremendous potential of scaling MOS transistors
– Gordon Moore, 1975. Predictions:
• Mosfet device dimensions scale down by a factor of 2 every 3
years
• #transistors/chip double every 1-2 years.
– Dennard: Constant-field scaling
• Reduce all lateral and vertical dimensions by α (α>1)
• Reduce threshold voltage and supply voltage by α
• Increase all doping levels by α

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CMOS/Short-Channel Effects/Scaling Theory
– Results of constant-field scaling
• all electrical fields in the transistor remain constant
• current capability of transistors drop by a factor of α
• all capacitances (channel capacitances, S/D junction capacitances) decrease
by a factor of α
• delay times decrease by a factor of α
• dynamic power dissipation drops by decrease by a factor of α3 (!)
• transconductance remains constant
– However:
• Reduction of supply voltage reduces dynamic range (of analog circuitry)
Lower end of dynamic range is limited by thermal noise
• To restore dynamic range the transconductance must be increased by α2.
• Sub-threshold conduction problems
• Problems caused by short-channel effects

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CMOS/Short-Channel Effects/Scaling Theory
– Because of these problems: Constant-voltage scaling
• leads to increased electric field strengths
– In practice:
Mixture of constant-field and constant-voltage trends

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CMOS/Processing technology
– Why MOS/CMOS?
Dimensions of MOS devices can be scaled down more easily than other transistor types
– Starting mid 1960’s: Shift from NMOS to CMOS
Main reason: “Zero” static power dissipation
– CMOS technology was attractive because of the relative small
number of masks (about 7)
– Modern CMOS processes:
• about 200 process steps
• about 25 masks
Number of masks heavily impacts unit price of the chip. Each mask costs n*$1k (total mask
cost typ. $200k). Lithography is slow.
• up to 6 (and sometimes more) metal layers
• Poly layers: 1 or 2 (standard) or more (non-standard, e.g. E2prom)
• Today’s standard: n-well CMOS process with self-aligned polysilicon gates

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CMOS/Processing technology

Source: TSMC

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CMOS/Process steps
– Process step: Wafer fabrication
• Czochralksi method:
– Seed of crystalline Si is immersed in molten amorphous Si (1425°C).
Molten Si contains desired level of p-type doping.
– Seed is gradually pulled out while rotating (30-180mm/h)
– Result: Large single-crystal cylindrical ingot
• Ingot is sliced into thin wafers
– Wafer sheet resistance: 50-200Ω
– Initial wafer thickness: 500-1000µm
– Wafer diameter: 75-300mm (12 inch)
• Wafers are polished and etched to remove surface damages

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CMOS/Process steps
– Process step: Grow thin layer of SiO2 on p-type wafer
• Place wafer in an oxidizing atmosphere at around 1000°C
• Unique property of Si: a very uniform oxide layer can be produced on the
surface with little strain in the lattice
• Oxide layers can be very thin (e.g. 50Å=5nm), only a couple of atomic layers
• Oxide can be used as gate dielectric (TOX). Oxide can also grown thick (field
oxide FOX) as a foundation for interconnect lines
• Oxide also serves as a protective coating during many process steps
(like in this process step)
SiO2

p-substrate

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CMOS/Process steps
– Process step: Lithography sequence for n-well
• Photolithography: Transfer circuit layout information to the wafer
Layout consists of polygons. Layout is first “written” to a transparant glass “mask” by a precisely
controlled electron beam.
• Negative Photoresist (PR) deposition
PR: A material whose etching properties change upon exposure to light. Negative PR “hardens”
in regions exposed to UV light. Positive PR “hardens” in regions not exposed to UV light.
• Exposure to ultraviolet (UV) light using the n-well mask
• Selective etching. Etchant dissolves “soft” PR
Photoresist

p-substrate

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CMOS/Process steps
– Process step: Create n-wells through ion implantation
• n-wells required for p-channel devices
n-channel devices will be fabricated directly in the native p-substrate
• Ion implantation: Selectively introduce dopants into the wafer
Doping atoms are accelerated as a high-energy focused beam, hitting the surface and penetrating
the exposed areas. Doping level determined by intensity and duration of implantation.
Retrograde profile: Peak of the doping concentration occurs well below the surface

Ion implantation n-type

p-substrate

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CMOS/Process steps
– Process step: Remove PR and oxide layer
• n-well completed
• Note: Ion implantation damages the Si lattice
Si lattice can be repaired through an annealing process. Annealing: Wafer is heated to 1000°C for
15-30min allowing the lattice bonds to form again. Annealing causes dopant diffusion in all
directions (e.g. side diffusion of S/D regions). Therefore, wafer is annealed only once after all
implantations have been completed

n-well
p-substrate

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 Poly
Interconnect
Gate M1 Gate M2
CMOS/Process steps n+ n+ n+ n+

– Process step: Channel-stop implant (1) Parasitic Inversion Layer

• Channel-stop implant required to prevent parasitic mosfets

Prevents conduction between unrelated transistor sources and drains (and wells). Two n+ regions
and the FOX from a transistor. FOX is thick, therefore transistor has a large Vth. Nonetheless, a
sufficiently positive potential on the interconnect line will turn on the transistor slightly (causing
a leakage path). Channel-stop implant raises Vth of parasitic transistor to a very large value.
• Create a stack of silicon oxide, silicon nitride, and positive PR

PR (positive)
Si3N4
SiO2

n-well
p-substrate

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CMOS/Process steps
– Process step: Channel-stop implant (2)
• Lithography sequence for channel-stop implant (based on positive PR)
• “Active” mask is used
Active or diffusion areas include the source/drain regions and the p+ and n+ openings for the
substrate and well ties

n-well
p-substrate

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CMOS/Process steps
– Process step: Channel-stop implant (3)
• Perform channel-stop ion implantation

Channel-stop implant

n-well
p-substrate

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CMOS/Process steps
– Process step: Channel-stop implant (4)
• Remove PR
• Thick oxide layer is grown in the exposed silicon areas producing the field
oxide (FOX)
FOX grows in areas where the silicon nitride layer is absent

Channel-stop implant FOX

n-well
p-substrate

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CMOS/Process steps
– Process step: Channel-stop implant (5)
• Remove protective silicon nitride layer
• Remove protective thin oxide layer
• Result: Active areas are exposed

n-well
p-substrate

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CMOS/Process steps
– Process step: Growth of gate oxide
• Growth of gate oxide serving as gate dielectric (TOX)
The growth of the gate oxide is a very critical step in the process. It’s thickness tox determines a
multitude of parameters of mosfets (current handling, transconductance, reliability). In order to
achieve good matching of transistors extremely uniform thickness across the wafer is required.
The oxide is therefore grown in a slow low-pressure CVD (chemical vapor deposition) process.
Also, the cleanness of the silicon surface underneath the oxide affects the electrical behaviour of
the mosfet.

TOX

n-well
p-substrate

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CMOS/Process steps
– Process step: Threshold-adjust implant
• Threshold-adjust implant after photolithographic process
The “native” threshold voltage of transistors is typically far from the desired value (VTHN≈0V
and VTHP ≈ -1V). A thin layer of dopants near the surface is implanted to adjust the native
threshold voltage. Thresholds of both NMOS and PMOS transistors will become more positive.

Threshold-adjust implant

n-well
p-substrate

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CMOS/Process steps
– Process step: Create polysilicon (poly) layer
• Deposit a layer of polysilicon on top of the gate oxide
Polysilicon is noncrystalline (or “amorphous”) silicon because this layer grows on top of silicon
dioxide, i.e. cannot form a crystal. Since polysilicon only serves as a conductor its amorphous
nature is unimportant.
• Carry out “poly mask” lithography

Poly

n-well
p-substrate

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CMOS/Process steps
– Process step: n-type implant (1)
• Deposit negative photoresist
• Photolithography using “N source/drain mask”
After the photolithography all areas to receive an n+ implant are exposed. These areas consist of
source and drain junctions of NMOS transistors, and the n-well ties.

Neg. PR

n-well
p-substrate

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CMOS/Process steps
– Process step: n-type implant (2)
• Ion implantation
Ion implantation forms the S/D regions of NMOS transistors and n-well ties. Note that the
implant also dopes the polysilicon layer of the NMOS transistors, reducing its sheet resistance.

N-type implant

n-well
p-substrate

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CMOS/Process steps
– Process step: n-type implant (3)
• Remove PR
• Self-aligned structure
The sequence of creating the gates first prior to n-type implantation yields a self-aligned
structure. The S/D regions are implanted at precisely the edges of the gate area. A small
misalignment in lithography has no major effect (it simply makes one junction slightly narrower
than the other).

n+ n+ n+
n-well
p-substrate

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CMOS/Process steps
– Process step: p-type implant (1)
• Photolithography sequence using “P source/drain mask”
After the photolithography all areas to receive an p+ implant are exposed. These areas consist of
source and drain junctions of PMOS transistors, and the substrate ties.
• Ion implantation
The implant also dopes the polysilicon layer of the PMOS transistors, reducing its sheet
resistance
P-type implant

n+ n+ n+
n-well
p-substrate

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CMOS/Process steps
– Process step: p-type implant (2)
• Remove PR
• Basic transistor fabrication complete
• Remaining processing steps: “Back-end processing”

p+ n+ n+ p+ p+ n+
n-well
p-substrate

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CMOS/Process steps
– Process step: Silicidation (1)
• Creation of oxide spacer
Purpose of Silicidation: Reduction of sheet resistance of doped polysilicon and S/D regions by
about an order of magnitude. During silicidation active areas (S/D regions, substrate and well
ties) are covered with a thin layer of highly conductive material (titanium silicide or tungsten).
The silicidation process begins with creating an oxide spacer at the edges of the polysilicon gate
such that the deposition of the silicide will not short the gate to the S/D regions.

Oxide spacer

p+ n+ n+ p+ p+ n+
n-well
p-substrate

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CMOS/Process steps
– Process step: Silicidation (2)
• Silicidation
Deposition of conductive material through CVD process

p+ n+ n+ p+ p+ n+
n-well
p-substrate

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CMOS/Process steps
– Process step: Contact windows
• Cover wafer with a thick layer of oxide
Thickness: 300-500nm
• Lithography using the “contact mask”
• Plasma etching
For increased reliability contacts to the gate polysilicon are not placed on top of the gate area

p+ n+ n+ p+ p+ n+
n-well
p-substrate

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CMOS/Process steps
– Process step: Metal interconnect 1 (1)
• Deposit layer of metal over the entire wafer
Common metals: Aluminium or copper

p+ n+ n+ p+ p+ n+
n-well
p-substrate

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CMOS/Process steps
– Process step: Metal interconnect 1 (2)
• Photolithography sequence using “Metal 1 mask”
• Metal selectively etched

p+ n+ n+ p+ p+ n+
n-well
p-substrate

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CMOS/Process steps
– Process step: Via windows
• Cover wafer with a layer of SiN3
• Lithography using the “via mask”
• Plasma etching

p+ n+ n+ p+ p+ n+
n-well
p-substrate

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CMOS/Process steps
– Process step: Metal interconnect 2 (1)
• Deposit layer of metal over the entire wafer

p+ n+ n+ p+ p+ n+
n-well
p-substrate

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CMOS/Process steps
– Process step: Metal interconnect 2 (2)
• Photolithography sequence using “Metal 2 mask”
• Metal selectively etched
– Metal interconnect layers:
• Two masks required for each additional metal layer: “via n mask” and “metal n mask”
• Reliability: Dimensions of contacts/vias cannot be changed by layout designer (to avoid “contact
spiking”). If a large contact area is required, many small contacts/vias are used in parallel.

p+ n+ n+ p+ p+ n+
n-well
p-substrate

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CMOS/Process steps
– Process step: Passivation
• Passivation
Wafer is covered with a layer of “glass” or “passivation”, protecting the surface against damages
caused by subsequent mechanical handling and dicing.

Passivation

p+ n+ n+ p+ p+ n+
n-well
p-substrate

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CMOS/Process steps
– Process step: Contact windows for bond pads
• Photolithography sequency
– Final processing steps:
• Testing, dicing, packaging, bonding, testing.
Bond pad

p+ n+ n+ p+ p+ n+
n-well
p-substrate

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CMOS/Sheet Resistance h L
W
ρ ⋅L L ρ⋅L
R= = = Rs Sheet Resistances
A h ⋅W W
Material Rs in Ω
ρ
Rs = Metal (top layer) 0.05

h Metal (lower layers) 0.1

To obtain the resistance of a Polysilicon (silicided) 6

conductor on a layer, multiply Diffusion (n+, p+, silicided) 10

the sheet resistance Rs by the
Polysilicon (doped) 30
ratio L/W of the conductor.
Note: Rs is a process parameter. Diffusion (n+, p+) 100
Ratio L/W is a design parameter.
n-well 5k

Nichrome several k
Mixed signal IC resistor material. Stable and laser-trimmable
ρ: Material resistivity in Ω m Polysilicon (undoped) several Meg
Rs: Sheet resistance in Ω

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CMOS/Process Example

Example process:
0.8um CMOS + HV module.
Data source: Process Parameter
Spec

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CMOS/Latch-Up
– Latch-Up: Destructive mechanisms in CMOS circuits
• Latch-Up is a parasitic circuit effect
• Result of the effect is a short-circuit between Vcc and GND lines, usually resulting in
chip destruction (or at least system failure with the requirement of power down)
• Mechanism did not exist in early MOS technologies (NMOS, PMOS)
• Initially led to the lack of acceptance of early CMOS processes
• In current processes parasitic circuit elements are well understood and controlled by
process innovations and circuit techniques

p+ n+ n+ p+ p+ n+
n-well
p-substrate

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CMOS/Latch-Up/Physical Origin
– Physical Origin
• Parasitic components Q1, Q2, R1, R2 shown below found in all CMOS circuits
• (Vertical) Q1 is associated with the PFET M1, the n-well, and the substrate
• (Lateral) Q2 is associated with the NFET M2, the substrate, and the n-well
– Observations:
• Base of each bipolar transistor is connected to the collector of the other
• Bases of Q1 and Q2 see a non-zero resistance to Vcc and GND, resp.
GND D GND Vcc D Vcc

M2 M1

p+ n+ n+
Q2 p+ p+ n+
n-well
p-substrate R1
R2 Q1
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 Vcc Vcc

CMOS/Latch-Up/Physical Origin
– Parasitic circuit redrawn R1

• Reveals a positive feedback loop around Q1 and Q2: Q1

node Y
– Current injected into node X node X
– V(X) rises and reaches “trigger point” (around 0.7V) Q2
– Collector current of Q2 increases R2
– V(Y) falls
– Collector current of Q1 increases
GND GND

GND D GND Vcc D Vcc

M2 M1

p+ n+ n+
Q2 p+ p+ n+
n-well
p-substrate R1
R2 Q1
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 Vcc Vcc

CMOS/Latch-Up/Feedback
– Feedback loop R1

• If the loop gain is greater than or equal to unity, the Q1

node Y
phenomenon continues until both transistors turn on node X
completely, drawing a large current from Vcc. The Q2
circuit is then “latched up”, equivalent to a short- R2
circuit between Vcc and GND.
• The current drawn from Vcc is only limited by
parameters of the parasitic components GND GND

• The current drawn is usually destructive to metal

lines supplying the latched up circuitry
• The latched up condition will persist until
– circuit destruction
– circuit powered down

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 Vcc Vcc

CMOS/Latch-Up/Causes
R1
– Various sources can trigger a “latch-up” Q1
• The bases of Q1 and Q2 are capacitively coupled to node Y
node X
the drains of M1 and M2. Large drain dV/dt’s can
Q2
inject significant displacement currents into the n-
well or substrate R2

• Forward biasing of source-bulk junction diodes

(mosfets used in output stages, or input protection GND GND
diodes). Notoriously dangerous: Driving inductive
loads
• Ground-bounce (again forward biasing junction
diodes)
• Transient conditions during chip power-up
• Apply signals to inputs while chip is powered down
• Radiation

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 CMOS/Latch-Up/Prevention
– Latch-Up Preventation
• Latch-up preventation is a challenge for both
process engineers and circuit designers
• Process: Proper choice of doping levels and doping
profiles as well as layout design rules to ensure a
low value for parasitic resistances and the current
gain of the bipolar transistors
• Layout: Substrate and n-well contacts with
sufficiently small spacing (to minimise resistance)
• External circuitry: controlled start-up, external
protection of IC inputs and outputs
• Technology design manual developed by foundry
provides an extensive set of layout rules

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