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Kuruvilla Varghese
DESE
Indian Institute of Science
Kuruvilla Varghese
• Structure
• Design
• Timing analysis
• Xilinx STA
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2
Synchronous Counter 3
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Output Waveform 4
CLK
tco
PS 0 1 ? 2 3
Three tco’s, for Q2, Q1, and Q0, Worst case is taken
Q2 Q1 Q0 Q2 Q1 Q0
0 0 1 0 0 1
Q1 < Q0 Q1 > Q0
0 1 1 0 0 0
0 1 0 0 1 0
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4
Detailed and Next Level 5
NS D
Next
PS
State
CK Q
Logic AR
Clock
Reset
Incrementer
Cascade of Half- Adders
D Q D Q D Q Q
Q2 Q1 0
CK CK CK =
AR AR AR = ⊕
CLK
RST
= ⊕ · ·⋯ ·
Maximum Possible Paths: 9, Total Paths: 6
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UP-DN/ Next NS D
State PS
CK Q
Logic AR
Clock
Reset
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6
Mod - 6 Counter with input UP-DN/ 7
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Asynchronous 8
NS
Next D
PS Q2 Q1 Q0
State Q
CK 0 0 1
Logic
AR
0 1 1
CLK
0 1 0
RST
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8
Asynchronous 9
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Next NS D
State PS
CK Q
Logic AR
Min Clock period (Max frequency)
Clock Tclk(min) > [tco + tcomb + ts]maxpath
Reset
fmax < 1 / Tclk(min)
CLK tco tcomb slack = Tclk(min) – [tco + tcomb + ts]maxpath
PS
th ts th
Avoid Hold time violation
NS (For each path i)
Tclk tco(min)i + tcomb(min)i > th(max)i
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Max Frequency / Hold time Violation 11
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• Our analysis assumes that the clock reaches all the flip flops at the
same instant (i.e. there is no clock skew). We will analyze the case
with clock skews later.
• For Minimum time period, we are considering the delay of the slowest
path from flip-flop to flip-flop. Our expression shows the delay of the
longest path.
• For hold time violation we are considering lowest delay of each path
from flip-flop to flip-flop.
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12
Max Frequency / Hold time Violation 13
13
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Number of Paths 15
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D Q D Q
Comb
CK CK
CLK
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Static Timing Analysis (STA) 17
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STA 18
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STA: Register to Register Path 19
Input D Q D Q Output
Comb
CK CK
CLK
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Xilinx Vivado: Setup Area (Max Delay Analysis) 21
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• Total Negative Slack (TNS): The sum of all WNS violations, when
considering only the worst violation of each timing path endpoint. Its
value is:
– 0 ns, when all timing constraints are met for max delay analysis.
– Negative when there are some violations.
• Number of Failing Endpoints: The total number of endpoints with a
violation (WNS < 0 ns).
• Total Number of Endpoints: The total number of endpoints analyzed.
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22
Vivado: Timing Report 23
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• TPWS (Total Pulse Width Slack): The sum of the violations for each
clock pin in the entire design or a particular clock domain for the
following checks:
– minimum low pulse width
– minimum high pulse width
– minimum period
– maximum period
– maximum skew (between two clock pins of a same leaf cell)
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Vivado: Timing Report 25
• WPWS (Worst Pulse Width Slack): The worst slack for all
pulse width, period, or skew checks on any given clock pin.
• The Total Slack (TNS, THS or TPWS) only reflects the
violations in the design. When all timing checks are met, the
Total Slack is null.
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Vivado: Timing Report 27
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• Tool is able to analyze the delay of any path from an input pin to input
of any register, which naturally should be less than the clock period
constraint.
• What is more important is to account for the input delay external to
the FPGA device
• E.g. if the input signal originate from another device on the board
clocked by the same clock, then the clock to output delay of that
device and the wire delay to FPGA has to be accommodated, this is
specified as input delay.
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STA: Input Delay 29
FPGA Device
D Q D Q D Q D Q
Comb
Input Output
CK CK CK CK
CLK
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• Tool takes into consideration the clock skew between clock input of
FPGA and FPGA Register clock.
• If you use the timing constraint wizard of the Vivado tool, it analyzes
the missing constraints and prompts you to specify the input delay in
terms of clock to output delay, wire (trace) delay etc. (min and max
values)
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30
STA: Output Delay 31
• Tool is able to analyze the delay of any path from the output of any
register to an output pin, which naturally should be less than the clock
period constraint
• What is more important is to account for delay external to the FPGA
device
• E.g. if the output signal goes to another device on board clocked by
the same clock, then wire delay to that device and the setup time of
the device FF has to be accommodated, this is specified as output
delay
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FPGA Device
D Q D Q D Q D Q
Comb
Input Output
CK CK CK CK
CLK
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STA: Output Delay 33
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Combinational Delay 34
FPGA Device
D Q D Q
comb
Input Output
Delay Delay
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34
Combinational Delay 35
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2 ns 1 ns
ts th
D’ D CLK
2 ns D Q 2 ns
CLK
D
CK ts’ 4 ns
th’ -1 ns
D’
ts’ = ts + td(skew)
th’ = th – td(skew)
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Setup, Hold Times with skew 37
• Most often, setup and hold times of flip-flops or registers with respect to a pin or
output of another register need to be analyzed.
• When there is a delay t in the path to D input, the setup time with respect to new
reference point D' is increased by t and hold time is decreased by t.
• In this case, hold time can take a negative value. A hold time of –t means that at
point D’, the data can be removed or changed t time before the active clock
edge.
• Note: Setup time is defined as time before clock data has to be setup. So, for
setup time positive value is going backward from clock edge, and negative value
means it is forward from clock edge. For hold time reverse case applies.
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2 ns 1 ns
ts th
CLK
3 ns
D D Q
D
CLK ts’
CLK’ 3 ns CK -1 ns
th’ 4 ns
CLK’
ts’ = ts – tc(skew)
th’ = th + tc(skew)
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Setup, Hold Times with skew 39
• When there is a delay t in the path to CLK input, the setup time with
respect to new reference point CLK’ is decreased by t and hold time is
increased by t.
• In this case, setup time can take a negative value. A setup time of –t
means that at point CLK’, the data can be setup t time after the active
clock edge.
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D’ d(skew) D Q
CLK’ c(skew) CK
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STA: Combinational Circuit 41
Port to Port
(Combinational Path)
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Input D Q D Q Output
Comb
CK CK
CLK
• Register to register path decides the clock frequency. But, if other 2 exceeds
one need to choose the maximum value as the minimum clock period.
• In real life, this is not a great concern many a time we are designing some IPs
which goes inside the chip interfaced to other blocks close by. Even in case
inputs are outputs are brought to external pins, proper placement should take
care of these delays.
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