Simulation 33

• Types of Simulation
– Trace Simulation
• Steps
• Analog

input System output

• Digital
– Event driven simulation
• Events, trigger computation
• Events on inputs / internal
signals

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Simulation 34

D Q D Q • Simulation Time
Comb
CK CK – Event time at which
CLK computation happens
– Events are ordered
CLK
chronologically
• Simulation Cycle
– Resolving concurrency, by
• Sequential Circuit sequential computation
– Cycle based simulation – Delta delay
• Simulated every clock cycle

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1
 Simulation Cycle - Timing 35
3 ns
a x
b
5 ns • Issue 1: Order of statements
y
c
architecture dflow of ckt1 is
– Resolving concurrency – order
begin of concurrent statements may not
y <= c nor x after 5 ns; match the data flow.
x <= a and b after 3 ns; – Solution: Event driven
end dflow; computation
Time(ns) a b c x y – Feedback
0 1 1 0 1 0
– Solution: Keep computing till
100 0 1 0
stable.
100 + 3 0 0
100 + 3 + 5 1
108 0 1 0 0 1
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Simulation Cycle – Functional/Logic 36

a x
b
y y
c

architecture dflow of ckt1 is x

begin
y <= c nor x;
c
x <= a and b;
end dflow;
b
Time(ns) a b c x y
0 1 1 0 1 0
100 0 1 0 a
100 + δ 0 0
100 + 2δ 1 0 100 100+δ 100+2δ
100 0 1 0 0 1

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2
 Logic Simulation 37

• Issue 2: Functional/ Logic • How small should be the δ

simulation delay (for simulator
– Elements have zero delay implementation)?
– Solution: δ delay for resolving – Smaller than the smallest time
sequence. delay in the circuit,
• Events – Smaller than smallest change in
any input signal
– Events (on external signals and
one happens on internal signals
due to computation) are ordered
in simulation time and are
handled in the same order.

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Simulation Cycle - Feedback 38

S y

R Z
Z
architecture dflow of bff is
begin
Y
Z <= R nand Y;
Y <= S nand Z;
end dflow; R

Time(ns) S R Y Z
0 1 0 0 1 S
100 0 1 0 100 100 + δ 100 + 2δ
100 + δ 1
100 + 2δ 0 Solution: Event driven computation
100 0 1 1 0 Keep computing till stable.
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3
 Simulation Cycle - Feedback 39

Y
Y
0 5 10

architecture dflow of bff is

begin
Y <= R not (Y) after 5 ns;
end dflow;

Time (ns) Y
0 0
5 1
10 0
. .
. . Solution: Event driven computation
. . Oscillates

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Only inputs in sensitivity list? 40

a x • In response to an event on any of the

b inputs (in sensitivity list), process
c y
computes from top to bottom once.
d
e z • Even if the order of assignments match
f the data flow, each assignment use value
of inputs at current simulation time,
process (a, b, c, d, e, f)
though the outputs are assigned after a
begin
delta cycle.
…
• i.e. x is assigned after first delta cycle. In
x <= f1 (a, b);
the next statement value of x used is that
…
of current simulation time.
y <= f2 (c, d, x);
• To force a process computation, in
…
response to assignment of values to
z <= f3 (e, f, y);
internal signal, internal signals should be
end process;
included in the sensitivity list.
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4
 Process – Correct usage 41

process (a, b, c, d, e, f, x, y)
begin
…
x <= f1 (a, b);
…
y <= f2 (c, d, x);
…
z <= f3 (e, f, y);
end process;

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Process – Concurrent statements 42

• A concurrent statement is equivalent to a • In order for these internal signal

process with signals in the RHS of the
concurrent statement in the process
sensitivity list.
• When a combinational block is coded in a
single process, all the input signals and all
the internal signals should be in the
sensitivity list.
• This is required as the assignment happens
at (t + delta) time for an event at ‘t’ and
the subsequent statements use the values
of internal signals at time ‘t’.
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assignments to trigger the process
computation, internal signals should be in
the sensitivity list. This is true even if the
order of statements are in the order of data
flow.
• Concurrent statements are equivalent to
process with signals on the RHS of
assignments in the sensitivity list.
• Similarly, a process could be equivalently
written with multiple concurrent statements
• In real cases, multiple concurrent
statements and multiple processes works
concurrently, responding to various events
on inputs or internal signals.

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 Synthesis 43

• eq <= ‘1’ when (a = b) else ‘0’; Exponential Complexity

a3 a2 a1 a0 b3 b2 b1 b0 eq Width 4  2 exp 8 terms

Width 8  2 exp 16 terms
0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 1 0 Operator Inferencing = ex-or / ex-
nor

y <= a + b;
0 0 0 1 0 0 0 0 0
y <= x + 1;

1 1 1 1 1 1 1 1 1

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Data Objects 44

• Classes
Constants, Signals, Variables, Files
• Syntax
class object_name: data type;
• Signals
Signals declared in architecture
declarative region and used anywhere
(architecture, processes, functions,
procedures)
signal carry: std_logic_vector(7
downto 0);
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• Constants
– For readability and easy modification
of code
constant width: integer := 8;
• Variables
– Declared in sequential bodies
(process, functions, procedures).
– Used in simulation extensively.
Indexing, temporary storage etc..
Synthesis is not well defined in non-
trivial cases.
variable count: integer range 0 to
255;

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6
 Data Objects, Types 45

• Files • Data Types

Used in test benches to store input – Scalar: enumerated, integer,
vectors and to write output vectors. float
Screen output
– Composite: array, record
type logic_data is file of character;
file logical_name: logic_data;
file logical_name: logic_data is • Enumerated
“inpvec.dat”;
type state_type (init, sample, wait,
file logical_name: logic_data open
read_mode is “inpvec.dat”; interrupt, out);

– Normally takes the values 0,1,2,3,4, ...

– Could be changed using attributes

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Data Types - Scalar 46

• Enumerated subtype std_logic is resolved

type boolean is (FALSE, TRUE); std_ulogic;
type bit is (‘0’, ‘1’);
type std_ulogic is resolved is the resolution function
( ‘U’, -- Un-initialized which computes the resultant
‘X’, -- Forcing Unknown values when there are multiple
drivers
‘0’, -- Forcing 0
‘1’, -- Forcing 1 – Synthesis: ‘0’, ‘1’, ‘L’, ‘H’, ‘Z’, ‘-’
‘Z’, -- High Impedance – Simulation: All except ‘-’
‘W’ -- Weak Unknown
‘L’, -- Weak 0
‘H’, -- Weak 1
‘-’ -- Don't care );

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7
 Data Types, Scalar Predefined 47

• Integer • Physical Types

type integer is range -2147483647 to type time is range -2147483647 to
2147483647; 2147483647
units
Range fs;
variable count: integer range 0 to ps = 1000 fs;
255; ns = 1000 ps;
constant width: integer := 16; us = 1000 ns;
ms = 1000 us;
• Floating types sec = 1000 ms;
min = 60 sec;
type real is range –1.0E38 to hr = 60 min;
+1.0E38 end units;
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Subtypes 48

• Subtype • What is the difference between

the above two?
– subtype my_int is integer range
48 to 56; – In the first one, all the operators
– subtype “UX01” is resolved defined for integer works. In the
std_ulogic range ‘U’ to ‘1’; second case various operators
need to be overloaded for the
• Type and subtype new my_int type.

– subtype my_int is integer range

48 to 56;
– type my_int is range 48 to 56;

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8
 User defined Data Types 49

• User defined • Array Types

– type MVL is (‘U’, ‘0’, ‘1’, ‘Z’);
– type index is range 0 to 15;
– type word_length is range 31 type word is array (15 downto 0) of bit;
downto 0; signal address: word;
– type volt_range is 3.3 downto 1.1;
– type current is range 0 to 1E9 • Unconstrained Array (constrained
units at the time of object declaration)
nA;
uA = 1000 nA; type bit_vector is array (natural range
mA = 1000 uA; <>) of bit;
amp = 1000 mA; type std_logic_vector is array (natural
range <>) of std_logic;
end units; signal a: std_logic_vector(3 downto 0);
– subtype filter_current is current
range 10 uA to 5 mA;

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Data Types - Composite 50

• Record Types
type table8x4 is array (0 to 7, 0 to 3) of
std_logic;
type iocell is record
constant ex_or: table8x4 := buffer_inp: std_logic_vector(7
downto 0);
(“000_0”, “001_1”,
enable: std_logic;
“010_1”, “011_0”,
buffer_out: std_logic_vector(7
“100_1”, “101_0”, downto 0);
“110_0”, “111_1”); end record;

signal busa, busb, busc: iocell;

signal vec: std_logic_vector(7
downto 0);

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9
 Data Types - Composite 51

busa.buffer_inp <= vec; • Array assignments

busb.buffer_inp <= busa.buffer_inp
busb.enable <= ‘1’; signal row: std_logic_vector(7 downto
busc <= busb; 0);
row <= (‘1’, ‘0’,’1’,’1’, ‘1’, ‘1’,’1’,’1’);
busa.buffer_out <= busa.buffer_inp row <= (7 =>’1’, 6 => ’0’, others => ’1’);
when (busa.enable = ‘1’) else row <= “10111111”;
(others => ‘Z’); row <= (‘1’, ‘0’, others => ‘1’);
row <= X“BF”;
• Alias row <= (others => ‘0’);
signal address: std_logic_vector(31 row <= (others => ‘Z’);
downto 0);
Base: Hexadecimal: X,
alias top_ad: std_logic_vector(3 Octal: O,
downto 0) is address(31 downto 28); Binary: B
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10