Carrier PWM algorithm with optimised defined as

switching loss for three-phase 8

< vr0;int max if 0  vr0;int max
four-leg multilevel inverters vr0;int ref ¼ 0 if vr0;int min < 0 < vr0;int max ð6Þ
:
vr0;intmin if 0  vr0;int min
N.V. Nho and M.J. Youn
where vr0,intmax ¼ [(n
1)=2
max] is the maximum zero sequence for
A novel approach to analyse a four-leg multilevel inverter as a model given fundamental voltages; max is the largest from three fundamental
of two simple inverters in series is presented and a carrier-based signals. The offset vr0,intSVM will be given by (6)–(9) as
SVPWM method is proposed. To obtain the optimised switching loss,
the zero sequence function is controlled by redundant parameters. n00 ¼ Intðvr0; int ref
vr0;int min Þ ð7Þ
The PWM analysis is simplified, and the use of complicated three-
v0r1 ¼ vr0; int ref
vr0;int min
n00 ð8Þ
dimensional SVPWM concepts is avoided. 8 0 0
> v
< r0;intmin þ n 0 þ 0:5 K 1 if 0  v r1  K1

Introduction: Different PWM methods have been introduced for vr0;int SVM ¼ vr0;intmin þ n00 þ K1 þ 0:5 K2 if K1 < v0r1  K1 þ K2
>
:
three-phase four-wire inverters. Many of them are derived from vr0;intmin þ n00 þ K1 þK2 þ 0:5 K3 if K1 þ K2 < v0r1 < 1
three-dimensional SVPWM concepts, which are rather inconvenient
ð9Þ
for complicated calculations [1]. A four-leg multilevel inverter can be
analysed as a voltage model consisting of two separate inverters in For a single-leg inverter, the reference modulating signal vr0,ext is
series. In this Letter, this model and the vector correlation between determined from reference output vr0 and internal SVPWM zero
SVPWM and CPWM in multilevel inverters [2] will be used to sequence vr0,int SVM as
propose a carrier PWM method in four-leg multilevel inverters. It vr0;ext ¼
vr0 þ vr0;int SVM ð10Þ
shows that the mathematical calculation is simple. A carrier PWM
algorithm with optimised switching loss will be presented. A block diagram for generating reference modulating signals of four-
leg inverters, using (6)–(10), is shown in Fig. 2 and diagrams of
generated signals are shown in Fig. 3. From unbalanced three-phase
Proposed carrier-based PWM: The voltage model of an inverter will signals vra0, vrb0, vrc0, the active (fundamental) and zero sequence vra12,
be derived under the assumption that the reference voltage vector in vrb12, vrc12, vr0 can be deduced. Using (9), from the reference input
a hexagonal area is modulated from the three nearest vectors, the vr0,int ref, the internal offset vr0,int SVM and reference modulating signals
switching sequence produces active and zero sequence voltages. The vra, vrb, vrc can be deduced for a three-leg inverter.
phase to DC neutral point voltages vx0 can be expressed as a
summation of active vx12 and internal zero sequence component
v0,int (Fig. 1a, b) as follows:
vx0 ¼ vx12 þ v0;int ; x ¼ a; b; c ð1Þ
The reference modulating signals of the three-leg inverter consist of
active modulating components vrx12 and zero sequence function vr0,int,
described as follows:
vrx0 ¼ vrx12 þ vr0;int ; x ¼ a; b; c ð2Þ
Analysis of the zero sequence function, vr0,int for three-leg n-level
inverters [2] gives
Fig. 2 Principle of proposed SVPWM method
n0 ¼ Intðvr 0;int
vr 0;int min Þ ð3Þ
vr1 ¼ vr 0;int
vr 0;int min
n0 ð4Þ
8
> v þ n0 þ x1 K1 if 0  vr1  K1
< r 0;int min
vr0;int ¼ vr 0;int min þ n0 þ K1 þ x2 K2 if K1 < vr1  K1 þ K2
>
:
vr 0;int min þ n0 þ K1 þ K2 þ x3 K3 if K1 þ K2 < vr1 < 1
ð5Þ

where (0  xj  1), j ¼ 1, 2, 3; int is an integer function; and

vr0,int min ¼ [
0.5(n
1)
min] min is the smallest from three-phase
fundamental signals. Switching time duties K1, K2 and K3 can be
determined from fundamental components vrx [2].

Fig. 3 Four-leg five-level inverter

The diagrams of vr0, vr0, int ref, vr0, int SVM and three reference modulating signals
of three-leg inverter vra, vrb and vrc for m ¼ 0.75 and vr0 ¼ 0.3 cos(y
p=6)

Conclusion: The proposed SVPWM method for four-leg multilevel

Fig. 1 Four-leg three-level inverter
a Circuit diagram
b Voltage model
The SVPWM method for three-leg inverters will be implemented
with two equally-centred redundant active voltage vectors and obtain
minimum common mode, which gives rise to optimised switching loss
[2]. For this, the zero sequence of the three-leg inverter, vr0, int SVM will
approximate to the reference internal zero sequence function vr0, int ref,
inverters is simple and applicable to cascade and diode clamped types.
The method can be modified for obtaining required performances by
changing the reference function vr 0, int ref.
# IEE 2005 12 September 2004
Electronics Letters online no: 20056612
doi: 10.1049/el:20056612
N.V. Nho and M.J. Youn (Department of Electrical Engineering,
Korea Advanced Institute of Science and Technology, 373-1,
Guseong-Dong, Yuseong-Gu, Daejeon 305-701, Republic of Korea)
E-mail: nvnho@hcmut.edu.vn

ELECTRONICS LETTERS 6th January 2005 Vol. 41 No. 1

References
1 Zhang, R., Prasad, V.H., Boroyevich, D., and Lee, F.C.: ‘Three-
dimensional space vector modulation for four-leg voltage-source
converters’, IEEE Trans. Power Electron., 2002, 17, (3), pp. 314–326
2 Nho, N.V., Moon, G.W., and Youn, M.J.: ‘Analysis of carrier based PWM
methods in relation to common mode voltage for multilevel inverter’.
Proc. IEEE Int. Conf. on Industrial Electronics, Control and
Instrumentation (ICEON), Pusan, South Korea, 2004 (accepted for
publication)

ELECTRONICS LETTERS 6th January 2005 Vol. 41 No. 1