You need to design a simple CISC architecture to carry out conversion of an 8-bit Binary number to 8-bit

Gray

code number and vice-versa. Verify the Verilog code in Modelsim simulator by writing a test bench.

While designing architecture for binary code to gray code, use following parameters. A similar approach

has to

be used to carry out the conversion of gray code to binary code. Valid assumptions, if made, need to be

specified

clearly.

Parameters:

1. Define two 8 bit PIPO (Parallel In Parallel Out) registers (R1 and R2); R1 (for storing the binary

number),

R2 (for storing the gray coded number), and two one bit registers (R3, R4) for holding 1 bit values to be

xored.

● Each register will have two input (flags): R1_in, R1_out

● When R1_in is high, register can take data from the external bus.

● When R1_out is high, register can send data to the external bus.

2. You can use only one XOR gate.

3. The interconnect structure should be implemented using tri sate buffers and MUXs so as to avoid bus

contention.

4. Define a Control Unit for controlling the process flow.

● It will have three inputs: Start, Convert and Clock. The Convert signal, if ‘0’ controls binary to

gray code conversion else gray to binary code conversion

● Output: R1_in, R1_out, R2_in, R2_out, R3_in, R3_out, R4_in, R4_out, and Done.

● When Start is high, process will start, else R2 register will hold 8 ’bzzzzzzzz value

● Done will go high when conversion is done and gray coded number is stored in R2, else will

remain in low.

● Use only Moore based FSM style for designing this control unit.
Verilog Code

// Code your design here

/*module control_unit
(start,clock,convert,R1_in,R1_out,R2_in,R2_out,R3_in,R3_out,R4_in,R4_out,reset,done);

input start;

input clock;

input reset;

input convert;

output R1_in;

output R1_out;

output R2_in;

output R2_out;

output R3_in;

output R3_out;

output R4_in;

output R4_out;

output done;
reg R1_in;

reg R1_out;

reg R2_in;

reg R2_out;

reg R3_in;

reg R3_out;

reg R4_in;

reg R4_out;

reg done;

reg counter_load,counter_decrement;

reg [2:0] counter ;

reg [4:0] present_state,next_state;

always @ (posedge clock or negedge reset) begin

if (!reset)

present_state <=5'd0;

else

present_state <= next_state;

end

always @(*) begin

R1_in <= 1'b0;

R1_out <= 1'b0;

R2_in <= 1'b0;

R2_out <= 1'b0;

R3_in <= 1'b0;

R3_out <= 1'b0;

R4_in <= 1'b0;

R4_out <= 1'b0;

counter_load <= 1'b0;

counter_decrement <= 1'b0;

case (present_state)

5'd0: next_state <= 5'd1;

 5'd1: begin

//if (&counter) begin

//R1_in <= 1'b0;

//next_state <= 5'd2;

//end

// else begin

R1_in <= 1'b1;

next_state <= 5'd2;

//end

end

5'd2: begin

R1_out <= (start?1'b1:1'b0);

next_state <= (start?5'd3:5'd2);

end

5'd3: begin

R2_in <= 1'b1;

next_state <= 5'd4;

counter_load <= 1'b1;

end

5'd4: begin

R1_out <= 1'b1;

counter_load <= 1'b0;

next_state <= convert?5'd12:5'd5;

end

5'd5: begin

R3_in <= 1'b1 ;

next_state <= 5'd6;

end

5'd6: begin

R1_out <= 1'b1;

next_state <= 5'd7;

end
5'd7: begin

R4_in <= 1'b1;

next_state <= 5'd8;

end

5'd8: begin

R3_out <= 1'b1;

next_state <= 5'd9;

end

5'd9: begin

R4_out <= 1'b1;

next_state <= 5'd10;

end

5'd10: begin

R2_in <= 1'b1;

counter_load <= 1'b0;

counter_decrement <= 1'b1;

next_state <= (counter == 3'd2)?5'd11:5'd 4;

end

5'd11: begin

done <= 1'b 1;

R2_out <= 1'b1;

counter_load <= 1'b1;

counter_decrement <= 1'b1;

next_state <= (counter == 3'd0) ? 4'd0 : 4'd11;

end

5'd12: begin

R3_in <= 1'b1;

next_state <= 5'd13;

counter_load <= 1'b1;

end

5'd13: begin

R1_out <= 1'b1;

 next_state <= 5'd14;

end

5'd14: begin

R4_in <= 1'b1;

next_state <= 5'd15;

end

5'd15: begin

R2_in <= 1'b1;

next_state <= (counter == 3'd1) ? 5'd0 : 5'd16;

counter_decrement <= 1'b1;

done <= (counter ==1);

end

5'd16: begin

R3_in <= 1'b1;

next_state <= 5'd17;

end

5'd17: begin

R1_out <= 1'b1;

next_state <= 5'd18;

end

5'd18: begin

R4_in <= 1'b1;

next_state <= 5'd15;

end

default : begin

R1_in <= 1'b0;

R1_out <= 1'b0;

R2_in <= 1'b0;

R2_out <= 1'b0;

R3_in <= 1'b0;

R3_out <= 1'b0;

R4_in <= 1'b0;

 R4_out <= 1'b0;

counter_load <= 1'b0;

counter_decrement <= 1'b0;

end

endcase

end

always @(posedge clock or negedge reset)

begin

if (!reset)

counter <= 3'b0;

else if (counter_load)

counter <= 3'b111;

else if (counter_decrement)

counter <= counter -3'd1;

end

endmodule

module xor_module (interconnect_data,xor_out,clock,reset,R3_out);

input interconnect_data;

input clock,reset,R3_out;

output xor_out;

reg xor_out;

reg xor_in0,R3_out_d1;

always@(posedge clock or negedge reset) begin

if (!reset)

R3_out_d1 <= 1'b0;

else

R3_out_d1 <= R3_out;

end
// Since interconnect can only hold current data, we need to hold the last data also for xoring

always@(posedge clock or negedge reset) begin

if (!reset) begin

xor_in0 <= 1'b0;

end

else if (R3_out_d1)

xor_in0 <= interconnect_data;

end

always@(posedge clock or negedge reset) begin

if (!reset)

xor_out <= 1'b0;

else

xor_out <= xor_in0 ^ interconnect_data;

end

endmodule

module interconnect_module
(R1_out,R2_out,R3_out,R4_out,xor_out,R1_data,R2_data,R3_data,R4_data,interconnect_data, clock,
reset);

input R1_out,R2_out,R3_out,R4_out,xor_out,R1_data,R2_data,R3_data,R4_data, clock, reset;

output interconnect_data;

reg interconnect_data;

//Control unit ensure that at a time only one of this will be 1 so its gray coded encoding

always@ (posedge clock or negedge reset) begin

if(!reset) interconnect_data <= 0;

else begin

case({R1_out,R3_out,R4_out})

3'b100: interconnect_data <= R1_data;

3'b010: interconnect_data <= R3_data;

3'b001: interconnect_data <= R4_data;

default: interconnect_data <= xor_out;

endcase

end

end

endmodule

module register_file
(interconnect_data,done,R1_in,R2_in,R3_in,R4_in,R1_data,R2_data,R3_data,R4_data,clock,reset,R1_o
ut,R2_out,R3_out,R4_out,external_bus);

input wire interconnect_data,R1_in,R2_in,R3_in,R4_in,R1_out,R2_out,R3_out,R4_out,clock,reset,done;

input [7:0] external_bus;

output wire R1_data,R2_data,R3_data,R4_data;

reg R3,R4;

reg [7:0] R1,R2;

reg [2:0] R1_read_pointer,R2_write_pointer;

//Register R3 & R4

always @ (posedge clock or negedge reset)

begin

if (!reset)

begin

R3 <= 1'b0;

R4 <= 1'b0;

end

else if (R3_in) begin

R3 <= interconnect_data;

R4 <= R4;

end

else if (R4_in) begin

R4 <= interconnect_data;

R3 <= R3;

end

end

assign R3_data = R3;

assign R4_data = R4;

//REG R1

always @ (posedge clock or negedge reset)

begin

if (!reset)

R1 <= 8'd0;

else if (R1_in)

R1 <= external_bus;

end

assign R1_data = R1[R1_read_pointer];

//read pointer for register R1

always @ (posedge clock or negedge reset)

begin

if (!reset)

R1_read_pointer <= 3'd7;

else if (R1_out)

R1_read_pointer <= R1_read_pointer-3'd1;

end

//REG R2

always @ (posedge clock or negedge reset)

begin

if (!reset)

R2 <= 8'bzzzzzzzz;

else if (R2_in)

case (R2_write_pointer)

3'b000 : R2[0]<= interconnect_data;

3'b001 : R2[1]<= interconnect_data;

3'b010 : R2[2]<= interconnect_data;

3'b011 : R2[3]<= interconnect_data;

3'b100 : R2[4]<= interconnect_data;

3'b101 : R2[5]<= interconnect_data;

3'b110 : R2[6]<= interconnect_data;

 3'b111 : R2[7]<= interconnect_data;

endcase

//R2[R2_write_pointer] <= interconnect_data;

end

//assign external_bus = done?R2:8'bzzzzzzzz;

//write pointer for register R2

always @ (posedge clock or negedge reset)

begin

if (!reset)

R2_write_pointer <= 3'd7;

else if (R2_in)

R2_write_pointer <= R2_write_pointer -3'd1;

end

endmodule

module top (clock,reset,start,convert,done,external_bus);

input clock,reset,start,convert;

output done;

input [7:0] external_bus;

wire
R1_in,R2_in,R3_in,R4_in,R1_out,R2_out,R3_out,R4_out,interconnect_data,R1_data,R2_data,R3_data,R
4_data;

control_unit u_CU (.*);

xor_module u_xor(.*);

interconnect_module u_BUS (.*);

register_file u_reg_file (.*);

endmodule

*/

TB:

module tb(input done, output clock,reset,start,convert, external_bus);

reg clock;

reg reset;
 reg start, convert;

top my_top(.*);

reg [7:0] external_bus = 8'd2;

//Set up the clock to toggle every 10 time units

initial

begin

$display($time, "Before the code start\n");

clock = 1'b0;

forever #5 clock = ~clock;

end

initial begin

$dumpfile("dump.vcd");

$dumpvars;

reset = 1'b1;

#15 reset = 1'b0;

#10 reset = 1'b1;

#500 $finish; //Terminating the simulation

end

initial begin

#20 convert = 0;

start = 1;

end

always @(*)

$monitor($time, "convert: %d, done: %d, external_bus: %d", convert,done,external_bus);

endmodule
Log File details:
[2020-04-04 14:01:31 EDT] irun -Q -unbuffered '-timescale' '1ns/1ns' '-sysv' '-access'
'+rw' design.sv testbench.sv
irun: 15.20-s038: (c) Copyright 1995-2017 Cadence Design Systems, Inc.
reg clock;
|
ncvlog: *W,ILLPDX (testbench.sv,5|10): Multiple declarations for a port not allowed in
module with ANSI list of port declarations (port 'clock') [12.3.4(IEEE-2001)].
reg reset;
|
ncvlog: *W,ILLPDX (testbench.sv,6|10): Multiple declarations for a port not allowed in
module with ANSI list of port declarations (port 'reset') [12.3.4(IEEE-2001)].
reg start, convert;
|
ncvlog: *W,ILLPDX (testbench.sv,7|10): Multiple declarations for a port not allowed in
module with ANSI list of port declarations (port 'start') [12.3.4(IEEE-2001)].
reg start, convert;
|
ncvlog: *W,ILLPDX (testbench.sv,7|19): Multiple declarations for a port not allowed in
module with ANSI list of port declarations (port 'convert') [12.3.4(IEEE-2001)].
reg [7:0] external_bus = 8'd2;
|
ncvlog: *W,ILLPDX (testbench.sv,9|23): Multiple declarations for a port not allowed in
module with ANSI list of port declarations (port 'external_bus') [12.3.4(IEEE-2001)].
Top level design units:
tb
ncelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009
SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV
2009 simulation semantics.
xor_module u_xor(.*);
|
ncelab: *W,CUVDSO (./design.sv,290|21): 1 output port was not connected by dot-star:
ncelab: (./design.sv,164): xor_out

interconnect_module u_BUS (.*);

|
ncelab: *W,CUVDSI (./design.sv,291|26): 1 input port was not connected by dot-star:
ncelab: (./design.sv,193): xor_out

Loading snapshot worklib.tb:sv .................... Done

ncsim: *W,DSEM2009: This SystemVerilog design is simulated as per IEEE 1800-2009
SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV
2009 simulation semantics.
ncsim> source /incisiv/15.20/tools/inca/files/ncsimrc
ncsim> run
0Before the code start

20convert: 0, done: x, external_bus: 2

475convert: 0, done: 1, external_bus: 2
Simulation complete via $finish(1) at time 525 NS + 0
./testbench.sv:27 #500 $finish; //Terminating the simulation
ncsim> exit
Waveforms: