La C701P

A B C D E
1 1
Compal Confidential
2
Broadwell M/B Schematics Document 2
Intel ULV Processor with DDRIIIL

Date : 2015/01/31
3 3
Version 0.3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-C701P
Date: Saturday, January 31, 2015 Sheet 1 of 61
A B C D E
A B C D E
Compal Confidential
Model Name : Broadwell
VRAM AMD PCI-Ex4
Lane 7-Lane10
File Name : AHL50 / ABL52 DDR3 X4 EXO-Pro M330
PCIe 2.0:5Gb/s
1 LA-C701P 18W PCIe 3.0:8Gb/s 1
P41~P42 P36~P40 DDR3L-SO-DIMM X 2
Dual Channel
P15~16
LVDS@
DDR3L 1600MHz 1.35V
LVDS panel eDP to LVDS Transmitter eDPx1
P19
RTD2132N P18
2.7Gb/s
eDP@
Broadwell SATA 3.0 Port 0
eDP panel 2.5" SATA HDD P29
FHD
eDPx1 Ultra Light & Thin GEN1 1.5Gb/s
GEN2 3Gb/s Port 1
eDP@ 2.7Gb/s ODD
GEN3 6Gb/s P29
1168P BGA
CRT Conn DP to VGA Transmitter DDIx2
P21
RTD2168 P21 USB3.0
HDMI 5Gb/s
HDMI Conn (BDW ULT) USB2.0 Port 0 Port 0
DDPB port P20 297MHz USB3.0 port
480Mb/s P30
2 2
LAN Lane 5 PCI-E Port 1

8166EH P22 USB2.0 port P30
PCIe 1.0:2.5Gb/s
PCIe 2.0:5Gb/s
Port 2
USB2.0 Port P34
Port 3
Lane 11 PCIe 1.0:2.5Gb/s WLAN P31
PCIe 2.0:5Gb/s
PCI-E
Port 4
WLAN(MiniPCIe slot) Camera P19
P31
Port 5
Touch Screen P19
Port 3 Port 3 (Reserved) USB2.0
3 480Mb/s 3
Port 6 Card reader

SMBUS
RTS5141 P24
1MHz
P26 Int.KBD ENE KB9022 LPC

P26 33MHz
PS2 P25 HDA 24MHz HDA Aduio codec
Touch Pad Internal SPK
ALC3227
P23
P33 FAN TPM
SLB 9665 Combo Jack
Lid switch P27
On small board
SPI
4 Thermal sensor 50MHz 4
P37 NCT7718 SPI ROM

8M P7
Block Diagrams
Dr-Bios.com
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
LA-C701P
A B C D E
A B C D E
Power rail Control (EC) Source (CPU)

+RTCVCC X X
@ is NO SMT part (empty) DIS@ : for AMD EXO <USB2.0 port>
VIN X X
BATT+ X X
@EMI@,@ESD@,@RF@ : Reserve , don't pop. UMA@ : for UMA only DESTINATION
B+ X X
+VL X X
TP@ : TP SMBus USB2.0 port UMA Dis
+3VL X X
RF@ : RF team request, must add. XTAL@ : for HSW SMT in DB phase only
1
+5VALW EC_ON X EMI@ : EMI team request, must add. GCLK@ : Support GCLK 0 USB 2.0/3.0(left side) USB 2.0/3.0(left side) 1
+3VALW EC_ON X
+3VALW_EC EC_ON X
ESD@ : ESD team request, must add. GCLKUMA@ : UMA 1 USB 2.0(left side) USB 2.0(left side)
+3V_PCH PCH_PWR_EN X
+1.35V_VDDQ SYSON PM_SLP_S5#/PM_SLP_S4#
SPI@ : SPI ROM request GCLKDIS@: DIS
2 USB 2.0(right side) USB 2.0(right side)
+5VS SUSP# PM_SLP_S3# LVDS@ : Support LVDS panel. 8111@ : for LAN giga
+3VS SUSP# PM_SLP_S3# 3 WLAN/BT WLAN/BT
+1.5VS SUSP# PM_SLP_S3#
eDP@ : Support eDP panel 8166@ : for LAN 10/100
+1.05VS SUSP# PM_SLP_S3# 4 Camera Camera
+0.6V_0.675VS SUSP#
+VCC_CORE X VR12.5_VR_ON 5 Touch screen Touch screen
6 Card reader Card reader

+3V_PCH +3VS
7 X X
R=2.2K TP_SMBCLK
QC7 TP_SMBDATA
2N7002 Touch Pad
2 UCPU1
<PCI-E,SATA,USB3.0> 2
+3V_PCH +3VS RC78 DESTINATION DESTINATION
PR2 RC79 XDP Lane# USB3.0 Lane# PCIE
R=2.2K R=10K UMA Dis UMA Dis
AP2 SMBCLK QC2 PCH_SMBCLK 0 USB3.0 0
USB3.0
AH1 SMBDATA 2N7002 PCH_SMBDATA
SO-DIMM 0 1 1
CPU
2
+3V_PCH 3 LAN LAN
RC72
SO-DIMM 1 DESTINATION
RC73 @ 0 ohm Lane# SATA
R=1K UMA Dis DESTINATION
SML0CLK
AN1 SML0DATA +3VS_CRT 0 HDD HDD Lane# PEG
AK1 UMA Dis
RTD2168_SMB_SCL 1 ODD ODD
R=0 RTD2168_SMB_SDA 0
DP to VGA RTD2168 2 WLAN WLAN
+3V_PCH +3VS 1
GPU
PR2 2
+3VS_RT PCIE DESTINATION
AU3 SML1CLK
R=2.2K
QC6
R=2.2K
EC_SMB_CK2 CIICSCL1
3
Lane# REQ
AH3 SML1DATA 2N7002 EC_SMB_DA2 R=0 CIICSDA1 UMA Dis
eDP to LVDS bridge RTD2132R 0 LAN LAN
1 X X
3
Thermal Sensor for CPU 2 WLAN WLAN 3
3 X GPU
UK1:+3VALW_EC 4 PU PU
+3VS_VGA
5 PU PU
DIS@ DIS@
79 EC_SMB_CK2 Q2416 R=10K R327 R328
EC_SMB_DA2 Board ID control
80 2N7002
VGA_SMB_CK3 GPU
EC @ 0 ohm VGA_SMB_DA3 15"
UMA
RK4
DB
0 ohm
SI
15K ohm
PV
27K ohm
MV
43K ohm
+3VS_VGA DIS
+3VS 12k ohm 20k ohm 33k ohm 56k ohm
+3VS_VGA RK4
EC_SMB_CK3 R=2.2K R=2.2K
83 EC_SMB_DA3 Thermal Sensor
84 2N7002 Thermal Sensor for GPU
CPU internal : PECI protocal
PCH internal : 0x90
+3VALW_EC
GPU internal : 0x82
R=2.2K
CPU external : 0x98
77 EC_SMB_CK1 GPU external : 0x98
78 EC_SMB_DA1 R=100
4
BAT 4
Charger
Notes List
Custom 0.1
LA-C701P
A B C D E
5 4 3 2 1
<11,6,9> +1.05VS_VCCST +1.05VS_VCCST

UCPU1A BDW_ULT_DDR3L(Interleaved)
<11,15,16,17,34,49> +1.35V_VDDQ +1.35V_VDDQ
<10,11,12,24,36,6,7,9> +3V_PCH +3V_PCH
<20> PCH_DPB_N2 C54 C45 +VCCIOA_OUT

C55 DDI1_TXN0 EDP_TXN0 B46 EDP_CPU_LANE_N0_C <18> <11> +VCCIOA_OUT
<20> PCH_DPB_P2 DDI1_TXP0 EDP_TXP0 EDP_CPU_LANE_P0_C <18>
<20> PCH_DPB_N1 B58 A47 <eDP> +VCCIO_OUT
DDI1_TXN1 EDP_TXN1 EDP_CPU_LANE_N1_C <18> <11,6> +VCCIO_OUT
C58 B47
<20> PCH_DPB_P1 DDI1_TXP1 EDP_TXP1 EDP_CPU_LANE_P1_C <18>
B55
<20> PCH_DPB_N0 DDI1_TXN2
<20> PCH_DPB_P0 A55 C47 DB phase :
A57 DDI1_TXP2 EDP_TXN2 C46
<HDMI> <20> PCH_DPB_N3
B57 DDI1_TXN3 EDP_TXP2 A49 add eDP Lan1 for FHD
D <20> PCH_DPB_P3 DDI1_TXP3 EDP_TXN3 D
DDI EDP B49
C51 EDP_TXP3 20141117
<21> PCH_DPC_N0 DDI2_TXN0
<21> PCH_DPC_P0 C50 A45
C53 DDI2_TXP0 EDP_AUXN B45 EDP_CPU_AUX#_C <18>
<DP TO CRT> <21> PCH_DPC_N1
B54 DDI2_TXN1 EDP_AUXP EDP_CPU_AUX_C <18> <eDP>
<21> PCH_DPC_P1 DDI2_TXP1
C49 D20 EDP_COMP
B50 DDI2_TXN2 EDP_RCOMP A43
A53 DDI2_TXP2 EDP_DISP_UTIL remove BKL_PWM_CPU
B53 DDI2_TXN3 20141113
DDI2_TXP3
RC11 2 1 10K_0402_5% H_CPUPWRGD_R

+3V_PCH COMPENSATION PU FOR eDP
1 OF 19 +VCCIOA_OUT L Layout notes
DG V0.9 PEG_COMP
BDW-ULT-DDR3L-IL_BGA1168
1
SA011306191 Trace width=20mil and spacing=25mil
RC234 EDP_COMP 2 1
+VCCIO_OUT 10K_0402_5% 24.9_0402_1% RC3 Max length=100mil
UCPU1B BDW_ULT_DDR3L(Interleaved)
2
1
RC4 PROC_DETECT# D61

62_0402_5% PAD T51 @ K61 PROC_DETECT MISC
N62 CATERR J62 XDP_PRDY#
<25> H_PECI PECI PRDY XDP_PRDY# <6>
K62 XDP_PREQ#
XDP_PREQ# <6>
2
PREQ E60 XDP_TCK

PROC_TCK E61 XDP_TCK <6>
XDP_TMS_CPU
JTAG PROC_TMS XDP_TMS_CPU <6>
<25> PROCHOT# PROCHOT# RC6 1 2 56_0402_5% H_PROCHOT#_R K63 E59 XDP_TRST#_CPU
PROCHOT THERMAL
PROC_TRST F63 XDP_TDI_CPU
PROC_TDI XDP_TDI_CPU <6> +1.05VS_VCCST
1 F62 XDP_TDO_CPU
PROC_TDO XDP_TDO_CPU <6>
ESD@ @
SI : pop C295 C295 <11,6> +1.05VS_PG RC7 1 2 H_CPUPWRGD_R C61
PROCPWRGD
Layout notes 10P_0402_50V8J 1K_0402_1% PWR
2 J60 XDP_TDI_CPU @ RC12 2 1 51_0402_1%
L DG V0.5 Trace width=12~15 mil <6> H_CPUPWRGD_R BPM#0
BPM#1
H60
H61
XDP_OBS0_R
XDP_OBS1_R
<6>
<6>
Max length=500mil DB phase XDP_OBS2_R T52 @ PAD XDP_PREQ# @ RC13 2 1 51_0402_1%
BPM#2 H62 XDP_OBS3_R T53 @ PAD
For XDP 20151112 SM_RCOMP0 AU60 BPM#3 K59 XDP_OBS4_R T54 @ PAD
C
DDR3 COMPENSATION SIGNALS SM_RCOMP1 AV60 SM_RCOMP0 DDR3L BPM#4 H63 XDP_OBS5_R T55 @ PAD XDP_TRST#_CPU
C
SM_RCOMP1 BPM#5 XDP_TRST#_CPU <6>

SM_RCOMP2 AU61 K60 XDP_OBS6_R T56 @ PAD
200_0402_1% 2 1 RC18 SM_RCOMP0 DDR3_DRAMRST# AV15 SM_RCOMP2 BPM#6 J61 XDP_OBS7_R T57 @ PAD
SM_DRAMRST BPM#7 1
DDR_PG_CNTL AV61 ESD@
120_0402_1% 2 1 RC19 SM_RCOMP1 SM_PG_CNTL1 CC99
0.1U_0402_16V7K
100_0402_1% 2 1 RC20 SM_RCOMP2 2 OF 19 2
SA011306191 SI : pop CC99
+1.35V_VDDQ
+1.35V_VDDQ
1
RC308
470_0402_5%
UC10
5 1
2
DDR3_DRAMRST# VCC NC
DDR3_DRAMRST# <15,16>
1 2 DDR_PG_CNTL
4 A
<15,49> SM_PG_CTRL Y
ESD@ CC88 3
GND
0.1U_0402_16V7K
2 74AUP1G07GW_TSSOP5
SI : pop CC88 SA00004BV00
B B
A A

DDI,MSIC,XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C
LA-8661P
LA-C701P 0.1

5 4 3 2 1
5 4 3 2 1
<17> +V_SM_VREF_CNT +V_SM_VREF_CNT

<15> DDR_A_D[0..63] <16> DDR_B_D[0..63]
<17> +V_DDR_REFA_R +V_DDR_REFA_R
BDW_ULT_DDR3L(Interleaved) <17> +V_DDR_REFB_R +V_DDR_REFB_R

UCPU1D
UCPU1C BDW_ULT_DDR3L(Interleaved) <DDR3L>

<DDR3L>
DDR_B_D0 AP58 AM38
DDR_A_D0 AH63 AU37 DDR_B_D1 AR58 SB_DQ0 SB_CK#0 AN38 M_CLK_DDR#2 <16>
D
DDR_A_D1 AH62 SA_DQ0 SA_CLK#0 AV37 M_CLK_DDR#0 <15> DDR_B_D2 AM57 SB_DQ1 SB_CK0 AK38 M_CLK_DDR2 <16> D
DDR_A_D2 AK63 SA_DQ1 SA_CLK0 AW36 M_CLK_DDR0 <15> DDR_B_D3 AK57 SB_DQ2 SB_CK#1 AL38 M_CLK_DDR#3 <16>
DDR_A_D3 AK62 SA_DQ2 SA_CLK#1 AY36 M_CLK_DDR#1 <15> DDR_B_D4 AL58 SB_DQ3 SB_CK1 M_CLK_DDR3 <16>
DDR_A_D4 AH61 SA_DQ3 SA_CLK1 M_CLK_DDR1 <15> DDR_B_D5 AK58 SB_DQ4 AY49
DDR_A_D5 AH60 SA_DQ4 AU43 DDR_B_D6 AR57 SB_DQ5 SB_CKE0 AU50 DDR_CKE0_DIMMB <16>
DDR_A_D6 AK61 SA_DQ5 SA_CKE0 AW43 DDR_CKE0_DIMMA <15> DDR_B_D7 AN57 SB_DQ6 SB_CKE1 AW49 DDR_CKE1_DIMMB <16>
DDR_A_D7 AK60 SA_DQ6 SA_CKE1 AY42 DDR_CKE1_DIMMA <15> DDR_B_D8 AP55 SB_DQ7 SB_CKE2 AV50
DDR_A_D8 AM63 SA_DQ7 SA_CKE2 AY43 DDR_B_D9 AR55 SB_DQ8 SB_CKE3
DDR_A_D9 AM62 SA_DQ8 SA_CKE3 DDR_B_D10 AM54 SB_DQ9 AM32
DDR_A_D10 AP63 SA_DQ9 AP33 DDR_B_D11 AK54 SB_DQ10 SB_CS#0 AK32 DDR_CS0_DIMMB# <16>
DDR_A_D11 AP62 SA_DQ10 SA_CS#0 AR32 DDR_CS0_DIMMA# <15> DDR_B_D12 AL55 SB_DQ11 SB_CS#1 DDR_CS1_DIMMB# <16>
DDR_A_D12 AM61 SA_DQ11 SA_CS#1 DDR_CS1_DIMMA# <15> DDR_B_D13 AK55 SB_DQ12 AL32
DDR_A_D13 AM60 SA_DQ12 AP32 DDR_B_D14 AR54 SB_DQ13 SB_ODT0
DDR_A_D14 AP61 SA_DQ13 SA_ODT0 DDR_B_D15 AN54 SB_DQ14 AM35
DDR_A_D15 AP60 SA_DQ14 AY34 DDR_B_D16 AK40 SB_DQ15 SB_RAS AK35 DDR_B_RAS# <16>
DDR_A_D16 AY58 SA_DQ15 SA_RAS AW34 DDR_A_RAS# <15> DDR_B_D17 AK42 SB_DQ16 SB_WE AM33 DDR_B_WE# <16>
DDR_A_D17 AW58 SA_DQ16 SA_WE AU34 DDR_A_WE# <15> DDR_B_D18 AM43 SB_DQ17 SB_CAS DDR_B_CAS# <16>
DDR_A_D18 AY56 SA_DQ17 SA_CAS DDR_A_CAS# <15> DDR_B_D19 AM45 SB_DQ18 AL35
DDR_A_D19 AW56 SA_DQ18 AU35 DDR_B_D20 AK45 SB_DQ19 SB_BA0 AM36 DDR_B_BS0 <16>
DDR_A_D20 AV58 SA_DQ19 SA_BA0 AV35 DDR_A_BS0 <15> DDR_B_D21 AK43 SB_DQ20 SB_BA1 AU49 DDR_B_BS1 <16>
DDR_A_D21 AU58 SA_DQ20 SA_BA1 AY41 DDR_A_BS1 <15> DDR_B_D22 AM40 SB_DQ21 SB_BA2 DDR_B_BS2 <16>
DDR_A_D22 AV56 SA_DQ21 SA_BA2 DDR_A_BS2 <15> DDR_B_D23 AM42 SB_DQ22 AP40 DDR_B_MA0 DDR_B_MA[0..15] <16>
DDR_A_D23 AU56 SA_DQ22 AU36 DDR_A_MA0 DDR_A_MA[0..15] <15> DDR_B_D24 AM46 SB_DQ23 SB_MA0 AR40 DDR_B_MA1
DDR_A_D24 AY54 SA_DQ23 SA_MA0 AY37 DDR_A_MA1 DDR_B_D25 AK46 SB_DQ24 SB_MA1 AP42 DDR_B_MA2
DDR_A_D25 AW54 SA_DQ24 SA_MA1 AR38 DDR_A_MA2 DDR_B_D26 AM49 SB_DQ25 SB_MA2 AR42 DDR_B_MA3
DDR_A_D26 AY52 SA_DQ25 SA_MA2 AP36 DDR_A_MA3 DDR_B_D27 AK49 SB_DQ26 SB_MA3 AR45 DDR_B_MA4
DDR_A_D27 AW52 SA_DQ26 SA_MA3 AU39 DDR_A_MA4 DDR_B_D28 AM48 SB_DQ27 SB_MA4 AP45 DDR_B_MA5
C DDR_A_D28 AV54 SA_DQ27 SA_MA4 AR36 DDR_A_MA5 DDR_B_D29 AK48 SB_DQ28 SB_MA5 AW46 DDR_B_MA6 C
DDR_A_D29 AU54 SA_DQ28 SA_MA5 AV40 DDR_A_MA6 DDR_B_D30 AM51 SB_DQ29 SB_MA6 AY46 DDR_B_MA7
DDR_A_D30 AV52 SA_DQ29 SA_MA6 AW39 DDR_A_MA7 DDR_B_D31 AK51 SB_DQ30 SB_MA7 AY47 DDR_B_MA8
DDR_A_D31 AU52 SA_DQ30 DDR CHANNEL A SA_MA7 AY39 DDR_A_MA8 DDR_B_D32 AM29 SB_DQ31 DDR CHANNEL B SB_MA8 AU46 DDR_B_MA9
DDR_A_D32 AY31 SA_DQ31 SA_MA8 AU40 DDR_A_MA9 DDR_B_D33 AK29 SB_DQ32 SB_MA9 AK36 DDR_B_MA10
DDR_A_D33 AW31 SA_DQ32 SA_MA9 AP35 DDR_A_MA10 DDR_B_D34 AL28 SB_DQ33 SB_MA10 AV47 DDR_B_MA11
DDR_A_D34 AY29 SA_DQ33 SA_MA10 AW41 DDR_A_MA11 DDR_B_D35 AK28 SB_DQ34 SB_MA11 AU47 DDR_B_MA12
DDR_A_D35 AW29 SA_DQ34 SA_MA11 AU41 DDR_A_MA12 DDR_B_D36 AR29 SB_DQ35 SB_MA12 AK33 DDR_B_MA13
DDR_A_D36 AV31 SA_DQ35 SA_MA12 AR35 DDR_A_MA13 DDR_B_D37 AN29 SB_DQ36 SB_MA13 AR46 DDR_B_MA14
DDR_A_D37 AU31 SA_DQ36 SA_MA13 AV42 DDR_A_MA14 DDR_B_D38 AR28 SB_DQ37 SB_MA14 AP46 DDR_B_MA15
DDR_A_D38 AV29 SA_DQ37 SA_MA14 AU42 DDR_A_MA15 DDR_B_D39 AP28 SB_DQ38 SB_MA15
DDR_A_D39 AU29 SA_DQ38 SA_MA15 DDR_B_D40 AN26 SB_DQ39 AM58 DDR_B_DQS#0 DDR_B_DQS#[0..7] <16>
DDR_A_D40 AY27 SA_DQ39 AJ61 DDR_A_DQS#0 DDR_A_DQS#[0..7] <15> DDR_B_D41 AR26 SB_DQ40 SB_DQSN0 AM55 DDR_B_DQS#1
DDR_A_D41 AW27 SA_DQ40 SA_DQSN0 AN62 DDR_A_DQS#1 DDR_B_D42 AR25 SB_DQ41 SB_DQSN1 AL43 DDR_B_DQS#2
DDR_A_D42 AY25 SA_DQ41 SA_DQSN1 AV57 DDR_A_DQS#2 DDR_B_D43 AP25 SB_DQ42 SB_DQSN2 AL48 DDR_B_DQS#3
DDR_A_D43 AW25 SA_DQ42 SA_DQSN2 AV53 DDR_A_DQS#3 DDR_B_D44 AK26 SB_DQ43 SB_DQSN3 AN28 DDR_B_DQS#4
DDR_A_D44 AV27 SA_DQ43 SA_DQSN3 AW30DDR_A_DQS#4 DDR_B_D45 AM26 SB_DQ44 SB_DQSN4 AN25 DDR_B_DQS#5
DDR_A_D45 AU27 SA_DQ44 SA_DQSN4 AV26 DDR_A_DQS#5 DDR_B_D46 AK25 SB_DQ45 SB_DQSN5 AN21 DDR_B_DQS#6
DDR_A_D46 AV25 SA_DQ45 SA_DQSN5 AW22DDR_A_DQS#6 DDR_B_D47 AL25 SB_DQ46 SB_DQSN6 AN18 DDR_B_DQS#7
DDR_A_D47 AU25 SA_DQ46 SA_DQSN6 AV18 DDR_A_DQS#7 DDR_B_D48 AR21 SB_DQ47 SB_DQSN7
DDR_A_D48 AY23 SA_DQ47 SA_DQSN7 DDR_B_D49 AR22 SB_DQ48 AN58 DDR_B_DQS0 DDR_B_DQS[0..7] <16>
DDR_A_D49 AW23 SA_DQ48 AJ62 DDR_A_DQS0 DDR_A_DQS[0..7] <15> DDR_B_D50 AL21 SB_DQ49 SB_DQSP0 AN55 DDR_B_DQS1
DDR_A_D50 AY21 SA_DQ49 SA_DQSP0 AN61 DDR_A_DQS1 DDR_B_D51 AM22 SB_DQ50 SB_DQSP1 AL42 DDR_B_DQS2
DDR_A_D51 AW21 SA_DQ50 SA_DQSP1 AW57DDR_A_DQS2 DDR_B_D52 AN22 SB_DQ51 SB_DQSP2 AL49 DDR_B_DQS3
DDR_A_D52 AV23 SA_DQ51 SA_DQSP2 AW53DDR_A_DQS3 DDR_B_D53 AP21 SB_DQ52 SB_DQSP3 AM28 DDR_B_DQS4
DDR_A_D53 AU23 SA_DQ52 SA_DQSP3 AV30 DDR_A_DQS4 DDR_B_D54 AK21 SB_DQ53 SB_DQSP4 AM25 DDR_B_DQS5
DDR_A_D54 AV21 SA_DQ53 SA_DQSP4 AW26DDR_A_DQS5 DDR_B_D55 AK22 SB_DQ54 SB_DQSP5 AM21 DDR_B_DQS6
DDR_A_D55 AU21 SA_DQ54 SA_DQSP5 AV22 DDR_A_DQS6 DDR_B_D56 AN20 SB_DQ55 SB_DQSP6 AM18 DDR_B_DQS7
B
DDR_A_D56 AY19 SA_DQ55 SA_DQSP6 AW18DDR_A_DQS7 DDR_B_D57 AR20 SB_DQ56 SB_DQSP7 B
DDR_A_D57 AW19 SA_DQ56 SA_DQSP7 DDR_B_D58 AK18 SB_DQ57

DDR_A_D58 AY17 SA_DQ57 AP49 DDR_B_D59 AL18 SB_DQ58
SA_DQ58 SM_VREF_CA +V_SM_VREF_CNT SB_DQ59
DDR_A_D59 AW17 AR51 DDR_B_D60 AK20
SA_DQ59 SM_VREF_DQ0 +V_DDR_REFA_R SB_DQ60
DDR_A_D60 AV19 AP51 DDR_B_D61 AM20
SA_DQ60 SM_VREF_DQ1 +V_DDR_REFB_R SB_DQ61
DDR_A_D61 AU19 DDR_B_D62 AR18
DDR_A_D62 AV17 SA_DQ61 DDR_B_D63 AP18 SB_DQ62
DDR_A_D63 AU17 SA_DQ62 SB_DQ63
SA_DQ63
4 OF 19
3 OF 19
Interleaved Memory
A A

2011/06/29 2011/06/29 Title
Issued Date Deciphered Date DDRIII
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.1
LA-C701P
5 4 3 2 1
5 4 3 2 1
<12,15,16,18,19,20,21,22,23,24,25,27,31,32,33,34,35,36,37,56,7,8,9> +3VS +3VS

SI：Change BOM con/ig
<12,28,8> +RTCVCC +RTCVCC
INTVRMEN RG117 UMA@ 0_0402_5%
+RTCVCC
* H：Integrated
L：Integrated
VRM enable
VRM disable
PCH_RTCX1_0_R
UMA@
1 2
PCH_RTCX1 <28> <28> +RTCBATT +RTCBATT
1 2 PCH_RTCX2
<11,4> +VCCIO_OUT +VCCIO_OUT
330K_0402_5% 1 2 RC236 PCH_INTVRMEN RC31 10M_0402_5%
<11,4,9> +1.05VS_VCCST +1.05VS_VCCST
UMA@
YC1 <10,11,12,24,36,4,7,9> +3V_PCH +3V_PCH
1 2
<12,23,37,53> +1.5VS +1.5VS
UMA@ 1 32.768KHZ Q13FC1350000500
1
CC3 CC4 UMA@ +1.05VS_VCCSATA3PLL
<12,34> +1.05VS_VCCSATA3PLL
18P_0402_50V8J
18P_0402_50V8J UCPU1E BDW_ULT_DDR3L(Interleaved)
+3VL
2 2 <25,28,32,46,47,48> +3VL
<12,19,22,24,25,26,28,29,32,37,48,50,53,56,7> +3VALW +3VALW

1 PCH_RTCX1 AW5
RTCX1
1
+RTCVCC PCH_RTCX2 AY5
CC2 JCMOS1 RC35 1 2 1M_0402_5% SM_INTRUDER# AU6 RTCX2 J5
1U_0402_6.3V6K SHORT PADS
CMOS +RTCVCC
PCH_INTVRMEN AV7 INTRUDER SATA_RN0/PERN6_L3 H5
SATA_PRX_DTX_N0 <29>
INTVRMEN SATA_RP0/PERP6_L3 SATA_PRX_DTX_P0 <29>
2
2 PCH_SRTCRST# AV6 B15
D 1 2 PCH_RTCRST# PCH_RTCRST# AU7 SRTCRST
RTC
SATA_TN0/PETN6_L3 A15
SATA_PTX_DRX_N0 <29> 2.5" HDD D
RTCRST SATA_TP0/PETP6_L3 SATA_PTX_DRX_P0 <29>
RC32 20K_0402_5%
1 2 PCH_SRTCRST# J8 SATA_PRX_DTX_N1 <29>
RC34 20K_0402_5% SATA_RN1/PERN6_L2 H8
1 SATA_RP1/PERP6_L2 SATA_PRX_DTX_P1 <29> ODD
1
A17
SATA_TN1/PETN6_L2 SATA_PTX_DRX_N1 <29>
CC5 JME1 B17
SATA_TP1/PETP6_L2 SATA_PTX_DRX_P1 <29> +3VS
1U_0402_6.3V6K SHORT PADS ME CMOS
2
2 HDA_BIT_CLK AW8 J6
HDA_SYNC AV11 HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 H6 RC217 1 2 10K_0402_5%
HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 <9> MPHY_PWREN
HDA_RST# AU8 B14
AY10 HDA_RST/I2S_MCLK AUDIO SATA SATA_TN2/PETN6_L1 C15
<23> HDA_SDIN0 HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1
AU12 ODD_PLUG# RC218 1 2 100K_0402_5%
DB phase HDA_SDOUT AU11 HDA_SDI1/I2S1_RXD F5
HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0 PCIE_PRX_DTX_N6 <31>
2014-11-14 AW10 E5 PCIE_PRX_DTX_P6 <31>
AV10 HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0 C17 PCIE_PTX_DRX_N6 CC16 1 2 0.1U_0402_16V7K
Add ME_Flash_EN AY8 HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 D17 PCIE_PTX_DRX_P6 CC17 1 2 0.1U_0402_16V7K
PCIE_PTX_C_DRX_N6 <31> WLAN
I2S1_SCLK SATA_TP3/PETP6_L0 PCIE_PTX_C_DRX_P6 <31>
RF solution HDA_SDOUT: V1
ME Flash Descriptor Security Override SATA0GP/GPIO34 U1 ODD_PLUG#
Intel ME update Low : Disabled(Default) SATA1GP/GPIO35 V6 PCH_GPIO36 T159 PAD
ODD_PLUG# <29>
High : Enabled SATA2GP/GPIO36 AC1 mSATA_DET#
2014-10-01: SATA3GP/GPIO37 mSATA_DET# <7>
PCH_JTAG_RST# AU62
CM28 Follow skyfall/pixar Direct shorted PCH_TRST
@ PCH_JTAG_TCK AE62 A12 +1.05VS_VCCSATA3PLL
1 2 HDA_BITCLK_AUDIO PCH_JTAG_TDI AD61 PCH_TCK SATA_IREF L11 RC39
RC310 0_0402_5% PCH_JTAG_TDO AE61 PCH_TDI RSVD K10 3K_0402_1%
1 @ 2 HDA_SDOUT PCH_JTAG_TMS AD62 PCH_TDO RSVD C12 SATA_COMP 1 2
22P_0402_50V8J <25> ME_Flash_EN
PAD T156 AL11
AC4
PCH_TMS
RSVD
JTAG
SATA_RCOMP
SATALED
U3 SATA_LED# SATA_LED# <32,9>
L Layout notes
DG V0.9 SATA_COMP
CM29 RSVD
@ XDP_TCK_JTAGX AE63
1 2 HDA_RST_AUDIO# PAD T157 AV2 JTAGX Width=12mil
RSVD Max length=500mil
2
G
22P_0402_50V8J RC356
+1.5VS
1 2 1 3 HDA_SDOUT
5 OF 19
S
1K_0402_5% BDW-ULT-DDR3L-IL_BGA1168
HDA_SYNC_R RC353 1 short@ 2 0_0402_5% HDA_SYNC
Q32
2N7002_SOT23-3
PV:RC353 change to 0-ohm shortpad
Layout notes
RC367 place near CPU
EMI@ 2 RC367 1 HDA_BIT_CLK
Add RC367 EMI@ to isolate +3VS
<23> HDA_BITCLK_AUDIO RC240
Audio Clock by EMI request @ @ CC86
33_0402_5% EC_+1.05VS_PG 2 1 1 2
RP1
1 8 @ UC5 10K_0402_5% .1U_0402_16V7K JRTC1 RTC BAT conn +RTCBATT
C 2 7 HDA_RST# 2 16 C
<23> HDA_RST_AUDIO# 1OE VCC +RTCBATT_R +RTCBATT
<23> HDA_SYNC_AUDIO
3 6 HDA_SYNC_R
<23> HDA_SDOUT_AUDIO
4 5 HDA_SDOUT XDP_TDO_CPU 3 4 XDP_TDO +RTCVCC
33_0804_8P4R_5% 1A 1B 1K_0402_5%
5 2 1
15mils
2OE RC33 - +
DC1 15mils 15mils
XDP_TDI_CPU 6 7 XDP_TDI_SWITCH 15mils 2 2 1
2A 2B 1
12 1 3 +3VL
3OE CC6
+3V_PCH +3V_PCH 11 10 XDP_TMS 1U_0402_6.3V6K BAV70W 3P C/C_SOT-323 LOTES_AAA-BAT-054-K01
<4> XDP_TMS_CPU 3A 3B
15 2
4OE CONN@
1
RC41 @ RC46 <4> XDP_TRST#_CPU XDP_TRST#_CPU 14 13 XDP_TRST#

4A 4B
210_0402_5% 210_0402_5%
1
@ NC
R8
2
PCH_JTAG_TDI XDP_TCK_JTAGX 8 9
R4 GND NC
1
RC301 @ RC302 74CBTLV3126DS_SSOP16

100_0402_1% 100_0402_1%
@
2
+1.05VS_VCCST
1
+3V_PCH +3V_PCH +3V_PCH
R511 DB phase :
U16 @ 10K_0402_5%
For ESD request
1
1 5
NC VCC
2
RC283 @ RC45 @
210_0402_5% 210_0402_5% 2 20141117
<25> EC_+1.05VS_PG A 4 +1.05VS_PG <11,4>
3 Y
R3d GND
2
PCH_JTAG_TDO PCH_JTAG_TMS
R5 74AUP1G07GW_TSSOP5 <CPU,XDP,XDP Switch> +VCCIO_OUT +VCCIO_OUT
1
RC304 @ RC303 @ +VCCIO_OUT JXDP1

100_0402_1% 100_0402_1% 1 2
RG122 XDP_PREQ# 3 GND0 GND1 4 CFG17
<4> XDP_PREQ# OBSFN_A0 OBSFN_C0 CFG17 <14>
0.1U_0402_16V4Z
2.2U_0402_6.3V6M
1 short@ 2 0_0402_5% <4> XDP_PRDY# XDP_PRDY# 5 6 CFG16
OBSFN_A1 OBSFN_C1 CFG16 <14>
2
1 1 7 8
CFG0 9 GND2 GND3 10 CFG8
<14> CFG0 OBSDATA_A0 OBSDATA_C0 CFG8 <14>
CC127
CC128
CFG1 11 12 CFG9
PV:RG122 change to 0-ohm shortpad <14> CFG1
13 OBSDATA_A1 OBSDATA_C1 14 CFG9 <14>
B 2 2 CFG2 15 GND4 GND5 16 CFG10 B
S1 <14> CFG2
<14> CFG3
CFG3 17 OBSDATA_A2
OBSDATA_A3
OBSDATA_C2
OBSDATA_C3
18 CFG11
CFG10 <14>
CFG11 <14>
19 20
XDP_TRST# RC37 1 @ 2 0_0201_5% XDP_TRST#_CPU XDP_OBS0_R 21 GND6 GND7 22 CFG19
<CPU site> <4> XDP_OBS0_R
XDP_OBS1_R 23 OBSFN_B0 OBSFN_D0 24 CFG18
CFG19 <14>
<XDP> PCH_JTAG_RST#
Contact ok <4> XDP_OBS1_R
25 OBSFN_B1 OBSFN_D1 26 CFG18 <14>
<PCH site> Place near JXDP1 CFG4 27 GND8 GND9 28 CFG12
<14> CFG4 OBSDATA_B0 OBSDATA_D0 CFG12 <14>
CFG5 29 30 CFG13
S2 R6 <14> CFG5
31 OBSDATA_B1
GND10
OBSDATA_D1
GND11
32 CFG13 <14>
<PCH site> PCH_JTAG_TMS RC196 1 @ 2 0_0201_5% XDP_TMS_CPU <CPU site> CFG6 33 34 CFG14
Contact ok PCH_JTAG_TCK 51_0402_5% 1 @ 2 RC38 CFG7 35 36 CFG15
XDP_TMS 37 38
<XDP> H_CPUPWRGD_R
RC17 need to close to JCPU1
RC372 1 2 1K_0402_1% H_CPUPWRGD_XDP 39 GND12 GND13 40
<4> H_CPUPWRGD_R PWRGOOD/HOOK0 ITPCLK/HOOK4 CLK_CPU_ITP <7>
41 42
<25,8> PBTN_OUT# HOOK1 ITPCLK#/HOOK5 CLK_CPU_ITP# <7>
43 44
S3 45 VCC_OBS_AB VCC_OBS_CD 46 XDP_RST#_R RC374 2 1K_0402_1%
1
XDP_TDI_SWITCH RC199 1 @ 2 0_0201_5% XDP_TDI_CPU
XDP_TDI_CPU <4> <CPU> R9 ESD@
<11> CPU_PWR_DEBUG
<25,8> SYS_PWROK
47 HOOK2
HOOK3
RESET#/HOOK6
DBR#/HOOK7
48
PLT_RST# <22,25,27,31,35,8>
XDP_DBRESET# <7,8>
D23 49 50
XDP_TRST#_CPU RC16 2 @ 1 51_0402_1% 1 2 H_CPUPWRGD_R 51 GND14 GND15 52 XDP_TDO
J3S <15,16,18,21,7> PCH_SMBDATA
<15,16,18,21,7> PCH_SMBCLK
53 SDA
SCL
TD0
TRST#
54 XDP_TRST#
<PCH site> PCH_JTAG_TDO RC307 1 @ 2 0_0201_5% XDP_TDI_SWITCH <XDP> CK0402101V05_0402-2 XDP_TCK1 55 56 XDP_TDI
SCV00001K00 XDP_TCK 57 TCK1 TDI 58 XDP_TMS
59 TCK0 TMS 60 2 1 CFG3
J4d DB phase : SI : pop D23
GND16 GND17 RC373 1K_0402_1%
<XDP> XDP_TDI RC200 1 2 0_0201_5% XDP_TDI_SWITCH SAMTE_BSH-030-01-L-D-A CONN@
short@ For ESD request
20141117
PCH_JTAG_TDI RC195 1 2 0_0201_5% XDP_TDI +1.05VS_VCCST
<PCH site> short@
R1d
J3D XDP_TDO_CPU RC10 2 1 51_0402_1%
XDP_TDO RC194 1 2 0_0201_5% PCH_JTAG_TDO <PCH site>
<XDP> short@
S4 +1.05VS_VCCST
RC198 1 @ 2 0_0201_5% XDP_TDO_CPU
XDP_TDO_CPU <4>
R7 Topolog Description Be st Use for
Resistors Resistors
@ Stuffed ufStuffed
XDP_TDO RC14 2 1 51_0402_1%
XDP_TCK:XDP contact with CPU No 0ohm(RS5)
Default Setting: Dual In this topology, the - Run control oper. R1d,R2,R3d, J1s, J2s,
DB phase :
TCK S can Chains CPU JTAG chain will be - ME/Sx debug R4,R5,J1d J3s
<PCH site>
PCH_JTAG_TCK
RC201
1 short@ 2 0_0201_5% XDP_TCK1 For XDP
20141117
R2 (also known as controlled by TCK0 and J2d,J3d* R6,R7,R8,R9
RC15 2 1 51_0402_1%
XDP_TCK
"Shared JTAG" in TCK1 will control J4d and Rs5*
A other docum ent) the PCH JTAG chain. A
J1S
PCH_JTAG_TCK RC197 1 @ 2 0_0201_5% XDP_TCK XDP_TCK <4> <CPU and XDP>
J2D In th is topolog y, PCH -B oundary Scan/ J1s,J2s,J3s** R1d,r3d,J1d,J2d
<PCH site> XDP_TCK_JTAGX RC193 1 2 0_0201_5%
Single TCK scan chain TDI- TDO and CPU TDI-TDO Manufacturing est R2,R4,R5,R5s** J3d**,J4d,
short@ (also known as "Com m on will be chained to form
R6,R7,R8,R9
JTAG" in other docum one JTAG scan chain
J2S <XDP> ent)
<PCH site> XDP_TCK_JTAGX RC306 1 @ 2 0_0201_5% XDP_TDO controlled by TCK0
Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2011/06/29 Deciphered Date 2011/06/29
RTC,SATA,HDA,JTAG
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-C701P
5 4 3 2 1
5 4 3 2 1
<12> +1.05VS_AXCK_LCPLL +1.05VS_AXCK_LCPLL

PV phase : UCPU1F BDW_ULT_DDR3L(Interleaved)
<12,15,16,18,19,20,21,22,23,24,25,27,31,32,33,34,35,36,37,56,6,8,9> +3VS +3VS
Add pull-up at PCIECLKREQ1#
20150125 <10,11,12,24,36,4,6,9> +3V_PCH +3V_PCH
C43 A25
<22> CLK_PCIE_LAN# CLKOUT_PCIE_N0 XTAL24_IN CPU_XTAL24_IN <28>
PCIE LAN C42 B25 CPU_XTAL24_OUT
<22> CLK_PCIE_LAN CLKOUT_PCIE_P0 XTAL24_OUT
PCIECLKREQ0# U2
PCIECLKRQ0/GPIO18 K21 RC52
B41 RSVD M21 3K_0402_1%
CLKOUT_PCIE_N1 RSVD
A41
CLKOUT_PCIE_P1 DIFFCLK_BIASREF
C26 PCH_CLK_BIASREF 1 2 +1.05VS_AXCK_LCPLL SI：Change BOM con/ig
PCIECLKREQ1# Y5
PCIECLKRQ1/GPIO19 C35 TESTLOW1 4 5 RPH22 RG120 0_0402_5%
C41 CLOCK TESTLOW_C35 C34 TESTLOW2 3 6 CPU_XTAL24_IN 1 2 CPU_XTAL24_IN_R
D <31> CLK_PCIE_WLAN# CLKOUT_PCIE_N2 TESTLOW_C34 D
WLAN B42 AK8 TESTLOW3 2 7 UMA@
<31> CLK_PCIE_WLAN AD1 CLKOUT_PCIE_P2 SIGNALS TESTLOW_AK8 AL8 1 8
<22> LAN_CLKREQ# TESTLOW4
PCIECLKRQ2/GPIO20 TESTLOW_AL8 10K_0804_8P4R_5% UMA@
B38 AN15 CLK_PCI0 EMI@ RC61 1 2 22_0402_5% CLK_PCI_LPC CPU_XTAL24_OUT 2 1
<35> CLK_PCIE_GPU# CLKOUT_PCIE_N3 CLKOUT_LPC_0 CLK_PCI_LPC <25>
GPU C37 AP15 CLK_PCI1 EMI@ RC62 1 2 22_0402_5% CLK_PCI_TPM <EC> 1M_0402_5% RC48
<35> CLK_PCIE_GPU CLKOUT_PCIE_P3 CLKOUT_LPC_1 CLK_PCI_TPM <27>
PCIECLKREQ3# N1
PCIECLKRQ3/GPIO21 B35 CLK_CPU_ITP#
CLKOUT_ITPXDP CLK_CPU_ITP# <6>
A39 A35 CLK_CPU_ITP <XDP CLK > 3 1
B39 CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P CLK_CPU_ITP <6> 3 1
U5 CLKOUT_PCIE_P4 UMA@ GNDGND
<36> GPU_CLKREQ# PCIECLKRQ4/GPIO22 1 1 UMA@
CC9 CC10
B37 4 UMA@ 2 18P_0402_50V8J
SI phase : A37 CLKOUT_PCIE_N5 18P_0402_50V8J YC2
Modify CLK request channel <31> WLAN_CLKREQ#
T2 CLKOUT_PCIE_P5 2 2
24MHZ 12PF 5YEA24000122IF40Q3
+3VS PCIECLKRQ5/GPIO23
20141214
6 OF 19
RC125
2 @ 1 10K_0402_5% GPU_CLKREQ# UCPU1G BDW_ULT_DDR3L(Interleaved)
RC376 LPC_AD0 AU14 AN2 SMBALERT# RF solution

<25,27> LPC_AD0 LAD0 SMBALERT/GPIO11 SMBALERT# <9>
1 2 LAN_CLKREQ# LPC_AD1 AW12 AP2 SMBCLK
<25,27> LPC_AD1 AY12 LAD1 SMBCLK AH1
10K_0402_5% LPC_AD2 LPC SMBDATA
<25,27> LPC_AD2 LAD2 SMBUS SMBDATA
LPC_AD3 AW11 AL2 USB_CR_PWREN USB_CR_PWREN <8>
<25,27> LPC_AD3 LAD3 SML0ALERT/GPIO60
RPH11 LPC_FRAME# AV12 AN1 SML0CLK @RF@
4 5 <25,27> LPC_FRAME# LFRAME SML0CLK AK1 CM30
PCIECLKREQ0# SML0DATA
3 6 SML0DATA AU4 SML1ALERT# 1 2 CLK_PCI_LPC
2 7 XDP_DBRESET# <6,8> SML1ALERT/PCHHOT/GPIO73 AU3 SML1ALERT# <9>
SML1CLK Layout notes
EC_KBRST# <25,9> SML1CLK/GPIO75
1 8 AH3 SML1DATA
MSATA_DET# <6>
PCH_SPI_CLK
PCH_SPI_CS0#
AA3
Y7 SPI_CLK
SML1DATA/GPIO74
AF2
L avoid stub trace too long 22P_0402_50V8J
10K_0804_8P4R_5% @RF@
SPI_CS0 CL_CLK CM31
Y4 AD2
AC2 SPI_CS1 SPI C-LINK
CL_DATA AF4 1 2 CLK_PCI_TPM
+3VS PCH_SPI_SI AA2 SPI_CS2 CL_RST
RPH12 PCH_SPI_SO AA4 SPI_MOSI
4 5 PCH_GPIO33 PCH_SPI_SIO2 Y6 SPI_MISO 22P_0402_50V8J
PCH_GPIO33 <9> SPI_IO2
C 3 6 PCIECLKREQ3# PCH_SPI_SIO3 AF1 @RF@ C
2 7 SPI_IO3 CM33
PCIECLKREQ1#
1 8 WLAN_CLKREQ# 1 2 PCH_SPI_CLK_R
10K_0804_8P4R_5%
7 OF 19 22P_0402_50V8J
+3V_PCH
Layout notes
L RC368 place near CPU EON SA000046400 S IC FL 64M EN25Q64-104HIP SOP 8P
RC369 place near EC SPI ROM (8MByte ) MXIC
WINBOND
SA00006N100
SA000039A30
S
S
IC
IC
FL
FL
64M
64M
MX25L6473EM2I-10G SOP 8P
W25Q64FVSSIQ SOIC 8P SPI ROM
RC56 place near SPI ROM Micron SA00005L100 S IC FL 64M N25Q064A13ESEC0F SO8W 8P
PCH_SPI_CLK RC368 1 EMI@ 2 0_0402_5%PCH_SPI_CLK_R SML0CLK 1K_0402_5% 1 2 RC72
SML0DATA 1K_0402_5% 1 2 RC73
1 EMI@ 2 EC_SPI_CLK_R RC56 1 2 0_0402_5% PCH_SPI_CLK_R

<25> EC_SPI_CLK +3V_PCH
RC369 0_0402_5% SMBCLK RP2 1 8 2.2K_0804_8P4R_5%
SI : add net name EC_SPI_CLK_R. +3V_PCH SMBDATA 2 7
SML1CLK 3 6
0.1U_0402_16V4Z
1 SML1DATA 4 5
1 2 PCH_SPI_WP# C4965
RC85 3.3K_0402_5%
2
RC84 1 2 PCH_SPI_HOLD#
RPH19 3.3K_0402_5%
PCH_SPI_CS0# 8 1 PCH_SPI_CS0#_R
PCH_SPI_SO 7 2 PCH_SPI_SO_R
PCH_SPI_SI 6 3 PCH_SPI_SI_R +3V_PCH +3V_PCH +3VS +3VS
PCH_SPI_HOLD# 5 4 PCH_SPI_SIO3
UC2
2
B B
15_0804_8P4R_5% PCH_SPI_CS0#_R 1 8
@ RC80 PCH_SPI_SO_R 2 /CS VCC 7 PCH_SPI_HOLD#
DO(IO1) /HOLD(IO3)
2
3.3K_0402_5% PCH_SPI_WP# 3 6 PCH_SPI_CLK_R
RPH20 4 /WP(IO2) CLK 5 PCH_SPI_SI_R RC78 RC79
8 1 PCH_SPI_SI_R GND DI(IO0) 10K_0402_5%
<25> EC_SPI_SI 10K_0402_5%
1
7 2 PCH_SPI_SO_R W25Q64FVSSIQ_SO8
<25> EC_SPI_SO
2
6 3 PCH_SPI_CS0#_R PCH_SPI_CS0#_R QC2A 2N7002DWH_SOT363-6
<25> EC_SPI_CS0#
1
PCH_SPI_SIO2 5 4 PCH_SPI_WP#
SMBCLK 6 1
PCH_SMBCLK <15,16,18,21,6>
15_0804_8P4R_5%
5
2N7002DWH_SOT363-6
QC2B
SMBDATA 3 4
PCH_SMBDATA <15,16,18,21,6>
+3V_PCH +3VALW +3VS
+3VS CPU THERMAL SENSOR
2
SI : add CPU thermal sensor 12/23 RC81 RC82
2
1 10K_0402_5% 10K_0402_5% 2N7002DWH_SOT363-6
0.1U_0402_16V4Z
TP@ TP@
2
CC120 TP@ SML1CLK 6 1

EC_SMB_CK2 <18,21,25,36>
5
2 SMBCLK 1 6 QC6A
TP_SMBCLK <26>
UC3 QC7A
1 8 EC_SMB_CK2 2N7002DWH_SOT363-6 SML1DATA 3 4
VDD SCL EC_SMB_DA2 <18,21,25,36>
5
A H_THERMDA 2 7 EC_SMB_DA2 2N7002DWH_SOT363-6 2N7002DWH_SOT363-6 A

CC119 D+ SDA QC7B QC6B
1 2 H_THERMDC 3 6 ALERT_L 1 2 +3VS SMBDATA 4 3
D- ALERT# TP_SMBDATA <26>
2200P_0402_50V7K RC97 33K_0402_5%
CPU_THERM# 4 5 TP@
T_CRIT# GND
1 2
+3VS
RC96 33K_0402_5% NCT7718W_MSOP8
Address: 1001100xb NCT7718W

(x is R/W bit) Security Classification Compal Secret Data Compal Electronics, Inc.
CLK,SPI,SMB,LPC
C 0.1
LA-C701P
5 4 3 2 1
5 4 3 2 1
<10,11,12,24,36,4,6,7,9> +3V_PCH +3V_PCH
<12,15,16,18,19,20,21,22,23,24,25,27,31,32,33,34,35,36,37,56,6,7,9> +3VS +3VS

D24 @ESD@ +3V_DSW_P
<12,9> +3V_DSW_P
1 2 SUSACK#
CK0402101V05_0402-2
DB phase :
For ESD request
D25 ESD@
20141117
1 2 PM_PWROK_R
CK0402101V05_0402-2 T83 RC268 1 short@ 2 0_0201_5% PM_SLP_S0#_R

SCV00001K00 SI: pop D25 PAD
D D
RC269 1 @ 2 0_0201_5% PM_SLP_S3#
+RTCVCC
UCPU1H BDW_ULT_DDR3L(Interleaved)
DSWODVREN - On Die DSW VR Enable
DSWODVREN RC254 2 1 330K_0402_5%
<9> SUSWARN#_R RC91 1 @ 2 0_0201_5% SYSTEM POWER MANAGEMENT * H:Enable
L:Disable DSWODVREN RC255 2 @ 1 330K_0402_5%
Non Deep S3 RC91-->SMT short@ RC93 1 2 0_0201_5% SUSACK#_R AK2 AW7 DSWODVREN RC371 1 short@ 2 0_0201_5% AOAC_PME#
<25> SUSACK# SUSACK DSWVRMEN
Deep S3 RC93-->SMT <6,7> XDP_DBRESET# short@ RC94 1 2 0_0201_5% SYS_RESET# AC3 AV5 PCH_DPWROK_R
SYS_PWROK AG2 SYS_RESET DPWROK AJ5
<25,6> SYS_PWROK SYS_PWROK WAKE PCH_PCIE_WAKE# <31>
short@ RC99 1 2 0_0201_5% PM_PWROK_R AY7
short@ RC100 1 2 0_0201_5% APWROK_R AB5 PCH_PWROK
<25> PCH_PWROK APWROK
PLT_RST#_PCH AG7 V5
PLTRST CLKRUN/GPIO32 PM_CLKRUN# <25>
AG4 SUS_STAT# T147 @ PAD
SUS_STAT/GPIO61 AE6
SUSCLK/GPIO62 SUSCLK <31> +3VS
AP5
SLP_S5/GPIO63 PM_SLP_S5# <25>
<25> PCH_RSMRST# AW6 T142 @
short@ RC104 1 2 0_0201_5% SUSWARN#_R AV4 RSMRST PAD
Deep S3 <25> PCH_SUSWARN# SUSWARN/SUSPWRDNACK/GPIO30
<25,6> PBTN_OUT# short@ RC103 1 2 0_0201_5% PBTN_OUT#_R AL7 AJ6 PM_SLP_S4# <25>
1 2 DC2 ACIN_R AJ8 PWRBTN SLP_S4 AT4
<25,36,47> ACIN ACPRESENT/GPIO31 SLP_S3 PM_SLP_S3# <25>
PM_BATLOW# AN4 AL5 T145PAD @
CH751H-40PT_SOD323-2 PM_SLP_S0#_R AF3 BATLOW/GPIO72 SLP_A AP4 RC286 1 short@ 2 0_0201_5% PM_CLKRUN# RC110 2 1 8.2K_0402_5%
SLP_S0 SLP_SUS PM_SLP_SUS# <25>
PCH_SLP_WLAN# AM5 AJ7
SLP_WLAN/GPIO29 SLP_LAN
Non Deep S3 RC286-->@
Deep S3 RC286-->SMT
+3V_DSW_P
8 OF 19 T143 T144
BDW-ULT-DDR3L-IL_BGA1168 PAD PAD
@ @ PCH_PCIE_WAKE# RC98 1 2 1K_0402_5%
SUSCLK RC109 1 2 10K_0402_5%
C PCH_RSMRST# RC106 2 1 10K_0402_5% C
ESD@ C592
1 2 PCH_PWROK CH751H-40PT_SOD323-2
PCH_RSMRST# 1 2 DC3 PCH_PWROK
0.047U_0402_16V7K
CH751H-40PT_SOD323-2
DC4 2 1
SPOK <48>
+3V_DSW_P
RC112 2 1 100K_0402_5% SYS_PWROK
SYS_PWROK PCH_DPWROK_R RC316 1 short@ 2 0_0201_5% PCH_DPWROK <25>
1
C127
0.1U_0402_10V6K
@ESD@
RPH15
2 PM_BATLOW# 1 8
USB_CR_PWREN 2 7
<7> USB_CR_PWREN
3 6
PCH_SLP_WLAN# 4 5
10K_0804_8P4R_5%
ACIN_R RC101 1 2 10K_0402_5%
UCPU1I BDW_ULT_DDR3L(Interleaved)
PV:RC114,RC115,RC116,RC118,RC121,RC122
change to 0-ohm shortpad
RC114 1 short@ 2 0_0402_5% BKL_PWM_CPU_R B8 B9
<18,19> BKL_PWM_CPU 1 short@ 2 0_0402_5% A9 EDP_BKLCTL DDPB_CTRLCLK C9 PCH_DDPB_CLK <20>
RC115 ENBKL_CPU
<25> ENBKL EDP_BKLEN eDP SIDEBAND DDPB_CTRLDATA PCH_DDPB_DAT <20> <HDMI>
RC116 1 short@ 2 0_0402_5% ENVDD_CPU_R C6 D9 RC107 1 @ 2 2.2K_0402_5%
B <19> ENVDD_CPU EDP_VDDEN DDPC_CTRLCLK B
D11 RC102 1 2 2.2K_0402_5%
DDPC_CTRLDATA +3VS
1 short@ 2 0_0402_5% DGPU_PWROK_CPU U6

Displayport Port C Enable pin RC102 pull high +3VS
<36,9> DGPU_PWROK RC118
RC121 1 short@ 2 0_0402_5% DGPU_PWR_EN_CPU P4 PIRQA/GPIO77 C5
<25,37,54,9> DGPU_PWR_EN PIRQB/GPIO78 DDPB_AUXN
RC122 1 short@ 2 0_0402_5% DGPU_HOLD_RST#_CPU N4 B6
<35,9> DGPU_HOLD_RST# N2 PIRQC/GPIO79 DISPLAY DDPC_AUXN B5 DDI2_AUX_DN <21>
PCH_GPIO80
<25> AOAC_PME# 1 @ 2 AOAC_PME#_R AD4 PIRQD/GPIO80 DDPB_AUXP A6 DP TO CRT ( RTD2168)
PME PCIE DDPC_AUXP DDI2_AUX_DP <21>
RC305 0_0402_5%
U7
L1 GPIO55
PCH_MC_WAKE# L3 GPIO52 C8
PCH_MIC_DET R5 GPIO54 DDPB_HPD A8
PCH_DDPB_HPD <20> <HDMI>
1 2 100K_0402_5% PAD T154 @ L4 GPIO51 DDPC_HPD D6
DDI2_HPD <21> DP TO CRT HPD ( RTD2168)
RC120 ENVDD_CPU PCH_HP_DET
GPIO53 EDP_HPD EDP_HPD <18>
<eDP HPD>
9 OF 19
RC300
1 short@ 2 0_0402_5% PV:RC300 change to 0-ohm shortpad
+3VS
+3VS
5
@ UC9
1 PLT_RST#_PCH <CPU>
P
4 IN1
<22,25,27,31,35,6> PLT_RST# O 2
IN2
G
RPH27 4 5 PCH_MC_WAKE#
3 6 PCH_GPIO80 SN74AHC1G08DCKR_SC70-5
3
2 7 PCH_HP_DET
1 8 DEVSLP1
DEVSLP1 <9>
10K_0804_8P4R_5%
A A

PM,GPIO,DDI
C 0.1
LA-C701P
5 4 3 2 1
5 4 3 2 1
<10,11,12,24,36,4,6,7> +3V_PCH +3V_PCH <11,4,6> +1.05VS_VCCST +1.05VS_VCCST
<12,8> +3V_DSW _P +3V_DSW _P <12,15,16,18,19,20,21,22,23,24,25,27,31,32,33,34,35,36,37,56,6,7,8> +3VS +3VS

+3VS +1.05VS_VCCST
1
UCPU1J BDW_ULT_DDR3L(Interleaved)
EC_FB_CLAMP_TGL_REQ# RK11 1 2 10K_0402_5% RC242
1K_0402_5%
RC129 0_0402_5%
2
PCH_AUDIO_PW REN P1 D60 H_THERMTRIP#_C 1 short@ 2 H_THEMTRIP#
AU2 BMBUSY/GPIO76 THRMTRIP V4 EC_KBRST#
GPIO8 RCIN/GPIO82 EC_KBRST# <25,7>
D <22> LAN_PW R_EN LAN_PW R_EN AM7 T4 SERIRQ SERIRQ <25,27> Layout notes D
EC_LID_OUT# AD6 LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ AW15PCH_OPIRCOMP 2 1
<25> EC_LID_OUT# GPIO15 PCH_OPI_RCOMP
EC_FB_CLAMP_TGL_REQ# Y1 MISC AF20 RC131 DG V0.9 PCH_OPIRCOMP
T3
AD5
GPIO16
GPIO17
RSVD
RSVD
AB21 49.9_0402_1% L Width=12mil,spacing=12mil
short@ UART_W AKE#
RC124 1 2 0_0201_5% EC_PME#_R AN5 GPIO24 Max length=500mil
<22,25> EC_PME# GPIO27
PAD T148 AD7
GPIO28
Boot BIOS Strap
PV:RC124 change to 0-ohm shortpad PAD T149 AN3
GPIO26 R6 NGFF_W IFI_3.3_PW REN
BT_ON AG6 GSPI0_CS/GPIO83 L6 W W AN_PW REN
GPIO56 GSPI0_CLK/GPIO84 PCH_GPIO86 Boot BIOS Location
AP1 N6 PCH_GPIO85 RC108 1 @ 2 0_0201_5%
GPIO57 GSPI0_MISO/GPIO85 DGPU_PW R_EN <25,37,54,8>
RC119 1 2 PCH_GPIO58 AL4 L8
<35,8> DGPU_HOLD_RST#
<10,31> W L_OFF#
@
0_0201_5% W L_OFF# AT5 GPIO58
GPIO59
GSPI0_MOSI/GPIO86
GSPI1_CS/GPIO87
R7
MSATA_SSD_PW REN
PCH_GPIO87 RC1171 @ 2 0_0201_5% DGPU_PW ROK <36,8>
* 0 SPI
<25> NMI_DBG#_CPU NMI_DBG#_CPU AK4 GPIO L5

LPDDR3_ID1 AB6 GPIO44 GSPI1_CLK/GPIO88 N7 TOUCH_PANEL_PW REN
LPDDR3_ID2 U4 GPIO47 GSPI1_MISO/GPIO89 K2 SATA1_PW REN
DGPU_PRSNT# Y3 GPIO48 GSPI_MOSI/GPIO90 J1 PCH_LAN_RST#
PAD T150 P3 GPIO49 UART0_RXD/GPIO91 K3 PCH_LAN_W AKE#
Y2 GPIO50 UART0_TXD/GPIO92 J2 PCH_CR_RST#
<6> MPHY_PW REN HSIOPC/GPIO71 UART0_RTS/GPIO93
USB32_P0_PW REN_R# AT3 SERIAL IO G1 PCH_CR_W AKE#
AH4 GPIO13 UART0_CTS/GPIO94 K4
USB_CAM_PW REN AM4 GPIO14 UART1_RXD/GPIO0 G2
TS_GPIO_CPU AG5 GPIO25 UART1_TXD/GPIO1 J3
<19> TS_GPIO_CPU GPIO45 UART1_RST/GPIO2
AG3 J4 ODD_DA# ODD_DA# <29>
GPIO46 UART1_CTS/GPIO3 F2 I2C_0_SDA
PCH_GPIO9 AM3 I2C0_SDA/GPIO4 F3 I2C_0_SCL
EC_SCI# AM2 GPIO9 I2C0_SCL/GPIO5 G4 I2C_1_SDA
<25> EC_SCI# GPIO10 I2C1_SDA/GPIO6
PCH_GPIO33 P2 F1 I2C_1_SCL
<7> PCH_GPIO33 DEVSLP0/GPIO33 I2C1_SCL/GPIO7
PAD T158 Dummy C4 E3
C DEVSLP1 L2 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 F4 C
<8> DEVSLP1 DEVSLP1/GPIO38 SDIO_CMD/GPIO65
N5 D3
HDA_SPKR V2 DEVSLP2/GPIO39 SDIO_D0/GPIO66 E4
<23> HDA_SPKR SPKR/GPIO81 SDIO_D1/GPIO67 C3 ODD_PW R NGFF_W IFI_3.3_PW REN 4 5 RPH21
SDIO_D2/GPIO68 ODD_PW R <29>
E2 W W AN_PW REN 3 6
+3VS SDIO_D3/GPIO69 MSATA_SSD_PW REN 2 7
+3V_PCH 10 OF 19 TOUCH_PANEL_PW REN 1 8
BDW-ULT-DDR3L-IL_BGA1168 10K_0804_8P4R_5%
<SI> PRH14.4 change from +3V_PCH to +3VS for S3 leakage
RPH23 4 5 ODD_DA#
3 6 EC_LID_OUT# +3V_PCH +3VS +3VS
2 7 UART_W AKE# +3VS
1 8 BT_ON
1
1
10K_0804_8P4R_5%
RC135 RC261 RC262
RPH24 4 5
3 6 USB_OC0# 10K_0402_5% 10K_0402_5% 10K_0402_5%
USB_OC0# <10>
2 7 USB_OC1# @ @ UMA@
USB_OC1# <10>
2
2
1 8 USB_OC2# LPDDR3_ID1
USB_OC2# <10>
10K_0804_8P4R_5% LPDDR3_ID2 PCH_CR_W AKE# 4 5 RPH28
DGPU_PRSNT# PCH_CR_RST# 3 6
RPH25 4 5 PCH_GPIO58 PCH_LAN_W AKE# 2 7
3 6 NMI_DBG#_CPU PCH_LAN_RST# 1 8
1
1
2 7 USB32_P0_PW REN_R# DIS@ 10K_0804_8P4R_5%
1 8 PCH_GPIO9 @RC263 @RC264 RC265 @
10K_0804_8P4R_5%
<PV>PRH14 change to RPH23. 10K_0402_5% 10K_0402_5% 10K_0402_5%
I2C_1_SDA 8 1 RPH18
2
2
B PRH15 change to RPH24. I2C_0_SCL 7 2 B
I2C_0_SDA 6 3
+3VS PRH16 change to RPH25. I2C_1_SCL 5 4
1K_0804_8P4R_5%
@
+3V_PCH
RPH26 4 5 SERIRQ
3 6 SATA_LED# RPH14 4 5 SUSW ARN#_R
SATA_LED# <32,6> SUSW ARN#_R <8>
2 7 3 6 SML1ALERT#
SML1ALERT# <7>
1 8 2 7 SMBALERT#
SMBALERT# <7>
10K_0804_8P4R_5% 1 8 EC_SCI#
10K_0804_8P4R_5%
RPH10 4 5 SATA1_PW REN
3 6 PCH_AUDIO_PW REN
2 7 USB_CAM_PW REN
1 8 LAN_PW R_EN
10K_0804_8P4R_5%
+3V_DSW _P
A * GPIO27 RC277 1 2 10K_0402_5% EC_PME#

A
PCH_GPIO27 (Have internal Pull-High)

High: VCCVRM VR Enable
Low: VCCVRM VR Disable
GPIO,UART,I2C
Custom 0.1
LA-C701P
5 4 3 2 1
5 4 3 2 1
<11,12,24,36,4,6,7,9> +3V_PCH +3V_PCH
D D
UCPU1K BDW_ULT_DDR3L(Interleaved)
<35> PCIE_CRX_GTX_N0 F10 AN8

PERN5_L0 USB2N0 USB20_N0 <30>
<35> PCIE_CRX_GTX_P0 E10 AM8 USB2.0/USB3.0
PERP5_L0 USB2P0 USB20_P0 <30>
C4 1 DIS@2 .1U_0402_16V7K PCIE_PTX_DRX_N5_L0 C23 AR7
<35> PCIE_CTX_GRX_N0 C5 PETN5_L0 USB2N1 USB20_N1 <30>
<35> PCIE_CTX_GRX_P0 1 DIS@2 .1U_0402_16V7K PCIE_PTX_DRX_P5_L0 C22 AT7 USB2.0
PETP5_L0 USB2P1 USB20_P1 <30>
F8 AR8
<35> PCIE_CRX_GTX_N1 PERN5_L1 USB2N2 USB20_N2 <32>
E8 AP8 USB2.0 ( on small BD )
<35> PCIE_CRX_GTX_P1 PERP5_L1 USB2P2 USB20_P2 <32>
C6 1 DIS@2 .1U_0402_16V7K PCIE_PTX_DRX_N5_L1 B23 AR10
<35> PCIE_CTX_GRX_N1 C3 1 DIS@2 .1U_0402_16V7K A23 PETN5_L1 USB2N3 AT10 USB20_N3 <31>
DGPU PCIE_PTX_DRX_P5_L1 WLAN/BT
<35> PCIE_CTX_GRX_P1 PETP5_L1 USB2P3 USB20_P3 <31>
H10 AM15
<35> PCIE_CRX_GTX_N2 G10 PERN5_L2 USB2N4 AL15 USB20_N4 <19>
<35> PCIE_CRX_GTX_P2 PERP5_L2 USB2P4 USB20_P4 <19> Camera
C7 1 DIS@2 .1U_0402_16V7K PCIE_PTX_DRX_N5_L2 B21 AM13
<35> PCIE_CTX_GRX_N2 C8 PETN5_L2 USB2N5 USB20_N5 <19>
1 DIS@2 .1U_0402_16V7K PCIE_PTX_DRX_P5_L2 C21 AN13 Touch screen
<35> PCIE_CTX_GRX_P2 PETP5_L2 USB2P5 USB20_P5 <19>
E6 AP11
<35> PCIE_CRX_GTX_N3 PERN5_L3 USB2N6 USB20_N6 <32>
F6 AN11 Card reader
<35> PCIE_CRX_GTX_P3 PERP5_L3 USB2P6 USB20_P6 <32>
C9 1 DIS@2 .1U_0402_16V7K PCIE_PTX_DRX_N5_L3 B22 AR13
<35> PCIE_CTX_GRX_N3 C10 PETN5_L3 USB2N7
1 DIS@2 .1U_0402_16V7K PCIE_PTX_DRX_P5_L3 A21 AP13
<35> PCIE_CTX_GRX_P3 PETP5_L3 USB2P7
<22> PCIE_PRX_DTX_N3 PCIE_PRX_DTX_N3 G11

PCIE_PRX_DTX_P3 F11 PERN3 G20
<22> PCIE_PRX_DTX_P3 PERP3 USB3RN1 USB3_RX0_N <30>
LAN H20 USB3_RX0_P <30>
CC14 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_N3 C29 USB3RP1
<22> PCIE_PTX_C_DRX_N3
CC15 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_P3 B30 PETN3 PCIE USB C33
USB2.0/USB3.0
<22> PCIE_PTX_C_DRX_P3 PETP3 USB3TN1 USB3_TX0_N <30>
C B34 C
F13 USB3TP1 USB3_TX0_P <30>
G13 PERN4 E18
PERP4 USB3RN2 F18
B29 USB3RP2
A29 PETN4 B33
PETP4 USB3TN2 A33
G17 USB3TP2
F17 PERN1/USB3RN3
C30
PERP1/USB3RP3 L Layout notes
DG V0.9 USBRBIAS
C31 PETN1/USB3TN3 AJ10 USBRBIAS RC111 1 2 22.6_0402_1%
PETP1/USB3TP3 USBRBIAS AJ11
Trace width=50ohm and spacing=15mil
F15 USBRBIAS AN10 Max length=500mil
G15 PERN2/USB3RN4 RSVD AM10
PERP2/USB3RP4 RSVD
B31
A31 PETN2/USB3TN4
PETP2/USB3TP4 AL3 USB_OC0#
OC0/GPIO40 AT1 USB_OC0# <9>
USB_OC1#
OC1/GPIO41 USB_OC1# <9>
AH2 USB_OC2#
E15 OC2/GPIO42 AV3 USB_OC2# <9>
RC113 USB1_PWR_EN
3K_0402_1% E13 RSVD OC3/GPIO43
1 2 PCH_PCIE_RCOMP A27 RSVD +3V_PCH
<Page12> +1.05VS_VCCUSB3PLL
B27 PCIE_RCOMP
PCIE_IREF RPH29
4 5
3 6
L Layout notes
DG V0.9 PCIE_RCOMP BDW-ULT-DDR3L-IL_BGA1168
11 OF 19 <31,9> WL_OFF# WL_OFF#
USB1_PWR_EN
2
1
7
8
Width=12mil,spacing=12mil 10K_0804_8P4R_5%
Max length=500mil
B B
A A

PCIE,USB
C 0.1
LA-C701P
5 4 3 2 1
5 4 3 2 1
<34,51,52> +VCC_CORE +VCC_CORE
<15,16,17,34,4,49> +1.35V_VDDQ +1.35V_VDDQ
<4,6,9> +1.05VS_VCCST +1.05VS_VCCST
<4,6> +VCCIO_OUT +VCCIO_OUT
<4> +VCCIOA_OUT +VCCIOA_OUT
<12,24,25,28,34,37,50,51> +1.05VS +1.05VS
D D
+VCC_CORE@10000mA
+1.05VS_VCCST +VCC_CORE
Layout notes
SVID ALERT L DG V0.5 H_CPU_SVIDALRT#
UCPU1L BDW_ULT_DDR3L(Interleaved)
+1.35V_VDDQ L59 C36

RC154 close to CPU<300mil RSVD VCC
1
J58 C40
RSVD VCC
RC154 Max length=1000~2000mil 2500mA AH26 VCC
C44
+VCC_CORE C48
75_0402_5% AJ31 VDDQ VCC C52
AJ33 VDDQ VCC C56
2
AJ37 VDDQ VCC E23
RC155 1 2 H_CPU_SVIDALRT# AN33 VDDQ VCC E25
<51> VR_SVID_ALRT# VDDQ VCC
<PWR VR12.6> 43_0402_1% AP43 E27
AR48 VDDQ VCC E29
AY35 VDDQ VCC E31
AY40 VDDQ VCC E33
+1.05VS_VCCST AY44 VDDQ VCC E35
AY50 VDDQ VCC E37
SVID DATA L Layout notes
VDDQ VCC
VCC
E39
1
F59 E41
RC156
110_0402_1%
DG V0.5 VIDSOUT
RC156 close to CPU<500mil
VCC_SENSE N58
AC58
VCC
RSVD
RSVD
VCC
VCC
VCC
E43
E45
E47
VCC
<PWR VR12.6> Max length=1000~2000mil <PWR VR12.6> <51> VCCSENSE VCCSENSE E63 E49
2
AB23 VCC_SENSE VCC E51

A59 RSVD VCC E53
C +VCCIO_OUT VCCIO_OUT VCC C
VR_SVID_DAT <VR IV and CPU> E20 E55
<51> VR_SVID_DAT +VCCIOA_OUT VCCIOA_OUT VCC
<EDP_COMP power rail> AD23 E57
AA23 RSVD VCC F24
AE59 RSVD VCC F28
RSVD VCC F32
H_CPU_SVIDALRT# L62 VCC F36
VR_SVID_CLK N63 VIDALERT HSW ULT POWER VCC F40
<51> VR_SVID_CLK VIDSCLK VCC
VR_SVID_DAT L63 F44
B59 VIDSOUT VCC F48
+VCCIO_OUT <4,6> +1.05VS_PG VCCST_PWRGD VCC
<51> VR_ON F60 F52
@ VR12.6PG_MCP C59 VR_EN VCC F56
<CPU> RC294 1 2 0_0402_5% VR_READY VCC G23
+1.05VS VCC
D63 G25
CPU_PWR_DEBUG H59 VSS VCC G27
P62 PWR_DEBUG VCC G29
P60 VSS VCC G31
P61 RSVD_TP VCC G33
N59 RSVD_TP VCC G35
N61 RSVD_TP VCC G37
T59 RSVD_TP VCC G39
AD60 RSVD VCC G41
AD59 RSVD VCC G43
AA59 RSVD VCC G45
AE60 RSVD VCC G47
AC59 RSVD VCC G49
AG58 RSVD VCC G51
+1.05VS_VCCST U59 RSVD VCC G53
V59 RSVD VCC G55
+VCC_CORE RSVD VCC G57
600mA AC22 VCC H23
AE22 VCCST VCC J23
+1.05VS_VCCST AE23 VCCST VCC K23
B
VCCST VCC K57 B
AB57 VCC L22
AD57 VCC VCC M23
VCC VCC
1
+3V_PCH AG57 M57

RC288 C24 VCC VCC P57
UC8 @ @ C28 VCC VCC U57
10K_0402_5% VCC VCC
1 5 C32 W57
NC VCC VCC VCC
2
2 12 OF 19
<51> VGATE A BDW-ULT-DDR3L-IL_BGA1168
4 VR12.6PG_MCP
3 Y
GND
74AUP1G07GW_TSSOP5
RG124
1 short@ 2 0_0402_5%
+1.05VS_VCCST
PV:RC223,RG124 change to 0-ohm shortpad +1.35V_VDDQ +1.35V_VDDQ
+1.05VS
+1.05VS_VCCST
150_0402_5%
1
RC166
2.2U_0402_6.3V6M
CC20
2.2U_0402_6.3V6M
CC21
2.2U_0402_6.3V6M
CC22
2.2U_0402_6.3V6M
CC23
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1 1
short@ 1 1 1 1 @ @ 1 1 @ 1 1 @ 1 1 @
1 2 CC24 + CC25 +
CC26
CC27
CC28
CC29
CC30
CC31
RC223 @
1U_0402_6.3V6K
2
0_0805_5% 330U_2.5V_M 330U_2.5V_M

2 2 2 2 2 2 2 2 2 2 2 2
CC71
22U_0805_6.3V6M
CPU_PWR_DEBUG <6> 1 1
CC72
10K_0402_5%
@
1
A 2 2 A
@
RC167
2

Power
Custom 0.1
LA-C701P
5 4 3 2 1
5 4 3 2 1
<10,11,24,36,4,6,7,9> +3V_PCH +3V_PCH

<24,34> +1.05VS_MODPHY +1.05VS_MODPHY
<11,24,25,28,34,37,50,51> +1.05VS +1.05VS
<24> +1.05V +1.05V
<23,37,53,6> +1.5VS +1.5VS
<8,9> +3V_DSW_P +3V_DSW_P
<15,16,18,19,20,21,22,23,24,25,27,31,32,33,34,35,36,37,56,6,7,8,9> +3VS +3VS
<19,22,24,25,26,28,29,32,37,48,50,53,56,7> +3VALW +3VALW
<34,6> +1.05VS_VCCSATA3PLL +1.05VS_VCCSATA3PLL
<34> +1.05VS_APPLOPI +1.05VS_APPLOPI
D D
PV:RC168,RC172,RC280,RC281,RC285,RC196,RC175,RC178 change to 0-ohm shortpad
+1.05VS_VCCUSB3PLL short@
RC168 1 2
1.838A +1.05VS_VCCHSIO
+1.05VS_MODPHY 65mA
1U_0402_6.3V6K
RC170 +3V_DSW_PRTCSUS 1 RC169 1 short@ 2 0_0402_5%
+3V_PCH
+1.05VS_MODPHY 1 2 +1.05VS_VCCUSB3PLL 0_0805_5% 1 1
1U_0402_6.3V6K
1U_0402_6.3V6K
41mA
CC32
47U_0805_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30%
CC33
CC34
1 1 1U_0402_6.3V6K 2
2 2
CC35
+RTCVCC
CC36
BDW_ULT_DDR3L(Interleaved) +RTCVCC
UCPU1M
2 2
0.1U_0402_16V7K
CC37
K9 1 1
1U_0402_6.3V6K
L10 VCCHSIO
M9 VCCHSIO
CC39
N8 VCCHSIO HSIO RTC AH11 @
+1.05VS_VCCSATA3PLL +1.05VS VCC1_05 VCCSUS3_3 2 2
1 P9 AG10
CC41 +1.05VS_VCCUSB3PLL B18 VCC1_05 VCCRTC AE7 CC40 1 2 0.1U_0402_16V7K
RC171 1U_0402_6.3V6K +1.05VS_VCCSATA3PLL B11 VCCUSB3PLL DCPRTC
1 2 +1.05VS_VCCSATA3PLL VCCSATA3PLL
+1.05VS_MODPHY 2
42mA 18mA
47U_0805_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30% RC173 Y20 SPI Y8 SPI ROM power rail

+3V_PCH
1U_0402_6.3V6K
1 @ 2 +1.05VS_APPLOPI AA21 RSVD VCCSPI

1 1 Use +1.05V +1.05V
W21 VCCAPLL
OPI 1
0_0402_5%
CC42
VCCAPLL AG14 CC44 @

CC43
VCCASW +1.05VS
2 1 AG13 0.1U_0402_16V7K
2 2 10U_0603_6.3V6M CC45 VCCASW 2
2 1 +1.05V_DCPSUS J13 USB3
C 1.6A C
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K CC46 DCPSUS3 J11
VCC1_05 +1.05VS
H11 1 1 1
+VCCSUSHDA AH14 HDA VCC1_05 H15
CC48
CC49
CC50
VCCHDA VCC1_05 AE8 RC174 CC52
1
1U_0402_6.3V6K
VCC1_05 AF22 5.11_0402_1% 1U_0402_6.3V6K
RC172 1 short@ 2 0_0402_5% AH13 VRM VCC1_05 AG19 2 1 1 2 2 2 2
CC51
+1.5VS DCPSUS2 CORE DCPSUSBYP AG20 0.658A
2 DCPSUSBYP AE9 +1.05VS_VCCASW 1 2
+1.05VS
1U_0402_6.3V6K
RC176 VCCASW AF9 RC175 short@ 0_0805_5%
1 2 +1.05VS_APPLOPI AC9 VCCASW AG8
CC54
+1.05VS +3V_PCH 1 1
22U_0805_6.3V6M
AA9 VCCSUS3_3 VCCASW AD10 +1.05V_DCPSUS
57mA
CC53
GPIO/LPC
22U_0805_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30% +3V_DSW_P AH10 VCCSUS3_3 DCPSUS1 AD8

CC55
1
1U_0402_6.3V6K
22U_0805_6.3V6M
V8 VCCDSW3_3 DCPSUS1
1 1 VCC3_3
W9 2 2
CC57
+3VS VCC3_3 J15

CC58
CC59
1 +1.5VS
22U_0805_6.3V6M
2 THERMAL SENSOR VCCTS1_5 K14

2 2 VCC3_3 +3VS
K16
VCC3_3
2 1 2
+1.05VS_AXCKDCB J18 CC76 0.1U_0402_16V7K
K19 VCCCLK SERIAL IO U8 +3V_1V8_SDIO
RC280 +1.05VS_AXCK_LCPLL A20 VCCCLK VCCSDIO T9 RC178
1U_0402_6.3V6K
1 2 +V1.05S_SSCF100 +V1.05S_SSCF100 J17 VCCACLKPLL VCCSDIO 1 2
+1.05VS VCCCLK 1 +3VS
62mA +V1.05S_SSCFF R21
short@ T21 VCCCLK LPT LP POWER short@
CC60
1U_0402_6.3V6K
0_0603_5% K18 VCCCLK SUS OSCILLATOR AB8 +1.05V_AOSCSUS 0_0603_5%

1 RSVD DCPSUS4 2
M20
V21 RSVD
CC61
RC281 AE20 RSVD AC20

2 +3V_PCH VCCSUS3_3 RSVD
+1.05VS 1 2 +V1.05S_SSCFF AE21 AG16
VCCSUS3_3 USB2 VCC1_05 AG17 @
124mA +1.05VS
1U_0402_6.3V6K
short@ VCC1_05 RC180

1
1U_0402_6.3V6K
RC179 0_0603_5% 1 +1.05V_AOSCSUS 1 2
+1.05V
1 2 +1.05VS_AXCKDCB
CC62
+1.05VS
47U_0805_6.3V6M
13 OF 19 2.2UH_LQM2MPN2R2NG0L_30%
CC65
1U_0402_6.3V6K
2.2UH_LQM2MPN2R2NG0L_30% 2 BDW-ULT-DDR3L-IL_BGA1168
1 1 1 1
1U_0402_6.3V6K
100U_1206_6.3V6K
2
CC63
CC67
B +3V_DSW_P B
@
CC64
CC66
2 2 Deep S3 and Non Deep S3 2 2 @
+3VALW RC285 1 short@ 2 0_0402_5% Deep S3 RC285-->SMT Total 1.05VS=1838+2274=4111mA

RC182 1 @ 2 0_0402_5% +3V_DSW_P Non Deep S3 RC182-->SMT Total 1.5VS=3mA
+3V_PCH
1
Total 1.8VS=7mA
1U_0402_6.3V6K
CC70
+1.05VS_AXCK_LCPLL
2 Total 3VS=0mA
RC181 Total 3VALW=200+62=262mA
1 2 +1.05VS_AXCK_LCPLL
+1.05VS
31mA Total 3V_PCH=99mA
47U_0805_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30%
1U_0402_6.3V6K
1 1 Total 1.05V=540+109=649mA
CC68
CC69
2 2
A A

Power
C
LA-8661P
LA-C701P 0.1

5 4 3 2 1
5 4 3 2 1
UCPU1N BDW_ULT_DDR3L(Interleaved)
A11 AJ35 UCPU1O BDW_ULT_DDR3L(Interleaved)

A14 VSS VSS AJ39
A18 VSS VSS AJ41 AP22 AV59
A24 VSS VSS AJ43 AP23 VSS VSS AV8
A28 VSS VSS AJ45 AP26 VSS VSS AW16
A32 VSS VSS AJ47 AP29 VSS VSS AW24
A36 VSS VSS AJ50 AP3 VSS VSS AW33 UCPU1P BDW_ULT_DDR3L(Interleaved)
D A40 VSS VSS AJ52 AP31 VSS VSS AW35 H17 D
A44 VSS VSS AJ54 AP38 VSS VSS AW37 D33 VSS H57
A48 VSS VSS AJ56 AP39 VSS VSS AW4 D34 VSS VSS J10
AA1 VSS VSS AJ63 AP54 VSS VSS AW44 D38 VSS VSS J63
AA58 VSS VSS AK23 AP57 VSS VSS AW47 D39 VSS VSS K1
AB10 VSS VSS AK3 AR11 VSS VSS AW50 D41 VSS VSS K12
AB20 VSS VSS AK52 AR15 VSS VSS AW51 D42 VSS VSS L13
AB22 VSS VSS AL10 AR17 VSS VSS AW59 D43 VSS VSS L15
AB7 VSS VSS AL13 AR23 VSS VSS AW60 D45 VSS VSS L17
AC61 VSS VSS AL17 AR31 VSS VSS AY11 D46 VSS VSS L18
AD21 VSS VSS AL20 AR33 VSS VSS AY16 D47 VSS VSS L20
AE10 VSS VSS AL26 AR49 VSS VSS AY24 D50 VSS VSS L7
AE5 VSS VSS AL29 AR5 VSS VSS AY26 D51 VSS VSS M22
AE58 VSS VSS AL31 AR52 VSS VSS AY30 D53 VSS VSS N10
AF11 VSS VSS AL33 AT13 VSS VSS AY33 D54 VSS VSS N3
AF12 VSS VSS AL36 AT35 VSS VSS AY4 D55 VSS VSS P59
AF14 VSS VSS AL39 AT37 VSS VSS AY51 D57 VSS VSS P63
AF15 VSS VSS AL40 AT40 VSS VSS AY53 D59 VSS VSS R10
C VSS VSS VSS VSS VSS VSS C
AG1 AL51 AT46 AY6 E11 T1
AG11 VSS VSS AL52 AT49 VSS VSS B20 E17 VSS VSS T58
AG21 VSS VSS AL54 AT61 VSS VSS B24 F20 VSS VSS U20
AG61 VSS VSS AL61 AU1 VSS VSS B32 F34 VSS VSS U9
AG62 VSS VSS AM1 AU16 VSS VSS B36 F38 VSS VSS V10
AG63 VSS VSS AM17 AU18 VSS VSS B4 F42 VSS VSS V3
AH17 VSS VSS AM23 AU20 VSS VSS B40 F46 VSS VSS V7
AH19 VSS VSS AM31 AU22 VSS VSS B44 F50 VSS VSS W20
AH20 VSS VSS AM52 AU24 VSS VSS B48 F54 VSS VSS W22
AH22 VSS VSS AN17 AU26 VSS VSS B52 F58 VSS VSS Y10
AH24 VSS VSS AN23 AU28 VSS VSS B56 F61 VSS VSS Y59
AH28 VSS VSS AN31 AU30 VSS VSS B60 G18 VSS VSS Y63
AH30 VSS VSS AN32 AU33 VSS VSS C11 G22 VSS VSS
AH32 VSS VSS AN35 AU51 VSS VSS C14 G3 VSS
AH34 VSS VSS AN36 AU53 VSS VSS C18 G5 VSS V58
AH36 VSS VSS AN39 AU55 VSS VSS C20 G6 VSS VSS AH46
AH38 VSS VSS AN40 AU57 VSS VSS C25 G8 VSS VSS V23
AH40 VSS VSS AN42 AU59 VSS VSS C27 H13 VSS VSS E62
AH42 VSS VSS AN43 AV14 VSS VSS C38 VSS VSS_SENSE AH16
VSSSENSE <51> <PWR VR12.6>
AH44 VSS VSS AN45 AV16 VSS VSS C39 16 OF 19 VSS
AH49 VSS VSS AN46 AV20 VSS VSS C57 BDW-ULT-DDR3L-IL_BGA1168
AH51 VSS VSS AN48 AV24 VSS VSS D12
B B
AJ13 VSS VSS AN60 AV36 VSS VSS D21
AJ25 VSS VSS AP10 AV43 VSS VSS D26
VSS VSS AV51 VSS VSS D30
AV55 VSS VSS D31
VSS 15 OF 19 VSS
14 OF 19 BDW-ULT-DDR3L-IL_BGA1168
A A

GND/VSSSEN
Document Number Rev
0.1
LA-C701P
5 4 3 2 1
5 4 3 2 1
UCPU1Q BDW_ULT_DDR3L(Interleaved) CFG4
1
DC_TEST_AY2_AW2 AY2 A3 TP_DC_TEST_A3_B3
DC_TEST_AY3_AW3 AY3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 A4 RC185
AY60 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 1K_0402_1%
DC_TEST_AY61_AW61 AY61 DAISY_CHAIN_NCTF_AY60 A60
2
DC_TEST_AY61_AW62 AY62 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 A61 DC_TEST_A61_B61
B2 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 A62
TP_DC_TEST_A3_B3 B3 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 AV1
DC_TEST_A61_B61 B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 AW1
D DC_TEST_B62_B63 B62 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW2 DC_TEST_AY2_AW2 D
B63 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW3 DC_TEST_AY3_AW3
DC_TEST_C1_C2 C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW61 DC_TEST_AY61_AW61 Display Port Presence Strap
C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 AW62 DC_TEST_AY61_AW62
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW63
17 OF 19 DAISY_CHAIN_NCTF_AW63 1 : Disabled; No Physical Display Port
Vinafix
CFG4 attached to Embedded Display Port
0 : Enabled; An external Display Port device is
UCPU1R BDW_ULT_DDR3L(Interleaved) * connected to the Embedded Display Port
N23
RSVD R23 CFG0
RSVD T23
AT2 RSVD
1
RSVD U10
AU44 RSVD
AV44 RSVD
D15 RSVD @ RC187
RSVD AL1 1K_0402_1%
RSVD AM11
2
RSVD AP7
F22 RSVD
RSVD AU10
H22 RSVD
RSVD AU15
C J21 RSVD C
RSVD AW14
RSVD AY14
RSVD
18 OF 19
UCPU1S BDW_ULT_DDR3L(Interleaved)
CFG0 AC60 AV63

<6> CFG0 AC62 CFG0 RSVD_TP AU63
CFG1
<6> CFG1 CFG1 RSVD_TP
CFG2 AC63
<6> CFG2 AA63 CFG2
CFG3
<6> CFG3 CFG3
CFG4 AA60 C63
<6> CFG4 Y62 CFG4 RSVD_TP C62
CFG5
<6> CFG5 Y61 CFG5 RSVD_TP B43
CFG6
<6> CFG6 CFG6 RSVD
CFG7 Y60
<6> CFG7 V62 CFG7 A51
CFG8
CFG9 V61 B51
<6> CFG9 V60 CFG9 RSVD_TP
CFG10
<6> CFG10 U60 CFG10 L60
B CFG11 B
CFG12 T63
<6> CFG12 T62 CFG12 RESERVED N60
CFG13
<6> CFG13 CFG13 RSVD
CFG14 T61
<6> CFG14 T60 CFG14 W23
CFG15
<6> CFG15 CFG15 RSVD Y22 2 1 49.9_0402_1%
MCP_RSVD_29 RC296 @
CFG16 AA62 RSVD AY15 PROC_OPI_COMP RC186 2 1 49.9_0402_1%
<6>
<6>
CFG16
CFG18
CFG18 U63
AA61
CFG16
CFG18
PROC_OPI_RCOMP
AV62
L Layout notes
DG V0.9 PROC_OPI_COMP
CFG17
<6> CFG17 U62 CFG17 RSVD D58
CFG19
<6> CFG19 CFG19 RSVD Width=12mil,spacing=12mil
2 1 CFG_RCOMP V63
CFG_RCOMP VSS
P22 Max length=500mil
RC188 49.9_0402_1% N21
A5 VSS
RSVD P20
E1 RSVD R20
D1 RSVD RSVD
J20 RSVD
H18 RSVD
1 2 TD_IREF B12 RSVD
RC191 8.2K_0402_5% TD_IREF
19 OF 19
A A

RSVD/CFG
Document Number Rev
0.1
LA-C701P
5 4 3 2 1
5 4 3 2 1
<11,16,17,34,4,49> +1.35V_VDDQ +1.35V_VDDQ
<16,49> +0.6V_0.675VS +0.6V_0.675VS
<19,24,26,29,30,32,34,37,48,49,56> +5VALW +5VALW
+V_VDDR_REFA_DQ <12,16,18,19,20,21,22,23,24,25,27,31,32,33,34,35,36,37,56,6,7,8,9> +3VS +3VS

+1.35V_VDDQ +1.35V_VDDQ
<16,17> +V_VDDR_REFA_CA +V_VDDR_REFA_CA
<17> +V_VDDR_REFA_DQ +V_VDDR_REFA_DQ

JDIMM1
+V_VDDR_REFA_DQ 1 2
D
3 VREF_DQ VSS1 4 DDR_A_D0 D
VSS2 DQ4
0.1U_0402_16V7K
DDR_A_D5 5 6 DDR_A_D1
<5> DDR_A_D[0..63] DQ0 DQ5
CD1
1 DDR_A_D4 7 8
9 DQ1 VSS3 10 DDR_A_DQS#0
<5> DDR_A_DQS[0..7] VSS4 DQS#0
11 12 DDR_A_DQS0
13 DM0 DQS0 14
<5> DDR_A_DQS#[0..7] 2 15 VSS5 VSS6 16
DDR_A_D2 DDR_A_D6
DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7
<5> DDR_A_MA[0..15] 19 DQ3 DQ7 20
DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12
DDR_A_D13 23 DQ8 DQ12 24 DDR_A_D9
25 DQ9 DQ13 26
DDR_A_DQS#1 27 VSS9 VSS10 28
DDR_A_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <16,4>
31 32 1
DDR_A_D15 33 VSS11 VSS12 34 DDR_A_D10 ESD@
DDR_A_D11 35 DQ10 DQ14 36 DDR_A_D14 CD99 +1.35V_VDDQ
37 DQ11 DQ15 38
VSS13 VSS14 0.1U_0402_16V7K
DDR_A_D16 39 40 DDR_A_D20 2
DQ16 DQ20
DDR_A_D17 41
43 DQ17 DQ21
42
44
DDR_A_D21
SI : pop CD99 +5VALW QD1
DDR_A_DQS#2 45 VSS15 VSS16 46 BSS138_NL_SOT23-3
DDR_A_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_A_D23 1 3 RD20 1 2 66.5_0402_1% M_ODT0
S
VSS18 DQ22
1
DDR_A_D22 51 52 DDR_A_D19
DDR_A_D18 53 DQ18 DQ23 54 RD21 RD22 1 2 66.5_0402_1% M_ODT1
55 DQ19 VSS19 56 DDR_A_D25
G
2
DDR_A_D29 57 VSS20 DQ28 58 DDR_A_D28 220K_0402_5% RD23 1 2 66.5_0402_1% M_ODT2
59 DQ24 DQ29 60 M_ODT2 <16>
DDR_A_D24
2
61 DQ25 VSS21 62 DDR_A_DQS#3 RD24 1 2 66.5_0402_1% M_ODT3
VSS22 DQS#3 M_ODT3 <16>
63 64 DDR_A_DQS3
65 DM3 DQS3 66
VSS23 VSS24
1
DDR_A_D31 67 68 DDR_A_D30 @
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D26 RD25 SM_PG_CTRL
DQ27 DQ31 SM_PG_CTRL <4,49>
71 72
VSS25 VSS26 2M_0402_5%
2
C C
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
<5> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <5>
75 76
77 VDD1 VDD2 78 DDR_A_MA15
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
<5> DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
M_CLK_DDR0 101 VDD9 VDD10 102 M_CLK_DDR1
<5> M_CLK_DDR0 CK0 CK1 M_CLK_DDR1 <5>
M_CLK_DDR#0 103 104 M_CLK_DDR#1
<5> M_CLK_DDR#0 CK0# CK1# M_CLK_DDR#1 <5>
105 106
DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 <5>
DDR_A_BS0 109 110 DDR_A_RAS#
<5> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <5>
111 112
DDR_A_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMA#
<5> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <5>
<5> DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
117 CAS# ODT0 118
DDR_A_MA13 119 VDD15 VDD16 120 M_ODT1 +V_VDDR_REFA_CA
DDR_CS1_DIMMA# 121 A13 ODT1 122
<5> DDR_CS1_DIMMA# 123 S1# NC2 124
125 VDD17 VDD18 126 +V_VDDR_REFA_CA
127 NCTEST VREF_CA 128
VSS27 VSS28
0.1U_0402_16V7K
DDR_A_D32 129 130 DDR_A_D36
DDR_A_D33 131 DQ32 DQ36 132 DDR_A_D37
DQ33 DQ37
CD3
133 134 1
DDR_A_DQS4 137 DQS#4 DM4 138
139 DQS4 VSS31 140 DDR_A_D38
DDR_A_D35 141 VSS32 DQ38 142 DDR_A_D39 2
DDR_A_D34 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D41
B
DDR_A_D40 147 VSS34 DQ44 148 DDR_A_D44 B
DDR_A_D46 149 DQ40 DQ45 150
153 VSS36 DQS#5 154 DDR_A_DQS5
155 DM5 DQS5 156
DDR_A_D47 157 VSS37 VSS38 158 DDR_A_D42
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D45
161 DQ43 DQ47 162
+1.35V_VDDQ DDR_A_D48 163 VSS39 VSS40 164 DDR_A_D49
DDR_A_D53 165 DQ48 DQ52 166 DDR_A_D52
167 DQ49 DQ53 168
DQS#6 DM6
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_A_DQS6 171 172

DQS6 VSS43
CD6
CD7
CD8
CD9
CD10
CD11
CD12
CD13
1 1 1 1 1 1 1 1 173 174 DDR_A_D54

DDR_A_D51 175 VSS44 DQ54 176 DDR_A_D55
@ @ DDR_A_D50 177 DQ50 DQ55 178
@ @ 179 DQ51 VSS45 180 DDR_A_D57
2 2 2 2 2 2 2 2 DDR_A_D56 181 VSS46 DQ60 182 DDR_A_D60
DDR_A_D61 183 DQ56 DQ61 184
187 VSS48 DQS#7 188 DDR_A_DQS7
189 DM7 DQS7 190
DDR_A_D62 191 VSS49 VSS50 192 DDR_A_D59 +0.6V_0.675VS
+1.35V_VDDQ DDR_A_D58 193 DQ58 DQ62 194 DDR_A_D63
195 DQ59 DQ63 196
197 VSS51 VSS52 198
199 SA0 EVENT# 200
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
PCH_SMBDATA
+3VS VDDSPD SDA PCH_SMBDATA <16,18,21,6,7>
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
CD24
10U_0603_6.3V6M
1 1 1 1 1 1 1 1 201 202 PCH_SMBCLK
SA1 SCL PCH_SMBCLK <16,18,21,6,7>
CD17
CD19
CD21
1 203 204 1 1 1
VTT1 VTT2 +0.6V_0.675VS
CD55
CD56
CD57
CD58
CD63
CD64
CD65
CD66
205 206
2 2 @ 2 @ 2 @ 2 2 2 2 G1 G2
2 DEREN_40-42045-20404RHF 2 2 2
SP070012JA0
CONN@
A A
DIMM_1 H:4mm Reverse

DDR3L DIMM0
C 0.1
LA-C701P
5 4 3 2 1
5 4 3 2 1
<11,15,17,34,4,49> +1.35V_VDDQ +1.35V_VDDQ

+V_VDDR_REFB_DQ +1.35V_VDDQ +1.35V_VDDQ
<15,49> +0.6V_0.675VS +0.6V_0.675VS
<12,15,18,19,20,21,22,23,24,25,27,31,32,33,34,35,36,37,56,6,7,8,9> +3VS +3VS
<17> +V_VDDR_REFB_DQ +V_VDDR_REFB_DQ

JDIMM2
+V_VDDR_REFB_DQ 1 2 +V_VDDR_REFA_CA
VREF_DQ VSS1 <15,17> +V_VDDR_REFA_CA
3 4 DDR_B_D8
VSS2 DQ4
0.1U_0402_16V7K
DDR_B_D13 5 6 DDR_B_D9
<5> DDR_B_D[0..63] DQ0 DQ5
CD27
1 DDR_B_D12 7 8
9 DQ1 VSS3 10 DDR_B_DQS#1
<5> DDR_B_DQS[0..7] VSS4 DQS#0
11 12 DDR_B_DQS1
D
13 DM0 DQS0 14 D
<5> DDR_B_DQS#[0..7] 2 15 VSS5 VSS6 16
DDR_B_D15 DDR_B_D11
DDR_B_D14 17 DQ2 DQ6 18 DDR_B_D10
<5> DDR_B_MA[0..15] 19 DQ3 DQ7 20
DDR_B_D5 21 VSS7 VSS8 22 DDR_B_D2
25 DQ9 DQ13 26
DDR_B_DQS#0 27 VSS9 VSS10 28
DDR_B_DQS0 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <15,4>
31 32
37 DQ11 DQ15 38
DB phase :
DB phase : DDR_B_D21 39 VSS13 VSS14 40 DDR_B_D18 For ESD request
For ESD request DDR_B_D20 41 DQ16 DQ20 42 DDR_B_D19
20141110
43 DQ17 DQ21 44
20141110 DDR_B_DQS#2 45 VSS15 VSS16 46
DDR_B_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D16
DDR_B_D23 51 VSS18 DQ22 52 DDR_B_D17 +1.35V_VDDQ
DDR_B_D22 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D31
DDR_B_D30 57 VSS20 DQ28 58 DDR_B_D27
DDR_B_D26 59 DQ24 DQ29 60
DQ25 VSS21 1 1 1 1
61 62 DDR_B_DQS#3 C5215 C5216 C5217 C5218
VSS22 DQS#3
@ESD@
@ESD@
@ESD@
@ESD@
63 64 DDR_B_DQS3
65 DM3 DQS3 66
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
+1.35V_VDDQ DDR_B_D25 67 VSS23 VSS24 68 DDR_B_D29 2 2 2 2
71 DQ27 DQ31 72
VSS25 VSS26
DDR_CKE0_DIMMB 73 74 DDR_CKE1_DIMMB
<5> DDR_CKE0_DIMMB CKE0 CKE1 DDR_CKE1_DIMMB <5>
1 1 1 1 1 1 1 75 76
77 VDD1 VDD2 78 DDR_B_MA15
@ESD@
@ESD@
@ESD@
@ESD@
@ESD@
@ESD@
@ESD@
C5219 C5220 C5221 C5222 C5223 C5224 C5225 DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14
<5> DDR_B_BS2 BA2 A14
81 82
0.22U_0201_6.3V
0.22U_0201_6.3V
0.22U_0201_6.3V
0.22U_0201_6.3V
0.22U_0201_6.3V
0.22U_0201_6.3V
0.22U_0201_6.3V
C C
2 2 2 2 2 2 2 DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
M_CLK_DDR2 101 VDD9 VDD10 102 M_CLK_DDR3
<5> M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 <5>
M_CLK_DDR#2 103 104 M_CLK_DDR#3
<5> M_CLK_DDR#2 CK0# CK1# M_CLK_DDR#3 <5>
105 106
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <5>
DDR_B_BS0 109 110 DDR_B_RAS#
<5> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <5>
111 112
+1.35V_VDDQ DDR_B_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMB#
<5> DDR_B_WE# WE# S0# DDR_CS0_DIMMB# <5>
<5> DDR_B_CAS# DDR_B_CAS# 115 116 M_ODT2 M_ODT2 <15>
117 CAS# ODT0 118
DDR_B_MA13 119 VDD15 VDD16 120 M_ODT3 +V_VDDR_REFA_CA
A13 ODT1 M_ODT3 <15>
DDR_CS1_DIMMB# 121 122
<5> DDR_CS1_DIMMB# 123 S1# NC2 124
125 VDD17 VDD18 126 +V_VDDR_REFA_CA
1 1 1 1 1 1 1 NCTEST VREF_CA
127 128
@ESD@
@ESD@
@ESD@
@ESD@
@ESD@
@ESD@
@ESD@
VSS27 VSS28
0.1U_0402_16V7K
C5226 C5227 C5228 C5229 C5230 C5231 C5232 DDR_B_D32 129 130 DDR_B_D36
DDR_B_D33 131 DQ32 DQ36 132 DDR_B_D37
0.22U_0201_6.3V
0.22U_0201_6.3V
0.22U_0201_6.3V
0.22U_0201_6.3V
0.22U_0201_6.3V
0.22U_0201_6.3V
0.22U_0201_6.3V
2 2 2 2 2 2 2 DQ33 DQ37
CD29
133 134 1
139 DQS4 VSS31 140 DDR_B_D35
DDR_B_D38 141 VSS32 DQ38 142 DDR_B_D34 2
DDR_B_D39 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D40
DDR_B_D45 149 DQ40 DQ45 150
153 VSS36 DQS#5 154 DDR_B_DQS5
155 DM5 DQS5 156
B
DDR_B_D42 157 VSS37 VSS38 158 DDR_B_D47 B
DDR_B_D43 159 DQ42 DQ46 160 DDR_B_D46
161 DQ43 DQ47 162
DDR_B_D52 165 DQ48 DQ52 166 DDR_B_D55
167 DQ49 DQ53 168
+1.35V_VDDQ 173 DQS6 VSS43 174 DDR_B_D48
DDR_B_D53 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_B_D61
VSS46 DQ60
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_B_D57 181 182 DDR_B_D60

DQ56 DQ61
CD33
CD34
CD35
CD36
CD37
CD38
CD39
CD40
1 1 1 1 1 1 1 1 DDR_B_D56 183 184

187 VSS48 DQS#7 188 DDR_B_DQS7
@ @ @ @ 189 DM7 DQS7 190
2 2 2 2 2 2 2 2 DDR_B_D58 191 VSS49 VSS50 192 DDR_B_D63
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D62 +0.6V_0.675VS
195 DQ59 DQ63 196
197 VSS51 VSS52 198
199 SA0 EVENT# 200 PCH_SMBDATA
+3VS VDDSPD SDA PCH_SMBDATA <15,18,21,6,7>
0.1U_0402_16V7K
201 202 PCH_SMBCLK

SA1 SCL PCH_SMBCLK <15,18,21,6,7>
CD44
0.1U_0402_16V7K
0.1U_0402_16V7K
CD50
10U_0603_6.3V6M
1 203 204
VTT1 VTT2 +0.6V_0.675VS
1
10K_0402_5%
RD4
CD45
CD46
1 1 1
205 206
G1 G2
+1.35V_VDDQ 2 +3VS FOX_AS0A626-H2SB-7H
CONN@ 2 2 2
2
SP070015AA0
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1
CD59
CD60
CD61
CD62
CD67
CD68
CD69
CD70
2 2 2 2 2 @ 2 @ 2 2
@
A A

DDR3L DIMM1
0.1
LA-C701P
5 4 3 2 1
5 4 3 2 1
<11,15,16,34,4,49> +1.35V_VDDQ +1.35V_VDDQ
<15,16> +V_VDDR_REFA_CA +V_VDDR_REFA_CA
<5> +V_SM_VREF_CNT +V_SM_VREF_CNT
<5> +V_DDR_REFA_R +V_DDR_REFA_R
D <15> +V_VDDR_REFA_DQ +V_VDDR_REFA_DQ D
<16> +V_VDDR_REFB_DQ +V_VDDR_REFB_DQ
+1.35V_VDDQ
DDR3L VREF
1
+1.35V_VDDQ
RD5
1.8K_0402_1%
RD7
1
2
<CPU> 1 2 <DDR3L_0> RD6
+V_DDR_REFA_R +V_VDDR_REFA_DQ
1 1.8K_0402_1%
@
2_0402_1% RD8
CD52
2
1
0.022U_0402_25V7K 1 2 <DDR3L_A_CA>
2 +V_SM_VREF_CNT +V_VDDR_REFA_CA
RD9 <CPU> 1
1
C
RD11 1.8K_0402_1% <DDR3L_B_CA> C
CD53 @ 2_0402_1%
1
24.9_0402_1% 0.022U_0402_25V7K
2
@ 2 RD10
1
RD12 1.8K_0402_1%
2
24.9_0402_1%
2
@
2
+1.35V_VDDQ
1
RD13
1.8K_0402_1%
RD15
2
<CPU> 1 2 <DDR3L_1>
+V_DDR_REFB_R +V_VDDR_REFB_DQ
@1
CD54 2_0402_1%
1
0.022U_0402_25V7K
2 RD17
1
B RD19 1.8K_0402_1% B
24.9_0402_1% @
2
2
A A

DDR3L VREF
Document Number Rev
0.1
LA-C701P
5 4 3 2 1
5 4 3 2 1
<12,15,16,19,20,21,22,23,24,25,27,31,32,33,34,35,36,37,56,6,7,8,9> +3VS +3VS
+3VS
JPHW3 need to short +3VS_RT <19,34> +LCDVDD +LCDVDD
@ JPHW3
L Layout notes
Close to LT5 Pin18 Pin13
L Layout notes
Close to Pin11 Pin27 Pin7
80mil 1 2
80mil
1 2
JUMP_43X79 +SWR_VDD +SWR_V12 ※ ROM only mode : PIN 30 4.7k pull low, Pin 31 4.7k pull high.
EP mode : PIN 30 4.7k pull high, Pin 31 4.7k pull low.
10U_0603_6.3V6M
0.1U_0402_16V4Z
22U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
L Layout notes
CT16~CT18 Close to Pin3
1 1 1 1 1 1 1 1 1 EEPROM : PIN 30 4.7k pull high, Pin 31 4.7k pull high.
CT7
CT8
CT9
CT10
CT11
CT12
CT13
CT14
CT15
〈 ※ Default mode 〉
D +DP_V33 2 2 2 2 2 2 2 2 2 D
+3VS_RT +3VS_RT
10U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
LVDS@
1 1 1
LVDS@ LVDS@ LVDS@ LVDS@ LVDS@ LVDS@ LVDS@ LVDS@ 2132S@
2
CT16
CT17
CT18
@
RT2 RT3
2 2 2 LVDS@
4.7K_0402_5% 4.7K_0402_5%
+3VS_RT
1
LVDS@ LVDS@ LVDS@ UT1 MIIC_SDA MIIC_SCL
LVDS@ 19 LVDS_CLKP
LT6 2 1 +DP_V33 40mil 3 TXEC+ 20 LVDS_CLKN
LVDS_CLKP <19>
LVDS_CLKN <19>
2132S@
DP_V33 TXEC-
2
FBMA-L11-201209-221LMA30T_0805 @
LVDS@ 100mil 13 SWR_VDD TXE2+
21 LVDS_TXP2 RT4 RT5
Power
80mil LT5 2 1 +SWR_VDD 40mil 18 22 LVDS_TXN2 LVDS@ 4.7K_0402_5% 4.7K_0402_5%
LVDS
FBMA-L11-201209-221LMA30T_0805 PVCC TXE2-
+SWR_V12 1 @ 2 +SWR_LX 40mil 12 23 LVDS_TXP1 PIN30 PIN31
SWR / LDO Mode select
1
SWR_LX TXE1+
LT7 0_1206_5% 40mil 11 SWR_VCCK TXE1-
24 LVDS_TXN1
<CONN>
40mil 27 VCCK
40mil 7 DP_V12 TXE0+
25 LVDS_TXP0 LVDS_TXP0 <19>
LDO SWR 26 LVDS_TXN0
TXE0- LVDS_TXN0 <19> +3VS_RT
<SI> LT7 change to 0 ohm short pad LVDS@
LCD_EDID_CLK RT6 1 2 4.7K_0402_5%
2132S Do not support mount LT7
use LDO mode translator only
EDP_CPU_AUX 2
RTD2132S LCD_EDID_DATA 1
LVDS@
2 4.7K_0402_5%
RT7
AUX_P
DP-IN
EDP_CPU_AUX# 1 14 DP_INT_PWM
<CONN>
GPIO
AUX_N GPIO(PWM OUT) DP_INT_PWM <19>
15 +DP_ENVDD
GPIO(Panel_VCC) +DP_ENVDD <19>
2132N Use 0 ohm mount LT7 EDP_CPU_LANE_P0 5 16 BKL_PWM_CPU
EDP_CPU_LANE_N0 6 LANE0P GPIO(PWM IN) 17 TS_BKOFF#
BKL_PWM_CPU <19,8> <CPU> PIN15 PIN16 Accept voltage input (high level)
LANE0N GPIO(BL_EN)
C C
※ If use 2132N, please select LDO mode as default. CIICSCL1 9

CIICSCL1 LVDS MIICSCL1
29 LCD_EDID_CLK 2132S TL_ENVDD 2132S 3.3V
CIICSDA1 10 28 LCD_EDID_DATA
<CPU CTRL> CIICSDA1 EDID MIICDA1
Other
LVDS@ 2132R +LCD_VDD * 2132R 1.5~3.3V
<8> EDP_HPD
EDP_HPD 1 2 RT192 32
HPD ROM MIICSCL0
31 MIIC_SCL
1K_0402_1% 30 MIIC_SDA
MIICSDA0
1
8 * Version R internal Power Switch, can * Version R has internal level shifter, remove
RT11 4 DP_REXT 33
DP_GND GND output 1A, Rds(on)=0.2 ohm level shifter circuit on AMD platform
2
100K_0402_5%
RT8 LVDS@ RTD2132N-CG QFN32

2
12K_0402_1% SA00007A300
LVDS@
RTD2132 SMBus revrse to PCH L Layout notes Different between 2132S and 2132R
1
RT8 close to pin8

RT193 1 2 0_0201_5% CIICSCL1 2132S 2132R
<21,25,36,7> EC_SMB_CK2
RT194 1 2 0_0201_5% CIICSDA1
<21,25,36,7> EC_SMB_DA2
RT195 1 @ 2 0_0201_5%
<15,16,21,6,7> PCH_SMBCLK
RT196 1 @ 2 0_0201_5% +LCDVDD 1. Support SWR mode 1. Support LDO mode and SWR mode
<15,16,21,6,7> PCH_SMBDATA
+DP_ENVDD 1 2
2. Internal ROM
RT9 0_0805_5% 3. Support LCD_VDD(internal Power switch)
L Layout notes LVDS@
CC97~CC102 must closed to connector 4. Integrates Level shifter
1
2
RT10
CT23 100K_0402_5%
CC102 1 2 .1U_0402_16V7K EDP_CPU_AUX 4.7U_0603_6.3V6K
<4> EDP_CPU_AUX_C
L Layout notes LVDS@ 1 LVDS@
2
<4> EDP_CPU_AUX#_C
CC101 1 2 .1U_0402_16V7K EDP_CPU_AUX# RT9 close to pin15 <CPU by PASS eDP> <eDP to connector>
B CC98 1 2 .1U_0402_16V7K EDP_CPU_LANE_P0
RT10 CT23 close to CONN B
<4> EDP_CPU_LANE_P0_C
+DP_ENVDD 80mil trace width RP9
CC97 1 2 .1U_0402_16V7K EDP_CPU_LANE_N0 0_0804_8P4R_5% eDP@ SD309000080
<4> EDP_CPU_LANE_N0_C
EDP_AUX 4 5 LCD_CLK
<CPU> EDP_CPU_LANE_N0 1 8 EDP_LANE_N0 EDP_AUX# 3 6 LCD_DATA
LCD_CLK <19>
LCD_DATA <19>
CC103 1 2 .1U_0402_16V7K EDP_CPU_LANE_P1 EDP_CPU_LANE_P0 2 7 EDP_LANE_P0 EDP_LANE_N0 2 7 LVDS_TXN2_LN0
<4> EDP_CPU_LANE_P1_C LVDS_TXN2_LN0 <19>
eDP@ EDP_CPU_AUX 3 6 EDP_AUX EDP_LANE_P0 1 8 LVDS_TXP2_LP0
LVDS_TXP2_LP0 <19>
CC100 1 2 .1U_0402_16V7K EDP_CPU_LANE_N1 EDP_CPU_AUX# 4 5 EDP_AUX#
<4> EDP_CPU_LANE_N1_C
eDP@ eDP@ SD309000080 0_0804_8P4R_5%
RP6
EDP_HPD RT34 1 eDP@ 2 0_0201_5% EDP_HPD_PANEL
4
DB phase :
add eDP Lan1 for FHD Delete BKL_PWM_CPU and DP_INT_PWM
EDP_HPD_PANEL <19> 2 L Layout notes
RP6 RP9 RP10 must closed to connector
20141113
20141117
EDP_CPU_LANE_P1 RT16 1 eDP@ 2 0_0402_5% LVDS_TXP1_LP1
<LVDS to connector>
LVDS_TXP1_LP1 <19>
0_0804_8P4R_5%
@ EDP_CPU_LANE_N1 RT17 1 eDP@ 2 0_0402_5% LVDS_TXN1_LN1
LVDS_TXN1_LN1 <19>
RT14 1 2 0_0402_5% LCD_EDID_CLK 1 8 LCD_CLK
LCD_EDID_DATA 2 7 LCD_DATA
CT24
LVDS_TXN2 3 6 LVDS_TXN2_LN0
@ LVDS_TXP1 RT18 1 LVDS@ 2 0_0402_5% LVDS_TXP1_LP1 LVDS_TXP2 4 5 LVDS_TXP2_LP0
+3VS 1 2
LVDS_TXN1 RT19 1 LVDS@ 2 0_0402_5% LVDS_TXN1_LN1 LVDS@ SD309000080
RP10
0.1U_0402_16V7K
5
UT3
<RTS2132> TS_BKOFF# 1
DB phase : L Layout notes
P
B 4 add eDP Lan1 for FHD RT16~RT19 must closed to connector

EC_BKOFF# 2 Y EC_TS_BKOFF# <19> <LVDS Panel>
<EC CTRL> <25> EC_BKOFF# A 20141117
G
A A
TC7SH08FUF_SSOP5
3
1
LVDS@
RT12 PD 100K on LVDS page
100K_0402_5%
LVDS@
2

eDP@ 2013/3/1 2015/3/1 Title
Issued Date Deciphered Date
RT15 1 2 0_0402_5% LVDS Translator-RTD2132N
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-C701P 0.1
5 4 3 2 1
5 4 3 2 1
<12,15,16,18,20,21,22,23,24,25,27,31,32,33,34,35,36,37,56,6,7,8,9> +3VS +3VS
<37,47,48,49,51,53,54> B+ +19.5VB
<12,22,24,25,26,28,29,32,37,48,50,53,56,7> +3VALW +3VALW
<18,34> +LCDVDD +LCDVDD

+3VS
EDP Power Main SA000028Y10
<20,23,24,25,26,29,33,37,51,54> +5VS +5VS
eDP@ UG1 2nd SA00006EE00
<15,24,26,29,30,32,34,37,48,49,56> +5VALW +5VALW
5 1 W=60mils W=60mils
IN OUT +LCDVDD
2 INVPWR_B+ +19.5VB
GND
RG1 1 @ 2 0_0201_5% 4 3 1 1 L1 short@
D SS EN CG2 CG3 1 2 0_0805_5% D
1
PV:L1,L2 change to 0-ohm shortpad
4.7U_0603_6.3V6K
0.1U_0402_16V7K
CG1 G5243AT11U SOT-23 L2 short@
eDP@ SA000028Y10 2 2 1 2 0_0805_5%
1500P_0402_50V7K 2
1 1
@EMI@ C117 C118
680P_0402_50V7K 68P_0402_50V8J
RG3 1 @ 2 0_0402_5% 2 2
<18> +DP_ENVDD
R172 1 eDP@ 2 0_0402_5%

<8> ENVDD_CPU
@ESD@ SCA00000U10
D7
USB20_P4_R 2
1
USB20_N4_R 3
PESD5V0U2BT_SOT23-3
Camera C593 2
C594 2
1 220P_0402_50V7K
1 220P_0402_50V7K
INVTPWM
DISPOFF#
LCD/LED PANEL Conn.
C C
R170 1 2 0_0402_5%
<DB>LA1/LA2 closed to Aduio codec
EMI@
L12 @EMI@ D_MIC_CLK 1 2 D_MIC_L_CLK
1 2 USB20_N4_R <23> D_MIC_CLK LA1 FBMA-L10-160808-301LMT_2P
<10> USB20_N4 1 2
Part Number = SM070003Y00 D_MIC_DATA 1 short@ 2 0_0402_5% D_MIC_L_DATA
4 3 USB20_P4_R <23> D_MIC_DATA
<10> USB20_P4 4 3 R175
WCM-2012-900T_4P
R171 1 2 0_0402_5% @ESD@

D3
SCA00000U10
D_MIC_L_CLK 2 CONN@
1 JLVDS1
D_MIC_L_DATA 3 1
<18> LVDS_TXP0 1
2 41
<18> LVDS_TXN0 2 G1
3 42
PESD5V0U2BT_SOT23-3 4 3 G2 43
<18> LVDS_TXP1_LP1 4 G3
5 44
<18> LVDS_TXN1_LN1 6 5 G4 45
7 6 G5 46
<18> LVDS_TXP2_LP0 7 G6
8
<18> LVDS_TXN2_LN0 9 8
10 9
<18> LCD_CLK 11 10
<18> LCD_DATA 11
12
13 12
<18> LVDS_CLKP 13
Touch Screen
eDP@ 14
<18> LVDS_CLKN 14
<18,8> BKL_PWM_CPU R259 1 2 INVTPWM +LCDVDD 15
0_0402_5% 16 15
16
1
LVDS@ 17
<18> EDP_HPD_PANEL 17
R163 18
LVDS@ 19 18
100K_0402_5% 19
<18> DP_INT_PWM R258 1 2 20
0_0402_5% USB20_P5_R 21 20
Touch screen
2
+3VALW +5VALW R166 33_0402_5% USB20_N5_R 22 21
B
EC_TS_BKOFF# 1 2 DISPOFF# DISPOFF# 23 22 B
<18> EC_TS_BKOFF# 23
Touch Screen Power INVTPWM 24
24
1
TS_GPIO 25
25
1
eDP@ @ 26
RTS2 RTS3 R5176 27 26
INVPWR_B+ 27
100K_0402_5% 100K_0402_5% 10K_0402_5% 28
29 28
2
30 29
+VCC_TOUCH
2
31 30
31
1
eDP@ 32
D 32
1
RTS1 eDP@ 33
+3VS 33
1K_0402_5% QTS1 2 USB20_N4_R 34
TOUCH_ON# <25> 34
2N7002K_SOT23 G Camera USB20_P4_R 35
CTS2 36 35
S
2
1 2 D_MIC_L_CLK 37 36
+VCC_TOUCH eDP@ D_MIC_L_DATA 38 37
38
2
39
0.047U_0402_16V7K 39
G
TS_GPIO_CPU R260 1 @ 2 TS_GPIO 40

1 3 1 <9> TS_GPIO_CPU 40
+TOUCH_VCC RTS4 eDP@ 2 0_0402_5% +3VS 0_0402_5%
D
TS_GPIO_EC R261 1 short@ 2 0_0402_5% STARC_107K40-000001-G2

<25> TS_GPIO_EC
1 eDP@ RTS5 1 @ 2 0_0402_5% SP01000XE00
+5VS
CTS1 eDP@
0.1U_0402_16V4Z QTS2
2 S TR LP2301ALT1G 1P SOT-23-3
SI: Reserved 5V power for Touch.

1 R5175 2 0_0402_5%
D6
L13 USB20_P5_R 2
1 @EMI@ 2 USB20_N5_R 1
<10> USB20_N5 1 2 USB20_N5_R 3
Part Number = SM070003Y00
4 3 USB20_P5_R
<10> USB20_P5 4 3 PESD5V0U2BT_SOT23-3
A A
WCM-2012-900T_4P @ESD@ SCA00000U10
1 2 0_0402_5%
R173

LVDS Connector
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C701P 0.1

5 4 3 2 1
5 4 3 2 1
+3VS
PCH_DPB_P0 0.1U_0402_16V7K 1 2 CG27 PCH_DPB_P0_C +HDMI_CRT_5V
<4> PCH_DPB_P0 <21> +HDMI_CRT_5V
PCH_DPB_N0 0.1U_0402_16V7K 1 2 CG28 PCH_DPB_N0_C
<4> PCH_DPB_N0
<12,15,16,18,19,21,22,23,24,25,27,31,32,33,34,35,36,37,56,6,7,8,9> +3VS +3VS
PCH_DPB_P1 0.1U_0402_16V7K 1 2 CG29 PCH_DPB_P1_C
<4> PCH_DPB_P1
<CPU> PCH_DPB_N1 0.1U_0402_16V7K 1 2 CG30 PCH_DPB_N1_C +5VS
<4> PCH_DPB_N1 <19,23,24,25,26,29,33,37,51,54> +5VS
1
RG47
<4> PCH_DPB_P2
PCH_DPB_N2 0.1U_0402_16V7K 1 2 CG32 PCH_DPB_N2_C 1M_0402_5%
<4> PCH_DPB_N2
2
<4> PCH_DPB_P3
2
D PCH_DPB_N3 0.1U_0402_16V7K 1 2 CG34 PCH_DPB_N3_C D
<4> PCH_DPB_N3
1 6 HP_DETECT
<8> PCH_DDPB_HPD
20K_0402_5%
QG1A 1
5
6
7
8
5
6
7
8
1
2N7002KDW _SOT363-6 CM17 @
5V Level RG56 220P_0402_50V7K
2N7002KDW _SOT363-6 2
QG1B
4
3
2
1
4
3
2
1
3 4
2
RP3 RP4
470_0804_8P4R_5% 470_0804_8P4R_5%
5
+3VS
DB phase :
For ESD request
20141117 +3VS
@ESD@
D21
HDMI_R_CK+ 1 1 10 9 HDMI_R_CK+
HDMI_R_CK- 2 2 9 8 HDMI_R_CK-
PCH_DPB_P3_C RG59 1 2 12_0402_5% HDMI_R_CK+
HDMI_R_D0+ 4 4 7 7 HDMI_R_D0+
2
C RG71 @ HDMI_R_D0- 5 5 6 6 HDMI_R_D0- C
5
150_0402_5%
3 3 QG2B
PCH_DDPB_CLK 4 3 HDMI_SCLK
<8> PCH_DDPB_CLK
1
PCH_DPB_N3_C RG60 1 2 12_0402_5% HDMI_R_CK- 8

2N7002DW H_SOT363-6
SB00000DH00
L05ESDL5V0NA-4_SLP2510P8-10-9 +3VS
PCH_DPB_N0_C RG63 1 2 12_0402_5% HDMI_R_D0- SC300002C00
2
RG72 @
2
150_0402_5%
@ESD@
D22 PCH_DDPB_DAT 1 6 HDMI_SDATA
<8> PCH_DDPB_DAT
1
PCH_DPB_P0_C RG61 1 2 12_0402_5% HDMI_R_D0+ HDMI_R_D1- 1 1 10 9 HDMI_R_D1-

2N7002DW H_SOT363-6
HDMI_R_D1+ 2 2 9 8 HDMI_R_D1+ SB00000DH00 QG2A
PCH_DPB_P1_C RG65 1 2 12_0402_5% HDMI_R_D1+
HDMI_R_D2- 4 4 7 7 HDMI_R_D2-
2
RG73 @ HDMI_R_D2+ 5 5 6 6 HDMI_R_D2+ +HDMI_CRT_5V

150_0402_5%
3 3
+3VS
1
PCH_DPB_N1_C RG64 1 2 12_0402_5% HDMI_R_D1- 8 RG105

1 8 HDMI_SDATA
2 7 HDMI_SCLK
PCH_DPB_P2_C RG70 1 2 12_0402_5% HDMI_R_D2+ L05ESDL5V0NA-4_SLP2510P8-10-9 3 6 PCH_DDPB_DAT
B SC300002C00 4 5 PCH_DDPB_CLK B
2
RG74 @ 2.2K_0804_8P4R_5%
150_0402_5% HDMI Conn.
SC300002800
@ESD@ DG1
1
PCH_DPB_N2_C RG66 1 2 12_0402_5% HDMI_R_D2- HP_DETECT 1 1 10 9 HP_DETECT CONN@

JHDMI
HDMI_SDATA 2 2 9 8 HDMI_SDATA HP_DETECT 19
18 HP_DET
SI : EMI request to modify HDMI schematic. HDMI_SCLK 4 4 7 7 HDMI_SCLK
+HDMI_CRT_5V
17 +5V
HDMI_SDATA 16 DDC/CEC_GND
5 5 SDA
6 6 HDMI_SCLK 15
14 SCL
L Layout notes
40 mils
3 3 13
12
Utility
CEC
HDMI_R_CK-
8 @ @ 11 CK-
CK_shield
10P_0402_50V8J
10P_0402_50V8J
W=40mils 1 1 HDMI_R_CK+ 10
IP4292CZ10-TB CM26 CM27 HDMI_R_D0- 9 CK+
FG1 +HDMI_CRT_5V D0-
8
HDMI_R_D0+ 7 D0_shield
3 2 2 HDMI_R_D1- 6 D0+
OUT 5 D1-
1 HDMI_R_D1+ 4 D1_shield 23
+5VS IN D1+ GND1
1 HDMI_R_D2- 3 22
2 2 D2- GND2 21
GND HDMI_R_D2+ 1 D2_shield GND3 20
CG46 D2+ GND4
A
0.1U_0402_16V7K 2 ACON_HMRBL-AK120D A
AP2330W-7_SC59-3 DC232004700

HDMI Conn/Level shift
0.1
LA-C701P
5 4 3 2 1
5 4 3 2 1
DP to CRT converter
<19,20,23,24,25,26,29,33,37,51,54> +5VS +5VS
<12,15,16,18,19,20,22,23,24,25,27,31,32,33,34,35,36,37,56,6,7,8,9> +3VS +3VS
<20> +HDMI_CRT_5V +HDMI_CRT_5V
+3VS_CRT
For Power consumption
Measurement
+3VS +3VS_CRT_DVDD CRT@ CRT@ CRT@
+3VS +3VS_CRT C40 C41 C42 C43
D D
10U_0603_6.3V6M
0.1U_0402_16V4Z
1 1 1 1
1U_0402_6.3V6K
JPHW2 R34 1 2 0_0603_5%
1 2 @
1 2 short@ 0.1U_0402_25V6 @ESD@
2 2 2 2 D4
JUMP_43X39 SC300001G00
JP@ CRT_HSYNC_2 6 3 CRT_VSYNC_2
I/O4 I/O2
PV:R34 change to 0-ohm shortpad +HDMI_CRT_5V
5 2
VDD GND
CRT_CLK 4 1 CRT_DATA
I/O3 I/O1
AZC099-04S.R7G_SOT23-6
+3VS_CRT +3VS_CRT_DVDD
@ESD@
D5
SC300001G00
VGA_RE 6 3 VGA_GR
I/O4 I/O2
CRT@ CRT@ +HDMI_CRT_5V
C45 C46 CRT@ CRT@
1 1 C47 C48 5 2
VDD GND
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1
0.1U_0402_16V4Z
10U_0603_6.3V6M
PV:R38 change power for SVTP 3-9.
2 2 4 1 VGA_BL
2 2 I/O3 I/O1
+HDMI_CRT_5V AZC099-04S.R7G_SOT23-6
1
100K_0402_5%
1
2
3
4
R35 CRT@
C CRT@ CRT@ R38 PV : Remove Buffer. 2015-01-27 C
20
2.2K_0804_8P4R_5%
2
U4104
9
RTD2168_SMB_SCL CRT@ R53 1 2 0_0402_5%
1 2 0_0402_5% EC_SMB_CK2 <18,25,36,7>
RTD2168_SMB_SDA CRT@ R54
DVCC_33
DVCC_33
VDD_DAC_33
EC_SMB_DA2 <18,25,36,7>
8
7
6
5
<8> DDI2_HPD 1
HPD R39 1 @ 2 0_0402_5% 2014-11-24
PCH_SMBCLK <15,16,18,6,7> follow vendor suggest change 36 ohm
C49 CRT@ 1 2 0.1U_0402_16V7K DDI2_AUX_DN_C 27 6 CRT_DATA R40 1 @ 2 0_0402_5%
<8> DDI2_AUX_DN AUX_N VGA_SDA PCH_SMBDATA <15,16,18,6,7>
C52 CRT@ 1 2 0.1U_0402_16V7K DDI2_AUX_DP_C 26 4 CRT_CLK
<8> DDI2_AUX_DP AUX_P VGA_SCL 8 HSYNC
C50 CRT@ 2 1 0.1U_0402_16V7K PCH_DPC_P0_C 29 HSYNC 7 VSYNC
<4> PCH_DPC_P0 LANE0P VSYNC
C53 CRT@ 2 1 0.1U_0402_16V7K PCH_DPC_N0_C 30
<4> PCH_DPC_N0 LANE0N 15 VGA_RED CRT@
C51 CRT@ 2 1 0.1U_0402_16V7K PCH_DPC_P1_C 31 RED_P HSYNC 1 2 CRT_HSYNC_2
<4> PCH_DPC_P1 LANE1P
C54 CRT@ 2 1 0.1U_0402_16V7K PCH_DPC_N1_C 32 12 VGA_GRN L5 36_0402_1%
<4> PCH_DPC_N1 LANE1N GREEN_P CRT@
10 VGA_BLU VSYNC 1 2 CRT_VSYNC_2
BLUE_P L6 36_0402_1% 1 1
22 POL1_SDA CRT@ CRT@
POL1_SDA 23 POL1_SCL C56 C57
POL2_SCL +3VS_CRT +3VS_CRT 10P_0402_50V8J 10P_0402_50V8J
+VCCK_1V2 19 2 RTD2168_SMB_SCL 2 2
VCCK_12 SMB_SCL 3 RTD2168_SMB_SDA
+3VS_CRT_DVDD 24 SMB_SDA
C58 C59 AVCC_33
1 1
1
CRT@ CRT@ C60 CRT@ +VCCK_1V2 25
1 CRT@ C61 CRT@ AVCC_12
LDO_EN
21 LDO_EN_1V2 CRT@ L Layout notes
R61,R62,R58,R59 close to RTD2168
0.1U_0402_16V4Z
10U_0603_6.3V6M
C63 28 @ R42 R43

2.2U_0402_6.3V6M
0.1U_0402_16V4Z
2 2 1 RRX
1 4.7K_0402_5% 4.7K_0402_5% R55,R57,R60,R56 close to CONN
0.1U_0402_16V4Z
CRT@ 18 XTALOUT_2168
1
2
2 R44 11 XO
2 13 BLUE_N 17 XTALIN_2168
2
12K_0402_1%
14 GREEN_N XI/CKIN POL1_SDA POL1_SCL

16 GND_DAC
33 RED_N
2
EPAD_GND
1
RTD2168-CG_QFN32_5X5 CRT@
R45 @ R46
B B
4.7K_0402_5% 4.7K_0402_5%
2
XTALOUT_2168
R47 @
1M_0402_5%
XTALIN_2168
50 impedance CRT Connector
PV:Change L7,L8,L9 value and footprint.
+3VS_CRT |← →| CONN@
JCRT1
X1 @ 6
Crystal L7 EMICRT@ 11
3 4 VGA_RED 1 2 VGA_RE 1
@ OUT GND @ BLM15BA220SN1D_0402 SM01000LM00 7
1
C64 2 1 C65 L8 EMICRT@ CRT_DATA 12

GND IN VGA_GRN 1 2 VGA_GR 2
1
18P_0402_50V8J
18P_0402_50V8J
1 R48 BLM15BA220SN1D_0402 SM01000LM00 8 16

G
27MHZ_10PF_X3G027000BA1H-U 4.7K_0402_5% L9 EMICRT@ CRT_HSYNC_2 13 17
CRT@ VGA_BLU 1 2 VGA_BL 3 G
2
2 BLM15BA220SN1D_0402 SM01000LM00 9
+HDMI_CRT_5V
R49 75_0402_1%
R50 75_0402_1%
R51 75_0402_1%
2 CRT_VSYNC_2 14
1
LDO_EN_1V2 1 1 1 1 1 1 W=10mils 1 C72 4
0.1U_0201_10V6K
SI：Change BOM con/ig C66 C67 C68 C69 C70 C71 10
EMICRT@
EMICRT@
EMICRT@
EMICRT@
EMICRT@
EMICRT@
@ CRT_CLK 15
3.3P_0402_50V_C
3.3P_0402_50V_C
3.3P_0402_50V_C
3.3P_0402_50V_C
3.3P_0402_50V_C
3.3P_0402_50V_C
5
1
2 2 2 2 2 2 2
CRT@ 2
@ C-K_80454-5K1-152
R52 DC060004S10
CRT@
CRT@
4.7K_0402_5%
2
A A

Issued Date 2014/02/18 2015/02/20 Title
Deciphered Date
DP to CRT RTD2168
Custom 0.1
LA-C701P
5 4 3 2 1
5 4 3 2 1
<12,19,24,25,26,28,29,32,37,48,50,53,56,7> +3VALW +3VALW
<28> +LAN_VDD_3V3 +LAN_VDD_3V3 RTL8166EH (LDO mode):

<12,15,16,18,19,20,21,23,24,25,27,31,32,33,34,35,36,37,56,6,7,8,9> +3VS +3VS
Pin3,22,24 is NC , Internal LDO output is Pin30.
Pin30 supply 1.05V to Pin8.
JPHW1 need to short LDO mode Switcing mode
JPHW1
1 2 JP@
LL1 @ @
RTL8166EH (LDO mode)
1 2
+LAN_VDD_3V3 Rising time CL2 @ @
JUMP_43X79
+3VALW
@ UG2 need>0.5mS and <100mS LL2 @ SMT
CL3 @ SMT +LAN_VDD_1V0
5 1 @
IN OUT +LAN_VDD_3V3
LL1 1 2 0_0603_5%
D D
2
@ GND
1 RL1 20_0201_5% 1 4 3 8111@ LL2
SS EN +LAN_REGOUT 1 2
Main SA000028Y10
1U_0402_6.3V6K
1U_0402_6.3V6K
CL1 @ 2.2UH +-5% NLC252018T-2R2J-N
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
4.7U_0603_6.3V6K
G5243AT11U SOT-23 2nd SA00006EE00 1 1 1 1 1 1 1 1
0.1U_0402_16V7K
1500P_0402_50V7K 2 SA000028Y10 @ CL7 @
CL3
8111@ CL4
3rd SA00003AR00 1
CL5 CL6 CL9 CL8 CL11
8111@
CL2 8111@ 8111@
2 2 2 2 2 2 2 2
RL2 2 @ 1 LAN_PWR_EN_R 2
<9> LAN_PWR_EN
10K_0402_5%
1
@ CL12
+LAN_VDD_3V3 +VDDREG
2
0.1U_0402_16V7K
L Layout notes
LL2, CL3, CL4 for Switcing mode L
Layout notes
Place CL5~CL6 close UL1 Pin 3 , 8
CL8 & CL18 close LL2 Place CL7 CL9 close UL1 Pin 22
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
CL3,CL4 close LL2 pin2 Place CL8 CL11 close UL1 Pin 30 +LAN_VDD_3V3
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
@
1
@
1 1 1
8111@
1 1 SI phase : DB phase :
CL17
CL18
CL13 CL14 CL15 CL16 change net name form +LAN_VDD_3V3 to +VDDREG follow vender suggest reserve PU 10K to LAN_3V
1
8111@
2 2 2 2 2 2 20141213 20141117 RL5
@ 10K_0402_5%
2
LED1/GPO
UL1
8111@
RTL8111HSH-CG
L Layout notes
CL15 & CL16 close to UL1: Pin 11,32
L Layout notes SA000084T00
8166@ PV phase :
CL13 close to UL1: Pin 11 CL17 & CL18 close to UL1: Pin 23 UL1 +LAN_VDD_1V0
C
Remove for NOT using SWR mode. LL3,RL13 change to 0-ohm shortpad. C
CL14 close to UL1: Pin 32 20150125
LAN_MDIP0 1 3
LAN_MDIN0 2 MDIP0 AVDD10 8
LAN_MDIP1 4 MDIN0 AVDD10 30 +LAN_VDD_3V3
SI phase :
LAN_MDIN1 5 MDIP1 AVDD10 22 +LAN_VDD_3V3 Need to pop LL3 for LAN 1V regout XTLI
LAN_MDIP2 6 MDIN1 DVDD10
LAN_MDIN2 7 MDIP2 11
20141213 RG119 DIS@ 0_0402_5%
LAN_MDIP3 9 MDIN2 AVDD33 32 2 1 XTLO 1 2
MDIP3 AVDD33 XTLO_R <28>
DB phase : LAN_MDIN3 10 @ 1M_0402_5% RL3
MDIN3 23 +VDDREG 0_0805_5% 2 short@ 1 LL3 RL4 10K_0402_5% UMA@
Reserve PU 10K by LAN vendor suggest VDDREG(VDD33) 24 +LAN_REGOUT 2 1
+LAN_VDD_3V3
RL6 1 short@ 2 LAN_CLKREQ#_R 12 REGOUT
in CPU page <7> LAN_CLKREQ#
0_0201_5% 19 CLKREQB RTL8166CG 21 LANWAKEB 0_0201_5% 2 1 RL13
<25,27,31,35,6,8> PLT_RST# PERSTB LANWAKEB EC_PME# <25,9>
20141112 ISOLATEB
20 EC_LAN_ISOLATEB# short@ SI：Change BOM con/ig
15
<7> CLK_PCIE_LAN REFCLK_P
3
16 27 LAN_ACT# YL1
<7> CLK_PCIE_LAN# REFCLK_N LED0
10P_0402_50V8J
10P_0402_50V8J
26 LED1/GPO TH2 1 1
OSC
OSC
13 LED1/GPO 25 LED_LINK_LAN# CL19 CL20
<10> PCIE_PTX_C_DRX_P3 14 HSIP LED2(LED1) UMA@ UMA@
<10> PCIE_PTX_C_DRX_N3 HSIN
CR10 1 2 0.1U_0402_10V7K PCIE_PRX_C_DTX_P3 17 28 XTLI
GND
GND
<10> PCIE_PRX_DTX_P3 HSOP CKXTAL1 2 2
Layout notes CR11 1 2 0.1U_0402_10V7K PCIE_PRX_C_DTX_N3 18 29 XTLO UMA@
<10> PCIE_PRX_DTX_N3 HSON CKXTAL2 RSET
+VDDREG=40mil RSET 31 33
L
4
RSET GND
2
+LAN_VDD_3V3=40mil RL9
+LAN_REGOUT=60mil Layout notes 2.49K_0402_1% 25MHZ 10PF 5YEA25000102IF50Q3
L CR10,CR11 close UL1 Pin17,18 SA000063500
1
(SA000063500) 8166GSH 10/100 LDO mode EC_LAN_ISOLATEB# 2 1 +3VS
(SA000084T00) 8111HSH Giga switch mode 1K_0402_5% RL7
1
RL8
15K_0402_5%
2
B B
DB phase : RJ-45 CONN.

For ESD request JLAN1 CONN@
10
TSL1
20141117 +LAN_VDD_3V3 A2_AmberLED+
8111@ LAN_ACT# RL12 1 2 510_0402_5% LAN_ACT#_R 9
GIGA LAN A1_AmberLED-
SP050005L00 Footprint SP050006800 RJ45_TX3- 8
TSL1 8166@ TX3-
RJ45_TX3+ 7
+V_DAC 1 24 D27 @ESD@ TX3+
LAN_MDIN3 2 TCT1 MCT1 23 RJ45_TX3- RP8 LAN_MDIP2 6 3 LAN_MDIN3 RJ45_RX1- 6
LAN_MDIP3 3 TD1+ MX1+ 22 RJ45_TX3+ 1 8 I/O4 I/O2 RX1-
TD1- MX1- 2 7 RJ45_TX2- 5
4 21 3 6 TX2-
LAN_MDIN2 5 TCT2 MCT2 20 RJ45_TX2- 4 5 5 2 RJ45_TX2+ 4
TD2+ MX2+ +3VALW VDD GND TX2+
LAN_MDIP2 6 19 RJ45_TX2+
TD2- MX2- 75_0804_8P4R_1% RJ45_RX1+ 3
7 18 SD300002E80 RX1+
TCT3 MCT3 2
LAN_MDIN1 8 17 RJ45_RX1- CL22 LAN_MDIN2 4 1 LAN_MDIP3 RJ45_TX0- 2
LAN_MDIP1 9 TD3+ MX3+ 16 RJ45_RX1+ SE167100J80 I/O3 I/O1 TX0- 13
TD3- MX3- 10P_1808_3KV AZC099-04S.R7G_SOT23-6 RJ45_TX0+ 1 GND1 14
10 15 1 SC300001G00 TX0+ GND2
LAN_MDIN0 11 TCT4 MCT4 14 RJ45_TX0- 2nd SC300001400 11
TD4+ MX4+ +LAN_VDD_3V3 B2_WhiteLED+
1
LAN_MDIP0 12 13 RJ45_TX0+ EMI@

TD4- MX4-
3
CL23 LED_LINK_LAN# RL11 1 2 510_0402_5% LED_LINK_LAN#_CONN 12

B1_WhiteLED-
YSLC05CH_SOT23-3
ESD@ LANGND 120P_0402_50V8

2
DL1
2
2 1 100 LAN D28 @ESD@
8111@ SP050003P00 LAN_MDIP0 6 3 LAN_MDIP1
CL25 CL26 I/O4 I/O2
DL2 @ESD@
1
0.01U_0402_16V7K
2
0.1U_0402_16V7K (SP050003P00) 10/100
YSLC05CH_SOT23-3
(SP050006800) Giga +3VALW
5 2
1
SC600001X00 VDD GND SCA00000U10

A A
1
LAN_MDIN0 4 1 LAN_MDIN1
I/O3 I/O1
AZC099-04S.R7G_SOT23-6
SC300001G00
2nd SC300001400

LAN 8166G-EH 10/100
0.1
LA-C701P
Date: Monday, February 02, 2015 Sheet 22 of 61
5 4 3 2 1
5 4 3 2 1
<12,15,16,18,19,20,21,22,24,25,27,31,32,33,34,35,36,37,56,6,7,8,9> +3VS +3VS +3VS +DVDD +DVDD_IO +1.5VS

RA2 Need to check 20141110
<12,37,53,6> +1.5VS +1.5VS
1 2 1 2
+5VS LA3
<19,20,24,25,26,29,33,37,51,54> +5VS
.1U_0402_16V7K
CA5
10U_0603_6.3V6M
CA6
.1U_0402_16V7K
CA7
10U_0603_6.3V6M
CA8
short@ SUPPRE_ KC FBMA-10-100505-101T 0402
L Layout notes 0_0603_5% 1 1 1 1 PCB Footprint = R_0402
CA5 CA6 close Pin1

UA1
CA7 CA8 close Pin9 2 2 2 2 <1/25>RA2,LA4 change to 0-ohm shortpad
20
MIC1_R DVDD
1 +DVDD CA9 CA10 close Pin26
19 9
MIC1_L DVDD_IO +DVDD_IO CA12 CA13 close Pin40
CA1 1 2 4.7U_0402_6.3V6M INT_MICR_C 18 26 +5VS_AVDD
INT_MIC RA3 1 2 1K_0402_5% CA4 1 2 4.7U_0402_6.3V6M INT_MICL_C 17 MIC2_R AVDD1 40
MIC2_L AVDD2 +1.5VS_AVDD
D D
31 41
MIC1_VREFO_L PVDD1 +5VS_PVDD +5VS_AVDD +5VS
30 46
<25> MUTE_LED_IN MIC1_VREFO_R PVDD2 +1.5VS_AVDD +1.5VS
+MIC2_VREFO 29 LA4
MIC2_VREFO
1
1 2
11/24 modify mute LED that controled by EC 23 45 SPK_R+ 1 2
10K_0402_5% LINE2_R SPK_OUT_R+
.1U_0402_16V7K
CA9
4.7U_0603_6.3V6K
CA10
24 44 SPK_R- short@ LA5
LINE2_L SPK_OUT_R-
.1U_0402_16V7K
CA12
4.7U_0603_6.3V6K
CA13
RA30 1 2 0_0603_5% SUPPRE_ KC FBMA-10-100505-101T 0402
Internal Speaker 1 2 PCB Footprint = R_0402
2
16 42 SPK_L+ Need to check 20141110
MONO_OUT SPK_OUT_L+ 43 SPK_L- change 30 ohm from vendor suggest
PC_BEEP 12 SPK_OUT_L- 2 1
PCBEEP 20141120 2 1
+3VS 10 33 HPOUT_R RA4 1 2 30_0402_1% HP_OUTR
<6> HDA_SYNC_AUDIO SYNC HPOUT_R 32 HPOUT_L RA5 1 2 30_0402_1% HP_OUTL
Headphone
HDA_RST_AUDIO# 11 HPOUT_L
<6> HDA_RST_AUDIO# RESET#
2 CPVDD 1 @ 2 5 GNDA
+3VS SDATA_OUT HDA_SDOUT_AUDIO <6>
RA6 8 SDATA_IN RA7 1 2 22_0402_5% GNDA
1 2 10U_0603_6.3V6M 7 SDATA_IN HDA_SDIN0 <6>
CA17 4.7K_0402_5% CA11 ALDO_CAP
LDO3-CAP 6 +5VS_PVDD +5VS
4.7U_0603_6.3V6K BCLK HDA_BITCLK_AUDIO <6>
1 CA14 1 2 2.2U_0402_6.3V6M ACPVEE 34 LA6
CPVDD 36 CPVEE 22 1 2
CBN 35 CPVDD LINE1_L 21 TAI-TECH HCB2012VF-601T20 0805
CBN LINE1_R
.1U_0402_16V7K
CA20
.1U_0402_16V7K
CA21
10U_0603_6.3V6M
CA22
10U_0603_6.3V6M
CA23
CA15 1 2 2.2U_0402_6.3V6M CBP 37 48 MIC_JD
CBP SPDIFO/GPIO2
1 1 2 2
15 JDREF RA9 2 1 20K_0402_1%
2 JDREF 28 AVREF CA16 2 1 .1U_0402_16V7K
<19> D_MIC_DATA
3 GPIO0/DMIC_DATA VREF 27 CA18 1 2 10U_0603_6.3V6M PV phase : Remove DA8.
<19> D_MIC_CLK GPIO1/DMIC_CLK LDO1_CAP 39 1 2 10U_0603_6.3V6M 2 2 1 1
CA19
LDO2_CAP 20150119
PLUG_IN# RA10 1 2 39.2K_0402_1% SENSEA 13 25 2 RA29 1 100K_0402_5%
14 SENSE_A AVSS1 38
SENSE_B AVSS2
4 GNDA
DVSS
47 49 add 100k from vendor suggest
+1.5VS +DVDD PDB Thermal Pad
20141120
SI phase :
1
C ALC3227-CG_MQFN48P_6X6 AVREFCA24 1 2 2.2U_0402_6.3V6M C

1
@
RA25 Change JSPK1 connector footprint.
<SI> QA2 change from NMOS to BJT
<PV> QA2 change to QA1.
2.2K_0402_5% 1K_0402_5%
RA26 GNDA GNDA
Internal SPK 20141222
2 2
CONN@
2
B
JSPK1
SPK_R- RA13 1 2 0_0603_5% SPK_R-_CONN 1
1
E
HDA_RST_AUDIO# 3 1 PD# SPK_R+ RA14 1 2 0_0603_5% SPK_R+_CONN 2

2
C
SPK_L- RA15 1 2 0_0603_5% SPK_L-_CONN 3

Part Number = SB000008E10 QA1 @ SPK_L+ RA16 1 2 0_0603_5% SPK_L+_CONN 4 3
4
1
MMBT3904WH_SOT323-3 5
6 G1
1 2 10K_0402_5% Power down (PD#) power stage for save power G2
<25> EC_MUTE#
@ DA3 RA11 0V: Power down power stage wide 40 MIL ACES_50278-00401-001
220P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
CH751H-40PT_SOD323-2 SP02000RR00
3.3V: Power up power stage
2
1 1 1 1
@EMI@ C123
@EMI@ C124
@EMI@ C125
C126
2 2 2 2
@EMI@
Reserve for ESD request.
INT_MIC_R GNDA HP_OUTR_R HP_OUTL_R
2
+MIC2_VREFO
Jack detect
2
B B
DA4
YSLC05CH_SOT23-3 DA6 Combo Mic = High
1
SCA00002900 YSLC05CH_SOT23-3
ESD@ SCA00000U10 Normal HP = Low
RA17
@ESD@ 2.2K_0402_5%
2
MIC_JD 1 2 INT_MIC
1
RA18
1
10U_0603_6.3V6M
CA32
22K_0402_5%
SI: pop DA4 2
GNDA
PV:RA27,RA28 change to 0-ohm shortpad

COMBO AUDIO JACK
JHP CONN@
RA27 1 short@ 2 0_0402_5% HPR, HPL, 15mil Keep 30mil
INT_MIC RA21 1 2 0_0402_5% INT_MIC_R 3
　
HP_OUTL RA22 1 2 0_0402_5% HP_OUTL_R 1
RA28 1 short@ 2 0_0402_5% PC Beep 　
PLUG_IN# 5
1 2 　
CA40 @EMI@ 6
.1U_0402_16V7K 1 2 PC_BEEP_R HP_OUTR RA23 1 2 0_0402_5% HP_OUTR_R 2 　
EC Beep <25> EC_BEEP#
4 　
CA31
.1U_0402_16V7K RA19 7 　
GND
100P_0402_50V8J
CA35
10P_0402_50V8J
CA36
10P_0402_50V8J
CA37
1 2 47K_0402_5% 1 1 1
1
CA38 @EMI@ SB Beep 1 2 1 2 1 2 PC_BEEP YUQIU_PJ750-F07J1BE-A

<9> HDA_SPKR
A .1U_0402_16V7K CA33 CA34 RA24 DC2301411240 A
1
.1U_0402_16V7K .1U_0402_16V7K 22K_0402_5%

@EMI@
@EMI@
@EMI@
2 2 2
1 2 RA20 GNDA
2
CA39 @EMI@ 10K_0402_5%

.1U_0402_16V7K L Layout notes Pin6 and Pin5
2
Normal OPEN
1 2 Close chip Pin12 GNDA GNDA GNDA GNDA
CA29 EMI@
.1U_0402_16V7K
1 2 Security Classification Compal Secret Data Compal Electronics, Inc.

CA30 EMI@ 2013/01/04 2015/01/04 Title
Issued Date Deciphered Date
.1U_0402_16V7K
AUDIO ALC3227-CG
C 0.1
GNDA DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-C701P
5 4 3 2 1
A B C D E
<11,12,25,28,34,37,50,51> +1.05VS +1.05VS <12,15,16,18,19,20,21,22,23,25,27,31,32,33,34,35,36,37,56,6,7,8,9> +3VS +3VS
<12> +1.05V +1.05V <15,19,26,29,30,32,34,37,48,49,56> +5VALW +5VALW
<10,11,12,36,4,6,7,9> +3V_PCH +3V_PCH <12,19,22,25,26,28,29,32,37,48,50,53,56,7> +3VALW +3VALW
1 1
+5VALW TO +5VS SYSON# SUSP
3
+5VS Q18A Q18B
10U_0603_6.3V6M
DMN66D0LDW-7_SOT363-6
22U_0805_6.3V6M
1 1 DMN66D0LDW-7_SOT363-6
C575
CC56
@ SYSON 2 5 SUSP#
<25,49> SYSON SUSP# <25,49,50,53>
4
Q21 2 2
+5VALW 1 14
2 VIN1 VOUT1 13
+5VALW VIN1 VOUT1
SUSP# 3 12 C554 1 2 100P_0402_50V8J
ON1 CT1
4 11
VBIAS GND
SUSP# 5 10 C557 1 2 680P_0402_50V7K
ON2 CT2
+3VALW 6 9 +3VS
7 VIN2 VOUT2 8
2 VIN2 VOUT2 2
15 +5VALW
GPAD 1
10U_0603_6.3V6M
C570
EM5209VF DFN 14P
SA00007PM00 2 RPH16
SYSON 8 1
SUSP 7 2
SYSON# 6 3
SUSP# 5 4
100K_0804_8P4R_5%
+3VALW TO +3VS
+1.05V TO +1.05VS +3VALW TO +3V_PCH

3 3
+1.05V
J1 need to short +1.05VS
JP@ +3VALW Q30 +3V_PCH
J1 AO3413L_SOT23-3
1 2
1 2 +3VALW 3 1
D
JUMP_43X79
20mils
G
2
1
2
C590
R559
100K_0402_5% 1U_0402_6.3V6K
2
1
D
0.1U_0402_16V7K
<25> PCH_PWR_EN 2 1
+1.05V TO +V1.05DX_MODPHY G
C591
S Q31 @
3
2N7002_SOT23-3
2
+1.05V +1.05VS_MODPHY
short@
R570 1 2 0_0805_5%
4 4
PV:R570 change to 0-ohm shortpad

DC Interface
Custom 0.1
LA-C701P
A B C D E
5 4 3 2 1
+3VL +3VALW_EC
LK1 +3VALW_EC
15" DB SI PV MV
<12,15,16,18,19,20,21,22,23,24,27,31,32,33,34,35,36,37,56,6,7,8,9> +3VS +3VS
RK1 FBMA-L11-160808-800LMT_0603 UMA
0.1U_0402_16V7K
0.1U_0402_16V7K
1 2 +3VALW_EC 1 2 +EC_VCCA 0 ohm 15K ohm
<45> +3VALW_EC +3VALW_EC 27K ohm 43K ohm
2
RK4
CK1
CK2
1 1 1
+3VL short@ RK2 DIS
<28,32,46,47,48,6> +3VL
0_0603_5% CK3 100K_0402_1% 12k ohm 20k ohm 33k ohm 56k ohm
RK4
ECAGND
<19,20,23,24,26,29,33,37,51,54> +5VS +5VS 0.1U_0402_16V7K
2 2 2
1
BOARD_ID Board ID control
+3V_EC_VDD
<DB>RK4 change to 12K ==>for 15" DIS
2
ESD@
CK4
D PV:RK1,RK3 change to 0-ohm shortpad 1 short@ 2 +3VL DIS@ <DB>RK4 change to 0 ===>for 15" UMA D
2 1 PLT_RST# RK3 0_0402_5% RK4
20K_0402_1% UMA@
SD034200280 RK4
1
0.1U_0402_16V7K
111
125
15K_0402_1% CH751H-40PT_SOD323-2
22
33
96
67
UK1
9
SD034150280 EC_ACIN 2 1 ACIN <36,47,8>
DK1
VCC_LPC
VCC
VCC
VCC
VCC
AVCC
VCC0
2014-11-14: CK6 2 1 100P_0402_50V8J
+3VALW_EC RK7 2 1 330K_0402_5% EC_RST# 1. remove GPIO00
1 21 EC_+1.05VS_PG <6>
1 2 EC_KBRST# 2 GATEA20/GPIO00 EC_VCCST_PG/GPIO0F 23 2014-11-13:
<7,9> EC_KBRST# KBRST#/GPIO01 BEEP#/GPIO10 EC_BEEP# <23> Pin64 from BOARD_ID to X no support KBL
CK5 0.1U_0402_16V7K <27,9> SERIRQ SERIRQ 3 26 EC_FAN_PWM1
SERIRQ EC_FAN_PWM/GPIO12 EC_FAN_PWM1 <33> Pin66 from X to BOARD_ID
LPC_FRAME# 4 PWM Output 27
<27,7> LPC_FRAME# LPC_FRAME# AC_OFF/GPIO13 Pin76 Pin97 swap
LPC_AD3 5 Pin84 from PM_SLP_S4# to USB_ON#
<27,7> LPC_AD3 LPC_AD3
LPC_AD2 7 Pin68 from +1.05V_VS_PG_PWR to MINI1_LED# RK8
<27,7> LPC_AD2 LPC_AD2
LPC_AD1 8 63 B/I# Pin70 NC , no support VR_HOT# 1 short@ 2 PROCHOT# <4>
<27,7> LPC_AD1 LPC_AD1 VCIN1_BATT_TEMP/AD0/GPIO38 B/I# <46> <51> VR_HOT#
LPC_AD0 10 64 VGA_AC_BATT
LPC_AD0LPC & MISC
Pin72 NC , no support
<27,7> LPC_AD0 VCIN1_BATT_DROP/AD1/GPIO39 VGA_AC_BATT <36> Pin86 NC , no suppout
65 ADP_I 0_0402_5%
ADP_I/AD2/GPIO3A ADP_I <45,47>
CLK_PCI_LPC 12 AD Input 66 BOARD_ID
<7> CLK_PCI_LPC CLK_PCI_EC AD_BID/AD3/GPIO3B
<22,27,31,35,6,8> PLT_RST# PLT_RST# 13 75 ADP_ID
PCIRST#/GPIO05 AD4/GPIO42 ADP_ID <45> D
1
EC_RST# 37 76 EC_PME#_EC_R 0_0201_5% 2 1 R5178 EC_PME# <22,9>
EC_SCI# 20 EC_RST# AD5/GPIO43 short@ H_PROCHOT#_EC 2
<9> EC_SCI# EC_SCI#/GPIO0E
<8> PM_CLKRUN# RK10 1 @ 2 PM_CLKRUN#_R 38 PV:R5178,RK8 change to 0-ohm shortpad G
1 short@ 2 0_0402_5% CLKRUN#/GPIO1D QK1
<31> EC_PCIE_WAKE# S
3
RK6 0_0402_5% 68 2N7002_SOT23-3 <PWR>
DA0/GPIO3C MINI1_LED# <31>
DA Output 70 NMI_DBG#
<26> KSI[0..7] EN_DFAN1/DA1/GPIO3D
KSI0 55 71 TS_GPIO_EC
KSI0/GPIO30 DA2/GPIO3E TS_GPIO_EC <19>
KSI1 56 72 EC_MUTE# SI:EC_MUTE# change from 83 to 72.
KSI1/GPIO31 DA3/GPIO3F EC_MUTE# <23>
KSI2 57
KSI3 58 KSI2/GPIO32 83 EC_SMB_CK3
KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A EC_SMB_CK3 <36>
KSI4 59 84 EC_SMB_DA3 SI:Add EC_SMB_CK3/DA3 for GPU.
C KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B EC_SMB_DA3 <36> C
KSI5 60 85 WLAN_OFF_LED#
KSI5/GPIO35 PSCLK2/GPIO4C WLAN_OFF_LED# <26>
KSI6 61 PS2 Interface 86 USB_ON# USB_ON# <30,32> SI:USB_ON# change from 84 to 86.
KSI7 62 KSI6/GPIO36 PSDAT2/GPIO4D 87 EC_TP_CLK RK22 1 short@ 2 0_0402_5%
<26> KSO[0..17] KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK <26>
KSO0 39 88 EC_TP_DATA RK9 1 short@ 2 0_0402_5% PV:RK22,RK9 change to 0-ohm shortpad
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <26>
KSO1 40 +3VALW
KSO2 41 KSO1/GPIO21
KSO3 42 KSO2/GPIO22 97 ENBKL EC_TP_CLK RK12 1 2 4.7K_0402_5%
KSO4 43 KSO3/GPIO23 ENKBL/GPXIOA00 98 ENBKL <8>
KSO4/GPIO24 WOL_EN/GPXIOA01 WL_PWREN_EC <29>
KSO5 44 99 ME_Flash_EN EC_TP_DATA RK13 1 2 4.7K_0402_5%
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH
ME_Flash_EN <6>
KSO6/GPIO26 Matrix VCIN0_PH1/GPXIOD00 VCIN0_PH <45>
KSO7 46
KSO8 47 KSO7/GPIO27
KSO8/GPIO28 SPI Device Interface
KSO9 48 119
KSO9/GPIO29 MISO/GPIO5B EC_SPI_SO <7>
KSO10 49 120
KSO10/GPIO2A MOSI/GPIO5C EC_SPI_SI <7> +3VL
KSO11 50 SPI Flash ROM 126
KSO11/GPIO2B SPICLK/GPIO58 EC_SPI_CLK <7>
KSO12 51 128
KSO12/GPIO2C SPICS#/GPIO5A EC_SPI_CS0# <7>
KSO13 52
KSO14 53 KSO13/GPIO2D RP12
KSO15 54 KSO14/GPIO2E 73 TOUCH_ON# PCH_PWR_EN 8 1
KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40 TOUCH_ON# <19>
KSO16 81 74 SYS_PWROK SYS_PWROK <6,8> PLT_RST# 7 2
KSO17 82 KSO16/GPIO48 SYS_PWROK/AD7/GPIO41 89 AOAC_PME# EC_ON 6 3
KSO17/GPIO49 GPIO50 AOAC_PME# <8>
90 BAT_CHG_LED DB phase : EC_ACIN 5 4
BATT_CHG_LED#/GPIO52 BAT_CHG_LED <45>
PV:RK6,RK15,RK16 change to 0-ohm shortpad 91 CAP_LOCK#
CAPS_LED#/GPIO53 CAP_LOCK# <26>
<46,47> EC_SMB_CK1
77 GPIO 92 PWR_LED#
PWR_LED# <32>
20141117 100K_0804_8P4R_5%
78 EC_SMB_CLK1/GPIO44 PWR_LED#/GPIO54 93 WLAN_ON_LED#
<46,47> EC_SMB_DA1 EC_SMB_DAT1/GPIO45 BATT_LOW_LED#/GPIO55 WLAN_ON_LED# <26>
RK15 1 short@ 2 0_0402_5% EC_SMB_CK2_R 79 95 SYSON PBTN_OUT# R295 1 @ 2 1K_0402_5%
<18,21,36,7> EC_SMB_CK2 EC_SMB_CLK2/GPIO46 SYSON/GPIO56 SYSON <24,49>
RK16 1 short@ 2 0_0402_5% EC_SMB_DA2_R 80 121 BT_ON_EC
<18,21,36,7> EC_SMB_DA2 EC_SMB_DAT2/GPIO47 VR_ON/GPIO57 BT_ON_EC <31>
127 PCH_DPWROK
DPWROK_EC/GPIO59 PCH_DPWROK <8>
SM Bus
PCH_RSMRST# <8> +3VALW_EC
<8> PM_SLP_S3# PM_SLP_S3# 6 100 PCH_RSMRST# CK7 2 1 100P_0402_50V8J ECAGND
2014-11-13: PM_SLP_S5# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101
Pin16 from MINI1_LED# to PM_SLP_SUS# <8> PM_SLP_S5# GPIO07 GPXIOA04 EC_LID_OUT# <9>
B <8> SUSACK# SUSACK# 15 102 VCIN1_PH VCIN1_PH <45> LID_SW# RK18 2 1 47K_0402_5% B
SI : Add RK27 for leakage of light Pin29 from PM_SLP_SUS# remove
PM_SLP_SUS# 16 GPIO08 VCIN1_ADP_PROCHOT/GPXIOA05 103 H_PROCHOT#_EC +3VS
Pin25 from EC_INVT_PWM remove <8> PM_SLP_SUS# GPIO0A VCOUT1_PROCHOT#/GPXIOA06
Pin19 from EC_+1.05VS_PG to GPU_HOT# PCH_SUSWARN# 17 104 MAINPWON
+5VS <8> PCH_SUSWARN# GPIO0B VCOUT0_MAIN_PWR_ON/GPXIOA07 MAINPWON <48>
Pin21 from GPU_HOT# to EC_+1.05VS_PG 18 105 EC_BKOFF# EC_BKOFF# <18> EC_SMB_CK1 8 1 RP11
19 GPIO0C BKOFF#/GPXIOA08 106 RK25 1 2 0_0402_5% EC_SMB_DA1 7 2
RK27
Pin25 from EC_INVT_PWM remove
<54> GPU_HOT# AC_PRESENT/GPIO0D GPIO GPO GPXIOA09 DGPU_PWR_EN <37,54,8,9>
Pin122 from GPU_THERMAL_DET# to PBTN_OUT# 25 107 PCH_PWR_EN EC_SMB_CK2 6 3
Pin123 from X to PM_SLP_S4# <23> MUTE_LED_IN PWM2/GPIO11 PCH_PWR_EN/GPXIOA10 PCH_PWR_EN <24>
2 1 MUTE_LED_OUT FAN_SPEED1 28 108 1.05V_VS_PG_PWR 2014-11-13: EC_SMB_DA2 5 4
Pin18 remove <33> FAN_SPEED1 FAN_SPEED1/GPIO14 PWR_VCCST_PG/GPXIOA11 1.05V_VS_PG_PWR <50> Pin108 from USB_ON# to +1.05V_VS_PG_PWR
29
100K_0402_5%
Pin36 remove no support USB CHR
E51TXD_P80DATA 30 FANFB1/GPIO15 Pin106 NC , no support
2.2K_0804_8P4R_5%
<31> E51TXD_P80DATA EC_TX/GPIO16 2014-11-18
E51RXD_P80CLK 31 110 EC_ACIN Pin108 from +1.05V_VS_PG_PWR to VGA_AC_BATT
RK26 <31> E51RXD_P80CLK EC_RX/GPIO17 VCIN1_AC_IN/GPXIOD01
PCH_PWROK 32 112 EC_ON 2014-11-24
<8> PCH_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON <48>
2 1 E51TXD_P80DATA AC_LED# 34 114 ON/OFF# Pin108 from VGA_AC_BATT to 1.05V_VS_PG_PWR EC_SCI# 10K_0402_5% 2 @ 1 RK14
<45> AC_LED# SUSP_LED#/GPIO19 ON/OFF#/GPXIOD03 ON/OFF# <32>
<26> MUTE_LED_OUT MUTE_LED_OUT 36 GPI 115 LID_SW# LID_SW# <32>
100K_0402_5% NUM_LED#/GPIO1A LID_SW#/GPXIOD04 116 SUSP#
SUSP#/GPXIOD05 SUSP# <24,49,50,53>
117 GPXIOD06 RK24 1 388N@ 2 0_0402_5% +1.05VS 1.05V_VS_PG_PWR 10K_0402_5% 2 1 RK23
GPXIOD06 118 EC_PECI RK17 1 2 43_0402_1%
PECI/GPXIOD07 H_PECI <4>
<6,8> PBTN_OUT# PBTN_OUT# 122
PM_SLP_S4# 123 PBTN_OUT#/GPIO5D 124 +V18R RK28 1 2 0_0402_5% 2014-11-25 2014-11-24
<8> PM_SLP_S4# PM_SLP_S4#/GPIO5E V18R/VCC_IO2 +3VALW_EC
RK19 100K_0402_5% 1 9022@ Reserve for co-lay Nuvoton NPCE388N +1.05VS PU 10K From Power
AGND
1 @ 2 PCH_DPWROK CK8 UK1.124 2014-12-24

GND
GND
GND
GND
GND
KBC 9012/Nuvoton : +V18R RK24 pull high +1.05VS for Nuvoton NPCE388N.
1 @ 2 PCH_PWROK 4.7U_0603_6.3V6K KBC 9022 : +3VALW_EC Add RK28 for NPCE388N , for clean power.
RK20 100K_0402_5% KB9022QD_LQFP128_14X14 2
11
24
35
94
113
69
+3VALW_EC
20mil
1
LK2
RK21 ECAGND 2 1
10K_0402_5% FBMA-L11-160808-800LMT_0603
2
ECAGND <45>
A A
NMI_DBG# 1 2 NMI_DBG#_CPU <9>
DK2
CH751H-40PT_SOD323-2

EC ENE-KB9022
Custom 0.1
LA-C701P
5 4 3 2 1
<12,19,22,24,25,28,29,32,37,48,50,53,56,7> +3VALW +3VALW
<15,19,24,29,30,32,34,37,48,49,56> +5VALW +5VALW
TP Button BD Connector
+3VALW <25> KSI[0..7]
CONN@ KSI7
JTP1
KSI6
KSI5
Keyboard conn
1 KSI4
2 1 KSI3
<25> TP_CLK 2
3 KSI2 JKB1
<25> TP_DATA 4 3 1
KSI1 KSI1
5 4 KSI0 KSI7 2 1
<7> TP_SMBCLK 5 2
6 KSI6 3
<7> TP_SMBDATA 7 6 4 3
KSO9
8 G1 KSI4 5 4
G2 KSI5 6 5
<25> KSO[0..17] 6
KSO17 KSO0 7
PS2+SMBus JXT_FP202DH-006M10M
7
2
SP01001YK00 KSO16 KSI2 8

DM5 KSO15 KSI3 9 8
KSO14 KSO5 10 9
YSLC05CH_SOT23-3 10
KSO13 KSO1 11
SCA00000U10 11
KSO12 KSI0 12
@ESD@ KSO11 KSO2 13 12
KSO10 KSO4 14 13
KSO9 KSO7 15 14
KSO8 KSO8 16 15
1
KSO7 KSO6 17 16
KSO6 KSO3 18 17
KSO5 KSO12 19 18
KSO4 KSO13 20 19
KSO3 KSO14 21 20
KSO2 KSO11 22 21
KSO1 KSO10 23 22
KSO0 KSO15 24 23
KSO16 25 24
KSO17 26 25
27 26
+5VS 27
CAP_LOCK# R203 1 2 3.3K_0402_5% 28
<25> CAP_LOCK# 28
<25> MUTE_LED_OUT R207 1 2 3.3K_0402_5% 29
+5VALW +5VALW WLAN_OFF_LED# 30 29
WLAN_ON_LED# 31 30 33
32 31 G1 34
+5VS 32 G2
1 ACES_50690-0320N-P01
@EMI@ CAP_LOCK# CONN@ SP01001RG00
C134 MUTE_LED_OUT
470P_0402_50V8J
2
2014-11-24
1 1
BOM control
CC122 CC123
1
Amber White 2
100P_0402_50V8J
2
100P_0402_50V8J
ESD@ ESD@
R157 R158
3.3K_0402_5% 3.3K_0402_5%
2
<25> WLAN_OFF_LED# WLAN_ON_LED# <25>

ESD@
KSI0 C193 2 1 100P_0402_50V8J

KB/TP
B 0.1
LA-C701P
5 4 3 2 1
<12,15,16,18,19,20,21,22,23,24,25,31,32,33,34,35,36,37,56,6,7,8,9> +3VS +3VS
D D
TPM2.0 Screw Hole

+3VS H4 H1 H2 H14 H12 H6 H5 H3
H_2P5 H_2P5 H_2P5 H_2P8 H_2P8 H_2P5 H_2P5 H_2P8
TPM@
R26 1 2 0_0402_5% +3VS_TPM HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
@ @ @ @ @ @ @ @
1
0.1U_0402_16V4Z
1 TPM@ 1 @ 1 @ 1
@ C35 C36 C37 GNDA
C34
0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2
C C
0.1U_0402_16V4Z
H15 H16 H17 H11 H9 H10

TPM@ H_5P0 H_5P0 H_5P0 H_5P0 H_5P0 H_5P0
U4
26 5 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
<25,7> LPC_AD0 LAD0 VDD
23 10
<25,7> LPC_AD1 20 LAD1 VDD 19
<25,7> LPC_AD2 17 LAD2 VDD 24 @ @ @ @ @ @
<25,7> LPC_AD3
1
LAD3 VDD
22
<25,7> LPC_FRAME# LFRAME#
16
<22,25,31,35,6,8> PLT_RST# LRESET#
27 1
<25,9> SERIRQ SERIRQ NC
21 2
<7> CLK_PCI_TPM LCLK NC 3
R29 1 @ 2 4.7K_0402_5% 6 NC 8
+3VS_TPM GPIO NC
1 @ 2 7 9 R28 2 TPM@
TPM@1 PLT_RST# H19 H8 H18 H7
R27 PP NC 12 0_0402_5% H_3P0X2P4N H_2P4N H_3P0X2P4N H_2P5
4.7K_0402_5% 4 NC 13
11 GND NC 14 HOLEA HOLEA HOLEA HOLEA
18 GND NC 15
GND NC
1
25 28
R31 GND NC @ @ @ @
B B
1
TPM@ 4.7K_0402_5% SLB9665TT2.0-FW-5.00_TSSOP28
2
Change to NPTH
FD3 FD4 FD2 FD1
SLB9665 (SA00007XU00 )-->TPM2.0 @ @ @ @
1
SLB9660 (SA00007AB00 ) -->TPM1.2 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
A A

TPM/Screw
Document Number Rev
0.1
LA-C701P
5 4 3 2 1
5 4 3 2 1
<36,37,38,56> +1.8VS_VGA +1.8VS_VGA
<11,12,24,25,34,37,50,51> +1.05VS +1.05VS

BOM control <22> +LAN_VDD_3V3 +LAN_VDD_3V3
<25,32,46,47,48,6> +3VL +3VL

Platform Silego P/N Compal PN 25MHz(A) 32.768KHz 24MHz(B) 27MHz 8MHz Remark <12,19,22,24,25,26,29,32,37,48,50,53,56,7> +3VALW +3VALW
<6> +RTCBATT +RTCBATT

D
Intel ULT UMA SLG3NB3455VTR SA00008IQ00 1 1 1 X X @ <12,6,8> +RTCVCC +RTCVCC
D
Intel ULT Dis SLG3NB3456VTR SA00008J800 1 1 1 1 X DIS@ 20141120 vendor recommend

1. AMD GPU power rail should be 1.8V, please modify +3VS_VGA to AMD GPU power rail.
2. CG47, CG48, CG49, CG50 and CG51 must placed close to UGCLK1.11, UGCLK1.3, UGCLK1.8, UGCLK1.15 and UGCLK1.2.
3. Please place RG114, RG109, RG111 and RG113 close to UGCLK1 for Impedance matching.
Base on A32 32.768KHz use 10ppm, G-CLK 25MHz X'TAL use 10ppm. 4. Modify RG114 Symbol from @ to GCLK@.
5. Change RG109 value from 33ohm to 10ohm.
6. We recommend to add RGxxx and RGyyy for isolated 32.768k and 24M clock tail.
7. We recommend to add CGxx, it is reserved for EMI.
8. We recommend to change CG54 Symbol from GCLK@ to @.
+RTCBATT
+RTCVCC
1
RG106 DIS@
1
330_0402_5%
+1.8VS_VGA +1.05VS +LAN_VDD_3V3 +3VL +3VALW RG107 @
0_0402_5%
2
1 1 DIS@ 1 DIS@ 1 DIS@ 1 DIS@
2
Depop if GCLK DIS@
L
2.2U_0603_6.3V6K
CG47 CG48 CG49 CG50 CG51 Layout notes
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
C with UMA 0.1U_0402_10V7K 1 C

CG52 1
2 2 2 2 2 22U_0805_6.3V6M Please place RG114, RG109, RG111 and RG113 close to UGCLK1 for Impedance matching.
CG53
DIS@
DIS@ 2 DIS@
UGCLK1 2
20141120
GCLK_VRTC 10 14 RTC_VOUT add RG115 RG116 isolated GreenCLKtail Change RG109 to 10 ohm recommend by vender
L Layout notes 15
VBAT VDD_RTC_OUT from vendor suggest
+3VL
CG47 Close UGCLK1.11 +V3.3A
2 DIS@ DIS@
CG48 Close UGCLK1.13 +3VALW VDD 9 PCH_RTCX1_R 1 2 1
PCH_RTCX1_R_R 2
CG49 Close UGCLK1.8 32kHz RG114 0_0402_5% RG115 0_0402_5%
PCH_RTCX1 <6> <CPU> YC1 P6
CG50 Close UGCLK1.15 DIS@
+1.8VS_VGA
11 12 VGA_X1_R 1 DIS@ 2 XTALIN_R 1 2 <GPU> Y6 P37
CG41 Close UGCLK1.2 VDDIO_27M 27MHz XTALIN <36>
SI phase 20141225 +LAN_VDD_3V3
8
VDDIO_25M_A 25MHz_A
6 LAN_X1_R
RG109 10_0402_5%
1 DIS@ 2 33_0402_5% XTLI_R
RG110
1 2
0_0402_5%
XTLO_R <22> <LAN> YL1 P22
Change YG1 PN to SJ10000FO00 +1.05VS
3
VDDIO_25M_B 25MHz_B
5 PCH_X1_R 1
RG111
2 PCH_X1_R_R 1
DIS@
2
RG112 DIS@
CPU_XTAL24_IN <7>
0_0402_5%
<CPU> YC2 P7
DIS@ RG116 0_0402_5%
1
CLK_X1 1 RG113 0_0402_5%
CLK_X2 16 XTAL_IN CG54
XTAL_OUT
GND1
GND2
GND3
GND4
5P_0402_50V8C
2
@
S CRYSTAL 25MHZ 12PF +-10PPM RP25000099
SJ10000FO00 S IC SLG3NB3456VTR TQFN 16P CRYSTAL Layout notes
L
4
7
13
17
SA00008J800
YG1 DIS@ For isolated GreenCLK tail
4 3 CLK_X2 RG110 close to Y6 (27M for GPU)
GND OUT
2 2
DIS@ 1 2 DIS@ RG112 close to YL1 (25M for LAN)
CG59 IN GND CG58 @ VGA_X1_R
UGCLK1
RG115 close to YC1 (32.768k for CPU)
12P_0402_50V8J 15P_0402_50V8J
1 1 RG116 close to YC2 (24M for CPU)
1
SA00008IQ00
CLK_X1 S IC SLG3NB3455VTR TQFN 16P CRYSTAL CG57
B
5P_0402_50V8C B
2
@
<SI> Change CG59 to 12pf , CG58 to 15pf recommend by vender
L Layout notes
Place CG57 between UGCLK1 and RG109
Reserve CG55 for vendor Place between UGCLK1 and RG113
PCH_X1_R
1
CG55
5P_0402_50V8C
2
@
A A

GCLK
0.1
LA-C701P
5 4 3 2 1
5 4 3 2 1
<19,20,23,24,25,26,33,37,51,54> +5VS +5VS
2.5" SATA HDD <15,19,24,26,30,32,34,37,48,49,56>
<12,19,22,24,25,26,28,32,37,48,50,53,56,7>
+5VALW
+3VALW
+5VALW
+3VALW
<31> +3VS_WLAN_R +3VS_WLAN_R

D D
CONN@
JHDD
1
+5VS_HDD1 1
+5VS 2
C155 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 3 2
<6> SATA_PTX_DRX_P0 3
short@ <6> SATA_PTX_DRX_N0 C156 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 4
R201 1 2 0_0805_5% 5 4
+5VS_HDD1 5
C153 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 6 9
R202 1 short@ 2 0_0805_5% <6> SATA_PRX_DTX_N0 C154 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P0 7 6 G1 10
<6> SATA_PRX_DTX_P0 8 7 G2
8
ACES_51524-0080N-001
HDD power on sub board. SP01001A900
PV : Change R201,R202 to 0-ohm shortpad.

20150125
SI : Change HDD pin define.
C
Follow Cocoa. 12/25 C
2.5" SATA ODD

+5VS ODD power on sub board.
+5VS_ODD
B U20 CONN@ B
10U_0603_6.3V6M
C227
10U_0603_6.3V6M
1 1 1 14 JODD
@ 2 VIN1 VOUT1 13 CS11 2 1 0.01U_0402_16V7K SATA_PTX_C_DRX_P1 1
VIN1 VOUT1 <6> SATA_PTX_DRX_P1 1
C229
C226 <6> SATA_PTX_DRX_N1 CS14 2 1 0.01U_0402_16V7K SATA_PTX_C_DRX_N1 2

3 12 1 2 3 2
2 2 <9> ODD_PWR ON1 CT1 2 1 0.01U_0402_16V7K 4 3
CS15 SATA_PRX_C_DTX_N1
4 11 560P_0402_50V7K <6> SATA_PRX_DTX_N1 CS18 2 1 0.01U_0402_16V7K SATA_PRX_C_DTX_P1 5 4
+5VALW VBIAS GND <6> SATA_PRX_DTX_P1 5
C230 6
5 10 2 1 RC126 1 2 0_0201_5% ODD_PLUG#_R 7 6
<25> WL_PWREN_EC ON2 CT2 +3VS_WLAN_R <6> ODD_PLUG# short@ 8 7
+3VALW +5VS_ODD 8
6 9 100P_0402_50V8J 9
7 VIN2 VOUT2 8 10 9
VIN2 VOUT2 <9> ODD_DA# 10
1U_0603_10V4Z
1
10U_0603_6.3V6M
C228
C223
1 15 11
GPAD 12 GND
1 1 GND
1U_0603_10V4Z
C224
EM5209VF DFN 14P C44 ESD@

2 ACES_51524-0100N-001
2 SA00007PM00
0.1U_0402_25V6
2 2 SP01001AI00
SI : ESD request.
A A

HDD/ODD Conn
Document Number Rev
B 0.1
LA-C701P
5 4 3 2 1
A B C D E
<15,19,24,26,29,32,34,37,48,49,56> +5VALW +5VALW

<10> USB3_TX0_N USB3_TX0_N 2 1 CS2 USB3_TX0_C_N 1 2 USB3TXDN0_C_R
0.1U_0402_16V7K RS2 0_0402_5%
USB3.0 need support 3.5A
CMMI21T-900Y-N
4 3
change USB PWR SW SA00007AO00
+USB_VCCA
4 3 +5VALW low active SGA00002N80
SM070003K00 @EMI@ LM1 US1 W=100mils
1000P_0402_50V7K
150U_B2_6.3VM_R45M
1 2 W=100mils 1
0.1U_0402_16V7K
1 2 OUT
47U_0805_6.3V6M
5
RS1 0_0402_5% IN 2
1
1 GND 1 1
<10> USB3_TX0_P USB3_TX0_P 2 1 CS1 USB3_TX0_C_P 1 2 USB3TXDP0_C_R 4 1 1 1
EN +
CS6
CS22
0.1U_0402_16V7K CS3 3
OCB CS4 CS5
0.1U_0402_16V7K
2
LM1,LM2 2nd : SM070003K00 SY6288D20AAC_SOT23-5 2 2 2 2
1 2 USB3RXDN0_C SA00007AO00
<10> USB3_RX0_N
RS6 0_0402_5%
CMMI21T-900Y-N
4 3 USB_ON# 1 @ 2 0_0402_5% SI Phase:Add CS22,CS4 DB Phase
4 3 <25,32> USB_ON#
RS4
@EMI@ SM070003K00 20141226 add CS22 reserve
1 2
1 2 20141113
LM2
RS3 0_0402_5% @ESD@
1 2 USB3RXDP0_C DM1 SCA00000U10
<10> USB3_RX0_P 2 USB20_N0_C
1
3 USB20_P0_C
YSLC05CH_SOT23-3
2 LM3 2nd : SM070002J00 USB2.0/USB3.0 port 1 2
RS7 0_0402_5% SC300002C00 +USB_VCCA JUSB1 CONN@

1 @EMI@ 2 USB20_P0_C ESD@ DM2 1
<10> USB20_P0 VBUS
USB3RXDN0_C 1 1 10 9 USB3RXDN0_C USB20_N0_C 2
USB20_P0_C 3 D-
2 2 D+
1 WCM-2012-900T_4P 2 USB3RXDP0_C 9 8 USB3RXDP0_C 4
1 2 USB3RXDN0_C 5 GND
LM3 EMI@ 4 4 SSRX-
SM070003Y00 USB3TXDN0_C_R 7 7 USB3TXDN0_C_R USB3RXDP0_C 6 10
4 3 7 SSRX+ GND 11
4 3 5 5 GND GND
USB3TXDP0_C_R 6 6 USB3TXDP0_C_R USB3TXDN0_C_R 8
SSTX- GND
12
USB3TXDP0_C_R 9 13
1 @EMI@ 2 USB20_N0_C 3 3 SSTX+ GND
<10> USB20_N0
RS8 0_0402_5% TAITW_PUBAU1-09FLBS1NN4H0
8
IP4292CZ10-TB
SI : pop DM2.
3 USB2.0 port x 1 3
+USB_VCCA
Conn@
D29
@ESD@ JUSB2
RS15 @EMI@ 0_0402_5% 2 USB20_N1_C 1
1 2 USB20_N1_C 1 USB20_N1_C 2 VBUS
<10> USB20_N1 D-
3 USB20_P1_C USB20_P1_C 3
4 D+
1 2 SHIELD
1 2 WCM-2012-900T_4P YSLC05CH_SOT23-3 5
LM5 EMI@ Part Number = SM070003Y00 6 GND
4 3 7 GND
4 3 8 GND
GND
1 @EMI@ 2 USB20_P1_C TAITW_PUBAU0-04FLBSCNN4H0
<10> USB20_P1
RS16 0_0402_5%
LM5 2nd : SM070002J00
4 4

USB 3.0/2.0 conn
Document Number Rev
B 0.1
LA-C701P
A B C D E
5 4 3 2 1
<12,15,16,18,19,20,21,22,23,24,25,27,32,33,34,35,36,37,56,6,7,8,9> +3VS +3VS
<15,19,24,26,29,30,32,34,37,48,49,56> +5VALW +5VALW
<12,19,22,24,25,26,28,29,32,37,48,50,53,56,7> +3VALW +3VALW
<29> +3VS_WLAN_R +3VS_WLAN_R
D D
+3VS_WLAN
JWLAN1
2
+3VS_WLAN
RN7 DB Phase
4.7K_0402_5%
1 2 For RF request
3 1_GND 3.3V_2 4
<10> USB20_P3 20141117
1
5 3_USB_D+ 3.3V_4 6 +3VS_WLAN
<10> USB20_N3 5_USB_D- LED1#_6 MINI1_LED# <25>
7 8
9 7_GND N/C_8 10
9_N/C N/C_10
1
100P_0402_50V8J
0.1U_0402_25V6
11 12 R5179 R5180
13 11_N/C N/C_12 14 @RF@ @RF@
15 13_N/C N/C_14 16
DB Phase
2
15_N/C LED2#_16 For RF request
1
0.1U_0402_25V6
100P_0402_50V8J
0.1U_0402_25V6
100P_0402_50V8J
17 18 @RF@ @RF@ @RF@ @RF@
19 17_N/C GND_18 20 R5181 R5182 R5183 R5184
21 19_N/C N/C_20 22
20141117
2
+3VS_WLAN 23 21_N/C N/C_22
23_N/C
25 24
33_GND N/C_32
1
27 26
<6> PCIE_PTX_C_DRX_P6 35_PERp0 N/C_34
RN3 <6> PCIE_PTX_C_DRX_N6 29 28
31 37_PERn0 N/C_36 30
10K_0402_5% 39_GND CLink Reset_38 E51TXD_P80DATA <25>
33 32
<6> PCIE_PRX_DTX_P6 41_PETp0 CLink DATA_40 E51RXD_P80CLK <25>
35 34
<6> PCIE_PRX_DTX_N6
2
37 43_PETn0 CLink CLK_42 36

39 45_GND COEX3_44 38
<7> CLK_PCIE_WLAN 41 47_REFCLKP0 COEX2_46 40 RN14 0_0201_5%
<7> CLK_PCIE_WLAN# 49_REFCLKN0 COEX1_48
43 42 1 2 SUSCLK <8>
short@ 45 51_GND SUSCLK_50 44
<7> WLAN_CLKREQ# 53_CLKREK0# PERST0#_52 PLT_RST# <22,25,27,35,6,8> +3VS_WLAN_R +3VS_WLAN
RN13 1 2 0_0201_5% 47 46
<25> EC_PCIE_WAKE# 55_PEWake0# W_DISABLE2#_54 BT_ON_EC <25>
C 49 48 WL_OFF# <10,9> C
MC_WAKE# 51 57_GND W_DISABLE1#_56 50
53 59_N/C N/C_58 52 R271 short@
55 61_N/C N/C_60 54 1 2
PV:RN13 change to 0-ohm shortpad 63_GND N/C_62
0.1U_0402_16V7K
57 56
65_N/C RESERVED_64
1
10P_0402_50V8J
10P_0402_50V8J
CN3
59 58 0_0805_5% 1@
R5185
R5186
67_N/C N/C_66 1
@RF@ @RF@ 61 60 CN2
63 69_GND N/C_68 62
2
65 71_N/C N/C_70 64 4.7U_0603_6.3V6K
DB Phase 67 73_N/C 3.3V_72 66 2 2
For RF request 75_GND 3.3V_74
68
20141117 GND 69
GND 70
NC_70 71
NC_71 PV:R271 change to 0-ohm shortpad
LOTES_APCI0019-P003H
CONN@ SP070010DA0
NGFF and WLAN
+3VS +3VS_WLAN
2
B B
@
RL25
100K_0402_5%
2
G
1 3 MC_WAKE#
<8> PCH_PCIE_WAKE#
D
@
QB8
2N7002H_SOT23-3
Unpop QB4 and RL23 for not support OBFF
A A

WLAN-BT
0.1
LA-C701P
5 4 3 2 1
A B C D E
<25,28,46,47,48,6> +3VL +3VL
Powert Button Connector <15,19,24,26,29,30,34,37,48,49,56> +5VALW +5VALW
<12,15,16,18,19,20,21,22,23,24,25,27,31,33,34,35,36,37,56,6,7,8,9> +3VS +3VS
<12,19,22,24,25,26,28,29,37,48,50,53,56,7> +3VALW +3VALW
+3VL
1
IO BD Connector ( USB2.0,Card reader,HDD & PWR LED ) 1
@EMI@ 1 LID_SW#
11/26 change CONN.
C166 0.1U_0402_16V7K 1
2 CC124
JPWR 100P_0402_50V8J CONN@
1 2 JIO1
1 ESD@
<25> LID_SW# 2 +5VALW 1
3 2 5 2 1
<25> ON/OFF# 3 G1 2
4 6 3
4 G2 +3VL 4 3
E-T_6916K-Q04N-03R 5 4
CONN@ 6 5
R215 +3VS 6
SP01000TB10 7
+3VALW 7
ON/OFF# 2 1 USB20_N6_C 8
USB20_P6_C 9 8
Card reader 10 9
100K_0402_5% USB20_N2_C 11 10
2
@ USB20_P2_C 12 11
@ JPJ6 USB2.0 ( on small BD ) 13 12
JPJ9 <25,30> USB_ON# 13
14
1
2 SHORT PADS SHORT PADS 14 2
SATA_LED# 15 DB phase :
<6,9> SATA_LED# 15
PWR_LED# 16
L Layout notes
JPJ9 place Top layer,
<25> PWR_LED# 17
18
16
17
modify pin define
EMI@ C119
1 18 20141114
JPJ6 place Bottom layer 680P_0402_50V7K 19
G1 20
2 G2
PV phase : CVILU_CF31181D0R4-10-NH
SP011411241
Add C119 for EMI request.
20141130
RS13 @EMI@ 0_0402_5%

1 2 USB20_N2_C
<10> USB20_N2
1 WCM-2012-900T_4P 2
1 2
3 LM4 EMI@ Part Number = SM070003Y00 3
4 3
4 3
1 @EMI@ 2 USB20_P2_C
<10> USB20_P2
RS14 0_0402_5%
RS18 @EMI@ 0_0402_5%

1 2 USB20_N6_C
<10> USB20_N6
1 WCM-2012-900T_4P 2
1 2
LM6 EMI@ Part Number = SM070003Y00
4 3
4 3
1 @EMI@ 2 USB20_P6_C
<10> USB20_P6
RS17 0_0402_5%
4 4

IO CON
Document Number Rev
B 0.1
LA-C701P
A B C D E
A B C D E
<12,15,16,18,19,20,21,22,23,24,25,27,31,32,34,35,36,37,56,6,7,8,9> +3VS +3VS
<19,20,23,24,25,26,29,37,51,54> +5VS +5VS
PV phase :
R5177 change to 0-ohm shortpad.
1 1
+5VS 20150125
1A short@ 40 mils
R5177 +3VS
1 2+FAN1 L Layout notes
C4801 C5214 close to CONN
1
0_0805_5%
RE50
0.1U_0402_16V7K
C5214
10U_0603_6.3V6M
1 1 10K_0402_5% JFAN1
C4801 1
2 1
Close to Connector <25> EC_FAN_PWM1
2
3 2
2 2 <25> FAN_SPEED1 4 3
1 +FAN1
CE24 4
0.01U_0402_25V7K 5
6 GND1
2 GND2
ACES_50271-0040N-001
SP02000TS00
CONN@
+FAN1
2 2
SI phase :
RE51 Modify FAN pin define
1 @ 2 EC_FAN_PWM1
20141214
10K_0402_5%
3 3
4 4

FAN
Document Number Rev
B 0.1
LA-C701P
A B C D E
5 4 3 2 1
<12,15,16,18,19,20,21,22,23,24,25,27,31,32,33,35,36,37,56,6,7,8,9> +3VS +3VS
<15,19,24,26,29,30,32,37,48,49,56> +5VALW +5VALW
DB Phase <11,12,24,25,28,37,50,51> +1.05VS +1.05VS

For ESD request <18,19> +LCDVDD +LCDVDD
D D
@ESD@
20141117
<11,15,16,17,4,49> +1.35V_VDDQ +1.35V_VDDQ
D9
+3VS 1 2 +1.05VS_VCCSATA3PLL
<12,6> +1.05VS_VCCSATA3PLL
CK0402101V05_0402-2 +1.05VS_APPLOPI
<12> +1.05VS_APPLOPI
@ESD@
D10
1 2
CK0402101V05_0402-2 @ESD@
D17
+1.35V_VDDQ 1 2
CK0402101V05_0402-2
@ESD@
DB phase : D18
@ESD@ 1 2
D11 For ESD request
1 2 CK0402101V05_0402-2
+5VALW 20141117
C
CK0402101V05_0402-2 C
@ESD@ @ESD@
D14 D19
+1.05VS_MODPHY 1 2 +1.05VS_VCCSATA3PLL 1 2
CK0402101V05_0402-2 CK0402101V05_0402-2
@ESD@
D20
+1.05VS_APPLOPI 1 2
CK0402101V05_0402-2 DB phase :
For ESD request
20141117
B B
+1.05VS
@ESD@
D15
1 2
CK0402101V05_0402-2 @ESD@
D12
@ESD@ +VCC_CORE 1 2
D16
1 2 CK0402101V05_0402-2
CK0402101V05_0402-2 @ESD@
DB Phase D13
1 2 DB phase :
For ESD request
20141117 CK0402101V05_0402-2 For ESD request
20141117
A @ESD@ A
D8
+LCDVDD 1 2 DB phase :
CK0402101V05_0402-2 For ESD request Security Classification Compal Secret Data Compal Electronics, Inc.
20141117 Issued Date 2013/3/1 Deciphered Date 2015/3/1 Title
ESD RSVD
Vinafix
Document Number Rev
5 4 3 2 1
1 2 3 4 5
<37,38> +1.05VS_VGA +1.05VS_VGA
<12,15,16,18,19,20,21,22,23,24,25,27,31,32,33,34,36,37,56,6,7,8,9> +3VS +3VS
<36,37,38,54> +3VS_VGA +3VS_VGA
U666A DIS@
AC Coupling Capacitor
PCIe Gen3: Recommended value is 220 nF
A A
PCIe Gen1 and Gen2 only: Recommended value is 100 nF
AF30 AH30 PCIE_CRX_GTX_C_P0 0.1U_0402_16V7K 2 1 DIS@ C5187
<10> PCIE_CTX_GRX_P0 PCIE_RX0P PCIE_TX0P PCIE_CRX_GTX_P0 <10>
AE31 AG31 PCIE_CRX_GTX_C_N0 0.1U_0402_16V7K 2 1 DIS@ C5188
<10> PCIE_CTX_GRX_N0 PCIE_RX0N PCIE_TX0N PCIE_CRX_GTX_N0 <10>
AE29 AG29 PCIE_CRX_GTX_C_P1 0.1U_0402_16V7K 2 1 DIS@ C5189

AD28 AF28 PCIE_CRX_GTX_C_N1 0.1U_0402_16V7K 2 1 DIS@ C5190
AD30 AF27 PCIE_CRX_GTX_C_P2 0.1U_0402_16V7K 2 1 DIS@ C5191

AC31 AF26 PCIE_CRX_GTX_C_N2 0.1U_0402_16V7K 2 1 DIS@ C5192
AC29 AD27 PCIE_CRX_GTX_C_P3 0.1U_0402_16V7K 2 1 DIS@ C5193

AB28 AD26 PCIE_CRX_GTX_C_N3 0.1U_0402_16V7K 2 1 DIS@ C5194
No Use GPU Display Port outpud
AB30 AC25
AA31 PCIE_RX4P PCIE_TX4P AB25
PCIE_RX4N PCIE_TX4N U666F DIS@
AA29 Y23
Y28 PCIE_RX5P PCIE_TX5P Y24
PCIE_RX5N PCIE_TX5N AB11
VARY_BL AB12
Y30 AB27 DIGON
W31 PCIE_RX6P PCIE_TX6P AB26
PCIE_RX6N PCIE_TX6N
W29 Y27 AL15

V28 PCIE_RX7P PCIE_TX7P Y26 TXCAP_DPA3P AK14
PCIE_RX7N PCIE_TX7N TXCAM_DPA3N
B B
AH16
V30 W24 TX0P_DPA2P AJ15
U31 NC#V30 NC#W24 W23 TX0M_DPA2N
NC#U31 NC#W23 AL17
TX1P_DPA1P AK16
U29 V27 TX1M_DPA1N
T28 NC#U29 NC#V27 U26 AH18
NC#T28 NC#U26 TX2P_DPA0P AJ17
TX2M_DPA0N
PCI EXPRESS INTERFACE

T30 U24 AL19
R31 NC#T30 NC#U24 U23 NC_TXOUT_L3P AK18
NC#R31 NC#U23 NC_TXOUT_L3N
R29 T26 TMDP

P28 NC#R29 NC#T26 T27
NC#P28 NC#T27 AH20
TXCBP_DPB3P AJ19
P30 T24 TXCBM_DPB3N
N31 NC#P30 NC#T24 T23 AL21
NC#N31 NC#T23 TX3P_DPB2P AK20
TX3M_DPB2N
N29 P27 AH22
M28 NC#N29 NC#P27 P26 TX4P_DPB1P AJ21
NC#M28 NC#P26 TX4M_DPB1N
AL23
M30 P24 TX5P_DPB0P AK22
L31 NC#M30 NC#P24 P23 TX5M_DPB0N
NC#L31 NC#P23 AK24
NC_TXOUT_U3P AJ23
L29 M27 NC_TXOUT_U3N
K30 NC#L29 NC#M27 N26
NC#K30 NC#N26
C ? S3
216-0867030 EXO PRO C
CLOCK
AK30
<7> CLK_PCIE_GPU PCIE_REFCLKP
AK32
<7> CLK_PCIE_GPU# PCIE_REFCLKN +1.05VS_VGA
CALIBRATION
Y22 R5159 1 DIS@ 2 1.69K_0402_1%
PCIE_CALR_TX
R1400 1 DIS@ 2 1K_0402_5% N10 AA22 R717 1 DIS@ 2 1K_0402_1%
TEST_PG PCIE_CALR_RX
GPU_RST# AL27
PERSTB
216-0867030 EXO PRO S3

+3VS_VGA +3VS
1
@
DIS@R1681 R1691
0_0402_5% 0_0402_5%
2
2
5
U6
2 DIS@
P
<8,9> DGPU_HOLD_RST# B 4 GPU_RST#

1 Y
<22,25,27,31,6,8> PLT_RST# A
G
DIS@
3
R1631
MC74VHC1G08DFT2G_SC70-5 100K_0402_5%
D D
2

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AMD EXO_PCIE/DP
Custom 0.1
Date:
LA-C701P
Saturday, January 31, 2015 Sheet 35 of 61
1 2 3 4 5
1 2 3 4 5
+3VS_VGA
<35,37,38,54> +3VS_VGA +3VS_VGA +1.8VS_VGA
EC_SMB_DA2 1 @ 2 VGA_SMB_DA3
PS_0[3:1]=001 Strap Name :
<28,37,38,56> +1.8VS_VGA +1.8VS_VGA
R162 0_0402_5% PS_0[5:4]=11
1
U666B DIS@ U? +3V_PCH PS_0[1] ROM_CONFIG[0]
<10,11,12,24,4,6,7,9> +3V_PCH
1
EC_SMB_CK2 1 @ 2 VGA_SMB_CK3 DIS@
R164 0_0402_5% DIS@R327 DIS@R328 R5165 PS_0[2] ROM_CONFIG[1]
10K_0402_5% 10K_0402_5% 8.45K_0402_1%
AF2 PS_0[3] ROM_CONFIG[2]
2
NC#AF2
2
AF4 PS_0
2
NC#AF4
PS_0[4] N/A
1
6 1 VGA_SMB_DA3 1 N9 AG3
<18,21,25,7> EC_SMB_DA2 T201 1 L9 DBG_DATA16 NC#AG3 AG5 DIS@ PS_0[5] AUD_PORT_CONN_PINSTRAP[0]
T202 1 AE9 DBG_DATA15 NC#AG5
DIS@ Q2416A DPA C=NC R5166
T203 1 Y11 DBG_DATA14 AH3
ME2N7002D1KW-G 2N_SOT363-6 2K_0402_1%
T204 1 AE8 DBG_DATA13 NC#AH3 AH1
2
T205 DBG_DATA12 NC#AH1
5
1 AD9
T206 1 AC10 DBG_DATA11 AK3
A
3 4 T207 1 AD7 DBG_DATA10 NC#AK3 AK1 A
VGA_SMB_CK3
<18,21,25,7> EC_SMB_CK2 T208 1 AC8 DBG_DATA9 NC#AK1
T209 DVO
DIS@ Q2416B 1 AC7 DBG_DATA8 AK5
T210 1 AB9 DBG_DATA7 NC#AK5 AM3
ME2N7002D1KW-G 2N_SOT363-6 Resistor Divider Lookup Lable
T211 1 AB8 DBG_DATA6 NC#AM3
T212 1 AB7 DBG_DATA5 AK6 +1.8VS_VGA
T213 1 AB4 DBG_DATA4 NC#AK6 AM5
PS_1[3:1]=000 Strap Name :
T214 1 AB2 DBG_DATA3 NC#AM5 R_pu (ohm) R_pd (ohm) Bitd [3:1]
T215 DBG_DATA2 DPB PS_1[5:4]=11
1
1 Y8 AJ7
T216 1 Y7 DBG_DATA1 NC#AJ7 AH6 @
PS_1[1] STRAP_BIF_GEN3_EN_A
+3VS_VGA T217 DBG_DATA0 NC#AH6 NC 4.75k 000
R5167 PS_1[2] TRAP_BIF_CLK_PM_EN
AK8 8.45K_0402_1%
NC#AK8 AL7
8.45k 2k 001
PS_1[3] N/A
2
NC#AL7 PS_1
4.53k 2k 010
8
7
6
5
PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING
1
@ RP35 W6 6.98k 4.99k 011
V6 NC#W6 DIS@
10K_8P4R_5% NC#V6 V4 R5168
PS_1[5] STRAP_TX_DEEMPH_EN
AC6 NC#V4 U5
4.53k 4.99k 100 C=NC
4.75K_0402_1%
1
2
3
4
AC5 NC#AC5 NC#U5

3.24k 5.62k 101
2
NC#AC6 W3
VGA_AC_BATT_R AA5 NC#W3 V2
AA6 NC#AA5 NC#V2 3.4k 10k 110
DPC
NC#AA6 Y4
4.75k NC 111
ME2N7002D1KW-G 2N_SOT363-6
NC#Y4
6
W5
@ Q16A
@Q16A NC#W5
U1 AA3
0402 1% resistors are equired
2 W1 NC#U1 NC#AA3 Y2 +1.8VS_VGA
U3 NC#W1 NC#Y2 PS_2[3:1]=000 Strap Name :
Y6 NC#U3 J8 PS_2[5:4]=11
NC#Y6 NC#J8
3
AA1 Capacitor Divider Lookup Lable PS_2[1] N/A

@ Q16B NC#AA1
R=NC
5
PS_2[2] N/A
<25> VGA_AC_BATT Cap (nF) Bitd [5:4]
PS_2
PS_2[3] STRAP_BIOS_ROM_EN
I2C
4
DB phase : 680nF 00 PS_2[4] STRAP_BIF_VGA_DIS
1
R1 1
follow AMD check list R3 SCL
82nF 01 DIS@ DIS@ PS_2[5] N/A
SDA C5203 R5164
B
20141113 AM26
B
10nF 10 0.082U_0402_16V6K 4.75K_0402_1%
R AK26 2
GENERAL PURPOSE I/O
2
T292 1 1 @ 2 GPU_GPIO0 U6 AVSSN#AK26
1 DIS@ 2 U10 GPIO_0 AL25
NC 11
R169 0_0402_5%
R174 0_0402_5% T10 GPIO_1 G AJ25
+3VS_VGA VGA_SMB_DA3 U8 GPIO_2 AVSSN#AJ25
U7 SMBDATA AH24
VGA_AC_BATT_R <25,47,8> ACIN
ACIN 1 @ 2
VGA_SMB_CK3
T9 SMBCLK
GPIO_5_AC_BATT
B
AVSSN#AG25
AG25
T8
R1444 1 @ 2 100K_0402_5% ACIN pull up VGA_AC_BATT_R
R165
1
0_0402_5%
DIS@ 2 T7 GPIO_6
GPIO_7_BLON
DAC1
HSYNC
AH26 PS_3[3:1]=000 +1.8VS_VGA
Strap Name :
R1445 1 DIS@ 2 4.7K_0402_5% VGA_AC_BATT_R R1661 0_0402_5% P10 AJ27
P4 GPIO_8_ROMSO VSYNC
GPIO_9_ROMSI PS_3[5:4]=11
1
DB phase : P2 PS_3[1] BOARD_CONFIG[0] (Memory ID)
N6 GPIO_10_ROMSCK AD22 X76@
follow AMD check list N5 GPIO_11 RSET R5174 PS_3[2] BOARD_CONFIG[1] (Memory ID)
N3 GPIO_12 AG24 8.45K_0402_1%
R1445 keep GPIO_5 PU to +3VS_VGA via 4.7kohm (as default) Y9 GPIO_13 AVDD AE22 PS_3[3] BOARD_CONFIG[2] (Memory ID)
2
20141113 GPU_VID1 N1 GPIO_14_HPD2 AVSSQ PS_3
<54> GPU_VID1 M4 GPIO_15_PWRCNTL_0 AE23
GPIO_16 VDD1DI PS_3[4] AUD_PORT_CONN_PINSTRAP[1]
1
GPU_GPIO17 R6 AD23
W10 GPIO_17_THERMAL_INT VSS1DI X76@
1 GPIO19_CTF M2 GPIO_18 PS_3[5] AUD_PORT_CONN_PINSTRAP[2]
T291 FutureASIC/SEYMOUR/PARK C=NC R5169
GPU_VID2 P8 GPIO_19_CTF AM12 4.75K_0402_1%
+3VS_VGA <54> GPU_VID2 GPU_VID5 P7 GPIO_20_PWRCNTL_1 CEC_1
<54> GPU_VID5
2
N8 GPIO_21
GPU_VID4 AK10 GPIO_22_ROMCSB AK12
<54> GPU_VID4 AM10 GPIO_29 RSVD#AK12 AL11
@ RP34 GPU_VID3
1 8 <54> GPU_VID3 1 2 N7 GPIO_30 RSVD#AL11 AJ11
JTAG_TRSTB VGA_CLKREQ#_R
2 7 JTAG_TDI <7> GPU_CLKREQ# CLKREQB RSVD#AJ11
R167 0_0402_5%
3 6 JTAG_TMS @DIS@ JTAG_TRSTB L6
4 5 JTAG_TCK JTAG_TDI L5 JTAG_TRSTB
JTAG_TCK L3 JTAG_TDI
DB phase : 1
JTAG_TMS L1 JTAG_TCK AL13
10K_8P4R_5% C5213 @DIS@
follow AMD check list 68P_0402_50V8J T70 1 JTAG_TDO K4 JTAG_TMS GENLK_CLK AJ13
Memory ID Memory Type Configuration Size R5174 R5169 X76 P/N
JTAG_TDO GENLK_VSYNC
(default)
R167 non-pop by vendor TESTEN K7
2 AF24 TESTEN
20141113 NC#AF24 AG13
SWAPLOCKA
R1446 1 DIS@ 2 GPIO19_CTF
AB13 SWAPLOCKB
AH12 000 SA00006H400 Hynix H5TC2G63FFR-11C 1GB NC 4.75K X7662732L02
10K_0402_5%
C
R1443 1 DIS@ 2 GPU_CLKREQ# W8 GENERICA C
GENERICB
10K_0402_5% +3V_PCH W9
GENERICC 001 SA000077K00 Micron MT41J256M16HA-093G:E 2GB 8.45K 2K X7654132L0?
R1439 1 DIS@ 2 TESTEN W7 AC19 PS_0
1K_0402_5% AD10 GENERICD PS_0
GENERICE
DB phase : AJ9
NC#AJ9 PS_1
AD19 PS_1 010 SA000068U40 K4W2G1646Q-BC1A FBGA 96P 1GB 4.53K 2K X7662732L04
2
AL9
R1447 1 DIS@ 2 XO_IN follow AMD check list R5121 NC#AL9 AE17 PS_2
PS_2
R1448 1 DIS@ 2
10K_0402_5%
XO_IN2
XO_IN/XO_IN2 must PD @DIS@
10K_0402_5% 1
AC14
AB16 HPD1 AE20 PS_3
011 SA000067500 Micron MT41J128M16JT-093G:K 1GB 6.98K 4.99K X7654132L0?
20141113 T218 PX_EN PS_3
10K_0402_5%
1
GPU_CLKREQ#
AE19
100 SA000076P80 K4W4G1646E-BC1A FBGA 96P 2GB 4.53K 4.99K X7662732L03
1 AC16 TS_A
T221 DBG_VREFG
2
101 SA00006E8A0 H5TC4G63CFR-11C FBGA 96P 2GB 3.24K 5.62K X7662732L01

3
RG118 0_0402_5% R349 @ R5122

XTALIN 1 @ 2 XTALIN_R_R 1 2 XTALOUT @DIS@ 10K_0402_5%
10M_0402_5%
DGPU_PWROK 5
@ DDC/AUX
AE6
110 Nanya NT5CB256M16DP-FL 2GB 3.4K 10K X7654132L0?
1
PLL/CLOCK DDC1CLK AE5

DB phase : Nanya NT5CB128M16FP-FL 1GB X7654132L0?
@ Y6 Q4109B DDC1DATA
111 SA00007PY00 4.75K NC
4
4 3 follow RRR AD2

NC OSC ME2N7002D1KW-G 2N_SOT363-6 AUX1P AD4
1 2
20141118 AUX1N
OSC NC AC11
DDC2CLK AC13
2 27MHZ 10PF +-10PPM 7V27000050 2 DDC2DATA External VGA Thermal Sensor SI:SMBus change to EC_SMB_CK3/DA3 for GPU external sensor.
@ C341 SJ100009700 @ C350
8.2P_0402_50V_NPO 8.2P_0402_50V_NPO AM28 AD13 +3VS_VGA Address:1001100xb (x is R/W bit)
<28> XTALIN AK28 XTALIN AUX2P AD11 +3VS
XTALOUT RP13 @
1 1 XTALOUT AUX2N 8 1 THS_SCL PV:GPU external sensor change to unpop.
SI：Change BOM con/ig XO_IN AC22
XO_IN NC#AD20
AD20 7 2 THS_SDA
+3VS_VGA
R1442 1 DIS@ 2 10K_0402_5% XO_IN2 AB22 AC20 6 3 EC_SMB_CK3
XO_IN2 NC#AC20 +3VS_VGA 5 4 EC_SMB_DA3
AE16
Enable MLPS NC#AE16 AD16 @ 2.2K_0804_8P4R_5%
NC#AD16
2
2 1
SEYMOUR/FutureASIC AC1 CV271 0.1U_0402_16V4Z
RG126 DIS@ 0_0402_5% +1.8VS_VGA THERM_D+ T4 DDCVGACLK AC3 THS_SCL 1 6 EC_SMB_CK3
1 2 T2 DPLUS THERMAL DDCVGADATA EC_SMB_CK3 <25>
L54 DIS@ THERM_D- UV13 @
13mA DMINUS
5
1 2 1 8 Q4110A @
D +3VS BLM15BD121SN1D_0402 VDD SCL ME2N7002D1KW-G 2N_SOT363-6 D
GPIO28 R5 THERM_D+ 2 7 THS_SDA 4 3 EC_SMB_DA3
GPIO28_FDO D+ SDA EC_SMB_DA3 <25>
DIS@C414 2 1 10U_0603_6.3V6M +TSVDD AD17
TSVDD
5
U4107 @ AC17 THERM_D- 3 6 2 @ 1 Q4110B @

TSVSS D- ALERT# +3VS_VGA
2 DIS@C421 2 1 1U_0402_6.3V4Z RV134 2.2K_0402_5% ME2N7002D1KW-G 2N_SOT363-6
P
<56> 1.8V_PWRGD B 4 2 1 4 5
+3VS_VGA @
1 Y DGPU_PWROK <8,9> DIS@C438 2 1 0.1U_0402_10V6K RV133 2.2K_0402_5% T_CRIT# GND 1 2GPU_GPIO17
<54> GPU_PWRGD A
G
R168 @ 0_0402_5%
216-0867030 EXO PRO S3 ? NCT7718W_MSOP8
3
MC74VHC1G08DFT2G_SC70-5
RG125 0_0402_5%
@
1 2 Security Classification Compal Secret Data Compal Electronics, Inc.
AMD EXO_MSIC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
Date:
LA-C701P
Saturday, January 31, 2015
Sheet 36 of 61
1 2 3 4 5
1 2 3 4 5
<15,19,24,26,29,30,32,34,48,49,56> +5VALW +5VALW <11,12,24,25,28,34,50,51> +1.05VS +1.05VS

<12,23,53,6> +1.5VS +1.5VS
+1.5VS to +1.5VS_VGA (2.096A) <38,54,55> +VGA_CORE +VGA_CORE
<38,39,40,41> +1.5VS_VGA +1.5VS_VGA
<35,38> +1.05VS_VGA +1.05VS_VGA
<19,20,23,24,25,26,29,33,51,54> +5VS +5VS <19,47,48,49,51,53,54> +19.5VB +19.5VB

<12,15,16,18,19,20,21,22,23,24,25,27,31,32,33,34,35,36,56,6,7,8,9> +3VS +3VS
+1.5VS <12,19,22,24,25,26,28,29,32,48,50,53,56,7> +3VALW +3VALW
DIS@ +1.5VS_VGA +3VS_VGA
<35,36,38,54> +3VS_VGA
U4101
AO4354_SO8
8 1
7 2
2
0.1U_0402_16V7K
6 3
10U_0603_6.3V6M
1U_0402_6.3V4Z
1 5 1 1 DIS@ U666E DIS@ U?
C4105
C4106
C4107
R4102
10_0603_5%
4
A A
1
2 DIS@ 2 DIS@ 2 DIS@ AA27 A3
370mA (HDMI) No Use GPU Display Port outpud AB24 GND GND A30
GND GND
3
+1.8VS_VGA AB32 AA13
R319 188mA (Display Port) AC24 GND GND AA16
1 2 +DP_VDDR U666G DIS@ AC26 GND GND AB10
U?
1 DIS@ 2 1.5VSG_GATE 5 PXS_PWREN# AC27 GND GND AB15
+19.5VB GND GND
R4101 200K_0402_5% short@ AD25 AB6
C446
C447
DP POWER NC/DP POWER
QV4101B 0_0603_5% AD32 GND GND AC9
1 1
4
GND GND
1
@ 1 DIS@ ME2N7002D1KW-G 2N_SOT363-6 AG15 AE11 AE27 AD6
R4103 C4109 DIS@ AG16 DP_VDDR#AG15 NC#AE11 AF11 AF32 GND GND AD8
0.027U_0402_16V AF16 DP_VDDR#AG16 NC#AF11 AE13 AG27 GND GND AE7
1.5M_0402_5%
0.1U_0402_10V6K
1U_0402_6.3V4Z
PXS_PWREN# 2 2 2 AG17 DP_VDDR#AF16 NC#AE13 AF13 AH32 GND GND AG12
2 PV phase : DP_VDDR#AG17 NC#AF13 GND GND
@
AG18 AG8 K28 AH10
2
DIS@ R319,R320 Change to 0-ohm shortpad. AG19 DP_VDDR#AG18 NC#AG8 AG10 K32 GND GND AH28
SI phase :
1
QV4101A AF14 DP_VDDR#AG19 NC#AG10 L27 GND GND B10
ME2N7002D1KW-G 2N_SOT363-6 Change C4109 from 0.01u to 0.027u 20150125 DP_VDDR#AF14 M32 GND GND B12
N25 GND GND B14
20141214 N27 GND GND B16
P25 GND GND B18
AG20 AF6 P32 GND GND B20
AG21 DP_VDDC#AG20 NC#AF6 AF7 R27 GND GND B22
+1.05VS_VGA AF22 DP_VDDC#AG21 NC#AF7 AF8 T25 GND GND B24
R320 280mA AG22 DP_VDDC#AF22 NC#AF8 AF9 T32 GND GND B26
1 2 +DP_VDDC AD14 DP_VDDC#AG22 NC#AF9 U25 GND GND B6
DP_VDDC#AD14 U27 GND GND B8
short@ V32 GND GND C1
C450
C451
0_0603_5% W25 GND GND C32
1 1 GND GND
AG14 AE1 W26 E28
AH14 DP_VSSR NC#AE1 AE3 W27 GND GND F10
AM14 DP_VSSR NC#AE3 AG1 Y25 GND GND F12
1U_0402_6.3V4Z
0.1U_0402_10V6K
2 2 AM16 DP_VSSR NC#AG1 AG6 Y32 GND GND F14
DP_VSSR NC#AG6 GND GND
@
AM18 AH5 F16
AF23 DP_VSSR NC#AH5 AF10 GND F18
AG23 DP_VSSR NC#AF10 AG9 GND F2
B
+3VS to +3VS_VGA (25mA) AM20
AM22
DP_VSSR
DP_VSSR
NC#AG9
NC#AH8
AH8
AM6 M6
GND
GND
F20
F22
B
AM24 DP_VSSR NC#AM6 AM8 N13 GND GND F24

AF19 DP_VSSR NC#AM8 AG7 N16 GND GND F26
AF20 DP_VSSR NC#AG7 AG11 N18 GND GND F6
AE14 DP_VSSR NC#AG11 N21 GND GND
GND F8
DP_VSSR P6 GND GND G10
P9 GND GND G27
R12 GND GND G31
AF17 AE10 R15 GND GND G8
DIS@ DPAB_CALR NC#AE10 R17 GND GND H14
+3VS U4103 R20 GND GND H17
JG3 GND GND
60mA @ T13 H2
1 7 1 2 T16 GND GND H20
VIN VOUT 1 2 +3VS_VGA GND GND
2 8 216-0867030 EXO PRO S3? T18 H6
VIN VOUT GND GND
0.1U_0402_16V7K
0.1U_0402_16V7K
1 DIS@ 1 T21 J27
JUMP_43X39 GND GND
C4111
C4124
DGPU_PWR_EN 3 6 C4112 1 2 T6 J31
ON CT 470P_0402_50V7K U15 GND GND K11
U17 GND GND K2
2 DIS@ 4 2 DIS@ U20 GND GND K22
+3VALW VBIAS GND GND
5 U9 K6
GND 9 V13 GND GND
GND V16 GND
V18 GND
AOZ1336DI DFN 8P Y10 GND
SA00006U600 Y15 GND
Y17 GND
Y20 GND
R11 GND A32
T11 GND VSS_MECH AM1
AA11 GND VSS_MECH AM32
M12 GND VSS_MECH
N11 GND
V11 GND
GND
C C
216-0867030 EXO PRO?S3
+1.05VS to +1.05VS_VGA (2A)

AMD feedback : +1.05VS DIS@ +1.05VS_VGA +5VALW +VGA_CORE
U4102
Exo ASIC normally is 0.95v , AO4354_SO8
2
8 1 DIS@ DIS@
can support to 1.05v functionally. 7 2 R4113 R4114
2
0.1U_0402_16V7K
6 3 100K_0402_5% 470_0603_5%
10U_0603_6.3V6M
1U_0402_6.3V4Z
1 5 1 1 DIS@
C4113
C4114
C4115
R4107
3 1
6 1
10_0603_5% PXS_PWREN#
4
3 1
2 DIS@ 2 DIS@ 2 DIS@
DGPU_PWR_EN 5 2 PXS_PWREN#
<25,54,8,9> DGPU_PWR_EN
DIS@ DIS@
1
5 PXS_PWREN# Q4105B Q4105A
1
+5VS 1 DIS@ 2 0.95VSG_1.8VGS_GATE DIS@ R4115
R4109 6.98K_0402_5% DIS@Q4102B 100K_0402_5%
4
SI phase : ME2N7002D1KW-G 2N_SOT363-6

1
2
Change R4109 from 200K to 6.98K
6
@ R4104 DIS@ C4122

1.5M_0402_5% 0.22U_0402_10V
D 20141214 D
PXS_PWREN# 2 2
2
DIS@
Q4102A SI phase :
1
Change C4122 from 0.01u to 0.22u
20141214
Title
<56> 0.95VSG_1.8VGS_GATE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AMD EXO_Power/GND
Custom 0.1
Date:
LA-C701P
1 2 3 4 5
1 2 3 4 5
<28,36,37,56> +1.8VS_VGA +1.8VS_VGA
<37,39,40,41> +1.5VS_VGA +1.5VS_VGA
<35,37> +1.05VS_VGA +1.05VS_VGA
<35,36,37,54> +3VS_VGA +3VS_VGA
<37,54,55> +VGA_CORE +VGA_CORE
+1.5VS_VGA
A
+VGA_CORE 10uF 1uF 0.1uF A
C365
C367
C375
C370
C371
C372
C373
C374
1 1 1 1 1 1 1 1
VDDC TBD 5 (1@) 10 (2@) 0 +PCIE_PVDD:
+1.8VS_VGA
U666D DIS@ U? 50mA (PCIE2.0)
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2.2U_0402_6.3V5M
2.2U_0402_6.3V5M
2.2U_0402_6.3V5M
2.2U_0402_6.3V5M
2.2U_0402_6.3V5M
2 2 2 2 2 2 2 2
AM30 80mA (PCIE3.0)
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
VDDCI 3.5A 1 3 0 1A MEM I/O PCIE_PVDD
PCIE
C380
C387
C394
H13 AB23 1 1 1
H16 VDDR1 NC#AB23 AC23
H19 VDDR1 NC#AC23 AD24
J10 VDDR1 NC#AD24 AE24
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
J23 VDDR1 NC#AE24 AE25 2 2 2
+0.95VS_VGA 10uF 1uF 0.1uF J24 VDDR1 NC#AE25 AE26
DIS@
DIS@
DIS@
J9 VDDR1 NC#AE26 AF25
K10 VDDR1 NC#AF25 AG26
K23 VDDR1 NC#AG26
PCIE_VDDC 2.5A 2 (1@) 5 (1@) 0 K24 VDDR1
K9 VDDR1 L23
C389
C390
C391
C381
C392
C3719
C3720
C3721
C3722
C3723
VDDR1 PCIE_VDDC
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
2 2 2 2 2 1 1 1 1 1 L11 L24
L12 VDDR1 PCIE_VDDC L25
BIF_VDDC 1.4A 0 0 0 L13 VDDR1 PCIE_VDDC L26 +PCIE_VDDC:
VDDR1 PCIE_VDDC +1.05VS_VGA
L20 M22 1.88A (PCIE2.0)
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1 1 1 1 1 2 2 2 2 2 L21 VDDR1 PCIE_VDDC N22
DIS@
DIS@
DIS@
DIS@
DIS@
VDDR1 PCIE_VDDC
L22 N23 2.5A (PCIE3.0)
DIS@
DIS@
DIS@
DIS@
DIS@
SPLL_VDDC 100mA 1 1 1 VDDR1 PCIE_VDDC N24
PCIE_VDDC R22
PCIE_VDDC T22
C384
C386
C398
C399
C383
C403
C388
C3724
C3725
+1.8VS_VGA 13mA LEVEL PCIE_VDDC U22 1 1 1 1 1 1 1 1 1
1U_0402_6.3V6K
1U_0402_6.3V6K
L56 DIS@ TRANSLATION PCIE_VDDC V22
1 2 +VDD_CT AA20 PCIE_VDDC
+1.5VS_VGA 10uF 1uF 0.1uF BLM15BD121SN1D_0402 AA21 VDD_CT
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
AB20 VDD_CT AA15 2 2 2 2 2 2 2 2 2
C404
C405
C422
B VDD_CT CORE VDDC B
@
AB21 N15
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
1 1 1 VDD_CT VDDC N17
VDDR1 1.5A 3 5 5 +3VS_VGA VDDC R13
L24 DIS@ 25mA I/O VDDC R16
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 1 2 +VDDR3 AA17 VDDC R18
BLM15BD121SN1D_0402 AA18 VDDR3 VDDC Y21
DIS@
DIS@
DIS@
AB17 VDDR3 VDDC T12
C410
C417
C428
C429
AB18 VDDR3 VDDC T15 +VGA_CORE
+1.8VS_VGA 10uF 1uF 0.1uF 1 1 1 1 VDDR3 VDDC T17
V12 VDDC T20
Y12 VDDR4 VDDC U13
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 2 2 2 U12 VDDR4 VDDC U16
PCIE_PVDD 100mA 1 1 1 VDDR4 VDDC
@
U18
DIS@
DIS@
DIS@
VDDC V21
VDDC V15
VDDC V17
MPLL_PVDD 130mA 1 1 1 VDDC V20
VDDC
POWER
Y13
VDDC Y16
VDDC Y18
SPLL_PVDD 75mA 1 1 1 VDDC AA12
VDDC M11
VDDC N12
VDDC U11
VDDR4 (300mA) 0 0 0 VDDC
+1.8VS_VGA 21A (VDDC + VDDCI (Merged) - PRO S3 (DDR3))
L47 DIS@ 90mA PLL
1 2 +MPLL_PVDD PV:R398 change to 0-ohm shortpad
VDD_CT 13mA 1 1 1 MBK1608221YZF_2P
C406
C407
C433
1 1 1
1.4A +1.05VS_VGA
R21 R398
BIF_VDDC U21 +BIF_VDDC 1 short@ 2
+TSVDD 13mA 1 1 1 BIF_VDDC
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 L8 0_0805_5%
+1.8VS_VGA MPLL_PVDD +VGA_CORE
DIS@
DIS@
DIS@
C
L48 DIS@ 75mA C
C413
C415
C416
+DP_VDDR 0 0 0 1 2 +SPLL_PVDD
ISOLATED
CORE I/O 1 1 1
BLM15BD121SN1D_0402 M13
C408
C409
C434
H7 VDDCI M15
1 1 1 SPLL_PVDD VDDCI M16
+DP_VDDC 0 0 0
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
VDDCI M17 2 2 2
+1.05VS_VGA VDDCI
@
M18
100mA
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 L53 DIS@ VDDCI M20

1 2 +SPLL_VDDC H8 VDDCI M21
DIS@
DIS@
DIS@
BLM15BD121SN1D_0402 SPLL_VDDC VDDCI N20
C411
C412
C435
J7 VDDCI
+3VS_VGA 10uF 1uF 0.1uF 1 1 1 SPLL_PVSS
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2
VDDR3 25mA 0 2 (1@) 1 216-0867030 EXO PRO S3 ?
DIS@
DIS@
DIS@
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AMD EXO_Power
Custom 0.1
Date:
LA-C701P
1 2 3 4 5
1 2 3 4 5
M_DA[63..0]
<40,41> M_DA[63..0]
M_MA[15..0]
<40,41> M_MA[15..0]
M_DQM[7..0]
<40,41> M_DQM[7..0]
M_DQS[7..0]
<40,41> M_DQS[7..0]
A A
M_DQS#[7..0]
<40,41> M_DQS#[7..0]
DIS@
U666C U?
GDDR5/DDR3 GDDR5/DDR3
M_DA0 K27 K17 M_MA0
M_DA1 J29 DQA0_0 MAA0_0/MAA_0 J20 M_MA1
M_DA2 H30 DQA0_1 MAA0_1/MAA_1 H23 M_MA2
M_DA3 H32 DQA0_2 MAA0_2/MAA_2 G23 M_MA3
M_DA4 G29 DQA0_3 MAA0_3/MAA_3 G24 M_MA4
M_DA5 F28 DQA0_4 MAA0_4/MAA_4 H24 M_MA5
M_DA6 F32 DQA0_5 MAA0_5/MAA_5 J19 M_MA6
+1.5VS_VGA +1.5VS_VGA M_DA7 F30 DQA0_6 MAA0_6/MAA_6 K19 M_MA7
M_DA8 C30 DQA0_7 MAA0_7/MAA_7 G20 M_MA13
M_DA9 F27 DQA0_8 MAA0_8/MAA_13 L17 M_MA15
M_DA10 A28 DQA0_9 MAA0_9/MAA_15
DQA0_10
1
1
M_DA11 C28 J14 M_MA8
DIS@ DIS@ M_DA12 E27 DQA0_11 MAA1_0/MAA_8 K14 M_MA9
R363 R365 M_DA13 G26 DQA0_12 MAA1_1/MAA_9 J11 M_MA10
40.2_0402_1% 40.2_0402_1% M_DA14 D26 DQA0_13 MAA1_2/MAA_10 J13 M_MA11
M_DA15 F25 DQA0_14 MAA1_3/MAA_11 H11 M_MA12
2
M_DA16 A25 DQA0_15 MAA1_4/MAA_12 G11 M_BA2

DQA0_16 MAA1_5/MAA_BA2 M_BA2 <40,41>
+MVREFDA +MVREFSA M_DA17 C25 J16 M_BA0
DQA0_17 MAA1_6/MAA_BA0 M_BA0 <40,41>
M_DA18 E25 L15 M_BA1
DQA0_18 MAA1_7/MAA_BA1 M_BA1 <40,41>
M_DA19 D24 G14 M_MA14
DQA0_19 MAA1_8/MAA_14
1
1 1 M_DA20 E23 L16
MEMORY INTERFACE
DIS@ DIS@ DIS@ DIS@ M_DA21 F23 DQA0_20 MAA1_9/RSVD
R364 C467 R457 C514 M_DA22 D22 DQA0_21 E32 M_DQM0
100_0402_1% 1U_0402_6.3V4Z 100_0402_1% 1U_0402_6.3V4Z M_DA23 F21 DQA0_22 WCKA0_0/DQMA0_0 E30 M_DQM1
2 2 M_DA24 E21 DQA0_23 WCKA0B_0/DQMA0_1 A21 M_DQM2
2
M_DA25 D20 DQA0_24 WCKA0_1/DQMA0_2 C21 M_DQM3

M_DA26 F19 DQA0_25 WCKA0B_1/DQMA0_3 E13 M_DQM4
B
M_DA27 A19 DQA0_26 WCKA1_0/DQMA1_0 D12 M_DQM5 B
M_DA28 D18 DQA0_27 WCKA1B_0/DQMA1_1 E3 M_DQM6
M_DA29 F17 DQA0_28 WCKA1_1/DQMA1_2 F4 M_DQM7
M_DA30 A17 DQA0_29 WCKA1B_1/DQMA1_3
M_DA31 C17 DQA0_30 H28 M_DQS0
M_DA32 E17 DQA0_31 EDCA0_0/QSA0_0 C27 M_DQS1
M_DA33 D16 DQA1_0 EDCA0_1/QSA0_1 A23 M_DQS2
M_DA34 F15 DQA1_1 EDCA0_2/QSA0_2 E19 M_DQS3
M_DA35 A15 DQA1_2 EDCA0_3/QSA0_3 E15 M_DQS4
M_DA36 D14 DQA1_3 EDCA1_0/QSA1_0 D10 M_DQS5
DIS@ DIS@ M_DA37 F13 DQA1_4 EDCA1_1/QSA1_1 D6 M_DQS6
R5160 R455 M_DA38 A13 DQA1_5 EDCA1_2/QSA1_2 G5 M_DQS7
49.9_0402_1% 10_0402_1% M_DA39 C13 DQA1_6 EDCA1_3/QSA1_3
1 2 2 1 DRAM_RST M_DA40 E11 DQA1_7 H27 M_DQS#0
<40,41> DRAM_RST# DQA1_8 DDBIA0_0/QSA0_0B
M_DA41 A11 A27 M_DQS#1
M_DA42 C11 DQA1_9 DDBIA0_1/QSA0_1B C23 M_DQS#2
DQA1_10 DDBIA0_2/QSA0_2B
1
1 M_DA43 F11 C19 M_DQS#3

DIS@ DIS@ M_DA44 A9 DQA1_11 DDBIA0_3/QSA0_3B C15 M_DQS#4
C469 R5161 M_DA45 C9 DQA1_12 DDBIA1_0/QSA1_0B E9 M_DQS#5
120P_0402_50V8J 5.1K_0402_1% M_DA46 F9 DQA1_13 DDBIA1_1/QSA1_1B C5 M_DQS#6
2 M_DA47 D8 DQA1_14 DDBIA1_2/QSA1_2B H4 M_DQS#7
DQA1_15 DDBIA1_3/QSA1_3B
2
M_DA48 E7
M_DA49 A7 DQA1_16 L18 VRAM_ODT0
DQA1_17 ADBIA0/ODTA0 VRAM_ODT0 <40>
M_DA50 C7 K16 VRAM_ODT1
DQA1_18 ADBIA1/ODTA1 VRAM_ODT1 <41>
M_DA51 F7
M_DA52 A5 DQA1_19 H26 M_CLK0
DQA1_20 CLKA0 M_CLK0 <40>
M_DA53 E5 H25 M_CLK#0
DQA1_21 CLKA0B M_CLK#0 <40>
M_DA54 C3
M_DA55 E1 DQA1_22 G9 M_CLK1
DQA1_23 CLKA1 M_CLK1 <41>
M_DA56 G7 H9 M_CLK#1
L Layout notes
Place close to GPU (within 25mm)
M_DA57
M_DA58
G6
G1
DQA1_24
DQA1_25
CLKA1B
G22 M_RAS#0
M_CLK#1 <41>
DQA1_26 RASA0B M_RAS#0 <40>

M_DA59 G3 G17 M_RAS#1
and place componment close to each other M_DA60 J6 DQA1_27 RASA1B M_RAS#1 <41>
M_DA61 J1 DQA1_28 G19 M_CAS#0
C C
DQA1_29 CASA0B M_CAS#0 <40>
M_DA62 J3 G16 M_CAS#1
DQA1_30 CASA1B M_CAS#1 <41>
M_DA63 J5
DQA1_31 H22 M_CS#0
CSA0B_0 M_CS#0 <40>
+MVREFDA K26 J22
+MVREFSA J26 MVREFDA CSA0B_1
MVREFSA G13 M_CS#1
CSA1B_0 M_CS#1 <41>
J25 K13
R5162 1 DIS@ 2 120_0402_1% K25 NC#J25 CSA1B_1
MEM_CALRP0 K20 M_CKE0
CKEA0 M_CKE0 <40>
J17 M_CKE1
CKEA1 M_CKE1 <41>
G25 M_WE#0
WEA0B M_WE#0 <40>
DRAM_RST L10 H10 M_WE#1
DRAM_RST WEA1B M_WE#1 <41>
R460 @ 1 2 51.1_0402_1% C542 @1
@ 2 0.1U_0402_16V4Z K8
R373 @ 1 2 51.1_0402_1% C541 @
@1 2 L7 CLKTESTA
0.1U_0402_16V4Z CLKTESTB
Route 50ohms single-ended/100ohm diff and keep short

216-0867030 EXO PRO S3
debug only, for clock observation,if not need, DNI. ?
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AMD EXO_MEM
Custom 0.1
Date:
LA-C701P
1 2 3 4 5
1 2 3 4 5
Memory Partition A - Lower 32 bits <37,38,39,41> +1.5VS_VGA +1.5VS_VGA

M_DA[63..0]
<39,41> M_DA[63..0]
M_MA[15..0]
<39,41> M_MA[15..0]
M_DQM[7..0]
<39,41> M_DQM[7..0]
M_DQS[7..0]
<39,41> M_DQS[7..0]
M_DQS#[7..0]
<39,41> M_DQS#[7..0]
+1.5VS_VGA +1.5VS_VGA
A A
1
DIS@ DIS@
R452 R463
4.99K_0402_1% U1406 4.99K_0402_1% U1407
2
+FBA_VREF0 M8 E3 M_DA17 +FBA_VREF1 M8 E3 M_DA30
+FBA_DQ_VREF0 H1 VREFCA DQL0 F7 M_DA23 +FBA_DQ_VREF1 H1 VREFCA DQL0 F7 M_DA27
VREFDQ DQL1 F2 M_DA21 VREFDQ DQL1 F2 M_DA31
DQL2 DQL2
1
1 M_MA0 N3 F8 M_DA22 1 M_MA0 N3 F8 M_DA24
DIS@ DIS@ M_MA1 P7 A0 DQL3 H3 M_DA18 DIS@ DIS@ M_MA1 P7 A0 DQL3 H3 M_DA29
R453 C472 M_MA2 P3 A1 DQL4 H8 M_DA19 R464 C540 M_MA2 P3 A1 DQL4 H8 M_DA26
+1.5VS_VGA 4.99K_0402_1% 0.1U_0402_10V6K M_MA3 N2 A2 DQL5 G2 M_DA16 4.99K_0402_1% 0.1U_0402_10V6K M_MA3 N2 A2 DQL5 G2 M_DA28
2 M_MA4 P8 A3 DQL6 H7 M_DA20 2 M_MA4 P8 A3 DQL6 H7 M_DA25
2
M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7
A5 A5
1
M_MA6 R8 M_MA6 R8
DIS@ M_MA7 R2 A6 D7 M_DA5 M_MA7 R2 A6 D7 M_DA8
R466 M_MA8 T8 A7 DQU0 C3 M_DA3 M_MA8 T8 A7 DQU0 C3 M_DA14
4.99K_0402_1% M_MA9 R3 A8 DQU1 C8 M_DA4 M_MA9 R3 A8 DQU1 C8 M_DA9
M_MA10 L7 A9 DQU2 C2 M_DA1 M_MA10 L7 A9 DQU2 C2 M_DA12
A10/AP DQU3 A10/AP DQU3
2
+FBA_DQ_VREF0 M_MA11 R7 A7 M_DA6 M_MA11 R7 A7 M_DA10

M_MA12 N7 A11 DQU4 A2 M_DA0 +1.5VS_VGA M_MA12 N7 A11 DQU4 A2 M_DA15
M_MA13 T3 A12 DQU5 B8 M_DA7 M_MA13 T3 A12 DQU5 B8 M_DA11
A13 DQU6 A13 DQU6
1
1 M_MA14 T7 A3 M_DA2 M_MA14 T7 A3 M_DA13

A14 DQU7 A14 DQU7
1
DIS@ DIS@ M_MA15 M7 M_MA15 M7
R465 C515 A15/BA3 +1.5VS_VGA DIS@ A15/BA3 +1.5VS_VGA
4.99K_0402_1% 0.1U_0402_10V6K R468
2 M_BA0 M2 B2 4.99K_0402_1% M_BA0 M2 B2
<39,41> M_BA0
2
M_BA1 N8 BA0 VDD D9 M_BA1 N8 BA0 VDD D9

<39,41> M_BA1
2
M_BA2 M3 BA1 VDD G7 +FBA_DQ_VREF1 M_BA2 M3 BA1 VDD G7
<39,41> M_BA2 BA2 VDD BA2 VDD
K2 K2
VDD K8 VDD K8
VDD VDD
1
N1 1 N1
M_CLK0 J7 VDD N9 DIS@ DIS@ M_CLK0 J7 VDD N9
B <39> M_CLK0 CK VDD CK VDD B
M_CLK#0 K7 R1 R467 C543 M_CLK#0 K7 R1
<39> M_CLK#0 CK VDD CK VDD
M_CKE0 K9 R9 4.99K_0402_1% 0.1U_0402_10V6K M_CKE0 K9 R9
<39> M_CKE0 CKE/CKE0 VDD +1.5VS_VGA 2 CKE/CKE0 VDD +1.5VS_VGA
2
VRAM_ODT0 K1 A1 VRAM_ODT0 K1 A1
<39> VRAM_ODT0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
M_CS#0 L2 A8 M_CS#0 L2 A8
<39> M_CS#0 CS/CS0 VDDQ CS/CS0 VDDQ
M_RAS#0 J3 C1 M_RAS#0 J3 C1
<39> M_RAS#0 RAS VDDQ RAS VDDQ
M_CAS#0 K3 C9 M_CAS#0 K3 C9
<39> M_CAS#0 CAS VDDQ CAS VDDQ
M_WE#0 L3 D2 M_WE#0 L3 D2
<39> M_WE#0 WE VDDQ WE VDDQ
E9 E9
VDDQ F1 VDDQ F1
M_DQS2 F3 VDDQ H2 M_DQS3 F3 VDDQ H2
M_DQS0 C7 DQSL VDDQ H9 M_DQS1 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ
M_DQM2 E7 A9 M_DQM3 E7 A9
M_DQM0 D3 DML VSS B3 M_DQM1 D3 DML VSS B3
DMU VSS E1 DMU VSS E1
VSS G8 VSS G8
M_DQS#2 G3 VSS J2 M_DQS#3 G3 VSS J2
M_DQS#0 B7 DQSL VSS J8 M_DQS#1 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9
VSS P1 VSS P1
T2 VSS P9 DRAM_RST# T2 VSS P9
<39,41> DRAM_RST# RESET VSS RESET VSS
T1 T1
L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
1
J1 B1 J1 B1
M_CLK0 DIS@ L1 NC/ODT1 VSSQ B9 DIS@ L1 NC/ODT1 VSSQ B9
M_CLK#0 R454 J9 NC/CS1 VSSQ D1 R456 J9 NC/CS1 VSSQ D1
243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
2
2
VSSQ VSSQ
1
C E8 E8 C
R5171 R5170 VSSQ F9 VSSQ F9
40.2_0402_1% 40.2_0402_1% VSSQ G1 VSSQ G1
DIS@ DIS@ VSSQ G9 VSSQ G9
VSSQ VSSQ
2
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
H5TC2G63FFR-11C_FBGA96 H5TC2G63FFR-11C_FBGA96
1 X76@ X76@
DIS@
C506
0.01U_0402_25V7K
2 +1.5VS_VGA
+1.5VS_VGA
U1406 side
U1407 side
C491
C512
C511
C519
C510
C521
C532
C520
C480
C481
C482
C485
C483
C531
C486
C490
C496
C497
C498
C499
C518
C533
C516
C474
C475
C476
C477
C478
C534
C479
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
@
@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
@
@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AMD EXO_VRAM A Lower
Custom 0.1
Date:
LA-C701P
1 2 3 4 5
1 2 3 4 5
Memory Partition A - Upper 32 bits

M_DA[63..0]
<39,40> M_DA[63..0]
<37,38,39,40> +1.5VS_VGA +1.5VS_VGA
M_MA[15..0]
<39,40> M_MA[15..0]
M_DQM[7..0] +1.5VS_VGA
<39,40> M_DQM[7..0] +1.5VS_VGA
M_DQS[7..0]
<39,40> M_DQS[7..0]
1
1
M_DQS#[7..0] DIS@
<39,40> M_DQS#[7..0]
DIS@ R461
R458 4.99K_0402_1% U1409
4.99K_0402_1% U1408
2
A +FBA_VREF3 M8 E3 M_DA49 A
VREFCA DQL0
2
+FBA_VREF2 M8 E3 M_DA38 +FBA_DQ_VREF3 H1 F7 M_DA53
+FBA_DQ_VREF2 H1 VREFCA DQL0 F7 M_DA36 VREFDQ DQL1 F2 M_DA51
VREFDQ DQL1 DQL2
1
F2 M_DA37 1 M_MA0 N3 F8 M_DA54
DQL2 A0 DQL3
1
1 M_MA0 N3 F8 M_DA35 DIS@ DIS@ M_MA1 P7 H3 M_DA50
DIS@ DIS@ M_MA1 P7 A0 DQL3 H3 M_DA39 R462 C539 M_MA2 P3 A1 DQL4 H8 M_DA55
R459 C473 M_MA2 P3 A1 DQL4 H8 M_DA32 4.99K_0402_1% 0.1U_0402_10V6K M_MA3 N2 A2 DQL5 G2 M_DA48
4.99K_0402_1% 0.1U_0402_10V6K M_MA3 N2 A2 DQL5 G2 M_DA34 2 M_MA4 P8 A3 DQL6 H7 M_DA52
2
2 M_MA4 P8 A3 DQL6 H7 M_DA33 M_MA5 P2 A4 DQL7
2
M_MA5 P2 A4 DQL7 M_MA6 R8 A5
M_MA6 R8 A5 M_MA7 R2 A6 D7 M_DA60
M_MA7 R2 A6 D7 M_DA41 M_MA8 T8 A7 DQU0 C3 M_DA59
M_MA8 T8 A7 DQU0 C3 M_DA44 M_MA9 R3 A8 DQU1 C8 M_DA63
M_MA9 R3 A8 DQU1 C8 M_DA43 M_MA10 L7 A9 DQU2 C2 M_DA56
M_MA10 L7 A9 DQU2 C2 M_DA45 M_MA11 R7 A10/AP DQU3 A7 M_DA62
M_MA11 R7 A10/AP DQU3 A7 M_DA42 +1.5VS_VGA M_MA12 N7 A11 DQU4 A2 M_DA57
M_MA12 N7 A11 DQU4 A2 M_DA46 M_MA13 T3 A12 DQU5 B8 M_DA61
+1.5VS_VGA M_MA13 T3 A12 DQU5 B8 M_DA40 M_MA14 T7 A13 DQU6 A3 M_DA58
A13 DQU6 A14 DQU7
1
M_MA14 T7 A3 M_DA47 M_MA15 M7
M_MA15 M7 A14 DQU7 DIS@ A15/BA3 +1.5VS_VGA
A15/BA3
1
+1.5VS_VGA R471
DIS@ 4.99K_0402_1% M_BA0 M2 B2
R470 M_BA0 M2 B2 M_BA1 N8 BA0 VDD D9
<39,40> M_BA0
2
4.99K_0402_1% M_BA1 N8 BA0 VDD D9 +FBA_DQ_VREF3 M_BA2 M3 BA1 VDD G7
<39,40> M_BA1 BA1 VDD BA2 VDD
M_BA2 M3 G7 K2
<39,40> M_BA2
2
+FBA_DQ_VREF2 BA2 VDD K2 VDD K8

VDD VDD
1
K8 1 N1
VDD N1 DIS@ DIS@ M_CLK1 J7 VDD N9
VDD CK VDD
1
1 M_CLK1 J7 N9 R472 C544 M_CLK#1 K7 R1

<39> M_CLK1 CK VDD CK VDD
DIS@ DIS@ M_CLK#1 K7 R1 4.99K_0402_1% 0.1U_0402_10V6K M_CKE1 K9 R9
<39> M_CLK#1 CK VDD 2 CKE/CKE0 VDD +1.5VS_VGA
R469 C517 M_CKE1 K9 R9
<39> M_CKE1 CKE/CKE0 VDD
2
4.99K_0402_1% 0.1U_0402_10V6K +1.5VS_VGA
2 VRAM_ODT1 K1 A1
2
VRAM_ODT1 K1 A1 M_CS#1 L2 ODT/ODT0 VDDQ A8

<39> VRAM_ODT1 ODT/ODT0 VDDQ CS/CS0 VDDQ
M_CS#1 L2 A8 M_RAS#1 J3 C1
B <39> M_CS#1 CS/CS0 VDDQ RAS VDDQ B
M_RAS#1 J3 C1 M_CAS#1 K3 C9
<39> M_RAS#1 RAS VDDQ CAS VDDQ
M_CAS#1 K3 C9 M_WE#1 L3 D2
<39> M_CAS#1 CAS VDDQ WE VDDQ
M_WE#1 L3 D2 E9
<39> M_WE#1 WE VDDQ VDDQ
E9 F1
VDDQ F1 M_DQS6 F3 VDDQ H2
M_DQS4 F3 VDDQ H2 M_DQS7 C7 DQSL VDDQ H9
M_DQS5 C7 DQSL VDDQ H9 DQSU VDDQ
DQSU VDDQ
M_DQM6 E7 A9
M_DQM4 E7 A9 M_DQM7 D3 DML VSS B3
M_DQM5 D3 DML VSS B3 DMU VSS E1
DMU VSS E1 VSS G8
VSS G8 M_DQS#6 G3 VSS J2
M_DQS#4 G3 VSS J2 M_DQS#7 B7 DQSL VSS J8
M_DQS#5 B7 DQSL VSS J8 DQSU VSS M1
DQSU VSS M1 VSS M9
VSS M9 VSS P1
M_CLK1 VSS P1 DRAM_RST# T2 VSS P9
M_CLK#1 DRAM_RST# T2 VSS P9 RESET VSS T1
<39,40> DRAM_RST# RESET VSS VSS
T1 L8 T9
L8 VSS T9 ZQ/ZQ0 VSS
ZQ/ZQ0 VSS
1
1
R5173 R5172 J1 B1
NC/ODT1 VSSQ
1
40.2_0402_1% 40.2_0402_1% J1 B1 DIS@ L1 B9

DIS@ DIS@ DIS@ L1 NC/ODT1 VSSQ B9 R444 J9 NC/CS1 VSSQ D1
R410 J9 NC/CS1 VSSQ D1 243_0402_1% L9 NC/CE1 VSSQ D8
NC/CE1 VSSQ NCZQ1 VSSQ
2
243_0402_1% L9 D8 E2
2
NCZQ1 VSSQ E2 VSSQ E8
2
VSSQ E8 VSSQ F9
VSSQ F9 VSSQ G1
1 VSSQ VSSQ
DIS@ G1 G9
C507 VSSQ G9 VSSQ
0.01U_0402_25V7K VSSQ 96-BALL
2 96-BALL SDRAM DDR3
C SDRAM DDR3 H5TC2G63FFR-11C_FBGA96 C
H5TC2G63FFR-11C_FBGA96 X76@
X76@
+1.5VS_VGA +1.5VS_VGA
U1408 side U1409 side

C495
C525
C524
C526
C513
C527
C536
C528
C504
C508
C505
C509
C529
C535
C530
C492
C501
C502
C503
C500
C523
C538
C522
C487
C484
C488
C489
C493
C537
C494
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
@
@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AMD EXO_VRAM A Upper
Custom 0.1
Date:
LA-C701P
1 2 3 4 5
5 4 3 2 1
D D
@ 0 ohm
R
CPU GPU_PWRGD
PU801
DGPU_PWROK
+3VS 1. +3VS_VGA @
U4103 GPIO77
PU8
1.8V_PWRGD
DGPU_PWR_EN
C
GPIO78 EN C
PU801
2. VGA_CORE 0 ohm CPU
PXS_PWREN# DGPU_HOLD_RST#
NMOS
U4102
3. +1.05VS_VGA GPIO80
GPU_RST
+1.05VS GPU
B
PLT_RST# B
4. +1.5VS_VGA
U4102
+1.5VS
EN_1.8V
R 5. +1.8VS_VGA
PU8
C
A A

Issued Date Deciphered Date Title
RSVD
D 0.1
LA-C701P
5 4 3 2 1
5 4 3 2 1
+3VALWP
2. EC_ON
PU2 +VCC_CORE
D
+5VALWP D
3. PCH_DPWROK
1. ON/OFF#
18. VR_ON
4. PBTN_OUT# CPU
+3C_PCH 6. PCH_PWR_EN 19. VGATE PU5
Q30
5. PM_SLP_SUS#
+1.35VP 11. SYSON 7. PCH_RSMRST#

C
+0.675VSP PU3 13. SUSP# C
8. PCH_SUSWARN#
+5VS 9. SUSACK#
+3VS Q21 KBC
9022 10. PM_SLP_S5# CPU
12. PM_SLP_S3#
+1.5VS
PU6
B
14. EC_KBRST# B
(UMA)
+1.5VS 16. EC_+1.05VS_PG

PU7 21. PLT_RST#
(DIS) 17. PCH_PWROK
+1.05VS
PU4 20. SYS_PWROK
15. 1.05V_VS_PG_PWR
A A
Vinafix.com
Issued Date Deciphered Date Title
POWER SEQUENCE
D 0.1
LA-C701P
5 4 3 2 1
5 4 3 2 1
ZZZ004
D D
DB build CPU type HY1@

1G Hynix
X7662732L02
UCPU1 UCPU1 UCPU1 ZZZ004
2.4G@ 2.0G@ 1.7G@
i7-5500U BDW i3-5005U BDW i3 4005U HY2@

SA000089A00 SA000083E50 SA000072Q80 2G Hynix
X7662732L01
C C
ZZZ
ZZZ004
DAX
DA6001DO000 SAM2@
2G SAMSUNG
X7662732L03
ZZZ004
SAM1@
1G SAMSUNG
X7662732L04
B B
A A

BOM control
Document Number Rev
5 4 3 2 1
5 4 3 2 1
+19.5V_ADPIN +19.5V_VIN
EMI@ PL1
5A_Z120_25M_0805_2P
1 2
D D
@ PJP1 DISEMI@ PL2

ACES_51483-00801-001 5A_Z120_25M_0805_2P
1 1 2
1 2
2 3 @ PR1
1000P_0402_50V7K
3 4 0_0402_5%
100P_0402_50V8J
100P_0402_50V8J
1000P_0402_50V7K
4 5 1 2 ACIN_LED
5 6 <25> AC_LED#
1
ADP_SIGNAL
EMI@ PC1
EMI@ PC2
EMI@ PC3
EMI@ PC4
6 7 Charge_LED
7 8
1
ACIN_LED
2
9 8
10 GND PR2
GND 100K_0402_5%
2
PR3
10K_0402_5%
ADP_SIGNAL 1 2
ADP_ID <25> PR4
3
3
2K_0402_5%
1 2 Charge_LED
100P_0402_50V8J
1000P_0402_50V7K
<25> BAT_CHG_LED
GLZ3.6B_LL34-2
1
10K_0402_5%
PR5
PD3
@ PC5
PC6
PR6
2
100K_0402_5%
2
ESD@ PD1 ESD@ PD2
1
C L30ESD24VC3-2_SOT23-3 L30ESD24VC3-2_SOT23-3 C
2014-10-06: ADP_I <25,47>

Change EC Power Rail Name
+3VALW _EC
1
PR7 PR8
16.2K_0402_1% 5.9K_0402_1%
2
VCIN0_PH <25> VCIN1_PH <25>
1
PH1 PR9
100K_0402_1%_NCP15W F104F03RC 10K_0402_1%
2
ECAGND<25>
B B
A A

DC Conn
5 4 3 2 1
5 4 3 2 1
EMI@ PL3
D 5A_Z120_25M_0805_2P D
+14.8V_BATT+ 1 2 +14.8V_BATT
@ PJPB1 EMI@ PL4
TAITW _PMPCR3-08MLBS1ZZ4H4 5A_Z120_25M_0805_2P
1 1 2
1 2
2 3
3 4
1
EMI@ PC7 EMI@ PC8
4 5 1000P_0402_50V7K 0.01U_0402_25V7K
5 6
2
6 7
7 8
8 9
GND 10
GND PR10
100_0402_5%
1 2
EC_SMB_DA1 <25,47>
PR11
100_0402_5%
1 2
EC_SMB_CK1 <25,47>
+3VL
1
PR13
PR12 100K_0402_5%
C C
100_0402_5%
2
1 2
B/I# <25>
3
3
ESD@ PD4 ESD@ PD5
1
1
L30ESD24VC3-2_SOT23-3 L30ESD24VC3-2_SOT23-3
B B
A A

BATT Conn
5 4 3 2 1
A B C D
Protection for reverse input
Vgs = 20V
1
@ PQ201 D
2 Vds = 60V +19.5VB
G Id = 250mA
S 2N7002KW _SOT323-3
3
@ PR201 @ PR202
1M_0402_5% 3M_0402_5%
1 2 1 2 Rds(on) typ = 35mohm max
Vgs = 20V Rds(on) = 35mohm max
max Power loss 0.22W for 90W;0.12W for 65W system Vgs = 20V
Vds = 30V
1 1
Need check the SOA for inrush CSR rating: 1W

ID = 7.7A (Ta=70C) Vds = 30V
+19.5V_VIN PQ202 VACP-VACN spec < 80.64mV
PQ203 ID = 7.7A
PQ204(Ta=70C)
MDU1512RH_POW ERDFN56-8-5P1 AON7506_DFN33-8-5 P2
1 1 PR203 EMI@ PL201 CHG_B+ AON7506_DFN33-8-5
2 2 0.01_1206_1% 1UH_2.8A_30%_4X4X2_F 1
5 3 3 5 1 4 1 2 2
Isat: 4A 5 3
2200P_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
2 3
2200P_0402_50V7K
0.1U_0402_25V6
DCR: 27mohm
0.1U_0402_25V6
4
@EMI@PC205
1
1
PC203
PC204
EMI@ PC206
0_0402_5%
0.01U_0402_50V7K
PC201
@ PR204
4
1
1
+19.5V_VIN
PC202
PC207
2
2
2
VF = 0.5V
2
2
3
2
PD201
CHG_ACDRV_R BAS40CW _SOT323-3
0.1U_0402_25V6
CHG_BATDRV 1 2CHG_BATDRV_R
0.1U_0402_25V6
Rds(on) = 30mohm max
1
1
PC208
PR205
PC210
Vgs = 20V
SIS412DN-T1-GE3_POWERPAK8-5
1 1
1 2 PC211 4.12K_0603_1%
10_1206_1%
0.047U_0402_25V7K Vds = 30V
PR206
2
PC209 1 2
0.1U_0402_25V6
ID = 7A (Ta=70C)
VF = 0.37V
5
2.2_0603_5%
PR207
PD202
2
RB751V-40_SOD323-2 Support max charge 3.5A
PR215 7X7X3
CHG_ACP
Power loss: 0.245W
PQ205
0_0402_5%
Isat: 6.5A
CHG_VCC
2
CHG_DH 1 2 4 CSR rating: 1W
DCR: 30mohm VSRP-VSRN spec < 81.28mV
4.12K_0603_1%
4.12K_0603_1%
2 2
1
CHG_REGN
PC212 +14.8V_BATT
CHG_BST
PR208
PR209
CHG_DH
1 2 PL202
CHG_LX
PR210
3
2
1
1U_0603_25V6K 1 2 10UH_3.5A_20%_7X7X3_M 0.01_1206_1%
CHG_ACN
CHG_LX 1 2 CHG 1 4
2
PC213
5
1U_0603_25V6K 2 3
20
19
18
17
16
SIS412DN-T1-GE3_POWERPAK8-5
1CHG_CSON1
1CHG_CSOP1
1
680P_0402_50V7K 4.7_1206_5%
VCC
PHASE
HIDRV
BTST
REGN
10U_0805_25V6K
10U_0805_25V6K
21
@EMI@PC220 @EMI@ PR211

PAD
0.1U_0402_25V6
0.1U_0402_25V6
PC214
PC215
1
1
1 15 4
PQ206
DL_CHG
ACN LODRV
PC216
PC217
2
2
2 14
ACP DIS@ GND PR212
3
2
1
2
1
10_0603_1%
CHG_CMSRC 3 PU201 13 1
CHG_SRP 2 CHG_CSOP1
CMSRC SRP
1
PR213
2
6.8_0603_1%
CHG_ACDRV 4 12 1
CHG_SRN 2 CHG_CSON1
2
ACDRV SRN PC221
0.1U_0603_16V7K
UMA@ PU201 1 2 5 11 CHG_BATDRV
+3VL ACOK BATDRV
BQ24725ARGRR_QFN20_3P5X3P5 PR214 100K_0402_1%
ACDET
IOUT
SDA
SCL
ILIM
BQ24735RGRR_QFN20_3P5X3P5
<25,36,8> ACIN
6
10
PR216 +3VL
3 **Design Notes** 620K_0402_1% 3
CHG_ILIM 1 2
#For 65 /90W system, 3S1P/3S2P battery
Module model information Maximum Charging current 3.5A
100K_0402_1%
0.01U_0402_25V7K
CHG_ACDET
1
Battery discharge power 55W.
CHG_IOUT
PC222
PR217
1
BQ24735A_V1.mdd PR218
422K_0402_1% #Register Setting
+19.5V_VIN
1 2 1. 0X12 bit8 set 0 (default 1) to disable IFAULT HI if add ISN choke
2
BQ24735A_V2.mdd 2. 0X12 bit3 set 1 (default 0) to enable turbo boost function
2
3. Disable turbo when AC only

#Circuit Design
1. ACOK,ILIM pull high voltage need base on 3/5V enable control
2. Use 10X10 choke and 3X3 H/L side MOSFET
@ PR224 Charge current 3.5A
0_0402_5%
Power loss : 1.82W
2200P_0402_50V7K
1 2
EC_SMB_CK1 <25,46> Power density : 0.81 (15X15)
66.5K_0402_1%
100P_0402_50V8J
1
@ PR225 3. If use 4S per cell 4.35V battery, need additional circuit

PC223
1
PC224
PR222
0_0402_5%
1 2 for ACDET(PR218/PR220/PR222 change to 0.1%, parallel resistors
EC_SMB_DA1 <25,46>
2
with PR222 for ACDET setting)

2
@ PR223 4. PC223 2200p is for quick response when AC plug out.

2
0_0402_5%
1 2 5. For hybrid design, need double check PQ202,PQ203,PQ204,PQ205 component rating
ADP_I <25,45>
#Protect function
1. ACOVP : ACDET voltage > 3.14V
1
Vin Dectector 2. Charger timeout : No communication within 175s(default)

PC225 @
Min. Typ Max. 100P_0402_50V8J 3. ACOC : 3.33 X Input current DAC setting(default)
2
L-->H 17.16V 17.63V 18.12V 4. CHGOCP : 3/4.5/6A based on current current setting
4
Close EC chip 4
H-->L 16.76V 17.22V 17.70V 5. BATOVP : 103-106%

6. BATLOWV : 2.5V
7. TSHUT : 155C
VILIM = 20*ILIM*Rsr 8. IFAULT HI : 750mV (default)
ILIM = 3.3*100/(100+620)/20/0.01 9. IFAULT LOW : 110mV (default)
= 2.29 A Security Classification Compal Secret Data Compal Electronics, Inc.
PWR-CHARGER
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Common Circuit 0.1
A B C D
5 4 3 2 1
ENTRIP1 ENTRIP2
ENLDO (V) ENM (V) (V) (V) LDO5 LDO3 +5VALW +3VALW
Module model information
Low Low X X Off Off Off Off
RT8243A_V1.mdd ">1.6V"
=>High Low X X On On Off Off
">1.6V" ">2.3V"
=>High =>High Off Off On On Off Off
D ">1.6V" ">2.3V" D
ENTRIPx adjustment range: 0.5V~3V,

=>High =>High Off On On On Off On
floating or over 4.5V will shutdown channel. ">1.6V" ">2.3V"
=>High =>High On On On On On On
">1.6V" ">2.3V"
=>High =>High On Off On On On Off
PR38 PR39
13.3K_0402_1% 30K_0402_1%
1 2 1 2
PR40 PR43 Trace width need
100K_0402_1%
113K_0402_1%
+19.5VB_3V/5V 20K_0402_1% 20K_0402_1% +19.5VB_3V/5V
PR42 56K_0402_1%
1 2 1 2 meet LDO5 demand
1
EMI@ PL7
+19.5VB HCB2012KF-121T50_0805
1 2
2200P_0402_50V7K
4.7U_0805_25V6K
4.7U_0805_25V6K
ENTRIP22
ENTRIP12
+3VALW
PR41
PR44
0.1U_0402_25V6
4.7U_0805_25V6K
4.7U_0805_25V6K
1
FB=1.98V(Min) FB=1.98V(Min)
@EMI@ PC34
PC44
PC36
FB_3V
FB_5V
1
1
EMI@ PC35
PC33
PC39
2.006V(Typ) 2.006V(Typ)
10K_0402_1%
<8> SPOK 2.03V(Max) 2.03V(Max)
2
PR111
2
1
FB2
ENTRIP2
TON
ENTRIP1
FB1
2
21
C 6 PAD C
PR46 PGOOD 20
2.2_0603_5% BYP1 PR45 PC37
4
4
1 2 1 2 BST_3V 7 2.2_0603_5% 0.1U_0402_25V6
BOOT2 19 BST_5V 1 2 1 2
D1
D1
D1
G1
G1
D1
D1
D1
PC38 PU2 BOOT1
0.1U_0402_25V6 UG_3V 8 RT8243AZQW _W QFN20_3X3
PL9 10 9 UGATE2 18 UG_5V 9 10
3.3UH_6.3A_20%_7X7X3_M D1 D2/S1 UGATE1 D2/S1 D1 PL8
1 2 LX_3V LX_3V 9 2.2UH_7.8A_20%_7X7X3_M
+3VALWP PHASE2 17 LX_5V PQ8 LX_5V 1 2 +5VALWP
G2
G2
S2
S2
S2
S2
S2
S2
PHASE1
1
PQ7 AON7934_DFN3X3A8-10
4.7_1206_5%
1
10
@EMI@ PR47
AON7934_DFN3X3A8-10 LG_3V
4.7_1206_5%
5
5
LGATE2 16 LG_5V
@EMI@ PC42 @EMI@ PR48

ENLDO
LGATE1
LDO5
LDO3
ENM
VIN
220U 6.3VM_R15
220U 6.3VM_R15
1
2
2
+
PC40
PC45 0.1U_0603_25V7K
11
12
13
14
15
1
Typ: 175mA +
PC43
680P_0402_50V7K
680P_0402_50V7K
2 +3VL
ENM
@EMI@ PC41
+19.5VB_3V/5V
2
2
Rds(on):9.1mΩ~11.6mΩ
2
1
1
PC46
4.7U_0603_10V6K
2
PR49
499K_0402_1%
1 2
Typ: 225mA @ PJP2
+VL 1 2
+3VALWP 1 2 +3VALW
1
JUMP_43X118
150K_0402_1%
B B
1
PC47
PR50
4.7U_0603_10V6K @ PJP3
1 2
+5VALWP +5VALW
2
1 2
2
JUMP_43X118
PR51
2.2K_0402_5%
1 2 ENM
ENLDO threshold ON: 1.2min 1.6typ 2max <25> EC_ON
OFF: 0.9min 0.95typ 1max
@ PR52
0_0402_5%
5V=375KHz 3V=400KHz (Vin=12 ~ 25v)
1 2 (By Rton= 56K ohm)
B+ threshold ON: 5.19min 6.92typ 8.65max <25> MAINPWON
4.7U_0603_10V6K
OFF: 3.89min 4.11typ 4.33max

1
+5VALWP Ipeak=9.26A ; Imax=6.5A

1
PC48
PR53
Delta I=2.694A=>1/2Delta I=1.347A
VIN rising threshold: 5.1typ 5.5max 402K_0402_1%
Rds(on)=11.6m ohm(max) ; Rds(on)=9.1m ohm(typical)
2
falling threshold: 3.5min 4.5max OCP =11.1A~13.8A

2
+3.3VALWP Ipeak=4.26A ; Imax=3A

Delta I=1.583A=>1/2Delta I=0.7915A
Rds(on)=11.6m ohm(max) ; Rds(on)=9.1m ohm(typical) TDC:4.9A Fsw:321KHz
OCP = 9.41A~11.8A H-MOS PD:0.4173W ∆T:13.4℃
℃
A L-MOS PD:0.3442W ∆T:10℃
℃ A
Choke PD:1.9613W ∆T:30℃
℃
OVP margin for Vos:9% @ 330uF cap, 8% @ 220uF
TDC:4.31A Fsw:375KHz
H-MOS PD:0.3736W ∆T:12℃
℃
L-MOS PD:0.2713W ∆T:7.9℃
℃
Choke PD:1.5158W ∆T:24℃
℃
OVP margin for Vos:8% @ 330uF cap, 6% @ 220uF
3VALW/5VALW
Custom 0.1
LA-C701P
5 4 3 2 1
5 4 3 2 1

RT8207M_V1.mdd For Single layer
RT8207M_V2.mdd For Dual layer
D D
Pin19 need pull separate from +1.35VP.

If you have +1.35V and +0.675V sequence question, 0.675Volt +/- 5%
EMI@ PL10 you can change from +1.35VP to +1.35VS. TDC 0.7A
HCB2012KF-121T50_0805
+19.5VB 1 2 +19.5VB_1.35VP PR54 Peak Current 1A
2.2_0603_5%
BST_1.35VP_R 1 2 BST_1.35VP
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
+1.35VP
1
@EMI@ PC49
PC50
PC51
+0.675VSP
1
PC52 UG_1.35VP
2
0.1U_0603_25V7K
2
LX_1.35VP
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
PC53
PC54
16
17
18
19
20
2
C C
VLDOIN
PHASE
UGATE
BOOT
VTT
21
PAD
LG_1.35VP 15 1
LGATE VTTGND
1
14 2
D1
D1
D1
G1
PL11 PR55 PGND VTTSNS
1UH_11A_20%_7X7X3_M 11.5K_0402_1%
1 2LX_1.35VP 10 9 1 2 CS_1.35VP 13 3
+1.35VP D1 D2/S1 PC55 CS GND
1
1U_0402_10V6K
1 2 12 4 VTTREF_1.35VP
G2
S2
S2
S2
@EMI@ PR56 PR57 VDDP VTTREF
4.7_1206_5% 5.1_0603_5%
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
8
1
1 2 VDD_1.35VP 11 5
+5VALW +1.35VP
1 2
VDD VDDQ
1
PGOOD
PC60
PC56
PC57
PC58
PC59
PC61
PC62
1U_0402_10V6K
TON
2
1
@EMI@ PC64 0.033U_0402_16V7K
FB
S5
S3
2
680P_0402_50V7K
PC63
2
10
6
PQ11 PU3
AON7934_DFN3X3A8-10 PR65 RT8207PGQW _W QFN20_3X3
FB_1.35VP
TON_1.35VP
5.1_0603_5%
EN_1.35VP
EN_0.675VSP
Rds(on):9.1mΩ~11.6mΩ 1 2 PR58
8.06K_0402_1%
PR59 1 2 +1.35VP
470K_0402_1%
+19.5VB_1.35VP 1 2
B B
VFB=0.75V
1
+1.35VP Ipeak=7.4A ; Imax=6A
Delta I=2.2A=>1/2Delta I=1.1A (F=521K Hz) PR61 PR60
Rds(on)=11.6m ohm(max) ; Rds(on)=9.1m ohm(typical) 0_0402_5% 10K_0402_1%
1 2
2
<24,25> SYSON
OCP = 11A~13.7A
1
@ PC65
0.1U_0402_10V7K
Choke: 7x7x3
2
Rdc=8.3mohm(Typ), 10mohm(Max)
PR62
Switching Frequency: 285kHz 0_0402_5% @ PJP4
1 2 JUMP_43X118
Ipeak=10A <24,25,50,53> SUSP# 1 2
+1.35VP 1 2 +1.35V_VDDQ
Iocp~13A
OVP: 110%~120% @ PR63
0_0402_5%
VFB=0.75V, Vout=1.3545V 1 2
<15,4> SM_PG_CTRL
1
@ PC66 @ PJP5
JUMP_43X39
0.1U_0402_10V7K 1 2
+0.675VSP +0.6V_0.675VS
2
1 2
Mode Level +0.675VSP VTTREF_1.35V
S5 L off off
A A
S3 L off on
S0 H on on
Note: S3 - sleep ; S5 - power off

Title
RT8207P
5 4 3 2 1
A B C D

SY8003_V2.mdd
1 1
PR64
0_0402_5%
EN_1.05V 1 2
SUSP# <24,25,49,53>
20141124
0.1U_0402_16V7K
1
Pull high in HW side
@ PC67
1M_0402_5%
1
PR66
Note:Iload(max)=2.5A
2
2 <25> 1.05V_VS_PG_PWR 2
2
PU4
9
1 PGND 8
FB SGND
@ PJP6 2 7 PL12
PG EN 1UH_2.8A_30%_4X4X2_F @ PJP7
+3VALW 1 2 3 6 LX_1.05V 1 2 JUMP_43X79
1 2 IN LX +1.05VSP 1 2
4 5 +1.05VSP 1 2 +1.05VS
68P_0402_50V8J
22U_0603_6.3V6M
JUMP_43X79 PGND NC
1
1
@EMI@ PR67
4.7_0603_5%
7.5K_0402_1%
22U_0603_6.3V6M
22U_0603_6.3V6M
1
PC68
PC69
1
PR68
SY8003DFC_DFN8_2X2
2
Rup
PC70
PC71
2
2
2
FB_1.05V
1
10K_0402_1%
680P_0402_50V7K
1
FB=0.6V
@EMI@ PC72
Note:Iload(max)=3A Rdown
PR69
2
2
Note:
3 When design Vin=5V, please stuff snubber Vout=0.6V* (1+Rup/Rdown) 3
to prevent Vin damage
4 4

SY8003
A B C D
5 4 3 2 1
Module model information:

Base on BDW PDDG Rev_0_73 H-side MOS: MDV1525URH
ISL95813_V1A for IC module Rds(on):
15W 28W <10.1mohm@Vgs=10V
ISL95813_V1B for SW module
<14.0mohm@Vgs=4.5V
TDC 14A TDC 19A Id :24A@Vgs=10V
Location MAX 32A MAX 40A Note

D D
L-side MOS: MDU1511RH
OCP 39A OCP 48A Rds(on):
<2.4mohm@Vgs=10V
Loadline=-2.0mv/A Loadline=-2.0mv/A
<3.3mohm@Vgs=4.5V
+1.05VS Follow intel guideline Id :100A@Vgs=10V
PR70 130_0402_1% PR89 287 Ohm 348 Ohm OCP
1 2
PR85 1.27kOhm 1.58kOhm Droop Choke: 0.15UH (Size:7*7*4)

Rdc=0.66mohm +-7%
PC88 0.033uF 0.01uF RC Match Heat Rating Current=36A
PC73
1U_0402_6.3V6K PR71 54.9_0402_1%
1 2 1 2 PR72 90.9kOhm 113kOhm PROG1
PR75 95.3kOhm 95.3kOhm IMON

<11> VR_SVID_DAT
PC83 0.1uF ( 0402 ) 0.1uF ( 0402 ) RC Filter
Note:
VR_SVID_ALRT# Pull high on HW side
<11> VR_SVID_ALRT#
EMI@ PL13
5A_Z120_25M_0805_2P
<11> VR_SVID_CLK PR72 Note: CPU_B+ 1 2
90.9K_0402_1%
C
1 2 PR72=90.9K EMI@ PL19 +19.5VB C
=>Icc(max)=33A 5A_Z120_25M_0805_2P
VR_SVID_ALRT#
CPU_B+ 1 2
fsw=700KHz
VR_SVID_DAT
VR_SVID_CLK
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V6
<11> VR_ON
10U_0805_25V6K
MDV1525URH_PDFN33-8-5
@EMI@ PC76
EMI@ PC77
1 1
PRGM1
100U_25V_M
100U_25V_M
PC74
PC75
PR73
+ +
@ PC118
PC78
1.5K_0402_1%
PQ12
1 2
2
PR74
0_0603_5% 2 2
21
20
19
18
17
<11> VGATE 1 2 4
SCLK
SDA
PAD
ALERT#
PRGM1
PC79 VR_ON 1 16 LAGTE
3
2
1
1000P_0402_50V7K VR_ON LGATE PL14
1 2 0.15UH_29A_+-20%_7X7X4_M
2 15 PHASE 1 4
PR75 PGOOD PHASE +VCC_CORE
4.7_1206_5%
@EMI@ PR76
Note: 95.3K_0402_1% 2 3
1
1 2 IMON 3 PU5 14 UAGTE
MDU1511RH_POWERDFN56-8-5
VR_HOT# Pull high on HW side IMON UGATE
5
PR77 PC80
ISL95813HRZ-T_QFN20_3X4 2.2_0603_5% 0.22U_0603_16V7K
1
PQ13
<25> VR_HOT# 4 13 BOOT 1 2 1 2
PH2 VR_HOT# BOOT PR78
2
47P_0402_50V8J
470K_0402_5%_B25/50 4700K PR79 3.65K_0603_1%

1 2 1 2 NTC 5 12 4
NTC VCC +5VS
1
680P_0603_50V7K
PC81
@EMI@ PC82
2
1
3.83K_0402_1%
PR80 COMP 6 11 PRGM2
2
COMP PRGM2
1
27.4K_0402_1%
ISUMN
ISUMP
3
2
1
2
Over temperature protection: 1 2 PC83
RTN
124K_0402_1% 0.1U_0402_25V6
FB
OTP Setting: 100C active
2
1
Pin5 (NTC) voltage <0.88V, Protect
PR81
B B
7
10
Pin5 (NTC) voltage >0.92v, recovery

5.9K_0402_1%
1
FB Note:
ISUMN
ISUMP
PR82
33P_0402_50V8J
PR81=124K
1
6800P_0402_25V7K
2K_0402_1%
10_0402_1%
=>Slew rate=53mV/us
PC84
2
PR84
Vboot = 1.7V
2
@ PR83
1
1.27K_0402_1%
PC85
@
PR85
2
1
4.99M_0402_1%
1
330P_0402_50V7K
390P_0402_50V7K
PR87
2
1
PR86
2.61K_0402_1%
@ PC86
PC87
RC Match
Droop
2
2
@
2
1
@
PC88 PC89 PR88
0.033U_0402_25V7K 0.1U_0402_16V4Z 11K_0402_1%
2
1
<11> VCCSENSE
PH3
10K_0402_5%_B25/50 4250K
@ PC90
2
0.082U_0402_16V7K
1 2 OCP Setting
PC91
330P_0402_50V7K
1
PR89
1 2
A A
@
2
PC92 287_0402_1% 20150107

1 2
change PC88 PN
0.01U_0402_50V7K from SE000006OM8 to SE000006O00
@ PC93 @ PR90
1 2 1 2
<13> VSSSENSE 123
4700P_0402_25V7K 1.5K_0402_1% Title
Local sense put on HW site ISL95813 for BDW-Y&U(15W/28W) CPU

LA-C701P
5 4 3 2 1
5 4 3 2 1
+VCC_CORE
1
BDW-U 15W
D
+ PCZ42 220uF × 1 D
220U_D2 SX_2VY_R9M
2
22uF × 7
2.2uF × 1
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2.2U_0402_10V6M
1
1
PCZ69
PCZ68
PCZ67
PCZ66
PCZ64
PCZ62
PCZ61
PCZ70
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
@ @
PCZ60 @
PCZ59 @
PCZ58 @
1
1
PCZ57
PCZ56
C C
2
B B
A A

PROCESSOR DECOUPLING
5 4 3 2 1
A B C D
UMA@ PC94
22U_0603_6.3V6M
1 2
Imax= 2A, Ipeak= 3A
1 FB=0.6V 1
UMA@ PU6
@ PJP8 SY8032ABC_SOT23-6 UMA@ PL15
JUMP_43X79 1UH_2.8A_30%_4X4X2_F @ PJP9
+3VALW 1 2 IN_1.5V 4 3 LX_1.5V 1 2 1 2
1 2 IN LX +1.5VSP +1.5VSP 1 2 +1.5VS
5 2
PG GND JUMP_43X79
6 1
68P_0402_50V8J
22U_0603_6.3V6M
22U_0603_6.3V6M
FB EN
1
UMA@ PC95
UMA@ PC96
UMA@ PC97
1
@UMAEMI@ UMA@ PR92
UMA@ PR94 PR93 15K_0402_1%
2
0_0402_5% 4.7_0603_5%
1 2
<24,25,49,50> SUSP#
EN_1.5V
Rup
2
2
0.1U_0402_16V7K
SNUB_1.5V
1
1M_0402_1%
UMA@ PR95
@UMA@ PC98
1
FB_1.5V
1
@UMAEMI@
2
PC99
680P_0402_50V7K UMA@ PR96
2
10K_0402_1% Rdown
2
Note:
When design Vin=5V, please stuff snubber
2
to prevent Vin damage 2
Vout=0.6V* (1+Rup/Rdown)

SYX196D_V3.mdd EN pin don't floating
If have pull down resistor at HW side, pls delete PR702
DIS@ PR97
0_0402_5%
1 2 SUSP#
0.22U_0402_10V6K
1
1
1M_0402_1%
DIS@ PR98
@DIS@ PC100
2
2
@DISEMI@ PR99 @DISEMI@ PC101
4.7_1206_5% 680P_0603_50V7K
3
DISEMI@ PL16
DISEMI@PL16 1 2 SNUB_1.5VGA1 2 3
+19.5VB HCB2012KF-121T50_0805
1 2 VIN_1.5VGA 8
DIS@ PU7
IN EN
1 EN_1.5VGA DIS@ PR100 DIS@ PC103
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0_0603_5% 0.1U_0603_25V7K
6 BST_1.5VGA 1 2BST_1.5VGA_R 1 2 DIS@ PL17
BS
1
1
@DISEMI@ PC102
DIS@ PC104
DIS@ PC105
1UH_11A_20%_7X7X3_M
3VLDO_1.5VGA 9
GND LX
10 LX_1.5VGA 1 2
+1.5V_VGAP
2
30K_0402_1%
330P_0402_50V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
DIS@ PR102
@DIS@
1
4
DIS@ PC106
DIS@ PC107
DIS@ PC108
DIS@ PC109
DIS@ PC110
PR101 FB_1.5VGA
FB
0_0402_5%
ILMT_1.5VGA 3 7
Rup
ILMT BYP +3VALW
2
@ PJP10
4.7U_0603_6.3V6K
2
2
ILMT_1.5VGA 2 5 3VLDO_1.5VGA 1 2
4.7U_0603_6.3V6K
PG LDO +1.5V_VGAP 1 2 +1.5VS

1
DIS@ PC112
1
DIS@ PC111
SYX196DQNC_QFN10_3X3 JUMP_43X118
DIS@ FB = 0.6V
2
20K_0402_1%
PR104
2
DIS@ PR105
0_0402_5%
Rdown
2
2
Pin 7 BYP is for CS.
The current limit is set to 6A, 8A or 12A when this pin Common NB can delete +3VALW and PC15
is pull low, floating or pull high
VFB=0.6V
4 4
Vout=1.5V

+1.5VS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-8551P
LA-C701P 0.1
A B C D
A B C D E
GPIO21 GPIO29 GPIO30 GPIO20 GPIO15 AMD MARS series LP: DDR3 AMD SUN series UL: DDR3 Description
Pro/XT/XTX: GDDR5 Pro/XT/XTX: GDDR5
VID5 VID4 VID3 VID2 VID1 VDDC
0 1 1 1 0 1.150V GPU MARS XTX MARS XT MARS PRO MARS LP SUN UL SUN PRO SUN XT NA
1 0 0 0 0 1.100V
VDDC 0.775~1.175V 0.775~1.125V 0.775~1.050V 0.775~1.000V 0.775~1.125V 0.800~1.075V 0.800~1.150V NA
1 0 0 1 0 1.050V
1 0 0 1 1 1.025V TDC 32A (TDC) 25A (TDC) 21A (TDC) 17A (TDC) 16A (TDC) 19A (TDC) 25A (TDC) NA
1 0 1 0 0 1.000V
EDC 48A 37.5A 31.5A 26A 24A 28.5A 37.5A NA H-side MOS:MDU1516
1 0 1 0 1 0.975V Rds(on):
1 0 1 1 0 0.950V OCP 57.6A 45A 37.8A 31.2A 28.8A 34.2A 45A NA 9mohm@Vgs=10V
1
1 0 1 1 1 0.925V 7.8~9mohm@Vgs=4.5V 1
Vboot 0.85V 0.85V 0.85V 0.85V 0.9V 0.9V 0.9V NA Id :11A@Ta=25 degC
1 1 0 0 0 0.900V Vboot(merge)
1 1 0 0 1 0.875V Load line 1mohm 1mohm 1mohm --------- --------- --------- 1mohm NA L-side MOS:UDU1511
Remark: Rds(on):
1 1 0 1 0 0.850V
1. PWM3 (Pin24) tie to 5V & CLK# (Pin40) external pull high Ri for OCP and 2.4mohm@Vgs=10V
1 1 0 1 1 0.825V PR860 1.13K Ohm 887 Ohm 750 Ohm --------- --------- --------- 887 Ohm LoadLine Setting 2.7~3.3mohm@Vgs=4.5V
=> 2 phase CPU VR config
PWM3 (Pin24) tie to 5V & CLK# (Pin40) tie to GND or floating Id :24A@Ta=25 degC
=> 2 phase GPU VR config Rdroop for LoadLine
PR842 1.43K Ohm 1.13K Ohm 953 Ohm --------- --------- --------- 1.13K Ohm Setting
Choke: 0.22uH (Size:7*7*4)
2. When 2 Phase GPU config PR844 187K Ohm 147K Ohm 124K Ohm --------- --------- --------- 147K Ohm for Compensation Rdc=0.98mohm +-5%
a. DPSLPVR (Pin39)=0 PSI# (Pin2)=0 Heat Rating Current=28A
=>1 phase CCM operation mode Saturation Current=28A
b. DPSLPVR (Pin39)=0 PSI# (Pin2)=1 PR847 51.1K Ohm 51.1K Ohm 51.1K Ohm --------- --------- --------- 51.1K Ohm for Positive offset
20150129
=>2 phase CCM operation mode
unpop PC801 for lose dGPU issue
c. DPSLPVR (Pin39)=1 PSI# (Pin2)=0 or 1
=>1 phase DE operation mode Remark: MARS LP/ SUN UL/ SUN PRO
don't use this 2-phase solution DISEMI@ PL810
5A_Z120_25M_0805_2P
3. Rbias=147K =>overshoot reduction function disable DIS@ PR816 1 2
0_0402_5% +3VS_VGA Vboot regulation
Rbias=47k =>overshoot reduction function enable 1 2 +VGA_B+ @DISEMI@ PL811
5A_Z120_25M_0805_2P
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
<25,37,8,9> DGPU_PWR_EN 1 2
.1U_0402_16V7K
1 +19.5VB
@DIS@ PC801
4. Thermal throttling:
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
Protect: (6.98K+Rth)*60uA=1.2V
2
=> Rth=13.02K
@DISEMI@ PC802
DISEMI@ PC803
1
1
DIS@ PC804
DIS@ PC805
=>Tp=110C (+-3C)
MDU1516URH_POWERDFN56-8-5
DIS@ PR806
DIS@ PR802
@DIS@ PR803
@DIS@ PR804
@DIS@ PR805
@DIS@ PR812
@DIS@ PR808
DIS@ PR809
DIS@ PR810
DIS@ PR811
GPU_VID5 2
GPU_VID4 2
GPU_VID3 2
GPU_VID2 2
GPU_VID1 2
GPU_VID5 2
GPU_VID4 2
GPU_VID3 2
GPU_VID2 2
GPU_VID1 2
Recovery:(6.98K+Rth)*56uA=1.24V
2
=> Rth=15.16K DIS@ PR819
Module model information:
5
1 2DPRSLPVR_VGA-1
=> Tr=105C (+-3C)
ISL62883C_V1A for IC
DIS@ PQ801
10K_0402_1%
2
PR837=6.98K PR837=1.5K DIS@ PR863 ISL62883C_V1B for SW Choke/MOS on BTN 2
0_0603_5%
protect T protect T +3VS_VGA 1 2 UGATE2_VGA 1 2 4 ISL62883C_V2B for SW Choke on BTN, MOS on TOP
@DIS@ PR831
110C +-3 100C +-3 1.91K_0402_1% DIS@ PR817 DIS@ PC806
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
<36>
<36>
<36>
<36>
<36>
2.2_0603_5% 0.22U_0603_25V7K
Recovery T Recovery T BOOT2_VGA 1 2BOOT2_2_VGA 1 2
3
2
1
DIS@ PL802
105C +-3 96C +-3 <36> GPU_PWRGD
0.22UH_PCME064T-R22MS_28A_20% +VGA_CORE
PHASE2_VGA 1 4
5. Switching frequency set : +3VS_VGA 1 2 2 3
5
VRON_VGA
DIS@ PR833
GPU_VID6
Rfset(kohm)=[period(us)-0.29]*2.65
1
PQ806
100K_0402_5%
@DISEMI@ PR827
4.7_1206_5%
Rsum
=5.9Kohm
Rbias DIS@ PR834
fsw=1/period(us)=400KHZ 147K_0402_1% Ro
3.65K_0402_1%
PSI#_VGA
1
1 2 LGATE2_VGA 4
1_0402_1%
DIS@
10K_0402_1%
10K_0402_1%
SNUB2_VGA
2
DIS@ PR828
DIS@ PR829
DIS@ PR838
DIS@ PR830
RBIAS_VGA
3
2
1
2
DIS@ PR835 DIS@
680P_0603_50V7K
Layout Note:
40
39
38
37
36
35
34
33
32
31
100K_0402_5% PU801
@DISEMI@ PC810
PH801 should place near 1 2
CLK_EN#
VID6
VID5
VID4
VID3
VID2
VID1
VID0
DPRSLPVR
VR_ON
+3VS_VGA
1
phase1 H-side MOS
30 VSUM+_VGA ISEN2_VGA ISEN1_VGA VSUM-_VGA
<25> GPU_HOT# BOOT2 29
Rth
2
1 UGATE2 28
2 PGOOD PHASE2 27
6.98K_0402_1% 470K_0402_5%_B25/50 4700K 3 PSI# VSSP2 26
1 2 1 2 4 RBIAS LGATE2 25
VR_TT# VCCP +5VS
5 24
DIS@ PR837 DIS@ PH801 VW_VGA 6 NTC PWM3 23
1U_0603_10V6K
1U_0603_10V6K
VW LGATE1
1
COMP_VGA 7 22
DIS@ PC815
DIS@ PC811
FB_VGA 8 COMP VSSP1 21
1 2ISEN3_VGA 9 FB PHASE1
Rfset
2
2
UGATE1
10 ISEN3
1000P_0402_50V7K
BOOT1
ISUM+
ISEN2
1
ISEN1
ISUM-
VSEN
IMON
DIS@ PC814
5.9K_0402_1%
VDD
RTN
+VGA_B+
VIN
22P_0402_50V8J 41
DIS@ PR839
DIS@ PC816
AGND
1
ISL62883CHRTZ-T_TQFN40_5X5
11
12
13
14
15
16
17
18
19
20
3 3
DIS@ PR840 DIS@ PC817
2
499_0402_1% 390P_0402_50V7K TDC 28A

1 2FB1_VGA
1 2
ISUM-_VGA
VDD_VGA
Peak Current = 37.5A

RTN_VGA
MDU1516URH_POWERDFN56-8-5
OCP Current = 45A
10U_0805_25V6K
10U_0805_25V6K
DIS@ PR842
BOOT1_VGA
Load line=1.1mohm
5
2.49K_0402_1% 1 2
DIS@ PC830
DIS@ PC831
+5VS
1
1 2
DIS@ PQ804
DIS@ PC821 VSEN_VGA DIS@ PR813
220P_0402_50V7K @DIS@ PR849 0_0402_5% 10K_0402_1%
1 2 VIN_VGA 1 2 DIS@ PR864
Rdroop
2
ISEN2_VGA +VGA_B+ 0_0603_5%
DIS@ PC822 DIS@ PR844 DIS@ PR846 PR813 Pop: UGATE1_VGA 1 2 4
150P_0402_50V8J 147K_0402_1% ISEN1_VGA 1_0402_5%
1 2FB2_VGA1 2 1 2 for Loadline disable
0.22U_0402_16V7K
0.22U_0402_16V7K
PR813 @: 1 2 BOOT1_1_VGA 1 2
0.22U_0603_25V7K
+5VS
1
1
DIS@ PC824
DIS@ PC825
DIS@ PC826
DIS@ PC827
DIS@ PR850
51.1K_0402_1%
for Loadline enable
3
2
1
1
2.2_0603_5% DIS@ PC832 DIS@ PL803

DIS@ PR847
1U_0603_10V6K
and LL=1mohm 0.22U_0603_25V7K 0.22UH_PCME064T-R22MS_28A_20% +VGA_CORE

2
PHASE1_VGA 1 4
for positive offset
2
2 3
PQ805
1
VSUM-_VGA
4.7_1206_5%
@DISEMI@ PR853
1 2
+VGA_CORE
LGATE1_VGA 4 DIS@
VSUM+_VGA
SNUB1_VGA
1
DIS@ PR848
1_0402_1%
DIS@ PR856
10K_0402_1%
10K_0402_1%
3.65K_0402_1%
2
DIS@ PR854
DIS@ PR855
DIS@ PR858
10_0402_1%
Cn
2.61K_0402_1%
3
2
1
@DIS@ PR851
2
1
1
@DISEMI@ PC841
680P_0603_50V7K
1
DIS@ PC833
Rp Rntcs
0.033U_0402_16V7K
1000P_0402_50V7K
0.15U_0603_16V7K
2
330P_0402_50V7K
1NTC_VGA 2
2
1
@DIS@ PC839
11K_0402_1%
1
VSUM+_VGA ISEN1_VGA ISEN2_VGA

DIS@ PC834
DIS@ PC835
DIS@ PR857
VSUM-_VGA
10K_0402_1%_B25/50 3370K
Transient response :
Rntcnet=(Rntcs+Rntc)*Rp/(Rntcs+Rntc+Rp)
2
4 4
2
Cn=L*(Rntcnet+Rsum/N)/[Rntcnet*DCR*(Rsum/N)]
DIS@ PH802
1
DIS@ PC838
1000P_0402_50V7K N is the number of phases
2
Rntc
2
Rdroop=Io*LL/Idroop
DIS@ PR860
1K_0402_1%
1 2 1 2
VSUM-_VGA
DIS@ PR859
10_0402_1% Ri Layout Note:
1
DIS@ PC842
.1U_0402_16V7K PH802 should place near Security Classification Compal Secret Data Compal Electronics, Inc.
Phase1 Choke Issued Date 2013/01/03 Deciphered Date 2013/01/03 Title
2
ISL62883C
0.1
A B C D E
A
B
C
D
DIS@ PCV78
5
5
0.1U_0402_10V7K
2 1 2 1 2 1
DIS@ PCV79 DIS@ PCV74 DIS@ PCV67 DIS@ PCV51

0.1U_0402_10V7K 1U_0402_6.3V6K 10U_0603_6.3V6M 2.2U_0402_6.3V6M
2
1
+
2 1 2 1 2 1 2 1
DIS@ PCV48
DIS@ PCV80 DIS@ PCV75 DIS@ PCV68 DIS@ PCV52 560U_2.5V_M
+VGA_CORE
0.1U_0402_10V7K 1U_0402_6.3V6K 10U_0603_6.3V6M 2.2U_0402_6.3V6M

2 1 2 1 2 1 2 1

22U_0603_6.3V6M 1U_0402_6.3V6K 10U_0603_6.3V6M 2.2U_0402_6.3V6M
2 1 2 1 2 1 2 1
2
1
+

22U_0603_6.3V6M 1U_0402_6.3V6K 10U_0603_6.3V6M 2.2U_0402_6.3V6M DIS@ PCV49
2 1 2 1 2 1 2 1 560U_2.5V_M
DIS@ PCV71 DIS@ PCV55

10U_0603_6.3V6M 2.2U_0402_6.3V6M
2 1 2 1
2
1
+

10U_0603_6.3V6M 2.2U_0402_6.3V6M
2 1 2 1 DIS@ PCV50
560U_2.5V_M
10U_0603_6.3V6M 2.2U_0402_6.3V6M
2 1
DIS@ PCV58
4
4
2.2U_0402_6.3V6M
2 1
DIS@ PCV59
2.2U_0402_6.3V6M
2 1
DIS@ PCV60
2.2U_0402_6.3V6M
2 1
DIS@ PCV61
2.2U_0402_6.3V6M
2 1
Issued Date
DIS@ PCV62
1uF x 4
2.2U_0402_6.3V6M
Security Classification
10uF × 7
2 1
560U x 3
GPU 18W
2.2uF × 16
DIS@ PCV63
2.2U_0402_6.3V6M
2 1
DIS@ PCV64
2.2U_0402_6.3V6M
2 1
DIS@ PCV65
2.2U_0402_6.3V6M
2012/04/03
2 1
DIS@ PCV66
3
3
2.2U_0402_6.3V6M
Compal Secret Data

Deciphered Date
2016/09/30
2
2
Size
Title
Date:
LA-C701P
Document Number
Saturday, January 31, 2015

VGA CHIP DECOUPLING
Sheet
of55
1
1
60
0.1
Rev
A
B
C
D
5 4 3 2 1
D D
+5VALW
+3VALW
JUMP_43X79
DIS@ PC113
1
1U_0402_6.3V6K
@ PJP11
+3VS
1
2
2
1
C
DIS@ C
2
PR107 DIS@ PC114
100K_0402_5% 4.7U_0603_6.3V6K
1 2
6
2
5 VIN_1.8V
VPP
<36> 1.8V_PWRGD 7 VIN
POK 9
TPAD
HW pull high 200Kohm to 5VS DIS@ PR106 3
16.9K_0402_1% VO
+1.8VS_VGAP
12.7K_0402_1%
DIS@ PR108
1 2 8 4
0.01U_0402_25V7K
EN_1.8V
VEN VO
22U_0603_6.3V6M
DIS@ PC115
GND
10K_0402_1%
DIS@ PR109
0.22U_0402_10V6K
FB_1.8V
<37> 0.95VSG_1.8VGS_GATE ADJ
1
1
Rup
DIS@ PC116
DIS@ PC117
2
1
DIS@ PU8
2
2 G971ADJF11U_SO8
2
2
10K_0402_1%
DIS@ PR110
20141215
change value for hw request
B PU8.8 ==> 1.1V up to enable
Rdown B
2
@ PJP12
+1.8VS_VGAP 1 2 +1.8VS_VGA
1 2
JUMP_43X79
Vout =1.816V
A A

+1.8VS_VGA
Document Number Rev
B 0.1
LA-C701P
Date: Sheet 56 of 60
5 4 3 2 1
5 4 3 2 1
D D
AC
Adapter 19.5V
P.45 RT8243AZQW +1.05VS

+3VDS
Vin SY8003DFC
+3VLP SUSP#
EN EN PGOOD P.50
Charger +19.5VB
Charge 1.05V_VS_PG_PWR
Vin
BQ24735RGRR
DC/DC
P.47 (+5VALW/+3VALW) +1.5VS
+3VDS
Vin SY8003DFC
SUSP#
EN PGOOD
DC Discharge P.53
Battery
4S1P PGOOD P.48
P.46
SPOK
+1.35V_VDDQ
C Vin DDR +0.6V_0.675VS C
SYSON RT8027MZQW
EN
SUSP# P.49
+VCC_CORE
Vin ISL95813
VR_ON DC/DC
VR_ON VGATE
(CPU_CORE) PGOOD
P.51, 52
+1.5VS
Vin SYX196D
SUSP#
EN
P.53
B B
+VGA_CORE
Vin ISL62883C
DC/DC GPU_PWRGD
EN (VGA_CORE)
DGPU_PWR_EN
P.54, 55
+1.8VS_VGA
+3VALW
Vin G971A
DC/DC
EN
0.95VSG_1.8VGS_GATE
P.56 1.8V_PWRGD
A A

Power Block Diagram
5 4 3 2 1
5 4 3 2 1
Version change list (P.I.R. List)

Fixed
Item Date Reason for change Modify List Phase
Issue
D 1 change size use common part for 7x7 change PL202 size from 10x10 to 7x7 SI D
2 PR224 and PR225

change part no need 0ohm SI
change from 0ohm to short pad
3 change part HW request Change R, C value SI
PR106 100k => 16.9k
PR109 47k => 10k
PC116 0.1U => 0.22U
4 change part Change PN PC88 from SE000006OM8 to SE000006O00 PV
5 20150129 for lose dGPU issue unmount PC801 PV

C C
B B
A A

Issued Date Title
Deciphered Date
PIR List
B 0.1
LA-C701P
5 4 3 2 1
A B C D E
CPU_B+
Bead PU5 +VCC_CORE +3VS
PL13 ISL95813HRZ-T
EN Buck
CPU +1.05VS
VR_ON
+1.35V_VDDQ
1
PJP4 1
B+_DDR
Bead PU3 +1.35VP
PL10 RT8207PGQW DDR3L
EN Buck
SYSON
SO
SUSP#
+0.675VSP
DIMM
GPU
DP_VDDC
Bead B+_0.95V PU4
+1.05VS U4102 +1.05VS_VGA PCIE_VDDC
PL12 SY8003DFC DC/DC BIF_VDDC
EN Buck DGPU_PWR_EN#
SPLL_VDDC
+3VALW SUSP#
Bead B++ PU2

RT8243AZQW +5VALW Q21 +5VS LA4 +5VS_PVDD Audio Codec
PL7 DC/DC
EN3V/5V Buck SUSP#
PVDD
EC_ON LA6 +5VS_AVDD Audio Codec

+3VL AVDD
Lid Switch R201 +5VS_HDD1

2.5" SATA HDD
2
AC Adapter VIN 2
US1 +USB_VCCA
(15V - 19V) SY6288D20AAC USB3.0
EC Switch Port U20 +5VS_ODD
USB_ON# ODD
DC/DC
ODD_PWR
FG1 +HDMI_CRT_5V
Battery 19.5VB USB2.0
DC/DC
CRT Conn.
port/SB
Charger
KBD
CHG_ACDET EN HDMI Conn.
14.8V_BATT
Battery FAN
+3VALW Q21 +3VS

DC/DC
SUSP#
DP to VGA U20 JPHW3

Touch Panel Card Reader LCDVDD LVDS Panel Touch Pad Thermal Sensor TPM DC/DC
transmitter FAN
/SB NCT7718 WL_PWREN_EC
RTD2168
+3VALW +3VS_WLAN_R +3VS_RT
3 3
Q30
eDP to LVDS
For UMA Touch Pad Touch Panel EC LAN 8166EH WLAN transmitter
RTD2132N
PU6
Bead SY8032ABC +1.5VS +3V_PCH
PL15 Buck
SUSP#
For Discrete
U4101 Audio Codec SPI ROM 8M
AVDD
B+_Vramp PU7 DC/DC
Bead SYX196DQNC
PL16 Buck PXS_PWREN#
SUSP#
U4103
DC/DC
DGPU_PWR_EN
PU8
G971ADJF11U
Buck
0.95VSG_1.8VGS_GATE
GPU
+1.5VS_VGA
+1.8VS_VGA +3VS_VGA
GPU
DP_VDDR VDDR3 GPU EXO GPU_GDDR3 GPU_GDDR3
PCIE_PVDD TSVDD MEM Upper Lower
4 4
VDD_GPIO18 SPLL_PVDD
MPLL_PVDD
Bead VGA_B+ PU801 +VGA_CORE GPU

PL800 ISL62883CHRTZ-T
VDDC
EN Buck
DGPU_PWR_EN

System Power Tree
E 1.0
Date:
LA-C701P
A B C D E
5 4 3 2 1

Fixed
Issue
1 2014-11-25 A32 request [A32] Reserve XDP circuit DB
D D
2 2014-11-25 A32 request [A32] Reserve SMBUS from CPU to TP module DB
3 2014-11-25 BDW CPU ESD issue BDW CPU ESD issue solution [Compal] Reserve Capx19 & Varistor x13 for BDW CPU ESD issue DB
4 2014-11-25 [HP] Reserve XDP circuit A32 request [A32] eDP to VGA solution Sanrio--ITE IT6513 Candy--RTD2168 DB
5 2014-11-25 A32 request [A32] KBC solution solution Sanrio--ENE KBC9012 Candy--ENE KBC9022 DB
6 2014-11-25 reduce component [Compal] Remove WLAN LED circuit ,use KBC GPIO DB
C
7 2014-11-25 A32 request [A32] reserve TPM 1.2 & 2.0 TPM 1.2--SLB9665 TPM2.0--SLB9660 DB C
8 2014-11-25 reduce component [Compal] ODD load switch Sanrio use single load switch Candy use dual load switch DB
9 2014-11-25 A32 request [A32l] Change WLAN connector Sanrio--mini card Candy--M.2 Conn DB
10 2014-11-25 reduce component DB

[Compal] Sanrio use power switch for Fan control , Candy use PWM control from KBC
11 2014-11-25 A32 request [A32] Card reader solution Sanrio--RTS5239 Candy--RTS5141 DB
12 2014-11-25 A32 request [A32] GPU solution Sanrio--Nvidia N15V-GM (17W) Candy--AMD Exo pro (18W) DB
[Compal] +3VS to +3VS_VGA from dual load switch to single load switch
13 2014-11-25 reduce component DB
B
+1.8VS_VGA power direct support B
14 2014-12-14 For LAN 1V regout [Compal] Pop LL3 SI
15 2014-12-14 For fine turn DGPU power sequence [Compal] Change C4122 value from 0,01u to 0.22u SI
16 2014-12-14 For fine turn DGPU power sequence [Compal] Change R4109 value from 200K to 6.98K SI
17 2014-12-14 For fine turn DGPU power sequence [Compal] Change C4109 value from 0,01u to 0.027u SI
18 2014-12-14 Modify WLAN PCIE CLK request channel [Compal] Modify WLAN CLK request channel from 2 to 5. SI
A A

Issued Date Title
Deciphered Date
HW PIR List
B 0.1
LA-C701P
5 4 3 2 1
5 4 3 2 1

Fixed
Issue
19 2014-12-14 Modify DGPU PCIE CLK request channel [Compal] Modify DGPU CLK request channel from 3 to 4. SI
D D
20 2014-12-14 Modify LAN PCIE CLK request channel [Compal] Modify LAN CLK request channel from 0 to 2. SI
21 2014-12-23 HP request add thermal sensor for CPU PCB. [Compal]Add CPU external Thermal sensor at EC_SMB_CK2/DA2. SI
22 2014-12-23 CPU and GPU thermal sensor can't on the same bus. GPU thermal sensor change to EC_SMB_CK3/DA3 SI
23 2014-12-23 Modify EC co-lay pin117 & 124. SI
24 2014-12-24 EMI request to change HDMI schematic. SI
C
25 2014-12-25 Reserved +5VS Touch power. SI C
26 2015-01-26 BIOS request. Add pull-up at PCIECLKREQ1# PV
27 2015-01-27 SVTP 3-9 fail. R38 power change to +HDMI_CRT_5V , L7,L8,L9 change P/N. PV
28 2015-01-27 SVTP 3-9 fail. Remove Hsync,Vsync Buffer footprint. PV
29 2015-01-28 Reserved for test. Reserved 0 ohm on ODD_PLUG# , between CPU and ODD. PV
210 2015-01-30 EMI request Add 680p at PWR_LED#
B B
A A

Issued Date Title
Deciphered Date
HW PIR List
B 0.1
LA-C701P
5 4 3 2 1

La C701P

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A B C D E

Broadwell M/B Schematics Document 2

Intel ULV Processor with DDRIIIL

Security Classification Compal Secret Data Compal Electronics, Inc.

LAN Lane 5 PCI-E Port 1

Port 6 Card reader

P26 Int.KBD ENE KB9022 LPC

P37 NCT7718 SPI ROM

Power rail Control (EC) Source (CPU)

6 Card reader Card reader

<11,6,9> +1.05VS_VCCST +1.05VS_VCCST

<11,15,16,17,34,49> +1.35V_VDDQ +1.35V_VDDQ

<10,11,12,24,36,6,7,9> +3V_PCH +3V_PCH

<20> PCH_DPB_N2 C54 C45 +VCCIOA_OUT

RC11 2 1 10K_0402_5% H_CPUPWRGD_R

RC4 PROC_DETECT# D61

PREQ E60 XDP_TCK

SM_RCOMP1 BPM#5 XDP_TRST#_CPU <6>

SI : pop CC88 SA00004BV00

Security Classification Compal Secret Data Compal Electronics, Inc.

Date: Saturday, January 31, 2015 Sheet 4 of 61

<17> +V_SM_VREF_CNT +V_SM_VREF_CNT

BDW_ULT_DDR3L(Interleaved) <17> +V_DDR_REFB_R +V_DDR_REFB_R

UCPU1C BDW_ULT_DDR3L(Interleaved) <DDR3L>

DDR_A_D57 AW19 SA_DQ56 SA_DQSP7 DDR_B_D58 AK18 SB_DQ57

Security Classification Compal Secret Data Compal Electronics, Inc.

<12,15,16,18,19,20,21,22,23,24,25,27,31,32,33,34,35,36,37,56,7,8,9> +3VS +3VS

<12,19,22,24,25,26,28,29,32,37,48,50,53,56,7> +3VALW +3VALW

RC41 @ RC46 <4> XDP_TRST#_CPU XDP_TRST#_CPU 14 13 XDP_TRST#

RC301 @ RC302 74CBTLV3126DS_SSOP16

RC304 @ RC303 @ +VCCIO_OUT JXDP1

Security Classification Compal Secret Data

<12> +1.05VS_AXCK_LCPLL +1.05VS_AXCK_LCPLL

RC376 LPC_AD0 AU14 AN2 SMBALERT# RF solution

SML0DATA 1K_0402_5% 1 2 RC73

1 EMI@ 2 EC_SPI_CLK_R RC56 1 2 0_0402_5% PCH_SPI_CLK_R

+3V_PCH +3VALW +3VS

+3VS CPU THERMAL SENSOR

CC120 TP@ SML1CLK 6 1

A H_THERMDA 2 7 EC_SMB_DA2 2N7002DWH_SOT363-6 2N7002DWH_SOT363-6 A

Address: 1001100xb NCT7718W

<12,28,6> +RTCVCC +RTCVCC

<10,11,12,24,36,4,6,7,9> +3V_PCH +3V_PCH

<12,15,16,18,19,20,21,22,23,24,25,27,31,32,33,34,35,36,37,56,6,7,9> +3VS +3VS

CK0402101V05_0402-2 T83 RC268 1 short@ 2 0_0201_5% PM_SLP_S0#_R

SUSCLK RC109 1 2 10K_0402_5%

C PCH_RSMRST# RC106 2 1 10K_0402_5% C

1 short@ 2 0_0402_5% DGPU_PWROK_CPU U6

Security Classification Compal Secret Data Compal Electronics, Inc.

<10,11,12,24,36,4,6,7> +3V_PCH +3V_PCH <11,4,6> +1.05VS_VCCST +1.05VS_VCCST

<12,8> +3V_DSW _P +3V_DSW _P <12,15,16,18,19,20,21,22,23,24,25,27,31,32,33,34,35,36,37,56,6,7,8> +3VS +3VS

<25> NMI_DBG#_CPU NMI_DBG#_CPU AK4 GPIO L5

A * GPIO27 RC277 1 2 10K_0402_5% EC_PME#

PCH_GPIO27 (Have internal Pull-High)

<11,12,24,36,4,6,7,9> +3V_PCH +3V_PCH

<35> PCIE_CRX_GTX_N0 F10 AN8

<22> PCIE_PRX_DTX_N3 PCIE_PRX_DTX_N3 G11

Security Classification Compal Secret Data

<34,51,52> +VCC_CORE +VCC_CORE

<15,16,17,34,4,49> +1.35V_VDDQ +1.35V_VDDQ

<4,6,9> +1.05VS_VCCST +1.05VS_VCCST

<4,6> +VCCIO_OUT +VCCIO_OUT

<4> +VCCIOA_OUT +VCCIOA_OUT