1-MHz Self-Driven ZVS Full-Bridge Converter for
48-V Power Pod and DC/DC Brick
Ming Xu, Yuancheng Ren, Jinghai Zhou, and Fred C. Lee, Fellow, IEEE
Abstract—In this paper, a self-driven zero-voltage-switching
(ZVS) full-bridge converter is proposed. With the proposed
self-driven scheme, the combination of the ZVS technique and
Self-driven technique recycles the gate driving energy by making
use of the input capacitor of the secondary side synchronous rec-
tifier (SR) as the snubber capacitor of the primary side switches.
Compared with the external driver, the proposed converter can
save driving loss and synchronous rectifier body diode conduc-
tion loss. Additionally, compared with the existed level-shifted
self-driven scheme for bridge-type symmetrical topologies, its gate
signal is very clean and suitable for high-frequency applications.
A 1-MHz, 1.2-V/70-A prototype is built to verify the analysis.
Experimental results show that it can achieve 81.7% efficiency.
And there is an efficiency improvement of 4.7% over conventional
phase-shifted full-bridge converter with an external driver.
Index Terms—DC/DC brick, power pod, self-driven, zero voltage
switching (ZVS).
I. INTRODUCTION
M OST of today’s high-performance microprocessors for
workstations and servers are 64-b, and their power con-
sumption is higher than those of the 32-b microprocessors such
as the Pentium IV and the Xeon. Usually, the server has several
64-b microprocessors working together (see Fig. 1). So, com-
pared with the desktop voltage regulator module (VRM), the
server consumes much higher power (around several KW). As
a result, in order to reduce the loss on the bus, the power ar-
chitecture of the server or workstation uses a 48-V distributed
power system (DPS) instead of the 12-V bus in the desktop.
Besides lower loss on the bus, in a high-voltage DPS the tran-
sient response of the load has less effect on the bus voltage, as
well as less effect on the other loads. The input filter size of
the high-input-voltage power pod can be reduced significantly
[1]. Another merit of the 48-V-input power pod is that because
transformers are used, the duty cycle can be optimized for ef-
ficiency, ripple-canceling effect and transient by adjusting the
turn’s ratio.
The development of the server’s power supply, normally
called the power pod, has been driven by the fast development
of microprocessors. Most of today’s server microprocessors
operate with voltages between 1.3 V and 1.8 V and with
100-A current. And the current slew rate during a transition
Manuscript received January 5, 2004; revised February 21, 2005. This work
was supported by Intel, Texas Instruments, National Semiconductors, Intersil,
TDK, Hitachi, Hipro, Power-One, Delta Electronics, and ERC shared facilities
supported by the National Science Foundation under Award EEC-9731677.
The authors are with the Center for Power Electronics Systems, The Bradley
Department of Electrical and Computer Engineering, Virginia Polytechnic Insti-
tute and State University, Blacksburg VA 24061 USA (e-mail: mingxu@vt.edu).
Digital Object Identifier 10.1109/TPEL.2005.854019
© 2005 IEEE. Reprinted, with permission, from IEEE Transactions on Power Electronics 2005.
27
Fig. 1. Server power architectures.
is around 100 A/us. To further increase the processing speed
and decrease the power consumption, the operating voltages
of the next generation of computer microprocessors will be
reduced below 1.0 V. At the same time, it is expected that these
processors will require much more power and will present even
more dynamic loads than today’s microprocessors. To meet
the stringent transient response requirement and to reduce the
passive component size, the power pod switching frequency
should be pushed to the MHz range. This is a great challenge
for power pod design.
Today’s power pod uses pulse width modulation (PWM)
hard-switching topologies with synchronous rectifier (SR),
such as the half bridge [2], push-pull forward [3], full-bridge,
etc. In other work [4], a thorough comparison is made. The
push-pull forward converter with integrated magnetics shows
better performance than other topologies. However, when the
switching frequency is pushed to 500 kHz, the efficiency drops
dramatically (to around 10%). It can only reach around 75%
efficiency. Loss analysis indicates that high switching loss, high
body diode loss and high SR gate driving loss are three major
reasons.
Because the 48-V PWM topology is unable to achieve high
switching frequency, large output inductance and capacitance
have to be used, which results in a large footprint and high cost.
Generally, the output capacitors are one of the most expensive
parts in a power pod.
To reduce the switching loss, the phase-shifted full-bridge is
widely used because of its good performance and simple struc-
ture. At the same time, self-driven structures are also widely
used in the industry practice due to their simple structures and
low cost. However, for bridge-type symmetrical converters,
implementation of self-driven capability is difficult because
of dead time. One solution is the level-shifted self-driven
concept [Fig. 2(a)] [5]. Its real working waveforms, shown in
Fig. 2(b), illustrate that this configuration has several issues, as
follows: a) ringing occurs at the gate signal because the signal
is coming from the main power transformer and severe ringing
Fig. 2. The level-shifted self-driven scheme for bridge-type symmetrical converter: (a) level-shifted self-driven circuit and (b) operation principle of level-shifted
self-driven circuit.

Fig. 3. Proposed ZVS full-bridge and its control strategy: (a) power stage and (b) control strategy.

is coupled from the power stage, b) there is extra body diode in Fig. 3(b). For each leg of the primary side, the control is asym-
conduction loss, and c) there is large amount of conduction loss metrical. But for the main transformer, the voltage is still sym-
due to the low driving voltage during dead time. These issues metrical. Therefore, this control has the same transient response
prevent the level-shifted self-driven concept from being used in performance as the phase-shifted and other symmetrical PWM
high-frequency applications. controls. The detailed operation principle is illustrated in Fig. 4.
In order to overcome these issues, a self-driven zero-voltage- In stage 1 and are on and is off. The
switching (ZVS) full-bridge is proposed. The power stage is energy is transferred from the primary side to the output, which
shown in Fig. 3(a). By simply rearranging the control strategy, is the same as in the conventional phase-shifted full-bridge
it becomes very suitable for self-driven capability as well as (PS-FB).
achieving ZVS. The analysis shows that the self-driven quality In stage 2 turns off at and the reflected
can save driving loss and body diode conduction loss. The output current discharges and charges the output capacitor of
experimental results verify the analysis and reveal that this and , respectively. Given a suitable dead time, ZVS can
self-driven full-bridge is very promising for high-frequency be achieved. This stage is the same as the ZVS realization of the
applications. leading leg of the conventional PS-FB.
In stage 3 , the energy stored in the leakage inductor
of the transformer freewheels through and .
II. OPERATION PRINCIPLE OF THE POWER STAGE In stage 4 turns off at . The leakage inductor
of the transformer resonates with the output capacitors of
To make the bridge-type symmetrical converter more suitable and . At certain load conditions, energy stored in the leakage
for being self-driven, the control strategy is changed, as shown inductor is high enough to achieve ZVS for . This stage is
28
Fig. 4. Operation stages of the proposed circuit.
the same as the ZVS realization of the lagging leg of the con-
ventional PS-FB.
From , another half period starts, and the operation prin-
ciple is same except for polarity changes.
From the description of the operation principles, it is obvious
that this asymmetrical control strategy still achieves ZVS for the
primary switches, which is very important for high-frequency
applications.
III. IMPLEMENTATION OF THE SELF-DRIVEN SCHEME
Fig. 3(b) shows that the gate signal for SR is the same as the
voltage waveform at point A or B so that the signal and en-
ergy from these points can be used to drive the SR’s. Taking
the Q3-Q4-bridge as an example, a traditional level-shifted gate
drive scheme that can transfer a wide range of the duty cycle is
shown in Fig. 5. C and C represent the output capacitors
of Q3 and Q4, respectively. C is an additional snubber capac-
itor that is commonly seen in ZVS type converters. C is the
input side dc blocking capacitor with a bias voltage
The purpose of C is to level-shift the transformer secondary
voltage so that the gate voltage has the same waveform as .
Usually a diode is paralleled to the gate to provide a charging
path for C during the Q3 off period.
When the duty cycle of reduces during the step-down tran-
sient, for example, from D1 ( 0.5) to D2 ( 0.3) at time t (
5 ms), the voltage across C will change from to its
new steady state, . This excites an oscillation between
C and , the magnetizing inductor of the driver transformer.
The peak-to-peak amplitude will be – . However,
Fig. 5. Level-shifted driving scheme used in the isolated topologies.
on the secondary side, C lacks of a current path to discharge
it so that its voltage stays unchanged. This mismatch between
the bias voltages across C and C causes severe problems as
shown in Fig. 6(b). The SR gate voltage flies during the tran-
sient and the SR cannot be turned off properly.
To solve this problem, a new driver scheme is proposed, as
. shown in Fig. 7. A small MOSFET, (TSOP-6 package), re-
places the diode in Fig. 5, and a third winding is used to drive
it. During Q4 on time, the bias voltage across C will drive
to be on, which makes C in parallel with C and the voltage
across C can follow that across C instantaneously. Because
the gate of sees a negative voltage during its off time, low
threshold MOSFET is preferred in order to guarantee turning
on when C has very low bias voltage. This adding also pro-
vides fairly low gate-to-source impedance during the SR off pe-
riod to avoid any faults trigger due to the miller effect. The sim-
ulation waveforms in Fig. 8(a) show that the bias voltages across
29
Fig. 6. Waveforms of the driver shown in: (a) voltage across C (top) and across C (bottom) and (b) input signal V (top) and gate voltage V (bottom).

the steady state gate drive voltage is used to quantify the ringing,
which is

(1)

An additional gate resistor is used to dampen these os-

cillations, seen in Fig. 12(a). Since the analysis focuses on SR
turn-on interval, the tiny MOSFET has no effect and is not
drawn in the circuit. The insertion of increases the gate drive
loss, which will be discussed in the later part of the paper. Here,
the relationships of the gate voltage overshoot with ,
and , the rise-time of the voltage at node B, are analyzed
Fig. 7. Proposed self-driven circuit for the ZVS FB topology shown in Fig. 3. firstly. In Fig. 12(a), the voltage at node B, , is actually the
input source of the SR gate drive circuit. During the rising
edge of turns off. The reflected output inductor current
discharges output capacitor of C , and charges that of
C and C match well after a sudden duty cycle change. The C . Meanwhile, the snubber capacitor C and the gate
SR gate voltage duplicates the input voltage all the time, as capacitor C are also charged by this current. The reflected
shown in Fig. 8(b). filter inductor has fairly high impedance, and therefore, can be
Besides the full-bridge, the proposed self-driven method can modeled as a constant current source. To simplify the analysis,
also be applied to any other asymmetrically controlled topolo- we assume that increases linearly with a slope of , which
gies, such as the active-clamped forward (Fig. 9), forward-fly- is
back and asymmetrical half bridge (Fig. 10). The secondary
side can be a current doubler, a half-wave rectifier or a center- (2)
tapped rectifier. The cross-coupled structure can be applied in C
the proposed self-driven topology, and unlike the self-driven ap- where is the load current, is the power transformer turns
plication in the full-bridge converter, no additional windings are ratio, and C is the sum of C C C and the reflected
needed to deal with the transient issue specially. C . Also, the rise time of , can be calculated as .
Now we can stimulate the gate drive circuit using , a ramp
step signal. Fig. 12(b) shows an equivalent circuit when is
IV. ANALYSIS OF THE PROPOSED SELF-DRIVEN SCHEME
reflected to the secondary side of the driver transformer in which
A. SR Gate Voltage Ringing Analysis , and .
Define a function as
The addition of the driver transformer leakage and parasitic
trace inductances causes an oscillation between the leakage in-
(3)
ductors and the gate capacitor of the synchronous rectifiers. This
gate voltage ringing not only causes reliability problems of the
SR devices, but also increases the on resistance of the SR de- then, the input signal in Fig. 12(b) can be represented as
vices when it resonates back to its valley, as illustrated in Fig. 11. (4)
In Fig. 11, the ringing occurs only at the rising edge. The tiny
MOSFET across the SR gate and source clamps the ringing at where , and is the turns ratio of the gate driver
the falling edge. The percentage of the overshoot voltage over transformer. One can derive the time domain voltage waveforms
30
Fig. 8. Waveforms of the driver shown in Fig. 7: (a) voltage across (top) C and across (bottom) C and (b) input signal (top) V and gate voltage (bottom) V .

Fig. 9. Active-clamped forward with the proposed driver scheme.

across the gate capacitor, C , by Laplace transformation, as Fig. 10. Asymmetrical half bridge with the proposed driver scheme.
follows:

(5)

where

(6)
C

(7)
C Fig. 11. SR gate voltage when parasitic inductance and resistance are
considered.
(8)

(9) B. SR Gate Drive Loss Analysis

Turn-on of SR: The equivalent circuit shown in Fig. 12 can
According to (5), the peak value of the gate voltage C also be used to calculate the gate drive loss during the turn-on
is calculated and plotted as a form of overshoot percentage transition, which is the total energy dissipation on when the
over the different , and in Fig. 13. In the plot, we voltage across C rises from zero to its steady state. The in-
assume that the circuit drives two ST160NF02L MOSFETs stantaneous current in the driver loop during turn-on transition
from ST Semiconductors, which has a total input capacitance is calculated as
of 10 nF. Fig. 13(a) fixes 20 ns while varying and .
When increases, or decreases, the overshoot will be C C
less. Fig. 13(b) shows the overshoot with a fixed (0.5 )
while varying and . It is an important characteristic of C
this driving scheme that the ZVS operation of the power stage
reduces the gate ringing by means of increasing [6]–[11]. (10)
31
 discharge C C , and C . Ideally, if the gate driver path has
zero inductance and zero resistance, C C and the reflected
C are all in parallel and serve as a snubber capacitor of Q4.
As long as the ZVS condition is met, the gate charge can be all
recovered. The ZVS condition can be simplified as

C
(13)

Fig. 12. Turn-on equivalent circuit with
circuit and (b) the simplified circuit.
Fig. 13. Gate voltage overshoot versus (a) R and (b) t .
L and R : (a) turn-on equivalent where is the minimum load current required to achieve
ZVS for Q4. However, because of and , not all the gate
capacitor energy can be recovered. In Fig. 15(a), there are four
energy storage components and to get an analytical solution
becomes extremely complicated. As an alternative method, it
was simulated using the SABER simulation tool to analyze the
turn-off loss savings. The simulation was set up with the fol-
lowing conditions: 1 MHz, 48 V,
70 A, 4 nH; the primary devices are Hitachi’s
HAT2175, which has a C of 185 pF; C 1 nF, and there are
two ST160NF02L synchronous rectifiers in parallel. Fig. 15(b)
shows the turn-off losses of the self-driven circuit versus a con-
ventional external voltage driver for one leg of the current dou-
bler. The simulation was run while varying the gate drive re-
sistor and the gate drive transformer leakage inductor .
According to Fig. 15, the turn-off gate drive loss has similar re-
lationship with and as compared to the turn-on case.

C. SR Gate Driving Delay and Body Diode Conduction

Analysis
Due to the existance of and , there is a time delay from
the primary side node B to the SR gate. This time delay has to be
taken into account because it may cause additional body diode
conduction or shoot through problems. For the rising edge, ac-
cording to (4) and (5), the voltage waveforms at node B and
SR gate are determined. For a given threshold voltage, 1 V for
ST160NF02L, the delay time is plotted as a function of with
different in Fig. 16(a).
Fig. 14. Calculated turn-on gate driver loss. For the falling edge, since we cannot get a simple analyt-
ical solution for and , the Saber simulation tool is used
again. The curves in Fig. 16(b) show the relationship between
so that the turn-on gate drive loss is the falling edge delay time, and . It is interesting that there
are cases with negative delay time, which means that actu-
C (11) ally drops to earlier than . The reason is that when is
small, the oscillation between and C is not well dampened,
For a conventional external gate driver circuit, the power dis- so that may go below at some point.
sipation during the turn-on interval is calculated as The delay time for two edges has different impact on the
C (12) SR operations. Firstly, let us go back to Fig. 3 to see how cur-
rent flows at the secondary side before and after turns on
note that is a Rg independent variable. To drive a pair (rising edge). Before is off, is positive and equal to
of ST160NF02L at a switching frequency of 1 MHz, the gate half the load current. After a very short transition period
driver losses during turn-on by the proposed self-driven scheme turns on so that both the primary and the secondary of
and by the conventional method are plotted in Fig. 14. It also the power transformer are shorted. There is no voltage applied
shows that the larger the , the less the loss savings. Consid- to the leakage inductance , therefore continues to flow
ering the overshoot as discussed previously, also a smaller through its previous path before . In another word, no cur-
is preferred. It is very important to minimize by all means. rent flows through although it is ready to take the current.
Turn-off of SR: The equivalent gate driver circuit of the This zero-current-turn-on feature makes the rising edge of its
turn-off of SR is shown in Fig. 15(a). The energy stored in the gate signal less critical as long as the delay does not exceed the
transformer leakage inductor helps to charge C , and to overlapping time .
32
Fig. 15. Turn-off equivalent circuit (a) and the simulated turn-off gate driver loss (b).

Fig. 16. (a) Turn-on and (b) turn-off delay time.

Fig. 17. (a) Equivalent circuit and (b) key waveforms during S1 turn-off.
Fig. 18. Body diode conduction loss compared with the conventional
phase-shifted FB converter.

For the falling edge of the gate signal, the delay time in
fact may help to reduce the body diode conduction period. On drops to zero at . At the same time, S1 is turned off if the
the other hand, too much delay time will cause severe shoot delay time is zero. However, the current through S1 continues
through problem. The following analysis gives the maximum to flow until the current through the transformer secondary side
falling edge delay time. Firstly, assuming and are all winding changes its polarity from to at . From
zero, the gate voltage of an SR exactly follows with no to , the body diode of S1 conducts the current and the body
delay, as shown in Fig. 17(a). diode conduction loss for S1 can be calculated as
When Q3 is turned off at , the transformer leakage inductor
begins to resonate with C until the voltage at point B (14)

33
Fig. 19. Prototype of the (a) proposed self-driven ZVS FB and (b) its efficiency curve.

Fig. 20. Circuit waveforms: (a) ZVS condition for the primary switches and (b) the transformer primary current I , the voltage at point B V , and the gate
signal for the synchronous rectifier V .

where is the body diode forward voltage drop, typically Fig. 18 shows the total body diode conduction loss compar-
0.7 V. fs is the converter switching frequency ison between a phase-shifted FB converter with external driven
scheme and the proposed circuit. A typical gate dead time of
20 ns is set for the external driver. The transformer leakage in-
(15)
ductance is the variable. Both systems run at 1 MHz, 70 A load
current.
(16)
V. EXPERIMENTAL RESULTS
(17) A 1.2-V/70 A 1-MHz prototype is built to verify the analysis.
C The components are listed as follows. Primary switch: Si4850.
The delay time between and SR gate, when positive, helps Secondary switch: ST160NF02LA*2 for each branch of a cur-
to reduce , therefore reduces the body diode conduction loss. rent doubler. Transformer: nine-layer (2 oz), Philips EI-14 core.
In order to avoid severe shoot through problems, the delay time Inductor: 150 nH, nine-layer (2 oz), Philips EI-18 core. Output
must be less than . However, varies according to the dif- capacitor: 4*ESRE 270 uF. Gate resistance: 0.5 . Gate trans-
ferent load current . The possibility of shoot through at light former: TDK EE9.5. Gate MOSFET: Si3900.
load exists. Fortunately, the inclusion of the tiny gate MOSFET The prototype picture is shown in Fig. 19(a). Fig. 19(b) shows
as showed in Fig. 7 helps to prevent this from happening. The the efficiency comparison. Including the driver loss, the pro-
SR gate will clamp to ground as soon as touches zero at time posed self-driven ZVS full-bridge can achieve 81.7% efficiency.
in Fig. 17, no matter how much delay time is there. There is an efficiency improvement of 4.7% as compared with
34
Fig. 21. Gate voltage waveforms during a duty change: (a) with the conventional driver scheme in Fig. 5 and (b) with the proposed driver scheme in Fig. 7.
the conventional phase-shifted full-bridge with an external
driver. Fig. 20(a) shows the ZVS condition of the primary
switches. Fig. 20(b) shows the gate signal for the synchronous
rectifier. The waveform of the gate signal follows the voltage at
point B and is very clean.
Fig. 21 demonstrates the different experimental results
achieved with the conventional driver scheme (Fig. 5) and the
proposed driver scheme (Fig. 7), respectively. It is obvious
that the secondary-side gate signal of the conventional driver
cannot go back to the zero level when the primary-side signal
has a sudden duty-cycle change. The proposed driver scheme
can solve this problem. Additionally, compared with the diode
paralleled with the gate of SRs, the tiny MOSFET can help
SRs achieve faster turn-off due to the low impedance turn-off
path.
VI. CONCLUSION
A new method of self-driven synchronous rectification is
proposed in this paper. The self-driven circuit has gate drive
loss saving properties, a fast driving speed, and can hold syn-
chronous rectifiers on at the correct gate drive voltage, where
the state-of-the-art self-driven gate drive circuit cannot. The
proposed self-driven circuit is used in conjunction with a com-
plementary-controlled full bridge circuit with a current-doubler
secondary, which has ZVS property, an important feature for
high frequency operation. Moreover, the proposed self-driven
gate drive circuit can be applied to any complimentarily con-
trolled converter.
Due to the parasitic components in the gate drive path, this
paper analyzed the gate voltage ringing, the gate drive loss
saving, the gate drive delay, and the body diode conduction loss
saving. There are significant benefits in these aspects, which
is experimentally verified. The proposed circuit is potentially
35
a very promising candidate for high frequency, high current
dc-dc conversion applications.
ACKNOWLEDGMENT
The authors would like to thank Dr. K. Yao for his valuable
discussions.
REFERENCES
[1] X. Zhou, X. Zhang, J. Liu, P. Wong, J. Chen, H. Wu, L. Amoroso, F. C.
Lee, and D. Y. Chen, “Investigation of candidate VRM topologies for
future microprocessors,” in Proc. IEEE APEC’98, 1998, pp. 145–150.
[2] Y. Panov and M. Jovanovic, “Design and performance evaluation of
low-voltage/high-current dc/dc on-board modules,” in Proc. 14th Annu.
APEC’99, vol. 1, 1999, pp. 26–33.
[3] X. Zhou, B. Yang, L. Amoroso, F. C. Lee, and P. Wong, “A novel
high input voltage, high efficiency and fast transient voltage regulator
module—Push-pull forward converter,” in Proc. IEEE APEC’99, 1999,
pp. 279–283.
[4] M. Ye, P. Xu, B. Yang, and F. C. Lee, “Investigation of topology candi-
dates for 48 V VRM,” in Proc. 17th Annu. IEEE APEC’02, vol. 2, 2002,
pp. 699–705.
[5] P. Alou et al., “A new driving scheme for synchronous rectifiers: Single
winding self-driven synchronous rectification,” IEEE Trans. Power
Electron., vol. 16, no. 6, pp. 803–811, Nov. 2001.
[6] L. Xiao and R. Oruganti, “Soft switched PWM DC/DC converter with
synchronous rectifiers,” in Proc. 18th Int. Telecommunications Energy
Conf. (INTELEC’96), 1996, pp. 476–484.
[7] X. Xia and G. Gang, “Self-Driven synchronous rectification circuit for
low output voltage dc–dc converters,” U.S. Patent 627 540, Aug. 14,
2001.
[8] X. Xie et al., “Self-driven synchronous rectifier by retention of gate
charge,” U.S. Patent 6 377 477, Apr. 23, 2002.
[9] Z. Zhang et al., “Synchronous rectifier circuit,” U.S. Patent 6 370 044,
Apr. 9, 2002.
[10] R. Watson and F. C. Lee, “Analysis, design, and experimental results of
a 1-kW ZVS-FB-PWM converter employing magamp secondary-side
control,” IEEE Trans. Ind. Electron, vol. 45, no. 5, pp. 806–814, Oct.
1998.
[11] Y. Ren, M. Xu, Y. Meng, and F. C. Lee, “A novel quasiresonant phase-
shifted full-bridge converter for 48 V power pods,” in Proc. APEC’03,
2003, pp. 420–425.
 Ming Xu received the B.S. degree in electrical
engineering from Nanjing University of Aeronautics
and Astronautics, Nanjing, China, in 1991 and the
M.S. and Ph.D. degrees in electrical engineering
from Zhejiang University, Hangzhou, China, in 1994
and 1997, respectively.
he is currently a Research Assistant Professor at
the Center for Power Electronics Systems (CPES),
Virginia Polytechnic Institute and State University,
Blacksburg. His research interests include high-fre-
quency power conversion, distributed power system,
power factor correction techniques, low voltage high current conversion
techniques, high-frequency magnetics, and modeling and control of converters.
He holds two U.S. patents, seven Chinese patents, 18 invention disclosures,
and seven U.S. patents pending. He has published one book and approximately
80 technical papers in journals and conferences.
Yuancheng Ren received the B.S. and M.S. degrees
in electrical engineering from Zhejiang University,
Hangzhou, China, in 1997 and 2000, respectively,
and is currently pursuing the Ph.D. degree in power
electronics at the Center for Power Electronics
Systems (CPES), Virginia Polytechnic Institute and
State University, Blacksburg.
His research interests include low-voltage power
management, high-frequency high-density power
supplies, modeling and control for converters, and
design for distribute-power systems. He holds one
U.S. patent and has four U.S. patents pending.
Jinghai Zhou received the B.S. and M.S. degrees
in electrical engineering from Zhejiang University,
Hangzhou, China, in 1995 and 1998, respectively,
and is currently pursuing the Ph.D. degree at the
Center for Power Electronics Systems (CPES),
Virginia Polytechnic Institute and State University,
Blacksburg.
His research interests include high-frequency
power conversion, distributed power system, low
voltage high current conversion techniques, high-fre-
quency magnetics, and electronic ballast for HID
lamps. He holds two U.S. pending patents. He has published over 10 technical
papers in journals and conferences.
36
Fred C. Lee (S’72–M’74–SM’87–F’90) received
the B.S. degree in electrical engineering from the
National Cheng Kung University, Taiwan, R.O.C.,
in 1968 and the M.S. and Ph.D. degrees in electrical
engineering from Duke University, Durham, NC, in
1971 and 1974, respectively.
He is a University Distinguished Professor with
Virginia Polytechnic Institute and State University
(Virginia Tech), Blacksburg, and prior to that he was
the Lewis A. Hester Chair of Engineering at Virginia
Tech. He directs the Center for Power Electronics
Systems (CPES), a National Science Foundation engineering research center
whose participants include five universities and over 100 corporations. In
addition to Virginia Tech, participating CPES universities are the University
of Wisconsin-Madison, Rensselaer Polytechnic Institute, North Carolina A&T
State University, and the University of Puerto Rico-Mayaguez. He is also
the Founder and Director of the Virginia Power Electronics Center (VPEC),
one of the largest university-based power electronics research centers in
the country. VPEC’s Industry-University Partnership Program provides an
effective mechanism for technology transfer, and an opportunity for industries
to profit from VPEC’s research results. VPEC’s programs have been able to
attract world-renowned faculty and visiting professors to Virginia Tech who, in
turn, attract an excellent cadre of undergraduate and graduate students. Total
sponsored research funding secured by him over the last 20 years exceeds
$35 million. His research interests include high-frequency power conversion,
distributed power systems, space power systems, power factor correction
techniques, electronics packaging, high-frequency magnetics, device charac-
terization, and modeling and control of converters. He holds 30 U.S. patents,
and has published over 175 journal articles in refereed journals and more than
400 technical papers in conference proceedings.
Dr. Lee received the Society of Automotive Engineering’s Ralph R. Teeter
Education Award (1985), Virginia Tech’s Alumni Award for Research Excel-
lence (1990), and its College of Engineering Dean’s Award for Excellence in
Research (1997), in 1989, the William E. Newell Power Electronics Award, the
highest award presented by the IEEE Power Electronics Society for outstanding
achievement in the power electronics discipline, the Power Conversion and In-
telligent Motion Award for Leadership in Power Electronics Education (1990),
the Arthur E. Fury Award for Leadership and Innovation in Advancing Power
Electronic Systems Technology (1998), the IEEE Millennium Medal, and
honorary professorships from Shanghai University of Technology, Shanghai
Railroad and Technology Institute, Nanjing Aeronautical Institute, Zhejiang
University, and Tsinghua University. He is an active member in the professional
community of power electronics engineers. He chaired the 1995 International
Conference on Power Electronics and Drives Systems, which took place in
Singapore, and co-chaired the 1994 International Power Electronics and Motion
Control Conference, held in Beijing. During 1993-1994, he served as President
of the IEEE Power Electronics Society and, before that, as Program Chair
and then Conference Chair of IEEE-sponsored power electronics specialist
conferences.