A B C D E

1 1

2
Compal Confidential 2

QIWG7 DIS M/B Schematics Document

Intel Ivy Bridge Processor with DDRIII + Panther Point PCH
nVIDIA N13P-GL

2011-12-28
3 3

LA-7983P
REV:0.3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 1 of 60
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 A B C D E

Compal confidential
ZZZ
File Name : QIWG7 LS7988P CR_AUDIO/B
LA7983 LS7987P USB/B
LS6753P PWR/B
WĂŐĞϮϯͲϯϮ DA_PCB
DA80000RL00 LS6758P LED/B
LS675AP ODD/B
1 1

nVIDIA N13P-GL
Intel
PCI-E x16 Ivy Bridge
VRAM 128*16 ZĞǀĞƌƐĞDŽĚĞ DDR3 SO-DIMM *2
DDR3*8 Socket-rPGA989B BANK 0, 1, 2, 3 WĂŐĞϭϮͲϭϯ
37.5mm*37.5mm
Dual Channel Up to 8GB
WĂŐĞϯϱ WĂŐĞϱͲϭϭDDR3 1066MHz(1.5V)
HDMI W
DDR3 1333MHz(1.5V)
Connector DDR3 1600MHz(1.5V)
100MHz
WĂŐĞϯϰ 2.7GT/s FDI *8 DMI *4
CRT Zd
2 Connector Intel Audio Codec 2 channel speaker
WĂŐĞϰϭ
2

AZALIA Conexant
LVDS WĂŐĞϯϯ >s^ Panther Point CX20671-21Z
Int. MIC x1 WĂŐĞϰϭ
Connector HM75 / HM76
WĂŐĞϰϭ
Audio Jacks WĂŐĞϰϯ
WŽƌƚϯ͕WŽƌƚϰ FCBGA 989
USB3.0 *2(Left) 25mm*25mm USB2.0 *14
WŽƌƚϱ
Camera Conn.WĂŐĞϯϯ
PCI-E x1 *6
Option WĂŐĞϰϱ WŽƌƚϭϯ
SATA *6 BlueTooth Conn.
WĂŐĞϰϬ
USB3.0 WŽƌƚϰ WĂŐĞϭϰͲϮϮ
WŽƌƚϭϬ
Renesas
SPIROM Mini Card Slot *1
WĂŐĞϯϲ
uPD720202
BIOS WĂŐĞϭϰ
3 LPC BUS Card Reader WĂŐĞϰϯ 3

Arthros
WŽƌƚϭ
WĂŐĞϰϮ WŽƌƚϭϭ Reltek
AR8161(GLAN) EC RTS5178 for SDR50
SDXC/MMC
AR8162(10/100) ENE KB9012 A3
WĂŐĞϯϳ WŽƌƚϵ
USB2.0 *1(Right)
WĂŐĞϰϯ͖ϰϰ
WĂŐĞϯϴ
RJ-45 WŽƌƚϭ
WŽƌƚϮ USB2.0 *3(Left) (Port 2/Port 3 co-layout
Connector Touch Pad Int. KBD
WĂŐĞϰϯ WŽƌƚϯ WĂŐĞϰϱ with USB3.0 port3/port4)
WĂŐĞϰϯ
WŽƌƚϬ
PCI Express PCI-E(WLAN) SATA HDD WĂŐĞϰϬ
Mini Card Slot *1 WŽƌƚϮ Thermal Sensor (Port 0/Port 1 support SATA3)
EMC1403 WĂŐĞϯϵ WŽƌƚϮ
WLAN WĂŐĞϯϲ
SATA ODD WĂŐĞϰϬ
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 2 of 60
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 A B C D E

SIGNAL
Voltage Rails STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Full ON HIGH HIGH HIGH HIGH ON ON ON ON

+5VS S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

+3VS
power S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
plane +1.5VS
1
+V1.05S_VCCP S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1

+5VALW +1.5V +VCC_CORE

S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+B +VGA_CORE
+3VALW +VCC_GFXCORE_AXG
+1.8VS BOARD ID Table Board ID / SKU ID Table for AD channel
State +0.75VS Vcc 3.3V +/- 5%
+1.05VS
Board ID PCB Revision
Ra/Rc/Re 100K +/- 5%
0 0.1 Board ID Porject Phase
Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
1 G-series
0 0 0 V 0 V 0 V MP
2 G-series
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V PVT
3 G-series
2 18K +/- 5% 0.436 V 0.503 V 0.538 V DVT
4 G-series
3 33K +/- 5% 0.712 V 0.819 V 0.875 V EVT
S0
5 Y-series
O O O O 4 56K +/- 5% 1.036 V 1.185 V 1.264 V EVT
6 Y-series
5 100K +/- 5% 1.453 V 1.650 V 1.759 V DVT
7 Y-series
6 200K +/- 5% 1.935 V 2.200 V 2.341 V PVT
S3 Y-series
O O O X 7 NC 2.500 V 3.300 V 3.300 V MP
2 2

S5 S4/AC
O O X X
USB Port Table BOM Structure Table
S5 S4/ Battery only
O X X X 3 External BTO Item BOM Structure
USB 2.0 Port USB Port
S5 S4/AC & Battery
don't exist X X X X 0
UHCI0
Address 1 USB Port (Left Side)USB2.0
EC SM Bus1 address EC SM Bus2 address 2 USB Port (Left Side)USB3.0 GPU:N13P-GL N13P@
UHCI1
3 USB Port (Left Side)USB3.0 UMA only UMA@
Device Device Address EHCI1
Smart Battery 0001 011X b Thermal Sensor F75303M 1001_101xb USB3.0
4 HDMI HDMI@
UHCI2
5 Camera Interna-Intel-USB3.0 IU3@
6 External-NEC-USB3.0 EU3@
PCH SM Bus address UHCI3
7 Blue Tooth BT@
8 Connector ME@
Device Address UHCI4
9 USB/B (Right Side USB-BD) 45 LEVEL 45@
DDR DIMM0 1001 000Xb
DDR DIMM2 1001 010Xb
10 Mini Card(WLAN) 10/100 LAN 8162@
3 EHCI2 UHCI5 3
11 Card Reader GIGA LAN GIGA@
12 Camera CMOS@
NV-GPU SM Bus address UHCI6
13 Blue Tooth Green Clock GCLK@
GCLK244@
Device Address
Unpop @
Internal thermal sensor 1001 111Xb (0x9E)

SMBUS Control Table

Thermal
SOURCE VGA BATT KB9012 SODIMM WLAN
WWAN Sensor PCH
SMB_EC_CK1
SMB_EC_DA1 KB9012
+3VALW
X +3VALW
V X X X X X
SMB_EC_CK2
SMB_EC_DA2 KB9012
+3VALW
X X X X X X V
+3VS
SMBCLK
X X X V V X X
4 4

PCH
SMBDATA +3VALW +3VS +3VS
SML0CLK
SML0DATA PCH
+3VALW
X X X X X X X
SML1CLK
V X V X X V X
Security Classification Compal Secret Data Compal Electronics, Inc.
PCH 2011/10/27 2012/10/27 Title
SML1DATA +3VALW +3VS +3VS +3VS Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 3 of 60
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 5 4 3 2 1

Hot plug detect for IFP link C

VGA and GDDR3 Voltage Rails (N13P GPIO) Performance Mode P0 TDP at Tj = 102 C* (DDR3)
FBVDDQ PCI Express I/O and I/O and Other
GPIO I/O ACTIVE Function Description GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD PLLVDD
(4) (1,5) /MCLK NVVDD (1.35V) (1.35V) (6) (1.8V) (1.05V) (3.3V)
GPIO0 OUT - GPU VID4 Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W)

D D
GPIO1 OUT - GPU VID3 N13P-GL
64bit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
1GB
GPIO2 OUT H Panel Back-Light brightness(PWM capable) DDR3

GPIO3 OUT H Panel Power Enable

Physical Logical Logical Logical Logical
Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
GPIO4 OUT H Panel Back-Light On/Off (PWM)
ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
GPIO5 OUT - GPU VID1 ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
GPIO6 OUT - GPU VID2
STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
GPIO7 OUT N/A STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
GPIO8 I/O - Thermal Catastrophic Over Temperature
STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
GPIO9 OUT - Thermal Alert STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
CHANGE_GEN3
GPIO10 OUT - Memory VREF Control

GPIO11 OUT - GPU VID0 Device ID

C C
N13P-GL
GPIO12 IN AC Power Detect Input (10K pull low) (28nm) ???

GPIO13 OUT - GPU VID5

GPIO14 OUT N/A

GPIO15 IN Hot plug detect for IFP link C

GPU FB Memory (DDR3) ROM_SO ROM_SCLK ROM_SI STRAP2 STRAP1 STRAP0
GPIO16 OUT N/A
Samsung
GPIO17 IN N/A 900MHz
64Mx16 PD 10K PD 15K PD 20K PU 20K PD 35K PU 45K
GPIO18 IN Hot Plug Detect for IFPE
Hynix
GPIO19 IN N/A 900MHz
N13P-GL 64Mx16 PD 10K PD 15K PD 15K PU 20K PD 35K PU 45K

Samsung
900MHz
128Mx16 PD 10K PD 15K PD 20K PU 20K PD 35K PU 45K
B
+3VS_VGA B

Hynix
+VGA_CORE 900MHz
128Mx16 PD 10K PD 15K PD 20K PU 20K PD 35K PU 45K
tNVVDD >0
+1.5VS_VGA
X76
tFBVDDQ >0

+1.05VS_VGA
tPEX_VDD >0

1. all power rail ramp up time should be larger than 40us

2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ

A A

Tpower-off <10ms

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title
1.all GPU power rails should be turned off within 10ms
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 4 of 60
5 4 3 2 1
 5 4 3 2 1

PEG_ICOMPI and RCOMPO signals should be

shorted and routed
with - max length = 500 mils - typical
+V1.05S_VCCP impedance = 43 mohms
PEG_ICOMPO signals should be routed with -

1
max length = 500 mils
R1
D
24.9_0402_1% - typical impedance = 14.5 mohms D

JCPU1A

2
J22 PEG_COMP
PEG_ICOMPI J21
B27 PEG_ICOMPO H22
<16> DMI_CRX_PTX_N0 DMI_RX#[0] PEG_RCOMPO
<16> DMI_CRX_PTX_N1 B25
A25 DMI_RX#[1]
<16> DMI_CRX_PTX_N2 DMI_RX#[2] PCIE_CRX_GTX_N[0..15] <23>
B24 K33 PCIE_CRX_GTX_N15
<16> DMI_CRX_PTX_N3 DMI_RX#[3] PEG_RX#[0] M35 PCIE_CRX_GTX_N14
B28 PEG_RX#[1] L34 PCIE_CRX_GTX_N13
<16> DMI_CRX_PTX_P0 DMI_RX[0] PEG_RX#[2]
<16> DMI_CRX_PTX_P1 B26 J35 PCIE_CRX_GTX_N12 PEG Static Lane Reversal - CFG2 is for the 16x
A24 DMI_RX[1] PEG_RX#[3] J32 PCIE_CRX_GTX_N11
<16> DMI_CRX_PTX_P2

DMI
B23 DMI_RX[2] PEG_RX#[4] H34 PCIE_CRX_GTX_N10
<16> DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5] H31 PCIE_CRX_GTX_N9 1: Normal Operation; Lane # definition matches
G21 PEG_RX#[6] G33 PCIE_CRX_GTX_N8
<16> DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7] CFG2 socket pin map definition
E22 G30 PCIE_CRX_GTX_N7
<16> DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8]
F21 F35 PCIE_CRX_GTX_N6
<16> DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
D21 E34 PCIE_CRX_GTX_N5 0:Lane Reversed
<16>

<16>
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
G22
DMI_TX#[3]

DMI_TX[0]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
E32
D33
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_N3 *
D22 D31 PCIE_CRX_GTX_N2
<16> DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13]
F20 B33 PCIE_CRX_GTX_N1
<16> DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14]

PCI EXPRESS* - GRAPHICS

C21 C32 PCIE_CRX_GTX_N0
<16> DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
PCIE_CRX_GTX_P[0..15] <23>
J33 PCIE_CRX_GTX_P15
PEG_RX[0] L35 PCIE_CRX_GTX_P14
PEG_RX[1] K34 PCIE_CRX_GTX_P13
A21 PEG_RX[2] H35 PCIE_CRX_GTX_P12
<16> FDI_CTX_PRX_N0 FDI0_TX#[0] PEG_RX[3]
C H19 H32 PCIE_CRX_GTX_P11 C
<16> FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4]
E19 G34 PCIE_CRX_GTX_P10
<16> FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5]
F18 G31 PCIE_CRX_GTX_P9
<16> FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6]

Intel(R) FDI
B21 F33 PCIE_CRX_GTX_P8
<16> FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7]
C20 F30 PCIE_CRX_GTX_P7
<16> FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8]
D18 E35 PCIE_CRX_GTX_P6
<16> FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9]
E17 E33 PCIE_CRX_GTX_P5
<16> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10] F32 PCIE_CRX_GTX_P4
PEG_RX[11] D34 PCIE_CRX_GTX_P3
A22 PEG_RX[12] E31 PCIE_CRX_GTX_P2
<16> FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
G19 C33 PCIE_CRX_GTX_P1
<16> FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14]
E20 B32 PCIE_CRX_GTX_P0
<16> FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15]
G18
<16> FDI_CTX_PRX_P3 FDI0_TX[3] PCIE_CTX_GRX_N[0..15] <23>
B20 M29 PCIE_CTX_GRX_C_N15 C1 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N15
<16> FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
C19 M32 PCIE_CTX_GRX_C_N14 C2 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N14
<16> FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1]
D19 M31 PCIE_CTX_GRX_C_N13 C3 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N13
<16> FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2]
F17 L32 PCIE_CTX_GRX_C_N12 C4 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N12
<16> FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] L29 PCIE_CTX_GRX_C_N11 C5 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N11
J18 PEG_TX#[4] K31 PCIE_CTX_GRX_C_N10 C6 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N10
+V1.05S_VCCP <16> FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
<16> FDI_FSYNC1 J17 K28 PCIE_CTX_GRX_C_N9 C7 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N9
FDI1_FSYNC PEG_TX#[6] J30 PCIE_CTX_GRX_C_N8 C8 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N8
H20 PEG_TX#[7] J28 PCIE_CTX_GRX_C_N7 C9 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N7
<16> FDI_INT FDI_INT PEG_TX#[8] H29 PCIE_CTX_GRX_C_N6 C10 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N6
PEG_TX#[9]
1

J19 G27 PCIE_CTX_GRX_C_N5 C11 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N5

<16> FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10]
R7 <16> FDI_LSYNC1 H17 E29 PCIE_CTX_GRX_C_N4 C12 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N4
24.9_0402_1% FDI1_LSYNC PEG_TX#[11] F27 PCIE_CTX_GRX_C_N3 C13 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N3
PEG_TX#[12] D28 PCIE_CTX_GRX_C_N2 C14 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N2
PEG_TX#[13] F26 PCIE_CTX_GRX_C_N1 C15 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N1
2

PEG_TX#[14] E25 PCIE_CTX_GRX_C_N0 C16 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_N0

EDP_COMP A18 PEG_TX#[15]
B eDP_COMPIO PCIE_CTX_GRX_P[0..15] <23> B
eDP_COMPIO and ICOMPO signals A17 M28 PCIE_CTX_GRX_C_P15 C17 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P15
eDP_HPD B16 eDP_ICOMPO PEG_TX[0] M33 PCIE_CTX_GRX_C_P14 C18 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P14
should be shorted near balls eDP_HPD# PEG_TX[1] M30 PCIE_CTX_GRX_C_P13 C19 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P13
PEG_TX[2] L31 PCIE_CTX_GRX_C_P12 C20 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P12
and routed with typical PEG_TX[3]
C15 L28 PCIE_CTX_GRX_C_P11 C21 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P11
impedance <25 mohms D15 eDP_AUX PEG_TX[4] K30 PCIE_CTX_GRX_C_P10 C22 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P10
eDP_AUX# PEG_TX[5] K27 PCIE_CTX_GRX_C_P9 C23 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P9
eDP

PEG_TX[6] J29 PCIE_CTX_GRX_C_P8 C24 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P8

C17 PEG_TX[7] J27 PCIE_CTX_GRX_C_P7 C25 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P7
F16 eDP_TX[0] PEG_TX[8] H28 PCIE_CTX_GRX_C_P6 C26 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P6
C16 eDP_TX[1] PEG_TX[9] G28 PCIE_CTX_GRX_C_P5 C27 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P5
G15 eDP_TX[2] PEG_TX[10] E28 PCIE_CTX_GRX_C_P4 C28 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P4
eDP_TX[3] PEG_TX[11] F28 PCIE_CTX_GRX_C_P3 C29 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P3
C18 PEG_TX[12] D27 PCIE_CTX_GRX_C_P2 C30 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P2
E16 eDP_TX#[0] PEG_TX[13] E26 PCIE_CTX_GRX_C_P1 C31 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P1
D16 eDP_TX#[1] PEG_TX[14] D25 PCIE_CTX_GRX_C_P0 C32 N13P@1 2 0.22U_0402_10V6K PCIE_CTX_GRX_P0
F15 eDP_TX#[2] PEG_TX[15]
eDP_TX#[3]

TYCO_2013620-2_IVY BRIDGE 12/07 update to SE124224K80

A A

Security Classification Compal Secret Data

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(1/7) DMI,FDI,PEG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 5 of 60
5 4 3 2 1
 5 4 3 2 1

JCPU1B
D R10;R11 put on U4 side D
R10
A28 CLK_CPU_DMI_R 0_0402_5% 1 2
C26 BCLK A27 CLK_CPU_DMII#_R 0_0402_5% 1 2 CLK_CPU_DMI <15>

MISC

CLOCKS
<19> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <15>
R11
AN34
SKTOCC# A16 2 R12 1 1K_0402_5%
+V1.05S_VCCP DPLL_REF_CLK A15 2 R13 1 1K_0402_5%
DPLL_REF_CLK# +V1.05S_VCCP

T48 H_CATERR# AL33

CATERR#
R9 1
62_0402_5%

THERMAL
AN33 R8 H_DRAMRST#
<19,42> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>
2

R15

DDR3
MISC
56_0402_5%
H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 2 R16 1 140_0402_1%
<42,48> H_PROCHOT# PROCHOT# SM_RCOMP[0] A5 SM_RCOMP1 2 R17 1 25.5_0402_1%
SM_RCOMP[1] A4 SM_RCOMP2 2 R18 1 200_0402_1%
SM_RCOMP[2]
AN32 DDR3 Compensation Signals
<19> H_THRMTRIP# THERMTRIP#

+V1.05S_VCCP
AP29 XDP_PRDY# T97
PRDY# AP27 XDP_PREQ# T98
PREQ# XDP_TMS R20 2 1 51_0402_5%
AR26 XDP_TCK XDP_TDI R21 2 1 51_0402_5% PU/PD for JTAG signals
C R22 TCK AR27 XDP_TMS XDP_TDO R23 2 @ 1 51_0402_5% C

PWR MANAGEMENT
TMS

JTAG & BPM

1 2 H_PM_SYNC_R AM34 AP30 XDP_TRST#
<16> H_PM_SYNC PM_SYNC TRST# 2 1 51_0402_5%
XDP_TCK R24
0_0402_5% AR28 XDP_TDI XDP_TRST# R25 2 1 51_0402_5%
TDI AP26 XDP_TDO
0_0402_5%
0_0402_5%1 R26 2 H_CPUPWRGD_R AP33 TDO
<19> H_CPUPWRGD UNCOREPWRGOOD
2

R29 AL35 XDP_DBRESET# R28 2 1 1K_0402_5%

DBR# +3VS
1 R27 1 2 PM_DRAM_PWRGD_R V8
@ C549 130_0402_5% SM_DRAMPWROK
10K_0402_5%
AT28 XDP_BPM#0 T49
100P_0402_50V8J BPM#[0] AR29 XDP_BPM#1 T90
1

2 BPM#[1] AR30 XDP_BPM#2 T91

EMI Reserve BUF_CPU_RST# AR33 BPM#[2] AT30 XDP_BPM#3 T92
RESET# BPM#[3] AP32 XDP_BPM#4 T93
BPM#[4] AR31 XDP_BPM#5 T94
BPM#[5] AT31 XDP_BPM#6 T95
BPM#[6] AR32 XDP_BPM#7 T96
BPM#[7]

TYCO_2013620-2_IVY BRIDGE
+3VALW

1 Buffered reset to CPU

C33
0.1U_0402_16V4Z
+1.5V_CPU_VDDQ
2 +3VS
B B
1

1 R880@ 2
<16> SYS_PWROK
0_0402_5% R30
U1 200_0402_5% +V1.05S_VCCP
1
C34
5

0.1U_0402_16V4Z
2

1 R161 2 1
P

+3VS B 2
10K_0402_5% 4 PM_SYS_PWRGD_BUF R32
2 O 75_0402_5%
<16> PM_DRAM_PWRGD A
G

5
1

74AHC1G09GW_TSSOP5 R34 U2
2
3

@ 43_0402_1% 1 3V

P
R33 BUF_CPU_RST# 1 2 BUFO_CPU_RST# 4 NC
39_0402_5% Y 2 PCH_PLTRST#
A PCH_PLTRST# <18>
1

G
SN74LVC1G07DCKR_SC70-5
1 2

3
D R35 @
2 Q1 @ 0_0402_5%
<10> RUN_ON_CPU1.5VS3#
G 2N7002H_SOT23-3
2

S
3

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(2/7) PM,XDP,CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 6 of 60
5 4 3 2 1
 5 4 3 2 1

JCPU1C JCPU1D
<13> DDR_B_D[0..63]

AB6 AE2
<12> DDR_A_D[0..63] SA_CLK[0] AA6 M_CLK_DDR0 <12> SB_CLK[0] AD2 M_CLK_DDR2 <13>
DDR_A_D0 C5 SA_CLK#[0] V9 M_CLK_DDR#0 <12> DDR_B_D0 C9 SB_CLK#[0] R9 M_CLK_DDR#2 <13>
DDR_A_D1 D5 SA_DQ[0] SA_CKE[0] DDR_CKE0_DIMMA <12> DDR_B_D1 A7 SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB <13>
DDR_A_D2 D3 SA_DQ[1] DDR_B_D2 D10 SB_DQ[1]
DDR_A_D3 D2 SA_DQ[2] DDR_B_D3 C8 SB_DQ[2]
DDR_A_D4 D6 SA_DQ[3] AA5 DDR_B_D4 A9 SB_DQ[3] AE1
D C6 SA_DQ[4] SA_CLK[1] AB5 M_CLK_DDR1 <12> A8 SB_DQ[4] SB_CLK[1] AD1 M_CLK_DDR3 <13> D
DDR_A_D5 DDR_B_D5
DDR_A_D6 C2 SA_DQ[5] SA_CLK#[1] V10 M_CLK_DDR#1 <12> DDR_B_D6 D9 SB_DQ[5] SB_CLK#[1] R10 M_CLK_DDR#3 <13>
DDR_A_D7 C3 SA_DQ[6] SA_CKE[1] DDR_CKE1_DIMMA <12> DDR_B_D7 D8 SB_DQ[6] SB_CKE[1] DDR_CKE3_DIMMB <13>
DDR_A_D8 F10 SA_DQ[7] DDR_B_D8 G4 SB_DQ[7]
DDR_A_D9 F8 SA_DQ[8] DDR_B_D9 F4 SB_DQ[8]
DDR_A_D10 G10 SA_DQ[9] AB4 DDR_B_D10 F1 SB_DQ[9] AB2
DDR_A_D11 G9 SA_DQ[10] RSVD_TP[1] AA4 DDR_B_D11 G1 SB_DQ[10] RSVD_TP[11] AA2
DDR_A_D12 F9 SA_DQ[11] RSVD_TP[2] W9 DDR_B_D12 G5 SB_DQ[11] RSVD_TP[12] T9
DDR_A_D13 F7 SA_DQ[12] RSVD_TP[3] DDR_B_D13 F5 SB_DQ[12] RSVD_TP[13]
DDR_A_D14 G8 SA_DQ[13] DDR_B_D14 F2 SB_DQ[13]
DDR_A_D15 G7 SA_DQ[14] DDR_B_D15 G2 SB_DQ[14]
DDR_A_D16 K4 SA_DQ[15] AB3 DDR_B_D16 J7 SB_DQ[15] AA1
DDR_A_D17 K5 SA_DQ[16] RSVD_TP[4] AA3 DDR_B_D17 J8 SB_DQ[16] RSVD_TP[14] AB1
DDR_A_D18 K1 SA_DQ[17] RSVD_TP[5] W10 DDR_B_D18 K10 SB_DQ[17] RSVD_TP[15] T10
DDR_A_D19 J1 SA_DQ[18] RSVD_TP[6] DDR_B_D19 K9 SB_DQ[18] RSVD_TP[16]
DDR_A_D20 J5 SA_DQ[19] DDR_B_D20 J9 SB_DQ[19]
DDR_A_D21 J4 SA_DQ[20] DDR_B_D21 J10 SB_DQ[20]
DDR_A_D22 J2 SA_DQ[21] AK3 DDR_B_D22 K8 SB_DQ[21] AD3
K2 SA_DQ[22] SA_CS#[0] AL3 DDR_CS0_DIMMA# <12> K7 SB_DQ[22] SB_CS#[0] AE3 DDR_CS2_DIMMB# <13>
DDR_A_D23 DDR_B_D23
DDR_A_D24 M8 SA_DQ[23] SA_CS#[1] AG1 DDR_CS1_DIMMA# <12> DDR_B_D24 M5 SB_DQ[23] SB_CS#[1] AD6 DDR_CS3_DIMMB# <13>
DDR_A_D25 N10 SA_DQ[24] RSVD_TP[7] AH1 DDR_B_D25 N4 SB_DQ[24] RSVD_TP[17] AE6
DDR_A_D26 N8 SA_DQ[25] RSVD_TP[8] DDR_B_D26 N2 SB_DQ[25] RSVD_TP[18]
DDR_A_D27 N7 SA_DQ[26] DDR_B_D27 N1 SB_DQ[26]
DDR_A_D28 M10 SA_DQ[27] DDR_B_D28 M4 SB_DQ[27]
DDR_A_D29 M9 SA_DQ[28] AH3 DDR_B_D29 N5 SB_DQ[28] AE4
N9 SA_DQ[29] SA_ODT[0] AG3 M_ODT0 <12> M2 SB_DQ[29] SB_ODT[0] AD4 M_ODT2 <13>
DDR_A_D30 DDR_B_D30
M_ODT1 <12> M_ODT3 <13>

DDR SYSTEM MEMORY B

DDR_A_D31 M7 SA_DQ[30] SA_ODT[1] AG2 DDR_B_D31 M1 SB_DQ[30] SB_ODT[1] AD5

DDR SYSTEM MEMORY A

DDR_A_D32 AG6 SA_DQ[31] RSVD_TP[9] AH2 DDR_B_D32 AM5 SB_DQ[31] RSVD_TP[19] AE5
DDR_A_D33 AG5 SA_DQ[32] RSVD_TP[10] DDR_B_D33 AM6 SB_DQ[32] RSVD_TP[20]
DDR_A_D34 AK6 SA_DQ[33] DDR_B_D34 AR3 SB_DQ[33]
DDR_A_D35 AK5 SA_DQ[34] DDR_B_D35 AP3 SB_DQ[34]
DDR_A_D36 AH5 SA_DQ[35] DDR_B_D36 AN3 SB_DQ[35]
C DDR_A_D37 AH6 SA_DQ[36] C4 DDR_A_DQS#0 DDR_A_DQS#[0..7] <12> DDR_B_D37 AN2 SB_DQ[36] D7 DDR_B_DQS#0 DDR_B_DQS#[0..7] <13> C
DDR_A_D38 AJ5 SA_DQ[37] SA_DQS#[0] G6 DDR_A_DQS#1 DDR_B_D38 AN1 SB_DQ[37] SB_DQS#[0] F3 DDR_B_DQS#1
DDR_A_D39 AJ6 SA_DQ[38] SA_DQS#[1] J3 DDR_A_DQS#2 DDR_B_D39 AP2 SB_DQ[38] SB_DQS#[1] K6 DDR_B_DQS#2
DDR_A_D40 AJ8 SA_DQ[39] SA_DQS#[2] M6 DDR_A_DQS#3 DDR_B_D40 AP5 SB_DQ[39] SB_DQS#[2] N3 DDR_B_DQS#3
DDR_A_D41 AK8 SA_DQ[40] SA_DQS#[3] AL6 DDR_A_DQS#4 DDR_B_D41 AN9 SB_DQ[40] SB_DQS#[3] AN5 DDR_B_DQS#4
DDR_A_D42 AJ9 SA_DQ[41] SA_DQS#[4] AM8 DDR_A_DQS#5 DDR_B_D42 AT5 SB_DQ[41] SB_DQS#[4] AP9 DDR_B_DQS#5
DDR_A_D43 AK9 SA_DQ[42] SA_DQS#[5] AR12 DDR_A_DQS#6 DDR_B_D43 AT6 SB_DQ[42] SB_DQS#[5] AK12 DDR_B_DQS#6
DDR_A_D44 AH8 SA_DQ[43] SA_DQS#[6] AM15 DDR_A_DQS#7 DDR_B_D44 AP6 SB_DQ[43] SB_DQS#[6] AP15 DDR_B_DQS#7
DDR_A_D45 AH9 SA_DQ[44] SA_DQS#[7] DDR_B_D45 AN8 SB_DQ[44] SB_DQS#[7]
DDR_A_D46 AL9 SA_DQ[45] DDR_B_D46 AR6 SB_DQ[45]
DDR_A_D47 AL8 SA_DQ[46] DDR_B_D47 AR5 SB_DQ[46]
DDR_A_D48 AP11 SA_DQ[47] DDR_B_D48 AR9 SB_DQ[47]
DDR_A_D49 AN11 SA_DQ[48] D4 DDR_A_DQS0 DDR_A_DQS[0..7] <12> DDR_B_D49 AJ11 SB_DQ[48] C7 DDR_B_DQS0 DDR_B_DQS[0..7] <13>
DDR_A_D50 AL12 SA_DQ[49] SA_DQS[0] F6 DDR_A_DQS1 DDR_B_D50 AT8 SB_DQ[49] SB_DQS[0] G3 DDR_B_DQS1
DDR_A_D51 AM12 SA_DQ[50] SA_DQS[1] K3 DDR_A_DQS2 DDR_B_D51 AT9 SB_DQ[50] SB_DQS[1] J6 DDR_B_DQS2
DDR_A_D52 AM11 SA_DQ[51] SA_DQS[2] N6 DDR_A_DQS3 DDR_B_D52 AH11 SB_DQ[51] SB_DQS[2] M3 DDR_B_DQS3
DDR_A_D53 AL11 SA_DQ[52] SA_DQS[3] AL5 DDR_A_DQS4 DDR_B_D53 AR8 SB_DQ[52] SB_DQS[3] AN6 DDR_B_DQS4
DDR_A_D54 AP12 SA_DQ[53] SA_DQS[4] AM9 DDR_A_DQS5 DDR_B_D54 AJ12 SB_DQ[53] SB_DQS[4] AP8 DDR_B_DQS5
DDR_A_D55 AN12 SA_DQ[54] SA_DQS[5] AR11 DDR_A_DQS6 DDR_B_D55 AH12 SB_DQ[54] SB_DQS[5] AK11 DDR_B_DQS6
DDR_A_D56 AJ14 SA_DQ[55] SA_DQS[6] AM14 DDR_A_DQS7 DDR_B_D56 AT11 SB_DQ[55] SB_DQS[6] AP14 DDR_B_DQS7
DDR_A_D57 AH14 SA_DQ[56] SA_DQS[7] DDR_B_D57 AN14 SB_DQ[56] SB_DQS[7]
DDR_A_D58 AL15 SA_DQ[57] DDR_B_D58 AR14 SB_DQ[57]
DDR_A_D59 AK15 SA_DQ[58] DDR_B_D59 AT14 SB_DQ[58]
DDR_A_D60 AL14 SA_DQ[59] DDR_B_D60 AT12 SB_DQ[59]
DDR_A_D61 AK14 SA_DQ[60] AD10 DDR_A_MA0 DDR_A_MA[0..15] <12> DDR_B_D61 AN15 SB_DQ[60] AA8 DDR_B_MA0 DDR_B_MA[0..15] <13>
DDR_A_D62 AJ15 SA_DQ[61] SA_MA[0] W1 DDR_A_MA1 DDR_B_D62 AR15 SB_DQ[61] SB_MA[0] T7 DDR_B_MA1
DDR_A_D63 AH15 SA_DQ[62] SA_MA[1] W2 DDR_A_MA2 DDR_B_D63 AT15 SB_DQ[62] SB_MA[1] R7 DDR_B_MA2
SA_DQ[63] SA_MA[2] W7 DDR_A_MA3 SB_DQ[63] SB_MA[2] T6 DDR_B_MA3
SA_MA[3] V3 DDR_A_MA4 SB_MA[3] T2 DDR_B_MA4
SA_MA[4] V2 DDR_A_MA5 SB_MA[4] T4 DDR_B_MA5
SA_MA[5] W3 DDR_A_MA6 SB_MA[5] T3 DDR_B_MA6
AE10 SA_MA[6] W6 DDR_A_MA7 AA9 SB_MA[6] R2 DDR_B_MA7
B <12> DDR_A_BS0 AF10 SA_BS[0] SA_MA[7] V1 DDR_A_MA8 <13> DDR_B_BS0 AA7 SB_BS[0] SB_MA[7] T5 DDR_B_MA8 B
<12> DDR_A_BS1 V6 SA_BS[1] SA_MA[8] W5 DDR_A_MA9 <13> DDR_B_BS1 R6 SB_BS[1] SB_MA[8] R3 DDR_B_MA9
<12> DDR_A_BS2 SA_BS[2] SA_MA[9] AD8 DDR_A_MA10 <13> DDR_B_BS2 SB_BS[2] SB_MA[9] AB7 DDR_B_MA10
SA_MA[10] V4 DDR_A_MA11 SB_MA[10] R1 DDR_B_MA11
SA_MA[11] W4 DDR_A_MA12 SB_MA[11] T1 DDR_B_MA12
AE8 SA_MA[12] AF8 DDR_A_MA13 AA10 SB_MA[12] AB10 DDR_B_MA13
<12> DDR_A_CAS# AD9 SA_CAS# SA_MA[13] V5 <13> DDR_B_CAS# AB8 SB_CAS# SB_MA[13] R5
DDR_A_MA14 DDR_B_MA14
<12> DDR_A_RAS# AF9 SA_RAS# SA_MA[14] V7 DDR_A_MA15 <13> DDR_B_RAS# AB9 SB_RAS# SB_MA[14] R4 DDR_B_MA15
<12> DDR_A_WE# SA_WE# SA_MA[15] <13> DDR_B_WE# SB_WE# SB_MA[15]

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

+1.5V

@ R36 1 2 DRAMRST_CNTRL
<15> DRAMRST_CNTRL_PCH DRAMRST_CNTRL <10>
1

0_0402_5%
1 2 R37 R40 0_0402_5%
1K_0402_5%

R38
2

1K_0402_5%
S

H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2
<6> H_DRAMRST# DDR3_DRAMRST# <12,13>
2

Q2
R39 LBSS138LT1G_SOT-23-3
G
2

4.99K_0402_1%
1

A A

DRAMRST_CNTRL

1
C35
Eiffel used 0.01u Security Classification Compal Secret Data Compal Electronics, Inc.
Module design used 0.047u Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title
.047U_0402_16V7K
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(3/7) DDRIII
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 7 of 60

5 4 3 2 1
 5 4 3 2 1

CFG Straps for Processor

CFG2

1
R41
1K_0402_1%

2
D D

Interl request AH26 short GND

JCPU1E check on EVT phase PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition matches

AH27 PAD T13 CFG2
AK28 VCC_DIE_SENSE AH26 1 2 socket pin map definition
AK29 CFG[0] VSS_DIE_SENSE
CFG2 AL26 CFG[1] R60 0_0402_5% 0:Lane Reversed
CFG4
CFG5
AL27
AK26
AL29
CFG[2]
CFG[3]
CFG[4] RSVD28
L7
AG7
* CFG4
CFG6 AL30 CFG[5] RSVD29 AE7
CFG[6] RSVD30

1
CFG7 AM31 AK2
AM32 CFG[7] RSVD31
AM30 CFG[8] W8 @ R42

CFG
AM28 CFG[9] RSVD32 1K_0402_1%
+VCC_GFXCORE_AXG AM26 CFG[10]

2
AN28 CFG[11] AT26
+VCC_CORE AN31 CFG[12] RSVD33 AM33
AN26 CFG[13] RSVD34 AJ27
CFG[14] RSVD35
2

AM27
R252 AK31 CFG[15]
AN29 CFG[16]
49.9_0402_1% CFG[17]
2

Display Port Presence Strap

R253
1

49.9_0402_1% T8
C RSVD37 J16 C
1 : Disabled; No Physical Display Port
VCC_AXG_VAL_SENSE AJ31 RSVD38 H16 CFG4 * attached to Embedded Display Port
1

R82 1 @ 2 100_0402_1% VSS_AXG_VAL_SENSE AH31 VAXG_VAL_SENSE RSVD39 G16

VCC_VAL_SENSE AJ33 VSSAXG_VAL_SENSE RSVD40
R88 1 2 100_0402_1% VSS_VAL_SENSE AH33 VCC_VAL_SENSE
@
VSS_VAL_SENSE 0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
Need PWR add new circuit on 1.05V(refer CRB) AJ26 AR35
RSVD5 RSVD_NCTF1 AT34

RESERVED
RSVD_NCTF2 AT33
VSS_AXG_VAL_SENSE RSVD_NCTF3 AP35 CFG6
RSVD_NCTF4 AR34
RSVD_NCTF5 CFG5
VSS_VAL_SENSE

1
F25
Check F24 RSVD8
RSVD9
@ R43 @ R44
2

F23 1K_0402_1% 1K_0402_1%

R255 R257 D24 RSVD10 B34
G25 RSVD11 RSVD_NCTF6 A33
49.9_0402_1% 49.9_0402_1%

2
G24 RSVD12 RSVD_NCTF7 A34
E23 RSVD13 RSVD_NCTF8 B35
1

D23 RSVD14 RSVD_NCTF9 C35

C30 RSVD15 RSVD_NCTF10
A31 RSVD16
B30 RSVD17
B29 RSVD18
D30 RSVD19 AJ32
B31 RSVD20 RSVD51 AK32
INTEL 12/28 recommand RSVD21 RSVD52 PCIE Port Bifurcation Straps
A30
to add RC120, RC121, RC122, RC123 C29 RSVD22
RSVD23
Please place as close as JCPU1 11: (Default) x16 - Device 1 functions 1 and 2 disabled
B J20
B18 RSVD24
BCLK_ITP
BCLK_ITP#
AN35
AM35 CFG[6:5] *10: x8, x8 - Device 1 function 1 enabled ; function 2 B

RSVD25 disabled
01: Reserved - (Device 1 function 1 disabled ; function
J15 AT2 2 enabled)
RSVD27 RSVD_NCTF11 AT1
RSVD_NCTF12 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
AR1
RSVD_NCTF13

B1 CFG7
KEY

1
@R45
@ R45
1K_0402_1%

TYCO_2013620-2_IVY BRIDGE

2
PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

CFG7 de assertion

A
0: PEG Wait for BIOS for training A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(4/7) RSVD,CFG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 8 of 60
5 4 3 2 1
 5 4 3 2 1

JCPU1F POWER +V1.05S_VCCP

+VCC_CORE

EDS v1.5 QC=94A 8.5A

DC=53A
AG35
AG34 VCC1 AH13
AG33 VCC2 VCCIO1 AH10
AG32 VCC3 VCCIO2 AG10
D AG31 VCC4 VCCIO3 AC10 D
AG30 VCC5 VCCIO4 Y10
AG29 VCC6 VCCIO5 U10
AG28 VCC7 VCCIO6 P10
AG27 VCC8 VCCIO7 L10
AG26 VCC9 VCCIO8 J14
AF35 VCC10 VCCIO9 J13
AF34 VCC11 VCCIO10 J12
AF33 VCC12 VCCIO11 J11
AF32 VCC13 VCCIO12 H14
AF31 VCC14 VCCIO13 H12
AF30 VCC15 VCCIO14 H11
AF29 VCC16 VCCIO15 G14
AF28 VCC17 VCCIO16 G13
AF27 VCC18 VCCIO17 G12

PEG AND DDR

AF26 VCC19 VCCIO18 F14
AD35 VCC20 VCCIO19 F13
AD34 VCC21 VCCIO20 F12
AD33 VCC22 VCCIO21 F11
AD32 VCC23 VCCIO22 E14
AD31 VCC24 VCCIO23 E12
AD30 VCC25 VCCIO24
AD29 VCC26 E11
AD28 VCC27 VCCIO25 D14
AD27 VCC28 VCCIO26 D13
AD26 VCC29 VCCIO27 D12
AC35 VCC30 VCCIO28 D11
AC34 VCC31 VCCIO29 C14
AC33 VCC32 VCCIO30 C13
AC32 VCC33 VCCIO31 C12
AC31 VCC34 VCCIO32 C11
AC30 VCC35 VCCIO33 B14
C AC29 VCC36 VCCIO34 B12 C
AC28 VCC37 VCCIO35 A14
AC27 VCC38 VCCIO36 A13
AC26 VCC39 VCCIO37 A12
AA35 VCC40 VCCIO38 A11
AA34 VCC41 VCCIO39
AA33 VCC42 J23
AA32 VCC43 VCCIO40
AA31 VCC44 +V1.05S_VCCP
AA30 VCC45
AA29 VCC46
AA28 VCC47
AA27 VCC48
AA26 VCC49
Y35 VCC50
1
CORE SUPPLY

Y34 VCC51
Y33 VCC52 C99
Y32 VCC53 .1U_0402_16V7K
VCC54

1
Y31 2
Y30 VCC55 R46
Y29 VCC56
VCC57 75_0402_5%
Y28
Y27 VCC58
VR_SVID_CLK series-resistors close to VR

2
Y26 VCC59
V35 VCC60
V34 VCC61 AJ29 H_CPU_SVIDALRT# 1 R47 2 43_0402_1%
SVID

V33 VCC62 VIDALERT# AJ30 H_CPU_SVIDCLK 1 2 R48 VR_SVID_ALRT# <55>

0_0402_5%
V32 VCC63 VIDSCLK AJ28 1 2 R49 VR_SVID_CLK <55>
H_CPU_SVIDDAT 0_0402_5%
V31 VCC64 VIDSOUT VR_SVID_DAT <55>
V30 VCC65
V29 VCC66 2 1 130_0402_5%
VCC67
R50 +V1.05S_VCCP 0.1uF on power side
V28
B V27 VCC68 B
V26 VCC69
U35 VCC70
U34 VCC71
U33 VCC72
U32 VCC73
U31 VCC74
U30 VCC75
U29 VCC76
U28 VCC77 VCC_SENCE 100ohm +-1% pull-up to VCC near processor
U27 VCC78
U26 VCC79
R35 VCC80 +VCC_CORE
R34 VCC81
R33 VCC82
VCC83

1
R32
R31
R30
VCC84
VCC85
Trace Impedance =27-33 ohm R51
100_0402_1%
R29
R28
VCC86
VCC87
Trace Length Matc < 25 mils
SENSE LINES

2
R27 VCC88 AJ35 VCCSENSE_R 1 2 R52 0_0402_5%
R26 VCC89 VCC_SENSE AJ34 VSSSENSE_R 1 2 R53 VCCSENSE <55>
0_0402_5%
P35 VCC90 VSS_SENSE VSSSENSE <55>
P34 VCC91
VCC92 10/19 Update to @ for PWR modification.

1
P33
P32 VCC93 B10 1 R66 @2 R54
P31 VCC94 VCCIO_SENSE A10 1 VCCIO_SENSE <52,53>
VSSIO_SENSE_L R74 2VSSIO_SENSE 100_0402_1% 100_0402_1%
P30 VCC95 VSS_SENSE_VCCIO 10_0402_1%
P29 VCC96 @

2
P28 VCC97
VCC98 R74 & R79 put together +V1.05S_VCCP
P27
P26 VCC99 R79
A VCC100 2 1 A
VSSIO_SENSE_L <53>
10_0402_1%
10/19 Add off page to PWR side.
VSS_SENCE 100ohm +-1% pull-down to GND near processor

TYCO_2013620-2_IVY BRIDGE Security Classification Compal Secret Data

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(5/7) PWR,BYPASS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 9 of 60
5 4 3 2 1
 5 4 3 2 1

+1.5V +1.5V_CPU_VDDQ
@ J1 Q6

1
1 2 D LBSS138LT1G_SOT-23-3
R668 1 2 DRAMRST_CNTRL

1
PAD-OPEN 4x4m +VREF_DQ_DIMMA G DRAMRST_CNTRL <7>
1 2 R55 C92 @ +VREF_DQ_DIMMB R670@ S

3
<46,53,54> SUSP 0_0402_5% 220_0402_5% .1U_0402_16V7K 1 2 0_0402_5%~D +V_DDR_REFA_R
11/03 update @ 2 1 2 0_0402_5%~D +V_DDR_REFB_R
to 82K U3 R671@

12
DMN3030LSS-13_SOP8L-8 D

1
+3VALW +VSB 8 1 AP4800 Q3 2 RUN_ON_CPU1.5VS3#

1
7 2 2N7002_SOT23 G D
D 6 3 Id=9.6A @ S DRAMRST_CNTRL 2 R353 R64 D

3
1
5 G 1K_0402_1% 1K_0402_1%

1
R56 S @ @

2
@ R667 82K_0402_5% Q9

4
100K_0402_5% LBSS138LT1G_SOT-23-3
11/03 update

2
2
RUN_ON_CPU1.5VS3# RUN_ON_CPU1.5VS3 1 R885 2
to 0.047u M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

1
15K_0402_1% 1

1
D D +VCC_GFXCORE_AXG
1 2 2 Q7 @ 2 Q4 R57 C97
<42,53> CPU1.5V_S3_GATE
0_0402_5% @ R58 G 2N7002_SOT23 G 2N7002_SOT23 330K_0402_5% 0.047U_0402_25V7K

1
S S @ 2

2
1 2 R616
<25,42,46,51,52,53,54> SUSP#
0_0402_5% @ R59 10_0402_1%

2
RUN_ON_CPU1.5VS3# <6> VCC_AXG_SENSE <55>
POWER RUN_ON_CPU1.5VS3

1
Check
+VCC_GFXCORE_AXG JCPU1G R89 @
Q5-orignal part
100_0402_1% AP2302GN-HF_SOT23-3
AT24 AK35
SV-QC: 50A SB523020210 +1.5V

SENSE
LINES

2
AT23 VAXG1 VAXG_SENSE AK34 +1.5V_CPU_VDDQ
VAXG2 VSSAXG_SENSE VSS_AXG_SENSE <55>
AT21
SV-DC(GT2): 33A VAXG3

2
G
AT20 PMV45EN_SOT23-3
AT18 VAXG4 R626 Q5 @
VAXG5

1
AT17 10_0402_1% 3 1
AR24 VAXG6

D
AR23 VAXG7 R67 R62 @
+V_SM_VREF should

2
AR21 VAXG8 1K_0402_1% 1K_0402_1%
AR20 VAXG9 have 20 mil trace width

2
AR18 VAXG10 AL1 +V_SM_VREF_CNT 1 R61 @2 +V_SM_VREF
C
AR17 VAXG11 SM_VREF 0_0402_5% C
VAXG12

1
AP24 1

VREF
AP23 VAXG13
AP21 VAXG14 C98 R78 R63 @
AP20 VAXG15 B4 +V_DDR_REFA_R .1U_0402_16V7K 1K_0402_1% 1K_0402_1%
AP18 VAXG16 SA_DIMM_VREFDQ D1 +V_DDR_REFB_R 2

2
AP17 VAXG17 SB_DIMM_VREFDQ
AN24 VAXG18
AN23 VAXG19
AN21 VAXG20
AN20 VAXG21 +1.5V_CPU_VDDQ
AN18 VAXG22
5A

DDR3 -1.5V RAILS

AN17 VAXG23 +1.5V +1.5V_CPU_VDDQ
AM24 VAXG24 AF7

GRAPHICS
AM23 VAXG25 VDDQ1 AF4 C396 @
AM21 VAXG26 VDDQ2 AF1 .1U_0402_16V7K
VAXG27 VDDQ3 1
AM20 AC7 1 1 1 1 1 1 1 2
VAXG28 VDDQ4

10U_0603_6.3V6M
C117

10U_0603_6.3V6M
C118

10U_0603_6.3V6M
C119

10U_0603_6.3V6M
C120

10U_0603_6.3V6M
C121

10U_0603_6.3V6M
C122
AM18 AC4 + C123
AM17 VAXG29 VDDQ5 AC1 330U_2.5V_M C129 @
AL24 VAXG30 VDDQ6 Y7 .1U_0402_16V7K
AL23 VAXG31 VDDQ7 Y4 2 2 2 2 2 2 2 1 2
AL21 VAXG32 VDDQ8 Y1
AL20 VAXG33 VDDQ9 U7 C96
AL18 VAXG34 VDDQ10 U4 .1U_0402_16V7K
AL17 VAXG35 VDDQ11 U1 1 2
AK24 VAXG36 VDDQ12 P7
AK23 VAXG37 VDDQ13 P4 C95
AK21 VAXG38 VDDQ14 P1 .1U_0402_16V7K
AK20 VAXG39 VDDQ15 1 2
AK18 VAXG40
AK17 VAXG41
AJ24 VAXG42
AJ23 VAXG43
AJ21 VAXG44
AJ20 VAXG45 +VCCSA
B
AJ18 VAXG46 6A B

AJ17 VAXG47 M27 +VCCSA

AH24 VAXG48 VCCSA1 M26
SA RAIL

VAXG49 VCCSA2 1 1 1 1 1

10U_0603_6.3V6M
C124

10U_0603_6.3V6M
C125

10U_0603_6.3V6M
C126

10U_0603_6.3V6M
C127
AH23 L26
AH21 VAXG50 VCCSA3 J26 + C128 @
AH20 VAXG51 VCCSA4 J25 330U_D2_2.5VY_R9M
AH18 VAXG52 VCCSA5 J24 2 2 2 2
AH17 VAXG53 VCCSA6 H26 2
VAXG54 VCCSA7 H25
VCCSA8 @
1.8V RAIL

H23
+1.8VS VCCSA_SENSE +VCCSA_SENSE <52> +3VS +3VALW
R69 0_0805_5% 1.2A 1 @ 2
1 2 +1.8VS_VCCPLL B6 R68 0_0402_5%
VCCPLL1

2
A6 C22
MISC

VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 <52>

22U_0805_6.3V6M
C154

22U_0805_6.3V6M
C345

10U_0603_6.3V6M
C130

1U_0402_6.3V6K
C131

1U_0402_6.3V6K
C132

@ 1 1 1 1 1 A2 C24 R75 R76 @

VCCPLL3 VCCSA_VID[1] H_VCCSA_VID1 <52>
10K_0402_5% 10K_0402_5%

@ @

1
2 2 2 2 2 A19 H_VCCP_SEL 1 2
VCCIO_SEL VCCP_PWRCTRL <52>
R77 0_0402_5%
TYCO_2013620-2_IVY BRIDGE
IVY Bridge drives VCCIO_SEL low
VCCP_PWRCTRL:0
Sandy Bridge is NC for A19
VCCP_PWRCTRL:1
A A

Security Classification Compal Secret Data

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(6/7) PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 10 of 60
5 4 3 2 1
 5 4 3 2 1

JCPU1H JCPU1I

AT35 AJ22
AT32 VSS1 VSS81 AJ19
AT29 VSS2 VSS82 AJ16 T35 F22
AT27 VSS3 VSS83 AJ13 T34 VSS161 VSS234 F19
AT25 VSS4 VSS84 AJ10 T33 VSS162 VSS235 E30
AT22 VSS5 VSS85 AJ7 T32 VSS163 VSS236 E27
AT19 VSS6 VSS86 AJ4 T31 VSS164 VSS237 E24
AT16 VSS7 VSS87 AJ3 T30 VSS165 VSS238 E21
AT13 VSS8 VSS88 AJ2 T29 VSS166 VSS239 E18
AT10 VSS9 VSS89 AJ1 T28 VSS167 VSS240 E15
D D
AT7 VSS10 VSS90 AH35 T27 VSS168 VSS241 E13
AT4 VSS11 VSS91 AH34 T26 VSS169 VSS242 E10
AT3 VSS12 VSS92 AH32 P9 VSS170 VSS243 E9
AR25 VSS13 VSS93 AH30 P8 VSS171 VSS244 E8
AR22 VSS14 VSS94 AH29 P6 VSS172 VSS245 E7
AR19 VSS15 VSS95 AH28 P5 VSS173 VSS246 E6
AR16 VSS16 VSS96 AH25 P3 VSS174 VSS247 E5
AR13 VSS17 VSS98 AH22 P2 VSS175 VSS248 E4
AR10 VSS18 VSS99 AH19 N35 VSS176 VSS249 E3
AR7 VSS19 VSS100 AH16 N34 VSS177 VSS250 E2
AR4 VSS20 VSS101 AH7 N33 VSS178 VSS251 E1
AR2 VSS21 VSS102 AH4 N32 VSS179 VSS252 D35
AP34 VSS22 VSS103 AG9 N31 VSS180 VSS253 D32
AP31 VSS23 VSS104 AG8 N30 VSS181 VSS254 D29
AP28 VSS24 VSS105 AG4 N29 VSS182 VSS255 D26
AP25 VSS25 VSS106 AF6 N28 VSS183 VSS256 D20
AP22 VSS26 VSS107 AF5 N27 VSS184 VSS257 D17
AP19 VSS27 VSS108 AF3 N26 VSS185 VSS258 C34
AP16 VSS28 VSS109 AF2 M34 VSS186 VSS259 C31
AP13 VSS29 VSS110 AE35 L33 VSS187 VSS260 C28
AP10 VSS30 VSS111 AE34 L30 VSS188 VSS261 C27
AP7 VSS31 VSS112 AE33 L27 VSS189 VSS262 C25
AP4 VSS32 VSS113 AE32 L9 VSS190 VSS263 C23
AP1 VSS33 VSS114 AE31 L8 VSS191 VSS264 C10
C
AN30 VSS34 VSS115 AE30 L6 VSS192 VSS265 C1 C
AN27 VSS35 VSS116 AE29 L5 VSS193 VSS266 B22
AN25 VSS36 VSS117 AE28 L4 VSS194 VSS267 B19
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
AN16 AE9 L1 B13
AN13 VSS40 VSS121 AD7 K35 VSS198 VSS271 B11
AN10 VSS41 VSS122 AC9 K32 VSS199 VSS272 B9
AN7 VSS42 VSS123 AC8 K29 VSS200 VSS273 B8
AN4 VSS43 VSS124 AC6 K26 VSS201 VSS274 B7
AM29 VSS44 VSS125 AC5 J34 VSS202 VSS275 B5
AM25 VSS45 VSS126 AC3 J31 VSS203 VSS276 B3
AM22 VSS46 VSS127 AC2 H33 VSS204 VSS277 B2
AM19 VSS47 VSS128 AB35 H30 VSS205 VSS278 A35
AM16 VSS48 VSS129 AB34 H27 VSS206 VSS279 A32
AM13 VSS49 VSS130 AB33 H24 VSS207 VSS280 A29
AM10 VSS50 VSS131 AB32 H21 VSS208 VSS281 A26
AM7 VSS51 VSS132 AB31 H18 VSS209 VSS282 A23
AM4 VSS52 VSS133 AB30 H15 VSS210 VSS283 A20
AM3 VSS53 VSS134 AB29 H13 VSS211 VSS284 A3
AM2 VSS54 VSS135 AB28 H10 VSS212 VSS285
AM1 VSS55 VSS136 AB27 H9 VSS213
AL34 VSS56 VSS137 AB26 H8 VSS214
AL31 VSS57 VSS138 Y9 H7 VSS215
AL28 VSS58 VSS139 Y8 H6 VSS216
B B
AL25 VSS59 VSS140 Y6 H5 VSS217
AL22 VSS60 VSS141 Y5 H4 VSS218
AL19 VSS61 VSS142 Y3 H3 VSS219
AL16 VSS62 VSS143 Y2 H2 VSS220
AL13 VSS63 VSS144 W35 H1 VSS221
AL10 VSS64 VSS145 W34 G35 VSS222
AL7 VSS65 VSS146 W33 G32 VSS223
AL4 VSS66 VSS147 W32 G29 VSS224
AL2 VSS67 VSS148 W31 G26 VSS225
AK33 VSS68 VSS149 W30 G23 VSS226
AK30 VSS69 VSS150 W29 G20 VSS227
AK27 VSS70 VSS151 W28 G17 VSS228
AK25 VSS71 VSS152 W27 G11 VSS229
AK22 VSS72 VSS153 W26 F34 VSS230
AK19 VSS73 VSS154 U9 F31 VSS231
AK16 VSS74 VSS155 U8 F29 VSS232
AK13 VSS75 VSS156 U6 VSS233
AK10 VSS76 VSS157 U5
AK7 VSS77 VSS158 U3
AK4 VSS78 VSS159 U2
AJ25 VSS79 VSS160
VSS80

A A

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(7/7) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 11 of 60
5 4 3 2 1
 5 4 3 2 1

+1.5V

+VREF_DQ_DIMMA +1.5V +1.5V

4BA2/6W

1
<7> DDR_A_D[0..63]
R70
1K_0402_1% DDR3 SO-DIMM A <7> DDR_A_DQS[0..7]
JDIMM1
<7> DDR_A_DQS#[0..7]

2
+VREF_DQ_DIMMA 1 2
3 VREF_DQ VSS1 4 DDR_A_D4
VSS2 DQ4 <7> DDR_A_MA[0..15]

2.2U_0402_6.3V6M

.1U_0402_16V7K
DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5
1

C134

C133
1 1 DDR_A_D1 7 8
9 DQ1 VSS3 10 DDR_A_DQS#0
R71 DDR_A_DM0 11 VSS4 DQS#0 12 DDR_A_DQS0
1K_0402_1% 13 DM0 DQS0 14
D 2 2 DDR_A_D2 15 VSS5 VSS6 16 DDR_A_D6 D
2

DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7

19 DQ3 DQ7 20
DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
25 DQ9 DQ13 26
DDR_A_DQS#1 27 VSS9 VSS10 28 DDR_A_DM1
DDR_A_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <7,13>
31 32
DDR_A_D10 33 VSS11 VSS12 34 DDR_A_D14
DDR_A_D11 35 DQ10 DQ14 36 DDR_A_D15
37 DQ11 DQ15 38
DDR_A_D16 39 VSS13 VSS14 40 DDR_A_D20
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21
43 DQ17 DQ21 44
DDR_A_DQS#2 45 VSS15 VSS16 46 DDR_A_DM2
DDR_A_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_A_D22
DDR_A_D18 51 VSS18 DQ22 52 DDR_A_D23
DDR_A_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_A_D28
DDR_A_D24 57 VSS20 DQ28 58 DDR_A_D29
DDR_A_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_A_DQS#3
DDR_A_DM3 63 VSS22 DQS#3 64 DDR_A_DQS3
65 DM3 DQS3 66
DDR_A_D26 67 VSS23 VSS24 68 DDR_A_D30
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31
71 DQ27 DQ31 72
VSS25 VSS26

C DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA C
<7> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <7>
75 76
77 VDD1 VDD2 78 DDR_A_MA15
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
<7> DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
<7> M_CLK_DDR0 M_CLK_DDR0 101 VDD9 VDD10 102 M_CLK_DDR1 OSCAN (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
103 CK0 CK1 104 M_CLK_DDR1 <7>
<7> M_CLK_DDR#0 M_CLK_DDR#0 M_CLK_DDR#1
105 CK0# CK1# 106 M_CLK_DDR#1 <7>
DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1 +1.5V Layout Note: (10uF_0603_6.3V)*8
A10/AP BA1 DDR_A_BS1 <7>
<7> DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS#
DDR_A_RAS# <7>
Place near DIMM
111 BA0 RAS# 112
<7> DDR_A_WE# DDR_A_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMA# (0.1uF_402_10V)*4
WE# S0# DDR_CS0_DIMMA# <7>

1
<7> DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
CAS# ODT0 M_ODT0 <7>
117 118 R72
DDR_A_MA13 119 VDD15 VDD16 120 M_ODT1 1K_0402_1%
A13 ODT1 M_ODT1 <7>
DDR_CS1_DIMMA# 121 122
<7> DDR_CS1_DIMMA# S1# NC2 +1.5V
123 124

2
125 VDD17 VDD18 126 +VREF_CA
127 NCTEST VREF_CA 128
VSS27 VSS28

.1U_0402_16V7K

2.2U_0402_6.3V6M
DDR_A_D32 129 130 DDR_A_D36
DQ32 DQ36 EVT Check

1
C135

C136
DDR_A_D33 131 132 DDR_A_D37 1 1 1
DQ33 DQ37

10U_0603_6.3V6M
C137

10U_0603_6.3V6M
C138

10U_0603_6.3V6M
C139

10U_0603_6.3V6M
C140

10U_0603_6.3V6M
C141

10U_0603_6.3V6M
C142

10U_0603_6.3V6M
C143

10U_0603_6.3V6M
C144

.1U_0402_16V7K
C145

.1U_0402_16V7K
C146

.1U_0402_16V7K
C147

.1U_0402_16V7K
C148
133 134 1 1 1 1 1 1 1 1 1 1 1 1
DDR_A_DQS#4 135 VSS29 VSS30 136 DDR_A_DM4 R73 + C149 @
B DDR_A_DQS4 137 DQS#4 DM4 138 1K_0402_1% 220U_6.3V_M B
139 DQS4 VSS31 140 DDR_A_D38 2 2 @ @

2
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39 2 2 2 2 2 2 2 2 2 2 2 2 2
DDR_A_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D44
DDR_A_D40 147 VSS34 DQ44 148 DDR_A_D45
DDR_A_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#5
DDR_A_DM5 153 VSS36 DQS#5 154 DDR_A_DQS5
155 DM5 DQS5 156
VSS37 VSS38 VDDQ(1.5V) =
DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
DQ43 DQ47 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
161 162
DDR_A_D48 163 VSS39 VSS40 164 DDR_A_D52
DQ48 DQ52 6*0603 10uf (PER CONNECTOR) Layout Note:
DDR_A_D49 165 166 DDR_A_D53
167 DQ49 DQ53 168 Place near DIMM
DDR_A_DQS#6 169 VSS41 VSS42 170 DDR_A_DM6
DQS#6 DM6 VTT(0.75V) =
DDR_A_DQS6 171 172 7/28 Update connect GND directly
173 DQS6 VSS43 174 DDR_A_D54
VSS44 DQ54 3*0805 10uf 4*0402 1uf
DDR_A_D50 175 176 DDR_A_D55
DDR_A_D51 177 DQ50 DQ55 178 +0.75VS
DQ51 VSS45 VREF =
179 180 DDR_A_D60 DDR_A_DM0
DDR_A_D56 181 VSS46 DQ60 182 DDR_A_D61
del DDR_A_DM1
DQ56 DQ61 1*0402 0.1uf 1*0402 2.2uf
DDR_A_D57 183 184 DDR_A_DM2
185 DQ57 VSS47 186 DDR_A_DQS#7 DDR_A_DM3
VSS48 DQS#7 VDDSPD (3.3V)=

1U_0402_6.3V6K
C150

1U_0402_6.3V6K
C151

1U_0402_6.3V6K
C152

1U_0402_6.3V6K
C153
DDR_A_DM7 187 188 DDR_A_DQS7 DDR_A_DM4
189 DM7 DQS7 190 DDR_A_DM5
VSS49 VSS50 1*0402 0.1uf 1*0402 2.2uf 1 1 1 1
DDR_A_D58 191 192 DDR_A_D62 DDR_A_DM6
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63 DDR_A_DM7
1 R81 2 195 DQ59 DQ63 196 @ @
10K_0402_5% 197 VSS51 VSS52 198 2 2 2 2
199 SA0 EVENT# 200 SMB_DATA_S3
+3VS VDDSPD SDA SMB_DATA_S3 <13,15,36> Layout Note:
2.2U_0402_6.3V6M

.1U_0402_16V7K

A 201 202 SMB_CLK_S3 A

SA1 SCL SMB_CLK_S3 <13,15,36>
Place near DIMM
C155

C156

1 1 203 204 +0.75VS

VTT1 VTT2
1
10K_0402_5%
R83

205 206 1/76BA1/86W

G1 G2
2 2 FOX_AS0A626-U4SN-7F
ME@
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 12 of 60
5 4 3 2 1
 5 4 3 2 1

+1.5V
+VREF_DQ_DIMMB 4BA2/6W
<7> DDR_B_D[0..63]

1
+1.5V +1.5V
<7> DDR_B_DQS[0..7]
R84
1K_0402_1% JDIMM2
<7> DDR_B_DQS#[0..7]
+VREF_DQ_DIMMB 1 2
3 VREF_DQ VSS1 4 DDR_B_D4
<7> DDR_B_MA[0..15]

2
DDR_B_D0 5 VSS2 DQ4 6 DDR_B_D5
DDR_B_D1 7 DQ0 DQ5 8
DQ1 VSS3

2.2U_0402_6.3V6M

.1U_0402_16V7K
9 10 DDR_B_DQS#0
VSS4 DQS#0
1
1 1 DDR_B_DM0 11 12 DDR_B_DQS0
13 DM0 DQS0 14
VSS5 VSS6

C158

C157
R85 DDR_B_D2 15 16 DDR_B_D6
1K_0402_1% DDR_B_D3 17 DQ2 DQ6 18 DDR_B_D7
D 2 2 19 DQ3 DQ7 20 D
2

DDR_B_D8 21 VSS7 VSS8 22 DDR_B_D12

DDR_B_D9 23 DQ8 DQ12 24 DDR_B_D13
25 DQ9 DQ13 26
DDR_B_DQS#1 27 VSS9 VSS10 28 DDR_B_DM1
DDR_B_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <7,12>
31 32
DDR_B_D10 33 VSS11 VSS12 34 DDR_B_D14
For Arranale only +VREF_DQ_DIMMB DDR_B_D11 35 DQ10 DQ14 36 DDR_B_D15
supply from a external 1.5V voltage divide 37 DQ11 DQ15 38
DDR_B_D16 39 VSS13 VSS14 40 DDR_B_D20
circuit. DDR_B_D17 41 DQ16 DQ20 42 DDR_B_D21
43 DQ17 DQ21 44
DDR_B_DQS#2 45 VSS15 VSS16 46 DDR_B_DM2
DDR_B_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D22
DDR_B_D18 51 VSS18 DQ22 52 DDR_B_D23
DDR_B_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D28
DDR_B_D24 57 VSS20 DQ28 58 DDR_B_D29
DDR_B_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_B_DQS#3
DDR_B_DM3 63 VSS22 DQS#3 64 DDR_B_DQS3
65 DM3 DQS3 66
DDR_B_D26 67 VSS23 VSS24 68 DDR_B_D30
DDR_B_D27 69 DQ26 DQ30 70 DDR_B_D31
71 DQ27 DQ31 72
VSS25 VSS26

<7> DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB

CKE0 CKE1 DDR_CKE3_DIMMB <7>
75 76
C 77 VDD1 VDD2 78 DDR_B_MA15 C
DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14
<7> DDR_B_BS2 BA2 A14
81 82
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
M_CLK_DDR2 101 VDD9 VDD10 102 M_CLK_DDR3
<7> M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 <7>
<7> M_CLK_DDR#2 M_CLK_DDR#2 103 104 M_CLK_DDR#3
105 CK0# CK1# 106 M_CLK_DDR#3 <7>
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
109 A10/AP BA1 110 DDR_B_BS1 <7> +1.5V
DDR_B_BS0 DDR_B_RAS# Layout Note:
<7> DDR_B_BS0
111 BA0 RAS# 112 DDR_B_RAS# <7> (10uF_0603_6.3V)*8
DDR_B_WE# 113 VDD13 VDD14 114 DDR_CS2_DIMMB# Place near DIMM
<7> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <7>

1
DDR_B_CAS# 115 116 M_ODT2
<7> DDR_B_CAS#
117 CAS# ODT0 118
M_ODT2 <7>
R86 (0.1uF_402_10V)*4
DDR_B_MA13 119 VDD15 VDD16 120 M_ODT3 1K_0402_1%
A13 ODT1 M_ODT3 <7>
<7> DDR_CS3_DIMMB# DDR_CS3_DIMMB# 121 122
123 S1# NC2 124

2
125 VDD17 VDD18 126 +VREF_CB
NCTEST VREF_CA +1.5V

.1U_0402_16V7K

2.2U_0402_6.3V6M
127 128
DDR_B_D32 129 VSS27 VSS28 130 DDR_B_D36
DQ32 DQ36

1
C159

C160
DDR_B_D33 131 132 DDR_B_D37 1 1
DQ33 DQ37

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
133 134
VSS29 VSS30

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
DDR_B_DQS#4 135 136 DDR_B_DM4 R87
DQS#4 DM4

C161

C162

C163

C164

C165

C166

C167

C168

C169

C170

C171

C172
DDR_B_DQS4 137 138 1K_0402_1% 1 1 1 1 1 1 1 1 1 1 1 1
139 DQS4 VSS31 140 DDR_B_D38 2 2

2
B DDR_B_D34 141 VSS32 DQ38 142 DDR_B_D39 B
DDR_B_D35 143 DQ34 DQ39 144 @ @
145 DQ35 VSS33 146 DDR_B_D44 2 2 2 2 2 2 2 2 2 2 2 2
DDR_B_D40 147 VSS34 DQ44 148 DDR_B_D45
DDR_B_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#5
DDR_B_DM5 153 VSS36 DQS#5 154 DDR_B_DQS5
DM5 DQS5 VDDQ(1.5V) =
155 156
DDR_B_D42 157 VSS37 VSS38 158 DDR_B_D46
DQ42 DQ46 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
DDR_B_D43 159 160 DDR_B_D47
161 DQ43 DQ47 162
VSS39 VSS40 6*0603 10uf (PER CONNECTOR)
DDR_B_D48 163 164 DDR_B_D52
DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53
167 DQ49 DQ53 168
Layout Note:
VSS41 VSS42 VTT(0.75V) =
DDR_B_DQS#6 169
DQS#6 DM6
170 DDR_B_DM6 Place near DIMM
DDR_B_DQS6 171 172 3*0805 10uf 4*0402 1uf
173 DQS6 VSS43 174 DDR_B_D54
DDR_B_D50 175 VSS44 DQ54 176 DDR_B_D55
DDR_B_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_B_D60 +0.75VS
VSS46 DQ60 1*0402 0.1uf 1*0402 2.2uf
DDR_B_D56 181 182 DDR_B_D61
DDR_B_D57 183 DQ56 DQ61 184 DDR_B_DM0
DQ57 VSS47 VDDSPD (3.3V)=
185 186 DDR_B_DQS#7 DDR_B_DM1
DDR_B_DM7 187 VSS48 DQS#7 188 DDR_B_DQS7 DDR_B_DM2
DM7 DQS7 1*0402 0.1uf 1*0402 2.2uf

1U_0402_6.3V6K
C173

1U_0402_6.3V6K
C174

1U_0402_6.3V6K
C175

1U_0402_6.3V6K
C176
189 190 DDR_B_DM3
DDR_B_D58 191 VSS49 VSS50 192 DDR_B_D62 DDR_B_DM4
DQ58 DQ62 1 1 1 1
DDR_B_D59 193 194 DDR_B_D63 DDR_B_DM5
195 DQ59 DQ63 196 DDR_B_DM6
1 R95 2 197 VSS51 VSS52 198 @ @ DDR_B_DM7
10K_0402_5% 199 SA0 EVENT# 200 SMB_DATA_S3 2 2 2 2
201 VDDSPD SDA 202 SMB_DATA_S3 <12,15,36>
1 2 SMB_CLK_S3
+3VS SA1 SCL SMB_CLK_S3 <12,15,36>
.1U_0402_16V7K

R97 10K_0402_5% 203 204 +0.75VS

VTT1 VTT2 1/76BA1/86W
2.2U_0402_6.3V6M
C177

C178

A A
1 1
205 206
Layout Note:
G1 G2 Place near DIMM
FOX_AS0A626-U8SN-7F
2 2 ME@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT2
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 13 of 60
5 4 3 2 1
 5 4 3 2 1

PCH_RTCX1

W=20mils W=20mils 1 2 PCH_RTCX2

R98 10M_0402_5%
+RTCBATT +RTCVCC
Y1
R99 1 2
1K_0402_5% 32.768KHZ_12.5PF_CM31532768DZFT
2 1 1 1
C181
1

1 C180 18P_0402_50V8J
CLRP1 C179 15P_0402_50V8J
SHORT PADS 1U_0402_6.3V6K 2 2
2

2 CRYSTAL@
D R4956 D
1 2 PCH_RTCX1
0_0402_5%
R4957
1 2 GCLK_32K
GCLK_32K <36>
0_0402_5%
CMOS GCLK@
U4A

SHORT PADS
CLRP2
+RTCVCC
+RTCVCC PCH_RTCX1_R A20 C38 LPC_AD0
1 RTCX1 FWH0 / LAD0 LPC_AD0 <36,42>

1
R101 1 2 1M_0402_5% SM_INTRUDER# A38 LPC_AD1
FWH1 / LAD1 LPC_AD1 <36,42>

LPC
C183 PCH_RTCX2 C20 B37 LPC_AD2 EC and Mini card debug port
RTCX2 FWH2 / LAD2 LPC_AD2 <36,42>
R102 1 2 330K_0402_5% PCH_INTVRMEN 1U_0402_6.3V6K C37 LPC_AD3

2
2 FWH3 / LAD3 LPC_AD3 <36,42>
1 2 PCH_RTCRST# D20
R103 20K_0402_5% RTCRST# D36 LPC_FRAME#
INTVRMEN FWH4 / LFRAME# LPC_FRAME# <36,42>
烉Integrated
1 2 PCH_SRTCRST# G22
SRTCRST#
* HL烉 Integrated VRM enable R100 20K_0402_5% E36 +3VS
1 LDRQ0#

1
SHORT PADS
CLRP3
SM_INTRUDER# K22 K36 2 1 10K_0402_5%

RTC
VRM disable R104
C182 INTRUDER# LDRQ1# / GPIO23
(INTVRMEN should always be pull high.) 1U_0402_6.3V6K PCH_INTVRMEN C17 V5 SERIRQ
SERIRQ <42>

2
2 INTVRMEN SERIRQ

AM3 SATA_DTX_C_IRX_N0
+3VS SATA0RXN SATA_DTX_C_IRX_N0 <40>
HDA_BIT_CLK N34 AM1 SATA_DTX_C_IRX_P0
HDA_BCLK SATA0RXP SATA_DTX_C_IRX_P0 <40>
AP7 SATA_ITX_C_DRX_N0 0.01U_0402_16V7K 2 1 C184 SATA_ITX_DRX_N0

SATA 6G
SATA0TXN SATA_ITX_DRX_N0 <40> HDD
R105 1 @ 2 1K_0402_5% HDA_SPKR HDA_SYNC L34 AP5 SATA_ITX_C_DRX_P0 0.01U_0402_16V7K 2 1 C185 SATA_ITX_DRX_P0 SATA_ITX_DRX_P0 <40>
HDA_SYNC SATA0TXP
HIGH= Enable ( No Reboot ) HDA_SPKR T10 AM10 CAP on Conn, side
<41> HDA_SPKR SPKR SATA1RXN AM8
LOW= Disable (Default)
* HDA_RST# K34
HDA_RST#
SATA1RXP
SATA1TXN
AP11
AP10
SATA1TXP
C +3V_PCH HDA_SDIN0 E34 AD7 SATA_DTX_C_IRX_N2 C
<41> HDA_SDIN0 HDA_SDIN0 SATA2RXN SATA_DTX_C_IRX_N2 <40>
AD5 SATA_DTX_C_IRX_P2 ODD
SATA2RXP SATA_DTX_C_IRX_P2 <40>
R106 2 @ 1 1K_0402_5% HDA_SDOUT G34 AH5 SATA_ITX_C_DRX_N2
HDA_SDIN1 SATA2TXN AH4 SATA_ITX_C_DRX_N2 <40>
SATA_ITX_C_DRX_P2
SATA2TXP SATA_ITX_C_DRX_P2 <40>
Low = Disabled (Default) C34
* HDA_SDIN2 AB8

IHDA
High = Enabled [Flash Descriptor Security Overide] A34 SATA3RXN AB10
R109 HDA_SDIN3 SATA3RXP AF3
0_0402_5% SATA3TXN AF1
ME_FLASH 1 2 HDA_SDOUT A36 SATA3TXP
+3V_PCH <42> ME_FLASH HDA_SDO Y7

SATA
SATA4RXN Y5
2 1 1K_0402_5% SATA4RXP
R108 HDA_SYNC R107 1 @ 2 1K_0402_1% PCH_GPIO33 C36 AD3
HDA_DOCK_EN# / GPIO33 SATA4TXN AD1
10K_0402_5% 2 R264 @1 PCH_GPIO13 N32 SATA4TXP
+3V_PCH HDA_DOCK_RST# / GPIO13
This signal has a weak internal pull-down Y3
SATA5RXN Y1
On Die PLL VR is supplied by SATA5RXP AB3
* 1.5V when smapled high
1.8V when sampled low
2 R110 1 PCH_JTAG_TCK J3
JTAG_TCK
SATA5TXN
SATA5TXP
AB1
Needs to be pulled High for Chief River platfrom 51_0402_5% PCH_JTAG_TMS H7 Y11 R111
JTAG_TMS SATAICOMPO 37.4_0402_1% +1.05VS_VCC_SATA

JTAG
PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
+5VS JTAG_TDI SATAICOMPI
R112 PCH_JTAG_TDO H1
JTAG_TDO +1.05VS_SATA3
33_0402_5%
SATA3RCOMPO
AB12 R113 8MB SPI ROM FOR ME
1 2 HDA_BIT_CLK 49.9_0402_1%
<41> HDA_BITCLK_AUDIO
2
G

R114 Q10 AB13 SATA3_COMP 1 2

33_0402_5% LBSS138LT1G_SOT-23-3 SATA3COMPI & Non-share ROM.
1 2 HDA_SYNC_R 3 1 HDA_SYNC
<41> HDA_SYNC_AUDIO
SPI_CLK_PCH_R T3 AH1 RBIAS_SATA3 1 2
S

R116
33_0402_5% SPI_CLK SATA3RBIAS R115 +3VS
2

B 1 2 HDA_RST# SPI_SB_CS0# Y14 750_0402_1% B

<41> HDA_RST_AUDIO# SPI_CS0#
R118 R878 HDD_LED# R291
SPI_SB_CS1# T1 HDD_LED# <43>
33_0402_5% 1M_0402_5% R175 @ 0_0402_5% U6
SPI_CS1#
SPI

1 2 HDA_SDOUT 1 2 P3 2 R117 1 10K_0402_5% SPI_SB_CS1# 1 2 CS1# 1 8 0_0402_5%

<41> HDA_SDOUT_AUDIO SATALED# +3VS CS# VCC
SPI_SO_R 1 2 SPI_SO1 2 7 SPI_HOLD#1 R199
1

0_0402_5% SPI_SI V4 V14 PCH_GPIO21 2 R119 1 SPI_WP#1 3 SO HOLD# 6 SPI_CLK1 1 2 SPI_CLK_PCH_R

10K_0402_5% +3VS
SPI_MOSI SATA0GP / GPIO21 R188 4 WP# SCLK 5 SPI_SI1 1 2 SPI_SI
SPI_SO_R U3 P1 BBS_BIT0_R 2 R187 1 10K_0402_5% 33_0402_5% GND SI R196
+3V_PCH +3V_PCH +3V_PCH SPI_MISO SATA1GP / GPIO19 +3VS
Del Q10 check with codec 33_0402_5%
16M W25Q16CVSSIG SOIC 8P
VDDIO using 3VALW PANTHER-POINT_FCBGA989
1

+3VS
R121 @ R122 @ R123 @
200_0402_5% 200_0402_5% 200_0402_5%
SPI_CLK_PCH_R R266 1 2 SPI_WP#1
3.3K_0402_5%
U6 Rersver 4M+2M Solution
2

PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI

1

R221 1 2 SPI_HOLD#1 +3VS

1

R124 3.3K_0402_5%
R125 @ R126 @ R128 @ 33_0402_5% R127 1 2 SPI_WP# C191
100_0402_1% 100_0402_1% 100_0402_1% @ 3.3K_0402_5% 1 2
R130
R124;c190 close to U4.T3 pin
2

R129 1 2 SPI_HOLD# 0_0402_5% U5 0.1U_0402_16V4Z

2

3.3K_0402_5% SPI_SB_CS0# 1 2 CS# 1 8 0_0402_5%

C190 SPI_SO_R 1 2 SPI_SO_L 2 CS# VCC 7 SPI_HOLD# R132
DPDG1.1 SO HOLD#
22P_0402_50V8J SPI_WP# 3 6 SPI_CLK_PCH 1 2 SPI_CLK_PCH_R
@ 33_0402_5% 4 WP# SCLK 5 SPI_SI_R 1 2 SPI_SI
11/28 update to @ for power saving. GND SI
R131 R133
32M W25Q32BVSSIG SOIC 8P 33_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (1/9) SATA,HDA,SPI, LPC, XDP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 14 of 60
5 4 3 2 1
 5 4 3 2 1

U4B
Q60A
2N7002DW-T/R7_SOT363-6
PCIE_PRX_DTX_N1 BG34 6 1 SMB_CLK_S3
<37> PCIE_PRX_DTX_N1 PERN1 SMB_CLK_S3 <12,13,36>
LAN PCIE_PRX_DTX_P1 BJ34 E12 PCH_GPIO11 2 R134 1
<37> PCIE_PRX_DTX_P1 PERP1 SMBALERT# / GPIO11 +3V_PCH
C192 1 2 .1U_0402_16V7K PCIE_PTX_DRX_N1 AV32 10K_0402_5% 2.2K_0402_5% 2.2K_0402_5%
<37> PCIE_PTX_C_DRX_N1
C193 1 2 .1U_0402_16V7K PCIE_PTX_DRX_P1 AU32 PETN1 H14 PCH_SMBCLK 1 R136 2 1 2 R137 DIMM1

2
<37> PCIE_PTX_C_DRX_P1 PETP1 SMBCLK

<36> PCIE_PRX_DTX_N2
PCIE_PRX_DTX_N2 BE34
PERN2 SMBDATA
C9 PCH_SMBDATA
+3V_PCH
1 2 1
+3VS
2 DIMM2

5
PCIE_PRX_DTX_P2 BF34 R135 R138
WLAN
<36> PCIE_PRX_DTX_P2
<36> PCIE_PTX_C_DRX_N2
C194 1 2 .1U_0402_16V7K PCIE_PTX_DRX_N2 BB32 PERP2
PETN2
2.2K_0402_5% 2.2K_0402_5% MINI CARD
C195 1 2 .1U_0402_16V7K PCIE_PTX_DRX_P2 AY32 3 4 SMB_DATA_S3
<36> PCIE_PTX_C_DRX_P2 PETP2 SMB_DATA_S3 <12,13,36>

SMBUS
A12 DRAMRST_CNTRL_PCH
BG36 SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH <7>
2N7002DW-T/R7_SOT363-6
BJ36 PERN3 C8 PCH_SML0CLK
PERP3 SML0CLK Q60B
D AV34 2 R139 1 D
PETN3 +3V_PCH
AU34 G12 PCH_SML0DATA 1K_0402_5%
PETP3 SML0DATA Q61A
PCIE_PRX_DTX_N4 BF36 2 R140 1 10K_0402_5% 2N7002DW-T/R7_SOT363-6
<45> PCIE_PRX_DTX_N4 PERN4 +3V_PCH
PCIE_PRX_DTX_P4 BE36 6 1 EC_SMB_CK2
<45> PCIE_PRX_DTX_P4 PERP4 EC_SMB_CK2 <23,39,42>
USB3.0 C309 EU3@ 1 2 .1U_0402_16V7K PCIE_PTX_DRX_N4 AY34 C13 PCH_HOT#
<45> PCIE_PTX_C_DRX_N4 1 2 .1U_0402_16V7K PCIE_PTX_DRX_P4 BB34 PETN4 SML1ALERT# / PCHHOT# / GPIO74 PCH_HOT# <42>
C308 EU3@ 2.2K_0402_5%
<45> PCIE_PTX_C_DRX_P4 PETP4 E14 SML1CLK 1 R141 2 VGA

2
BG37 SML1CLK / GPIO58

PCI-E*
CAP on Conn, side
BH37 PERN5
PERP5 SML1DATA / GPIO75
M16 SML1DATA
+3V_PCH
1 2
+3VS EC

5
AY36 R142
BB36 PETN5
PETP5
2.2K_0402_5% thermal sensor
3 4 EC_SMB_DA2
EC_SMB_DA2 <23,39,42>
BJ38
BG38 PERN6 2N7002DW-T/R7_SOT363-6
AU36 PERP6 M7

Controller
PETN6 CL_CLK1 Q61B
AV36 +3V_PCH
PETP6 +3V_PCH

Link
BG40 T11
PERN7 CL_DATA1

2
BJ40
AY40 PERP7

2
BB40 PETN7 P10 R143
PETP7 CL_RST1# R544 R545
10K_0402_5%
BE38 2.2K_0402_5% 2.2K_0402_5%

1
BC38 PERN8 R144 0_0402_5%
AW38 PERP8 1 2

1
AY38 PETN8 CLK_REQ_VGA# <23> PCH_SML0CLK
PETP8
M10 PEG_CLKREQ#_R 1 R145 2 10K_0402_5% PCH_SML0DATA
R153 1 2 0_0402_5% CLK_PCIE_LAN#_R Y40 PEG_A_CLKRQ# / GPIO47 @
<37> CLK_PCIE_LAN# 1 2 Y39 CLKOUT_PCIE0N
LAN R154 0_0402_5% CLK_PCIE_LAN_R
<37> CLK_PCIE_LAN CLKOUT_PCIE0P AB37 CLK_PCIE_VGA#_R 1 2
R146 0_0402_5% CLK_PCIE_VGA#
C CLKREQ_LAN# J2 CLKOUT_PEG_A_N AB38 CLK_PCIE_VGA_R 1 2 CLK_PCIE_VGA# <23> C
R148 0_0402_5% CLK_PCIE_VGA

CLOCKS
<37> CLKREQ_LAN# 2 1 10K_0402_5% PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PCIE_VGA <23>
+3V_PCH R152

R149 1 2 0_0402_5% CLK_PCIE_WLAN1#_R AB49 AV22 CLK_CPU_DMI#

<36> CLK_PCIE_WLAN1# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# <6>
R150 1 2 0_0402_5% CLK_PCIE_WLAN1_R AB47 AU22 CLK_CPU_DMI
<36> CLK_PCIE_WLAN1 CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <6>
WLAN
<36> CLKREQ_WLAN# R156 1 2 0_0402_5% CLKREQ_WLAN#_R M1
R158 2 1 10K_0402_5% PCIECLKRQ1# / GPIO18 AM12
+3VS CLKOUT_DP_N AM13
AA48 CLKOUT_DP_P
AA47 CLKOUT_PCIE2N
CLKOUT_PCIE2P BF18 CLK_BUF_CPU_DMI# R155 1 2 10K_0402_5%
2 1 10K_0402_5% V10 CLKIN_DMI_N BE18
+3VS R147 PCH_GPIO20 CLK_BUF_CPU_DMI R157 1 2 10K_0402_5%
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P

R334 1 EU3@ 2 0_0402_5% CLK_USB30# Y37 BJ30 CLKIN_DMI2# R159 1 2 10K_0402_5%

<45> CLK_PCIE_USB30# 1 EU3@ 2 0_0402_5% Y36 CLKOUT_PCIE3N CLKIN_GND1_N BG30
R330 CLK_USB30 CLKIN_DMI2 R160 1 2 10K_0402_5%
<45> CLK_PCIE_USB30 CLKOUT_PCIE3P CLKIN_GND1_P
USB3.0
R326 1 EU3@ 2 0_0402_5% CLKREQ_USB30#_R A8
<45> CLKREQ_USB30# PCIECLKRQ3# / GPIO25
R301 2 1 10K_0402_5% G24 CLK_BUF_DREF_96M# R162 1 2 10K_0402_5%
+3V_PCH CLKIN_DOT_96N E24 CLK_BUF_DREF_96M R163 1 2 10K_0402_5%
Y43 CLKIN_DOT_96P
Y45 CLKOUT_PCIE4N
CLKOUT_PCIE4P AK7 CLK_BUF_PCIE_SATA# R164 1 2 10K_0402_5%
R165 2 1 10K_0402_5% PCH_GPIO26 L12 CLKIN_SATA_N AK5 CLK_BUF_PCIE_SATA R166 1 2 10K_0402_5%
+3V_PCH PCIECLKRQ4# / GPIO26 CLKIN_SATA_P
12/29, Y2 changes to SJ10000E800
V45
V46 CLKOUT_PCIE5N REFCLK14IN
K45 CLK_BUF_ICH_14M R167 1 2 10K_0402_5% S CRYSTAL 25MHZ 10PF +-20PPM 7V25000014
CLKOUT_PCIE5P
R168 2 1 10K_0402_5% PCH_GPIO44 L14 H45 CLK_PCI_LPBACK
+3V_PCH PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK <18>
B XTAL25_IN B
AB42 V47 XTAL25_IN_R
AB40 CLKOUT_PEG_B_N XTAL25_IN V49 XTAL25_OUT XTAL25_OUT 1 2
CLKOUT_PEG_B_P XTAL25_OUT R169 1M_0402_5%
R170 2 1 10K_0402_5% PCH_GPIO56 E6 R171 +1.05VS_VCCDIFFCLKN
+3V_PCH PEG_B_CLKRQ# / GPIO56 90.9_0402_1% Y2
Y47 XCLK_RCOMP 1 2 3 4
V40 XCLK_RCOMP OSC NC
V42 CLKOUT_PCIE6N 2 1
CLKOUT_PCIE6P NC OSC
R172 2 110K_0402_5% PCH_GPIO45 T13 25MHZ_20PF_FSX3M-25.M20FDO
+3V_PCH PCIECLKRQ6# / GPIO45 27M_SSC

1
V38 K43
V37 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 C196 C197
FLEX CLOCKS

CLKOUT_PCIE7P F47 12P_0402_50V8J 12P_0402_50V8J

2
R174 2 1 10K_0402_5% PCH_GPIO46 K12 CLKOUTFLEX1 / GPIO65
+3V_PCH PCIECLKRQ7# / GPIO46 H47 LAN_48M 1 R207 @2 22_0402_5%
AK14 CLKOUTFLEX2 / GPIO66 PCH_LAN_48M <37>
PCIE_CLK_8N AK13 CLKOUT_ITPXDP_N K49 PCH_GPIO67
PCIE_CLK_8P CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 PCH_GPIO67 <19>
BIOS Request SKU ID
PANTHER-POINT_FCBGA989
CRYSTAL@
XTAL25_IN R1381 1 2 0_0402_5% XTAL25_IN_R

GCLK_PCH_25MHZ R1382 1 2 0_0402_5%

<36> GCLK_PCH_25MHZ
GCLK@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (2/9) PCIE, SMBUS, CLK
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 15 of 60
5 4 3 2 1
 5 4 3 2 1

D D

U4C

DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0

<5> DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <5>
U15 DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1
<5> DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <5>
MC74VHC1G08DFT2G SC70 5P DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2
<5> DMI_CTX_PRX_N2 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N2 <5>
3

DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3

<5> DMI_CTX_PRX_N3 DMI3RXN FDI_RXN3 FDI_CTX_PRX_N3 <5>
1 BC12 FDI_CTX_PRX_N4
G

<55> VGATE A FDI_RXN4 FDI_CTX_PRX_N4 <5>

4 SYS_PWROK DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5
Y SYS_PWROK <6> <5> DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <5>
PCH_PWROK 2 DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6
B <5> DMI_CTX_PRX_P1 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 <5>
P

DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7

<5> DMI_CTX_PRX_P2 DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 <5>
DMI_CTX_PRX_P3 BJ20
<5> DMI_CTX_PRX_P3
5

DMI3RXP
1

BG14 FDI_CTX_PRX_P0
FDI_RXP0 FDI_CTX_PRX_P0 <5>
R180 @ DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1
<5> DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 <5>
100K_0402_5% DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2
<5> DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 <5>
+3VS DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3
<5> DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P3 <5>
DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4
FDI_CTX_PRX_P4 <5>
2

<5> DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4

DMI
FDI
BG12 FDI_CTX_PRX_P5
FDI_RXP5 FDI_CTX_PRX_P5 <5>
DMI_CRX_PTX_P0 AY24 BJ10 FDI_CTX_PRX_P6
<5> DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 <5>
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7
<5> DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <5>
DMI_CRX_PTX_P2 AY18
<5> DMI_CRX_PTX_P2 AU18 DMI2TXP
DMI_CRX_PTX_P3
<5> DMI_CRX_PTX_P3 DMI3TXP AW16 FDI_INT
FDI_INT FDI_INT <5>
+1.05VS BJ24 AV12 FDI_FSYNC0
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <5> +RTCVCC
1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <5>
R177 49.9_0402_1%
*

1
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0
C DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <5> C
R178 750_0402_1% R179
4mil width and place
within 500mil of the PCH
FDI_LSYNC1
BB10 FDI_LSYNC1
FDI_LSYNC1 <5>
烉
DSWODVREN - On Die DSW VR Enable

烉
H Enable
L Disable
330K_0402_5%

2
SUSACK# is only used on platform A18 DSWODVREN
DSWVRMEN
that support the Deep Sx state.

System Power Management

1
T72 SUSACK# C12 E22 PCH_DPWROK 1 R181 2 PCH_RSMRST#_R
SUSACK# DPWROK 0_0402_5% R183
330K_0402_5%
2 1 SYS_RST# K3 B9 WAKE# 1 R185 2 0_0402_5% +3VS
+3VS SYS_RESET# WAKE# PCIE_WAKE# <36,37,45> @
10K_0402_5% R184 1 2 10K_0402_5%
+3V_PCH

2
R186 @ R189 8.2K_0402_5%
SYS_PWROK P12 N3 PM_CLKRUN# 1 2
SYS_PWROK CLKRUN# / GPIO32
R299 10K_0402_5%
AEPWROK can be connect to PCH_PWROK 1 2 PCH_POK L22 G8 SUS_STAT# T74 2 1
<42> PCH_PWROK PWROK SUS_STAT# / GPIO61
PWROK if iAMT disable R190 0_0402_5%

R191 1 @ 2 APWROK L10 N14

<42> PCH_APWROK APWROK SUSCLK / GPIO62 SUSCLK <42>
PCH_POK 1 2 APWROK 0_0402_5% R302

0_0402_5% PM_DRAM_PWRGD B13 D10

<6> PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# <42>

+3VS 1 2 PCH_RSMRST#_R C21 H4

<42> EC_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# <42>
@ R193 0_0402_5%
+3V_PCH 2 R556 1 200_0402_5%
SUSWARN# K16 F4
SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# <42>
R192 2 1 300_0402_5% PM_DRAM_PWRGD Can be left NC
B 1 2 PBTN_OUT#_R E20 G10 SLP_A# T99 B
<42> PBTN_OUT# PWRBTN# SLP_A# when IAMT is not
R194 2 1 10K_0402_5% SUSWARN# R198 0_0402_5% support on the
R195 1 2 200K_0402_5% AC_PRESENT_R D29 1 2 AC_PRESENT_R H20 G16 PM_SLP_SUS# T71
platfrom
<42,49> ACIN ACPRESENT / GPIO31 SLP_SUS#
CH751H-40PT_SOD323-2
R197 2 1 10K_0402_5% PCH_RSMRST#_R 2 R200 1 PCH_GPIO72 E10 AP14 H_PM_SYNC
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <6>
10K_0402_5%

2 R201 1 RI# A10 K14 PCH_GPIO291 2 Can be left NC if no use

+3V_PCH RI# SLP_LAN# / GPIO29 +3V_PCH
10K_0402_5% R261 @ integrated LAN.
10K_0402_5%
PANTHER-POINT_FCBGA989

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (3/9) DMI,FDI,PM,
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 16 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS

U4D

1
D R523 R234 J47 AP43 D
<33> PCH_ENBKL M45 L_BKLTEN SDVO_TVCLKINN AP45 +3VS
2.2K_0402_5% 2.2K_0402_5%
<33> PCH_ENVDD L_VDD_EN SDVO_TVCLKINP
P45 AM42
<33> PCH_PWM

2
L_BKLTCTL SDVO_STALLN AM40
SDVO_STALLP

1
EDID_CLK EDID_CLK T40
+3VS <33> EDID_CLK K47 L_DDC_CLK AP39
EDID_DATA EDID_DATA HDMI@ R202 R203 HDMI@
<33> EDID_DATA L_DDC_DATA SDVO_INTN AP40 2.2K_0402_5% 2.2K_0402_5%
2.2K_0402_5%1 R204 2 CTRL_CLK T45 SDVO_INTP
2.2K_0402_5%1 R205 2 CTRL_DATA P39 L_CTRL_CLK

2
L_CTRL_DATA
2 R206
2.37K_0402_1% 1 LVDS_IBG AF37 P38 HDMICLK_NB
LVD_IBG SDVO_CTRLCLK HDMICLK_NB <35>
AF36 M39 HDMIDAT_NB
LVD_VBG SDVO_CTRLDATA HDMIDAT_NB <35>
LVD_VREF AE48
AE47 LVD_VREFH AT49
LVD_VREFL DDPB_AUXN AT47
DDPB_AUXP AT40 TMDS_B_HPD
DDPB_HPD TMDS_B_HPD <35>
AK39
<33> LVDS_ACLK# LVDSA_CLK#

LVDS
AK40 AV42 TMDS_B_DATA2#_PCHHDMI@ C200 1 2 .1U_0402_16V7K
<33> LVDS_ACLK LVDSA_CLK DDPB_0N HDMI_TX2-_CK <35>
AV40 TMDS_B_DATA2_PCH HDMI@ C201 1 2 .1U_0402_16V7K HDMI D2
AN48 DDPB_0P AV45 TMDS_B_DATA1#_PCHHDMI@ 1 2 HDMI_TX2+_CK <35>
C202 .1U_0402_16V7K
<33> LVDS_A0# AM47 LVDSA_DATA#0 DDPB_1N AV46 TMDS_B_DATA1_PCH HDMI@ 1 2 HDMI_TX1-_CK <35>
C203 .1U_0402_16V7K HDMI D1
<33> LVDS_A1# LVDSA_DATA#1 DDPB_1P HDMI_TX1+_CK <35>

Digital Display Interface

AK47 AU48 TMDS_B_DATA0#_PCHHDMI@ C204 1 2 .1U_0402_16V7K HDMI
C <33> LVDS_A2# AJ48 LVDSA_DATA#2 DDPB_2N AU47 TMDS_B_DATA0_PCH HDMI@ 1 2 HDMI_TX0-_CK <35> C
C205 .1U_0402_16V7K HDMI D0
LVDSA_DATA#3 DDPB_2P HDMI_TX0+_CK <35>
AV47 TMDS_B_CLK#_PCH HDMI@ C206 1 2 .1U_0402_16V7K
AN47 DDPB_3N AV49 TMDS_B_CLK_PCH 1 2 HDMI_CLK-_CK <35>
HDMI@ C207 .1U_0402_16V7K HDMI CLK
<33> LVDS_A0 AM49 LVDSA_DATA0 DDPB_3P HDMI_CLK+_CK <35>
<33> LVDS_A1 LVDSA_DATA1
AK49
<33> LVDS_A2 AJ47 LVDSA_DATA2 P46
LVDSA_DATA3 DDPC_CTRLCLK
CAP move on Conn, side
P42
DDPC_CTRLDATA
AF40
<33> LVDS_BCLK# LVDSB_CLK#
AF39 AP47
<33> LVDS_BCLK LVDSB_CLK DDPC_AUXN AP49
AH45 DDPC_AUXP AT38
<33> LVDS_B0# AH47 LVDSB_DATA#0 DDPC_HPD
<33> LVDS_B1# AF49 LVDSB_DATA#1 AY47
<33> LVDS_B2# LVDSB_DATA#2 DDPC_0N
AF45 AY49
LVDSB_DATA#3 DDPC_0P AY43
AH43 DDPC_1N AY45
<33> LVDS_B0 AH49 LVDSB_DATA0 DDPC_1P BA47
+3VS <33> LVDS_B1 AF47 LVDSB_DATA1 DDPC_2N BA48
<33> LVDS_B2 LVDSB_DATA2 DDPC_2P
AF43 BB47
DAC_BLU LVDSB_DATA3 DDPC_3N BB49
<34> DAC_BLU DDPC_3P
R208 2 1 150_0402_1%
1

DAC_GRN
<34> DAC_GRN
B R559 R524 R209 2 1 150_0402_1% N48 M43 B
2.2K_0402_5% 2.2K_0402_5% DAC_RED P49 CRT_BLUE DDPD_CTRLCLK M36
<34> DAC_RED T49 CRT_GREEN DDPD_CTRLDATA
R210 2 1 150_0402_1%
CRT_RED
2

AT45
DDPD_AUXN

CRT
CRT_DDC_CLK CRT_DDC_CLK T39 AT43
<34> CRT_DDC_CLK CRT_DDC_CLK DDPD_AUXP
CRT_DDC_DATA CRT_DDC_DATA M40 BH41
<34> CRT_DDC_DATA CRT_DDC_DATA DDPD_HPD
BB43
M47 DDPD_0N BB45
<34> CRT_HSYNC M49 CRT_HSYNC DDPD_0P BF44
<34> CRT_VSYNC CRT_VSYNC DDPD_1N BE44
DDPD_1P BF42
CRT_IREF T43 DDPD_2N BE42
T42 DAC_IREF DDPD_2P BJ42
CRT_IRTN DDPD_3N
1

BG42
R211 DDPD_3P
1K_0402_1% PANTHER-POINT_FCBGA989
2

A A

Security Classification Compal Secret Data

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (4/9) LVDS,CRT,DP,HDMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 17 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS

U4E
RP2 AY7
8 1 PCI_PIRQA# RSVD1 AV7
7 2 PCI_PIRQD# BG26 RSVD2 AU3
6 3 PCI_PIRQC# BJ26 TP1 RSVD3 BG4
5 4 PCI_PIRQB# BH25 TP2 RSVD4
BJ16 TP3 AT10
8.2K_0804_8P4R_5% BG16 TP4 RSVD5 BC8
RP1 AH38 TP5 RSVD6
D TP6 D
8 1 PCH_GPIO2 AH37 AU2
7 2 DGPU_PWR_EN_R AK43 TP7 RSVD7 AT4
6 3 PCH_GPIO4 AK45 TP8 RSVD8 AT3
5 4 ODD_DA#_R C18 TP9 RSVD9 AT1
N30 TP10 RSVD10 AY3
8.2K_0804_8P4R_5% H3 TP11 RSVD11 AT5
AH12 TP12 RSVD12 AV3
AM4 TP13 RSVD13 AV1
AM5 TP14 RSVD14 BB1
R213 1 2 8.2K_0402_5% PCH_GPIO5 Y13 TP15 RSVD15 BA3
K24 TP16 RSVD16 BB5
R225 1 2 8.2K_0402_5% PCH_WL_OFF# L24 TP17 RSVD17 BB3
AB46 TP18 RSVD18 BB7
R292 1 @ 2 8.2K_0402_5% PCH_GPIO51 AB45 TP19 RSVD19 BE8
TP20 RSVD20

RSVD
BD4
R557 1 @ 2 8.2K_0402_5% PCH_GPIO53
PPT EDS DOC#474146 RSVD21 BF6
RSVD22
R259 1 2 8.2K_0402_5% DGPU_PWR_EN1 B21 AV5
M20 TP21 RSVD23 AV10
R212 1 2 8.2K_0402_5% DGPU_HOLD_RST#_R
9/22 NA 9/26 Mount AY16 TP22 RSVD24
BG46 TP23 AT8
R214 1 @ 2 100K_0402_5% DGPU_HOLD_RST#_R TP24 RSVD25
AY5
9/22 from 8.2K NA 9/26 NA RSVD26 BA2
T1829 USB3_RX1_N BE28 RSVD27
T1825 BC30 USB3Rn1 AT12
USB3_RX3_N BE32 USB3Rn2 RSVD28 BF3
C Boot BIOS Strap bit1 BBS1 <45> USB3_RX3_N USB3Rn3 RSVD29 C
<45> USB3_RX4_N USB3_RX4_N BJ32
T1832 USB3_RX1_P BC28 USB3Rn4
Boot BIOS USB3Rp1
T1826 BE30 USB DEBUG=PORT1 AND PORT9
Bit11 Bit10 Destination <45> USB3_RX3_P USB3_RX3_P BF32 USB3Rp2
USB3Rp3
<45> USB3_RX4_P USB3_RX4_P BG32 C24
T1831 USB3_TX1_N AV26 USB3Rp4 USBP0N A24
0 1 Reserved USB3Tn1 USBP0P
GNT1#/ T1827 BB26 C25 USB20_N1
USB3Tn2 USBP1N USB20_N1 <44>
1 0 Reserved USB3_TX3_N AU28 B25 USB20_P1 (CR-B/D USB)
GPIO51 <45> USB3_TX3_N
USB3_TX4_N AY30 USB3Tn3 USBP1P C26 USB20_N2
USB20_P1 <44>
<45> USB3_TX4_N USB3Tn4 USBP2N USB20_N2 <45>
1 1 SPI (Default) T1830 USB3_TX1_P AU26 A26 USB20_P2 LEFT USB
* T1828 AY26 USB3Tp1
USB3Tp2
USBP2P
USBP3N
K28 USB20_N3
USB20_P2
USB20_N3
<45>
<45> (USB 3.0)
0 0 LPC USB3_TX3_P AV28 H28 USB20_P3 LEFT USB
<45> USB3_TX3_P USB3Tp3 USBP3P USB20_P3 <45>
USB3_TX4_P AW30 E28
<45> USB3_TX4_P USB3Tp4 USBP4N D28
USBP4P C28 USB20_N5
USBP5N USB20_N5 <33>
A28 USB20_P5 USB Camera
USBP5P USB20_P5 <33>
C29
DGPU_PWR_EN_R 1 2 NVDD_PWR_EN USBP6N B29
R319 0_0402_5% PCI_PIRQA# K40 USBP6P N28
@ PCI_PIRQB# K38 PIRQA# USBP7N M28
PIRQB# USBP7P

PCI
PCI_PIRQC# H38 L30
PCI_PIRQD# G38 PIRQC# USBP8N K30
PIRQD# USBP8P G30 USB20_N9
USBP9N USB20_N9 <44>
R553 1 2 0_0402_5% DGPU_HOLD_RST#_RC46 E30 USB20_P9 RIGHT USB
<23> DGPU_HOLD_RST# REQ1# / GPIO50 USBP9P USB20_P9 <44>

USB
GPIO55 R692 1 2 0_0402_5% DGPU_PWR_EN1 C44 C30
<54> NVDD_PWR_EN REQ2# / GPIO52 USBP10N USB20_N10 <36>
R691 1 2 0_0402_5% DGPU_PWR_EN_R E40 A30 WLAN
<23,25> DGPU_PWR_EN REQ3# / GPIO54 USBP10P USB20_P10 <36>
B PCH_WL_OFF# R215 1 @ 2 1K_0402_5% L32 USB20_N11 B
USBP11N USB20_N11 <43>
PCH_GPIO51 D47 K32 USB20_P11 CARD READER
GNT1# / GPIO51 USBP11P USB20_P11 <43>
PCH_GPIO53 E42 G32
PCH_WL_OFF# F46 GNT2# / GPIO53 USBP12N E32
<36> PCH_WL_OFF# GNT3# / GPIO55 USBP12P
A16 swap overide Strap/Top-Block C32 USB20_N13
USBP13N USB20_N13 <40>
Swap Override jumper A32 USB20_P13 Bluetooth
USBP13P USB20_P13 <40>
PCH_GPIO2 G42
R715 1 @ 2 0_0402_5% ODD_DA#_R G40 PIRQE# / GPIO2
Low=A16 swap <40,42> ODD_DA# PIRQF# / GPIO3
override/Top-Block PCH_GPIO4 C42 C33 USBRBIAS 1 R218 2
PCH_GPIO5 D44 PIRQG# / GPIO4 USBRBIAS# 22.6_0402_1%
PCI_GNT3# Swap Override enabled PIRQH# / GPIO5
High=Default Within 500 mils
* USBRBIAS
B33 +3V_PCH
K10
<42> PCI_PME# PME# 10K_1206_8P4R_5% RP3
PCH_PLTRST# C6 A14 USB_OC0# USB_OC5# 4 5
<6> PCH_PLTRST# PLTRST# OC0# / GPIO59 USB_OC0# <44>
K20 USB_OC1# USB_OC2# 3 6
OC1# / GPIO40 USB_OC1# <45>
B17 USB_OC2# USB_OC7# 2 7
22_0402_5% 1 2 R219 CLK_PCI_LPBACK_R H49 OC2# / GPIO41 C16 USB_OC3# USB_OC0# 1 8
<15> CLK_PCI_LPBACK CLKOUT_PCI0 OC3# / GPIO42
22_0402_5% 1 2 R220 CLK_PCI_EC_R H43 L16 USB_OC4#
<42> CLK_PCI_EC CLKOUT_PCI1 OC4# / GPIO43 USB_OC4# <44>
22_0402_5% 2 @ 1 R173 CLK_PCI_DB_R J48 A16 USB_OC5# 4 5
<36> CLK_PCI_DB CLKOUT_PCI2 OC5# / GPIO9
K42 D14 SMIB SMIB <45> USB_OC1# 3 6
H40 CLKOUT_PCI3 OC6# / GPIO10 C14 USB_OC7# USB_OC4# 2 7
1 R222 2 CLKOUT_PCI4 OC7# / GPIO14 USB_OC3# 1 8
0_0402_5%
PANTHER-POINT_FCBGA989 10K_1206_8P4R_5% RP4

SMIB 1 R267 2
A IU3@ A
3

10K_0402_5%
1 PCH_PLTRST#
G

4 A
<23,36,37,42,45> PLT_RST# Y 2
B
P

Security Classification Compal Secret Data

1

1 U7@
5

MC74VHC1G08DFT2G SC70 5P 2011/10/27 2012/10/27 Title

C208 @
Issued Date Deciphered Date
1U_0402_6.3V4Z
2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (5/9) PCI, USB
+3VS Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2

R223 Custom 0.3

100K_0402_5%
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 18 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS +3VS +3VS

2
10K_0402_5%

10K_0402_5%

10K_0402_5%
PCH_GPIO70 Function
@
@ R702
R703 0 14/15" R704
1 17"

1
PCH_GPIO69 PCH_GPIO70 PCH_GPIO71
PCH_GPIO71

2
10K_0402_5%

200K_0402_5%

200K_0402_5%
R707

@ R705 0 USB3.0 by PCH R706

@
D +3V_PCH 1 USB3.0 by NEC D

1
Weak internal pull-high
1 R235 2 10K_0402_5% EC_SMI#
9/22 from 10K 9/22 from 10K
U4F +3VS

1 R233 2 10K_0402_5% PCH_GPIO0 T7 C40 PCH_GPIO68 10K_0402_5%1 R224 2

+3VS BMBUSY# / GPIO0 TACH4 / GPIO68
1 R227 2 10K_0402_5% PCH_GPIO1 A42 B41 PCH_GPIO69
GPIO28 TACH1 / GPIO1 TACH5 / GPIO69
On-Die PLL Voltage Regulator 1 R228 2 10K_0402_5% PCH_GPIO6 H36 C41 PCH_GPIO70 +3VS
+3VS TACH2 / GPIO6 TACH6 / GPIO70
This signal has a weak internal pull up
烉
烉On-Die
<42> EC_SCI#
EC_SCI# E38
TACH3 / GPIO7 TACH7 / GPIO71
A40 PCH_GPIO71

2
H voltage regulator enable 9/22 from 10K
* L On-Die PLL Voltage Regulator disable <42> EC_SMI#
EC_SMI# C10
GPIO8
R236
10K_0402_5%
R240 1 @ 2 1K_0402_5% PCH_GPIO28 1 R229@ 2 10K_0402_5% PCH_GPIO12 C4
+3V_PCH LAN_PHY_PW R_CTRL / GPIO12

1
1 R230 2 1K_0402_5% EC_LID_OUT# G2 P4 +3VS
GPIO15 A20GATE GATEA20 <42>
<42> EC_LID_OUT#
AU16 PCH_PECI_R 1 @ 2
PECI H_PECI <6,42>
1 R231 2 10K_0402_5% PCH_GPIO16 U2 0_0402_5% R237
+3VS SATA4GP / GPIO16 P5 KBRST# KBRST# R226 1 2 10K_0402_5%
* PCH_GPIO27 (Have internal Pull-High) <46,54> DGPU_PWROK
R297 1 2 0_0402_5% RCIN# KBRST# <42>

GPIO
1
PU on power 2
side DGPU_PWROK_R D40 AY11
High: VCCVRM VR Enable +3VS TACH0 / GPIO17 PROCPW RGD H_CPUPWRGD <6>

CPU/MISC
R232 @ 10K_0402_1%
Low: VCCVRM VR Disable +3VS
1 2 BT_DISABLE# T5 AY10 PCH_THRMTRIP#_R 1 2 H_THRMTRIP#
H_THRMTRIP# <6>
C R238 10K_0402_5% SCLOCK / GPIO22 THRMTRIP# R239 390_0402_5% C
1 2 10K_0402_5% <36> BT_DISABLE# E8 T14
R245 @ PCH_GPIO27 ODD_EN
+3V_PCH <40> ODD_EN GPIO24 INIT3_3V#
PCH_THRMTRIP#_R <23>
PCH_GPIO27 E16 AY1
R241
GPIO27 DF_TVS INIT3_3V
1 2 10K_0402_5% PCH_GPIO28 P8 This signal has weak internal PU,can't pull low
GPIO28 AH8
<36,40> PCH_BT_ON# TS_VSS1
1 R242 2 10K_0402_5% PCH_BT_ON# K1
+3VS STP_PCI# / GPIO34 +1.8VS
AK11
+3VS 1 R243 2 10K_0402_5% PCH_GPIO35 K4 TS_VSS2
+3VS GPIO35 AH10
TS_VSS3
DMI Termination Voltage
PCH_GPIO36 V8
SATA2GP / GPIO36
1

1
AK10 Set to Vcc when HIGH
PCH_GPIO37 M5 TS_VSS4
R244 @ R250 @
SATA3GP / GPIO37
NV_CLE
10K_0402_5% 10K_0402_5% Set to Vss when LOW R216
PCH_GPIO38 N2 P37 2.2K_0402_5%
SLOAD / GPIO38 NC_1
2

2
PCH_GPIO37 PCH_GPIO36 R247 1 2 10K_0402_5% PCH_GPIO39 M3 NV_CLE 2 1
+3VS SDATAOUT0 / GPIO39 H_SNB_IVB# <6>
R217 1K_0402_5%
1

R248 1 2 10K_0402_5% PCH_GPIO48 V13 BG2 Weak internal CLOSE TO THE BRANCHING POINT
SDATAOUT1 / GPIO48 VSS_NCTF_15
1

PU,Do not pull low

R881 +3VS R249 1 2 10K_0402_5% PCH_GPIO49 V3 BG48
10K_0402_5% R547 SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
10K_0402_5% R251 1 2 10K_0402_5% PCH_GPIO57 D6 BH3
+3V_PCH
2

GPIO57 VSS_NCTF_17
2

BH47
VSS_NCTF_18
A4 BJ4
VSS_NCTF_1 VSS_NCTF_19
A44 BJ44
B VSS_NCTF_2 VSS_NCTF_20 B
A45 BJ45
VSS_NCTF_3 VSS_NCTF_21

NCTF
A46 BJ46
VSS_NCTF_4 VSS_NCTF_22
BIOS Request SKU ID
A5 BJ5
VSS_NCTF_5 VSS_NCTF_23
+3VS A6 BJ6
VSS_NCTF_6 VSS_NCTF_24
B3 C2
VSS_NCTF_7 VSS_NCTF_25
B47 C48
VSS_NCTF_8 VSS_NCTF_26
2

1
10K_0402_5%

10K_0402_5%

BD1 D1
VSS_NCTF_9 VSS_NCTF_27
BD49 D49
R711 R246 UMA@ VSS_NCTF_10 VSS_NCTF_28
BE1 E1
1

UMA@
VSS_NCTF_11 VSS_NCTF_29
PCH_GPIO38 BE49 E49
VSS_NCTF_12 VSS_NCTF_30
PCH_GPIO67 BF1 F1
PCH_GPIO67 <15> VSS_NCTF_13 VSS_NCTF_31
BF49 F49
VSS_NCTF_14 VSS_NCTF_32
2

1
10K_0402_5%

10K_0402_5%

N 13P@
N13P@
R708 R298 PANTHER-POINT_FCBGA989

PCH_GPIO38 PCH_GPIO67 Function

1

A A

0 0 Optimus
0 1 Reserved Security Classification Compal Secret Data
Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title
1 0 DIS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (6/9) GPIO, CPU, MISC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
1 1 UMA DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 19 of 60
5 4 3 2 1

Compal Electronics, Inc.

 5 4 3 2 1

L1 Change to 1 ohm P/N

S RES 1/10W 1 +-1% 0603
+1.05VS
EDS v2.1 Integrated Graphic: 1.3A U4G POWER +3VS PCH Power Rail Table
@ J2
63mA L1 1_0603_1% Refer to CPU EDS R1.5
2 1 +1.05VS_VCCCORE AA23 U48 +VCCADAC 2 1
AC23 VCCCORE[1] VCCADAC
VCCCORE[2] 1 1 1 1 S0 Iccmax

1U_0402_6.3V6K
C210

1U_0402_6.3V6K
C211

1U_0402_6.3V6K
C212
1 1 1 1 AD21 C395 Voltage Rail Voltage Current (A)

CRT
VCCCORE[3]

10U_0603_6.3V6M
C209
PAD-OPEN 4x4m AD23 U47 C213 C214 C215 10U_0603_6.3V6M
AF21 VCCCORE[4] VSSADAC 0.01U_0402_16V7K .1U_0402_16V7K 10U_0603_6.3V6M @

VCC CORE
AF23 VCCCORE[5] 2 2 2 2
VCCCORE[6]
V_PROC_IO 1.05 0.001
D 2 2 2 2 AG21 +3VS D
AG23 VCCCORE[7]
AG24 VCCCORE[8] AK36 +VCCA_LVDS 1mA* 2 1 V5REF 5 0.001
AG26 VCCCORE[9] VCCALVDS R295 0_0603_5%
AG27 VCCCORE[10] AK37
AG29 VCCCORE[11] VSSALVDS
VCCCORE[12]
V5REF_Sus 5 0.001
AJ23 +1.8VS
VCCCORE[13]

LVDS
AJ26 AM37 L2
AJ27 VCCCORE[14] VCCTX_LVDS[1] 0.1UH_MLF1608DR10KT_10%_1608
VCCCORE[15] 40mA Vcc3_3 3.3 0.228
AJ29 AM38 +VCCTX_LVDS 2 1
AJ31 VCCCORE[16] VCCTX_LVDS[2]
1 1 1 0.1uH inductor, 200mA
+1.05VS VCCCORE[17] AP36
VCCTX_LVDS[3]
VccADAC 3.3 0.001
C216 C217 C218
AP37 0.01U_0402_16V7K 0.01U_0402_16V7K 22U_0805_6.3V6M
2 1 +1.05VS_VCCDPLLEXP AN19 VCCTX_LVDS[4] 2 2 2
VCCIO[28]
VccADPLLA 1.05 0.075
R254 0_0603_5%

T47 +VCCAPLLEXP BJ22 +3VS VccADPLLB 1.05 0.075

VCCAPLLEXP 228mA
This pin can be left as no connect in V33 +3VS_VCC3_3_6 2 1
AN16 VCC3_3[6]

HVCMOS
R256 0_0603_5% VccCore 1.05 1.3
On-Die VR enabled mode (default). VCCIO[15]
1
AN17
VCCIO[16] V34 C219
VCC3_3[7]
VccDMI 1.05 0.042
.1U_0402_16V7K
AN21 2
VCCIO[17]
VccIO 1.05 3.709
AN26
VCCIO[18] 167mA
AN27 AT16 +VCCAFDI_VRM VccASW 1.05 0.903
VCCIO[19] VCCVRM[3]
+1.05VS Integrated Graphic: 3.709A AP21 +VCCP_VCCDMI +V1.05S_VCCP
C VCCIO[20] C
42mA VccSPI 3.3 0.01
+1.05VS_VCC_EXP AP23 AT20 +VCCP_VCCDMI 2 1
VCCIO[21] VCCDMI[1] R258 0_0603_5%
1
+1.05VS
1U_0402_6.3V6K
C222

1U_0402_6.3V6K
C223

1U_0402_6.3V6K
C224

1U_0402_6.3V6K
C225

DMI
1 1 1 1 1 AP24 VccDSW 3.3 0.001
VCCIO[22]
10U_0603_6.3V6M
C221

VCCIO
C220
AP26 AB36 +1.05VS_VCC_DMI_CCI 75mA 2 1 1U_0402_6.3V6K
VCCIO[23] VCCCLKDMI R294 0_0603_5% 2
1 VccDFTERM 1.8 0.002
2 2 2 2 2 AT24
VCCIO[24] C226
1U_0402_6.3V6K VccRTC 3.3 6 uA
AN33 2
VCCIO[25]
AN34 AG16 VccSus3_3 3.3 0.065
+3VS VCCIO[26] VCCDFTERM[1]

1 2 228mA +3VS_VCCA3GBG BH29 AG17 +VCCPNAND +1.8VS VccSusHDA 3.3 / 1.5 0.01
VCC3_3[3] VCCDFTERM[2]

DFT / SPI
0_0603_5% R260 1
C227 2mA*
.1U_0402_16V7K AJ16 2 1 VccVRM 1.8 / 1.5 0.167
167mA VCCDFTERM[3]
R293 0_0603_5%
2 +VCCAFDI_VRM AP16
VCCVRM[2] 1
AJ17 C228 VccCLKDMI 1.05 0.075
VCCDFTERM[4] .1U_0402_16V7K
This pin can be left as no connect in +1.05VS_VCCAPLL_FDI BG6
T50
On-Die VR enabled mode (default). VccAFDIPLL 2 +3VS VccSSC 1.05 0.095

+1.05VS
1 2 +1.05VS_VCCDPLL_FDIAP17 10mA R399
0_0603_5% R263 VCCIO[27] V1 +3V_VCCPSPI 1 2 VccDIFFCLKN 1.05 0.055
FDI

VCCSPI
AU20 1 0_0402_5%
+VCCP_VCCDMI VCCDMI[2]
VccALVDS 3.3 0.001
C230
B PANTHER-POINT_FCBGA989 1U_0402_6.3V6K B
2 VccTX_LVDS 1.8 0.04

+VCCAFDI_VRM
+1.5VS

2 1 +VCCAFDI_VRM
R265 0_0603_5%

Intel recommand VCCVRM==>1.5V FOR MOBILE

stuff R265 and unstuff R266 VCCVRM==>1.8V FOR DESKTOP
VCCVRM = 160mA detal waiting for newest spec

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (7/9) PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 20 of 60
5 4 3 2 1
 5 4 3 2 1

Have internal VRM

+3VS +1.05VS R268 @
0_0603_5%
2 1 +VCCACLK

2 1 +3VS_VCC_CLKF33 +3V_PCH
R303 0_0603_5% 1 1 R269 U4J POWER +1.05VS +5VALW +5VALW_PCH

10U_0603_6.3V6M
C231

1U_0402_6.3V6K
C232
2 1 +VCCPDSW R270
1 AD49 N26 +1.05VS_VCCUSBCORE 2 1
0_0603_5% VCCACLK VCCIO[29] R289
2 2 1
C234 P26 0_0603_5% 2 1
.1U_0402_16V7K T16 VCCIO[30] C233
D 2 VCCDSW3_3 1mA P28 1U_0402_6.3V6K D
0_0603_5%
VCCIO[31] 2
2 1 +PCH_VCCDSW V12 T27
DCPSUSBYP VCCIO[32]
C235 @ T29

烉On-Die PLL voltage regulator enable +3VS_VCC_CLKF33 T38 VCCIO[33] +3V_PCH

On-Die PLL Voltage Regulator .1U_0402_16V7K
VCC3_3[5]
H T101 65mA R272
T23 +3V_VCCPUSB 2 1
+VCCAPLL_CPY_PCH BH23 VCCSUS3_3[7]
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 VCCAPLLDMI2 80mA +5VALW_PCH

.1U_0402_16V7K
C236
T24 0_0603_5% +3V_PCH
,VCCAPLLSATA VCCSUS3_3[8] 1 +3V_PCH
2 1 +VCCDPLL_CPY AL29 R273
+1.05VS VCCIO[14]
R271 0_0603_5% V23 +3V_VCCAUBG 2 1
VCCSUS3_3[9]

USB
1

2
+VCCSUS1 AL24 V24 2 0_0603_5%
DCPSUS[3] 130mA VCCSUS3_3[10] C238 R275 D1
1
P24 .1U_0402_16V7K 10_0402_5% CH751H-40PT_SOD323-2
@ C239 VCCSUS3_3[6] 2 +1.05VS
1U_0402_6.3V6K AA19 R276

1
2 VCCASW[1] T26 +1.05VS_VCCAUPLL 2 1 +PCH_V5REF_SUS
+1.05VS AA21 VCCIO[34]
903mA VCCASW[2]

1
R277 0_0805_5% 0_0603_5%
1 2 +1.05VM_VCCASW AA24 M26 +PCH_V5REF_SUS C240
VCCASW[3] 1mA V5REF_SUS 0.1U_0402_25V6
1 1

2
22U_0805_6.3V6M
C241

22U_0805_6.3V6M
C242
AA26

Clock and Miscellaneous

VCCASW[4] AN23 +VCCA_USBSUS C243 @1
@ 2 1U_0402_6.3V6K
AA27 DCPSUS[4]
2 2 VCCASW[5] AN24 +3V_VCCPSUS 2 .1U_0402_16V7K
C316 @1
@
AA29 VCCSUS3_3[1]
VCCASW[6]
AA31 +5VS +3VS
VCCASW[7]
AC26 P34 +PCH_V5REF_RUN +3V_PCH
VCCASW[8] 1mA V5REF

2
C R278 C
1 1 1

1U_0402_6.3V6K
C244

1U_0402_6.3V6K
C245

1U_0402_6.3V6K
C246
AC27 2 1 R279 D2
VCCASW[9] N20 +3V_VCCPSUS CH751H-40PT_SOD323-2
VCCSUS3_3[2] 1 10_0402_5%
+1.05VS AC29 0_0603_5%

PCI/GPIO/LPC
2 2 2 VCCASW[10] N22 C247

1
AC31 VCCSUS3_3[3] 1U_0402_6.3V +PCH_V5REF_RUN
L5 VCCASW[11] P20 2 +3VS
VCCSUS3_3[4] 1
1 2 +1.05VS_VCCA_A_DPL AD29 R281
VCCASW[12] P22 2 1 C248
1

10UH_LB2012T100MR_20% AD31 VCCSUS3_3[5] 1U_0402_6.3V6K

VCCASW[13] 1 2
R300 C249 0_0603_5%
0_0603_5% W21 AA16 +3VS_VCCPCORE .1U_0402_16V7K
VCCASW[14] VCC3_3[1]
L6 W23 W16 2 +3VS
2

1 2 +1.05VS_VCCA_B_DPL VCCASW[15] VCC3_3[8] R282

10UH_LB2012T100MR_20% W24 T34 +3VS_VCCPPCI 2 1
VCCASW[16] VCC3_3[4]
1 1 1
220U_B2_2.5VM_R35
C250

22U_0805_6.3V6M
C186

1U_0402_6.3V6K
C251

220U_B2_2.5VM_R35
C252

22U_0805_6.3V6M
C187

1U_0402_6.3V6K
C253

1 1 1 1 W26 0_0603_5%
+ + VCCASW[17] C254
@ W29 +3VS .1U_0402_16V7K
VCCASW[18] R283 2
2 2 2 @2 2 2 W31 AJ2 +VCC3_3_2 2 1
VCCASW[19] VCC3_3[2] +1.05VS_SATA3 +1.05VS
1
W33 0_0603_5% R285
VCCASW[20] AF13 2 1
VCCIO[5] C255
2 .1U_0402_16V7K 1
+VCCRTCEXT N16 0_0603_5%
DCPRTC AH13 C257
1 VCCIO[12]
C258 1U_0402_6.3V6K
.1U_0402_16V7K +VCCAFDI_VRM Y49 167mA AH14 +1.05VS_SATA3 2
VCCVRM[4] VCCIO[13]
2
B AF14 B
2 1 +1.05VS_VCCA_A_DPL BD47 VCCIO[6]
+1.05VS VCCADPLLA 75mA AK1

SATA
R274 0_0603_5% +VCCSATAPLL T100

烉On-Die PLL voltage regulator enable

+1.05VS_VCCA_B_DPL BF47 VCCAPLLSATA
1 VCCADPLLB 75mA
+VCCAFDI_VRM On-Die PLL Voltage Regulator
C256 H
1U_0402_6.3V6K AF11 +VCCAFDI_VRM
+1.05VS_VCCDIFFCLKN +VCCDIFFCLK AF17 VCCVRM[1] +1.05VS_VCC_SATA +1.05VS
2 VCCIO[7] VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
AF33 R288
55mA AF34 VCCDIFFCLKN[1] AC16 +1.05VS_VCC_SATA 2 1 ,VCCAPLLSATA
2 1 +1.05VS_VCCDIFFCLKN AG34 VCCDIFFCLKN[2] VCCIO[2]
+1.05VS VCCDIFFCLKN[3]
R280 0_0603_5%
1 AC17 1 0_0603_5%
VCCIO[3] C261
C259 +1.05VS_SSCVCC AG33 AD17 1U_0402_6.3V6K
1U_0402_6.3V6K VCCSSC 95mA VCCIO[4]
2 2
+VCCSST V16 +1.05VS
DCPSST
1
2 1 C263
+1.05VS
R284 0_0603_5%
1 .1U_0402_16V7K +1.05VM_VCCSUS T17 T21
V19 DCPSUS[1] VCCASW[22]
C262 2 DCPSUS[2]
MISC

1U_0402_6.3V6K +V1.05S_VCCP V21

2 VCCASW[23]
CPU

@ R290 2 1 +V_CPU_IO BJ8

0_0603_5% R286 0_0603_5% V_PROC_IO 1mA T19
2 1 +1.05VM_VCCSUS VCCASW[21]
+1.05VS 1 1 1
4.7U_0603_6.3V6K
C265

.1U_0402_16V7K
C266

.1U_0402_16V7K
C267

+RTCVCC +3V_PCH
1 R287
A22 P32 +VCCSUSHDA 2 1
RTC

2 2 2 VCCRTC 10mA VCCSUSHDA

HDA

C264 @ @
1U_0402_6.3V6K
C268

.1U_0402_16V7K
C269

.1U_0402_16V7K
C270

1U_0402_6.3V6K 1 1 1 1 0_0603_5%
2 PANTHER-POINT_FCBGA989 C271
A 0.1U_0402_16V4Z A
@
2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

2011/10/27 2012/10/27 Title
Issued Date Deciphered Date PCH (8/9) PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 21 of 60
5 4 3 2 1
 5 4 3 2 1

U4I

AY4 H46
AY42 VSS[159] VSS[259] K18
AY46 VSS[160] VSS[260] K26
AY8 VSS[161] VSS[261] K39
B11 VSS[162] VSS[262] K46
D U4H B15 VSS[163] VSS[263] K7 D
H5 B19 VSS[164] VSS[264] L18
VSS[0] B23 VSS[165] VSS[265] L2
AA17 AK38 B27 VSS[166] VSS[266] L20
AA2 VSS[1] VSS[80] AK4 B31 VSS[167] VSS[267] L26
AA3 VSS[2] VSS[81] AK42 B35 VSS[168] VSS[268] L28
AA33 VSS[3] VSS[82] AK46 B39 VSS[169] VSS[269] L36
AA34 VSS[4] VSS[83] AK8 B7 VSS[170] VSS[270] L48
AB11 VSS[5] VSS[84] AL16 F45 VSS[171] VSS[271] M12
AB14 VSS[6] VSS[85] AL17 BB12 VSS[172] VSS[272] P16
AB39 VSS[7] VSS[86] AL19 BB16 VSS[173] VSS[273] M18
AB4 VSS[8] VSS[87] AL2 BB20 VSS[174] VSS[274] M22
AB43 VSS[9] VSS[88] AL21 BB22 VSS[175] VSS[275] M24
AB5 VSS[10] VSS[89] AL23 BB24 VSS[176] VSS[276] M30
AB7 VSS[11] VSS[90] AL26 BB28 VSS[177] VSS[277] M32
AC19 VSS[12] VSS[91] AL27 BB30 VSS[178] VSS[278] M34
AC2 VSS[13] VSS[92] AL31 BB38 VSS[179] VSS[279] M38
AC21 VSS[14] VSS[93] AL33 BB4 VSS[180] VSS[280] M4
AC24 VSS[15] VSS[94] AL34 BB46 VSS[181] VSS[281] M42
AC33 VSS[16] VSS[95] AL48 BC14 VSS[182] VSS[282] M46
AC34 VSS[17] VSS[96] AM11 BC18 VSS[183] VSS[283] M8
AC48 VSS[18] VSS[97] AM14 BC2 VSS[184] VSS[284] N18
AD10 VSS[19] VSS[98] AM36 BC22 VSS[185] VSS[285] P30
AD11 VSS[20] VSS[99] AM39 BC26 VSS[186] VSS[286] N47
AD12 VSS[21] VSS[100] AM43 BC32 VSS[187] VSS[287] P11
AD13 VSS[22] VSS[101] AM45 BC34 VSS[188] VSS[288] P18
AD19 VSS[23] VSS[102] AM46 BC36 VSS[189] VSS[289] T33
AD24 VSS[24] VSS[103] AM7 BC40 VSS[190] VSS[290] P40
AD26 VSS[25] VSS[104] AN2 BC42 VSS[191] VSS[291] P43
AD27 VSS[26] VSS[105] AN29 BC48 VSS[192] VSS[292] P47
AD33 VSS[27] VSS[106] AN3 BD46 VSS[193] VSS[293] P7
AD34 VSS[28] VSS[107] AN31 BD5 VSS[194] VSS[294] R2
C AD36 VSS[29] VSS[108] AP12 BE22 VSS[195] VSS[295] R48 C
AD37 VSS[30] VSS[109] AP19 BE26 VSS[196] VSS[296] T12
AD38 VSS[31] VSS[110] AP28 BE40 VSS[197] VSS[297] T31
AD39 VSS[32] VSS[111] AP30 BF10 VSS[198] VSS[298] T37
AD4 VSS[33] VSS[112] AP32 BF12 VSS[199] VSS[299] T4
AD40 VSS[34] VSS[113] AP38 BF16 VSS[200] VSS[300] W34
AD42 VSS[35] VSS[114] AP4 BF20 VSS[201] VSS[301] T46
AD43 VSS[36] VSS[115] AP42 BF22 VSS[202] VSS[302] T47
AD45 VSS[37] VSS[116] AP46 BF24 VSS[203] VSS[303] T8
AD46 VSS[38] VSS[117] AP8 BF26 VSS[204] VSS[304] V11
AD8 VSS[39] VSS[118] AR2 BF28 VSS[205] VSS[305] V17
AE2 VSS[40] VSS[119] AR48 BD3 VSS[206] VSS[306] V26
AE3 VSS[41] VSS[120] AT11 BF30 VSS[207] VSS[307] V27
AF10 VSS[42] VSS[121] AT13 BF38 VSS[208] VSS[308] V29
AF12 VSS[43] VSS[122] AT18 BF40 VSS[209] VSS[309] V31
AD14 VSS[44] VSS[123] AT22 BF8 VSS[210] VSS[310] V36
AD16 VSS[45] VSS[124] AT26 BG17 VSS[211] VSS[311] V39
AF16 VSS[46] VSS[125] AT28 BG21 VSS[212] VSS[312] V43
AF19 VSS[47] VSS[126] AT30 BG33 VSS[213] VSS[313] V7
AF24 VSS[48] VSS[127] AT32 BG44 VSS[214] VSS[314] W17
AF26 VSS[49] VSS[128] AT34 BG8 VSS[215] VSS[315] W19
AF27 VSS[50] VSS[129] AT39 BH11 VSS[216] VSS[316] W2
AF29 VSS[51] VSS[130] AT42 BH15 VSS[217] VSS[317] W27
AF31 VSS[52] VSS[131] AT46 BH17 VSS[218] VSS[318] W48
AF38 VSS[53] VSS[132] AT7 BH19 VSS[219] VSS[319] Y12
AF4 VSS[54] VSS[133] AU24 H10 VSS[220] VSS[320] Y38
AF42 VSS[55] VSS[134] AU30 BH27 VSS[221] VSS[321] Y4
AF46 VSS[56] VSS[135] AV16 BH31 VSS[222] VSS[322] Y42
AF5 VSS[57] VSS[136] AV20 BH33 VSS[223] VSS[323] Y46
AF7 VSS[58] VSS[137] AV24 BH35 VSS[224] VSS[324] Y8
AF8 VSS[59] VSS[138] AV30 BH39 VSS[225] VSS[325] BG29
AG19 VSS[60] VSS[139] AV38 BH43 VSS[226] VSS[328] N24
B AG2 VSS[61] VSS[140] AV4 BH7 VSS[227] VSS[329] AJ3 B
AG31 VSS[62] VSS[141] AV43 D3 VSS[228] VSS[330] AD47
AG48 VSS[63] VSS[142] AV8 D12 VSS[229] VSS[331] B43
AH11 VSS[64] VSS[143] AW14 D16 VSS[230] VSS[333] BE10
AH3 VSS[65] VSS[144] AW18 D18 VSS[231] VSS[334] BG41
AH36 VSS[66] VSS[145] AW2 D22 VSS[232] VSS[335] G14
AH39 VSS[67] VSS[146] AW22 D24 VSS[233] VSS[337] H16
AH40 VSS[68] VSS[147] AW26 D26 VSS[234] VSS[338] T36
AH42 VSS[69] VSS[148] AW28 D30 VSS[235] VSS[340] BG22
AH46 VSS[70] VSS[149] AW32 D32 VSS[236] VSS[342] BG24
AH7 VSS[71] VSS[150] AW34 D34 VSS[237] VSS[343] C22
AJ19 VSS[72] VSS[151] AW36 D38 VSS[238] VSS[344] AP13
AJ21 VSS[73] VSS[152] AW40 D42 VSS[239] VSS[345] M14
AJ24 VSS[74] VSS[153] AW48 D8 VSS[240] VSS[346] AP3
AJ33 VSS[75] VSS[154] AV11 E18 VSS[241] VSS[347] AP1
AJ34 VSS[76] VSS[155] AY12 E26 VSS[242] VSS[348] BE16
AK12 VSS[77] VSS[156] AY22 G18 VSS[243] VSS[349] BC16
AK3 VSS[78] VSS[157] AY28 G20 VSS[244] VSS[350] BG28
VSS[79] VSS[158] G26 VSS[245] VSS[351] BJ28
PANTHER-POINT_FCBGA989 G28 VSS[246] VSS[352]
G36 VSS[247]
G48 VSS[248]
H12 VSS[249]
H18 VSS[250]
H22 VSS[251]
H24 VSS[252]
H26 VSS[253]
H30 VSS[254]
H32 VSS[255]
H34 VSS[256]
F3 VSS[257]
VSS[258]
A A

PANTHER-POINT_FCBGA989

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (9/9) VSS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 22 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS_VGA

U65A N13P@
PCH_THRMTRIP#_R <19>

1
PCIE_CTX_GRX_N[0..15]
<5> PCIE_CTX_GRX_N[0..15]
PCIE_CTX_GRX_P0 AN12 Part 1 of 7
PEX_RX0

3
PCIE_CTX_GRX_P[0..15] PCIE_CTX_GRX_N0 AM12 P6 GPU_VID4 RV208
<5> PCIE_CTX_GRX_P[0..15] PEX_RX0_N GPIO0 GPU_VID4 <54>
PCIE_CTX_GRX_P1 AN14 M3 GPU_VID3 10K_0402_5% QV7B
PCIE_CRX_GTX_N[0..15] PEX_RX1 GPIO1 GPU_VID3 <54>
PCIE_CTX_GRX_N1 AM14 L6 N13P@ DMN66D0LDW-7 2N_SOT363-6
<5> PCIE_CRX_GTX_N[0..15]

2
PCIE_CTX_GRX_P2 AP14 PEX_RX1_N GPIO2 P5 VGA_GPIO3 0_0402_5% 1 @ 2DPRSLPVR_VGA 5 N13P@
PCIE_CRX_GTX_P[0..15] PEX_RX2 GPIO3 DPRSLPVR_VGA <54>
PCIE_CTX_GRX_N2 AP15 P7 RV113
<5> PCIE_CRX_GTX_P[0..15] PEX_RX2_N GPIO4

6
PCIE_CTX_GRX_P3 AN15 L7 GPU_VID1 QV7A
GPU_VID1 <54>

4
D PCIE_CTX_GRX_N3 AM15 PEX_RX3 GPIO5 M7 GPU_VID2 DMN66D0LDW-7 2N_SOT363-6 D
PEX_RX3_N GPIO6 GPU_VID2 <54>
PCIE_CTX_GRX_P4 AN17 N8 N13P@
PCIE_CTX_GRX_N4 AM17 PEX_RX4 GPIO7 M1 OVERT# 2
PCIE_CTX_GRX_P5 AP17 PEX_RX4_N GPIO8 M2 GC6_EVENT#_R
PCIE_CTX_GRX_N5 AP18 PEX_RX5 GPIO9 L1

1
PCIE_CTX_GRX_P6 AN18 PEX_RX5_N GPIO10 M5 GPU_VID0 N13P@

GPIO
PEX_RX6 GPIO11 GPU_VID0 <54>
PCIE_CTX_GRX_N6 AM18 N3 VGA_GPIO12 2 1
PEX_RX6_N GPIO12 VGA_AC_DET <42,54>
PCIE_CTX_GRX_P7 AN20 M4 GPU_VID5 DV3
PEX_RX7 GPIO13 GPU_VID5 <54>
PCIE_CTX_GRX_N7 AM20 N4 CH751H-40PT_SOD323-2
PCIE_CTX_GRX_P8 AP20 PEX_RX7_N GPIO14 P2 VGA_GPIO15 100K_0402_5% 1 @ 2 RV17
PCIE_CTX_GRX_N8 AP21 PEX_RX8 GPIO15 R8 VGA_GPIO16 0_0402_5% 1 @ 2 RV114 DPRSLPVR_VGA
PCIE_CTX_GRX_P9 AN21 PEX_RX8_N GPIO16 M6
PCIE_CTX_GRX_N9 AM21 PEX_RX9 GPIO17 R1 0_0402_5% 1 @ 2PSI#_VGA
PEX_RX9_N GPIO18 PSI#_VGA <54>
PCIE_CTX_GRX_P10 AN23 P3 RV233
PCIE_CTX_GRX_N10 AM23 PEX_RX10 GPIO19 P4
PCIE_CTX_GRX_P11 AP23 PEX_RX10_N GPIO20 P1
PCIE_CTX_GRX_N11 AP24 PEX_RX11 GPIO21 if GC6 is supported, stuff the BOM option to
PCIE_CTX_GRX_P12 AN24 PEX_RX11_N pull high to 3.3vs system power, if not, stuff
PCIE_CTX_GRX_N12 AM24 PEX_RX12 the BOM option to pull high to NV3V3;
+3VS_VGA PCIE_CTX_GRX_P13 AN26 PEX_RX12_N
PCIE_CTX_GRX_N13 AM26 PEX_RX13
+3VS_VGA PCIE_CTX_GRX_P14 AP26 PEX_RX13_N +3VS_VGA
PCIE_CTX_GRX_N14 AP27 PEX_RX14
PEX_RX14_N
2

PCIE_CTX_GRX_P15 AN27 AK9

RV24 RV25 PCIE_CTX_GRX_N15 AM27 PEX_RX15 DACA_RED AL10 GC6_EVENT#_R 1 N13P@ 2
2.2K_0402_5% 2.2K_0402_5% 12/07 update to SE124224K80 PEX_RX15_N DACA_GREEN
DACA_BLUE
AL9 RV49 10K_0402_5%
N13P@ N13P@ VGA_EDID_CLK 1 N13P@ 2

DACs
5

PCIE_CRX_GTX_P0 CV6 N13P@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P0 AK14 RV3 2.2K_0402_5%

1

QV1B PCIE_CRX_GTX_N0 CV7 N13P@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N0 AJ14 PEX_TX0 AM9 VGA_EDID_DATA 1 N13P@ 2
VGA_SMB_CK2 4 3 PCIE_CRX_GTX_P1 CV8 N13P@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P1 AH14 PEX_TX0_N DACA_HSYNC AN9 RV4 2.2K_0402_5%
EC_SMB_CK2 <15,39,42> PEX_TX1 DACA_VSYNC
PCIE_CRX_GTX_N1 CV9 N13P@ 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N1 AG14 VGA_CRT_DATA 1 N13P@ 2
2N7002DW-T/R7_SOT363-6 PCIE_CRX_GTX_P2 CV10 N13P@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P2 AK15 PEX_TX1_N 10K_0402_5% RV10 2.2K_0402_5%
C N13P@ PCIE_CRX_GTX_N2 CV11 N13P@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N2 AJ15 PEX_TX2 AG10 +DACA_VDD 2 RV107 1 VGA_CRT_CLK 1 N13P@ 2 C
PEX_TX2_N DACA_VDD

PCI EXPRESS
PCIE_CRX_GTX_P3 CV12 N13P@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P3 AL16 AP9 RV11 2.2K_0402_5%
PCIE_CRX_GTX_N3 CV13 N13P@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N3 AK16 PEX_TX3 DACA_VREF AP8 I2CB_SCL 1 N13P@ 2
PCIE_CRX_GTX_P4 CV15 N13P@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P4 AK17 PEX_TX3_N DACA_RSET RV12 2.2K_0402_5%
PEX_TX4 N13P@
2

PCIE_CRX_GTX_N4 CV17 N13P@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N4 AJ17 I2CB_SDA 1 N13P@ 2

QV1A PCIE_CRX_GTX_P5 CV19 N13P@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P5 AH17 PEX_TX4_N RV13 2.2K_0402_5%
VGA_SMB_DA2 1 6 PCIE_CRX_GTX_N5 CV14 N13P@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N5 AG17 PEX_TX5 OVERT# 1 N13P@ 2
EC_SMB_DA2 <15,39,42> PEX_TX5_N
PCIE_CRX_GTX_P6 CV16 N13P@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P6 AK18 RV1 10K_0402_5%
2N7002DW-T/R7_SOT363-6 PCIE_CRX_GTX_N6 CV18 N13P@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N6 AJ18 PEX_TX6 VGA_GPIO12 1 N13P@ 2
N13P@ PCIE_CRX_GTX_P7 CV20 N13P@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P7 AL19 PEX_TX6_N RV2 10K_0402_5%
PCIE_CRX_GTX_N7 CV22 N13P@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N7 AK19 PEX_TX7 R4 VGA_CRT_CLK
PCIE_CRX_GTX_P8 CV24 N13P@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P8 AK20 PEX_TX7_N I2CA_SCL R5 VGA_CRT_DATA
PCIE_CRX_GTX_N8 CV26 N13P@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N8 AJ20 PEX_TX8 I2CA_SDA
PCIE_CRX_GTX_P9 CV21 N13P@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P9 AH20 PEX_TX8_N R7 I2CB_SCL
PCIE_CRX_GTX_N9 CV23 N13P@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N9 AG20 PEX_TX9 I2CB_SCL R6 I2CB_SDA
PCIE_CRX_GTX_P10 CV25 N13P@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P10 AK21 PEX_TX9_N I2CB_SDA

I2C
PCIE_CRX_GTX_N10 CV27 N13P@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N10 AJ21 PEX_TX10 R2 VGA_EDID_CLK
PCIE_CRX_GTX_P11 CV29 N13P@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P11 AL22 PEX_TX10_N I2CC_SCL R3 VGA_EDID_DATA
PCIE_CRX_GTX_N11 CV31 N13P@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N11 AK22 PEX_TX11 I2CC_SDA +1.05VS_VGA
PCIE_CRX_GTX_P12 CV33 N13P@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P12 AK23 PEX_TX11_N T4 VGA_SMB_CK2
PCIE_CRX_GTX_N12 CV28 N13P@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N12 AJ23 PEX_TX12 I2CS_SCL T3 VGA_SMB_DA2
PEX_TX12_N I2CS_SDA 30 ohms @100MHz (ESR=0.05)
PCIE_CRX_GTX_P13 CV30 N13P@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P13 AH23
PCIE_CRX_GTX_N13 CV32 N13P@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N13 AG23 PEX_TX13 LV7
PCIE_CRX_GTX_P14 CV36 N13P@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P14 AK24 PEX_TX13_N 60mA +PLLVDD 1 2
PCIE_CRX_GTX_N14 CV41 N13P@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N14 AJ24 PEX_TX14 FBMA-10-100505-300T 0402

22U_0805_6.3V6M
.1U_0402_16V7K
CV34 N13P@1 2 AL25 PEX_TX14_N

N13P@ CV131
PCIE_CRX_GTX_P15 0.22U_0402_10V6K PCIE_CRX_C_GTX_P15 1 1 N13P@
CV35 N13P@1 2 AK25 PEX_TX15

N13P@ CV40
PCIE_CRX_GTX_N15 0.22U_0402_10V6K PCIE_CRX_C_GTX_N15
+3VS_VGA +3VS_VGA PEX_TX15_N
AD8 RV112 1 @ 2
AJ11 PLLVDD 0_0402_5% 2 2 Near GPU
PEX_WAKE_N AE8
45mA
CLK_PCIE_VGA AL13 SP_PLLVDD
<15> CLK_PCIE_VGA PEX_REFCLK 45mA
2

B @ CLK_PCIE_VGA# AK13 AD7 +SP_PLLVDD B

<15> CLK_PCIE_VGA# PEX_REFCLK_N VID_PLLVDD
RV105 CLK_REQ_GPU# AK12

CLK
10K_0402_5% PEX_CLKREQ_N N13P@
Differential signal 1 @ 2 PEX_TSTCLK_OUT AJ26 H3 XTALIN_R 1 2 XTALIN
PEX_TSTCLK_OUT XTAL_IN
5

RV20 200_0402_1% PEX_TSTCLK_OUT# AK26 H2 XTAL_OUT RV230 0_0402_5%

1

2 PEX_TSTCLK_OUT_N XTAL_OUT 1 2 GCLK_27MHZ

P

<18,36,37,42,45> PLT_RST# B GCLK_27MHZ <36>

4 PLT_RST_VGA# AJ12 J4 XTALOUT RV231 0_0402_5%
1 Y PEX_TERMP AP29 PEX_RST_N XTAL_OUTBUFF H1 XTALSSIN GCLK274@
<18> DGPU_HOLD_RST# A PEX_TERMP XTAL_SSIN
G

Under GPU
1

1
3

N13P@ UV2 RV18 RV26 RV27

2

NC7SZ08P5X_NL_SC70-5 100K_0402_5% 10K_0402_5% 10K_0402_5%

N13P@ RV22 N13P@ N13P@
2.49K_0402_1% N13P-PES-A1_FCBGA908
2

2
N13P@
1

1 2
RV23 10M_0402_5% Under GPU(below 150mils)
<18,25> DGPU_PWR_EN N13P@
N13P@
150mA
YV1 +1.05VS_VGA 1 2 +SP_PLLVDD
2

4 3 XTAL_OUT LV1

22U_0805_6.3V6M

.1U_0402_16V7K

.1U_0402_16V7K
4.7U_0402_6.3V6M
+3VS_VGA NC OSC

N13P@ CV4

N13P@ CV5
N13P@ CV112

N13P@ CV113
BLM18PG330SN1D_0603 1 1 1 1
RV29 XTALIN 1 2 180ohms (ESR=0.2) Bead
10K_0402_5% OSC NC
N13P@ 1 27MHZ 16PF +-30PPM X3G027000FG1H-HX 1
1

CV42 CV37 N13P@ CV38 2 2 2 2

2 1 RV30 18P_0402_50V8J 18P_0402_50V8J
N13P@ 10K_0402_5% N13P@ N13P@
2

.1U_0402_16V7K N13P@ 2 2
G

A 1 3 CLK_REQ_GPU# A
<15> CLK_REQ_VGA#
D

QV2 N13P@
2N7002H 1N_SOT23-3 @ RV32
10K_0402_5%

1 2
Security Classification Compal Secret Data Compal Electronics, Inc.
1

RV110 @ 0_0402_5%
Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13X-PCIE/DAC/GPIO
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 23 of 60
5 4 3 2 1
 5 4 3 2 1

U65D

Part 4 of 7
AM6
AN6 IFPA_TXC P8
AP3 IFPA_TXC_N NC AC6
AN3 IFPA_TXD0 NC AJ28
AN5 IFPA_TXD0_N NC AJ4
AM5 IFPA_TXD1 NC AJ5
AL6 IFPA_TXD1_N NC AL11
AK6 IFPA_TXD2 NC C15
IFPA_TXD2_N NC

NC
AJ6 D19
AH6 IFPA_TXD3 NC D20
D IFPA_TXD3_N NC D23 D
NC D26
AJ9 NC H31
AH9 IFPB_TXC NC T8
AP6 IFPB_TXC_N NC V32
AP5 IFPB_TXD4 NC
AM7 IFPB_TXD4_N
AL7 IFPB_TXD5
AN8 IFPB_TXD5_N
AM8 IFPB_TXD6
AK8 IFPB_TXD6_N
AL8 IFPB_TXD7
IFPB_TXD7_N L4 VCCSENSE_VGA
VDD_SENSE VCCSENSE_VGA <54>
AK1
AJ1 IFPC_L0
AJ3 IFPC_L0_N L5 VSSSENSE_VGA
IFPC_L1 GND_SENSE VSSSENSE_VGA <54>
AJ2
AH3 IFPC_L1_N
IFPC_L2 trace width: 16mils
AH4
AG5 IFPC_L2_N differential voltage sensing.
AG4 IFPC_L3
IFPC_L3_N differential signal routing.
TEST
AM1 AK11 TESTMODE
AM2 IFPD_L0 TESTMODE
AM3 IFPD_L0_N AM10
IFPD_L1 JTAG_TCK TV2

1
AM4 AM11
IFPD_L1_N JTAG_TDI TV3
AL3 AP12
IFPD_L2 JTAG_TDO TV4 10K_0402_5%
C AL4 AP11 C
IFPD_L2_N JTAG_TMS TV5
AK4 AN11 1 2 RV33
AK5 IFPD_L3 JTAG_TRST_N RV34 10K_0402_5% N13P@

2
IFPD_L3_N

LVDS/TMDS
N13P@
AD2
AD3 IFPE_L0
AD1 IFPE_L0_N
AC1 IFPE_L1 SERIAL
AC2 IFPE_L1_N H6 ROM_CS
AC3 IFPE_L2 ROM_CS_N H4 ROM_SCLK
IFPE_L2_N ROM_SCLK ROM_SCLK <32>
AC4 H5 ROM_SI ROM_SI <32>
AC5 IFPE_L3 ROM_SI H7 ROM_SO
IFPE_L3_N ROM_SO ROM_SO <32>

AE3
AE4 IFPF_L0
AF4 IFPF_L0_N
AF5 IFPF_L1 +3VS_VGA
AD4 IFPF_L1_N GENERAL RV35 10K_0402_5%
AD5 IFPF_L2 L2 2 1
AG1 IFPF_L2_N BUFRST_N N13P@ RV232 10K_0402_5%
AF1 IFPF_L3 L3 NV_CEC 2 1
IFPF_L3_N CEC N13P@
J1 1 N13P@ 2
MULTI_STRAP_REF0_GND RV38 40.2K_0402_1%
AG3
AG2 IFPC_AUX_I2CW _SCL
IFPC_AUX_I2CW _SDA_N J2 STRAP0
STRAP0 STRAP0 <32>
J7 STRAP1
B STRAP1 STRAP1 <32> B
AK3 J6 STRAP2 STRAP2 <32>
AK2 IFPD_AUX_I2CX_SCL STRAP2 J5 STRAP3
IFPD_AUX_I2CX_SDA_N STRAP3 STRAP3 <32>
J3 STRAP4 STRAP4 <32>
STRAP4
AB3
AB4 IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N K3
THERMDP K4
AF3 THERMDN
AF2 IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N
Reserve 1MB SPI ROM FOR VBIOS ROM
+3VS_VGA
CV295
N13P-PES-A1_FCBGA908
2 1 20mils
N13P@

1
0.1U_0402_16V4Z
@ RV229 @ @ RV225
10K_0402_5% 10K_0402_5%

2
@ RV224
@RV224 0_0402_5% UV15 @
ROM_CS 1 2 ROM_CS_R 1 8
ROM_SO 1 2 ROM_SO_R 2 CS# VCC 7 ROM_HOLD#
@RV226
@ RV226 0_0402_5% 3 DO HOLD# 6
4 W P# CLK 5 @ RV228 0_0402_5%
GND DIO ROM_SCLK_R 1 2 ROM_SCLK
A MX25L1005AMC-12G SOP ROM_SI_R 1 2 ROM_SI A
@ RV227 0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13X-LVDS/HDMI/DP/THM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 24 of 60
5 4 3 2 1
 5 4 3 2 1

+1.5VS_VGA U65E
Near GPU
Near GPU Part 5 of 7 2000mA +1.05VS_VGA
3.5A
D AA27 AG19 N13P@ D
FBVDDQ_0 PEX_IOVDD_0

22U_0805_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
CV273

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
AA30 AG21
FBVDDQ_1 PEX_IOVDD_1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
CV269

CV270

CV271

CV272

CV43

CV44

CV45

CV46

CV47

CV48

CV49

CV50

CV51

CV52
1 2 2 2 2 AB27 AG22 1 1 1 1 1 1 2 2 2 2
AB33 FBVDDQ_2 PEX_IOVDD_2 AG24
AC27 FBVDDQ_3 PEX_IOVDD_3 AH21
@ AD27 FBVDDQ_4 PEX_IOVDD_4 AH25 N13P@
2 1 1 1 1 AE27 FBVDDQ_5 PEX_IOVDD_5 2 2 2 2 2 2 1 1 1 1
N13P@ AF27 FBVDDQ_6
+1.5VS_VGA AG27 FBVDDQ_7 AG13 N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@
N13P@ N13P@ N13P@ B13 FBVDDQ_8 PEX_IOVDDQ_0 AG15
4.7uF X7R 0402 * 2 FBVDDQ_9 PEX_IOVDDQ_1 Under GPU(below 150mils) +1.05VS_VGA
B16 AG16
FBVDDQ_10 PEX_IOVDDQ_2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
Under GPU(below 150mils) B19 AG18
FBVDDQ_11 PEX_IOVDDQ_3

CV54

CV53

CV56

CV55
1uF X7R 0402 * 2 0.1uF X7R 0402 * 8 E13 AG25 1 1 1 1
E16 FBVDDQ_12 PEX_IOVDDQ_4 AH15
FBVDDQ_13 PEX_IOVDDQ_5
.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
E19 AH18
FBVDDQ_14 PEX_IOVDDQ_6
1U_0402_6.3V6K

1U_0402_6.3V6K
CV267

CV268

CV277

CV278

CV279

CV280

CV292

CV287

CV294

CV284

CV285

CV286
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1 1 1 1 1 1 1 1 1 1 1 1 H10 AH26
H11 FBVDDQ_15 PEX_IOVDDQ_7 AH27 2 2 2 2
H12 FBVDDQ_16 PEX_IOVDDQ_8 AJ27
H13 FBVDDQ_17 PEX_IOVDDQ_9 AK27
2 2 2 2 2 2 2 2 2 2 2 2 H14 FBVDDQ_18 PEX_IOVDDQ_10 AL27 N13P@ N13P@ N13P@ N13P@

POWER
H15 FBVDDQ_19 PEX_IOVDDQ_11 AM28
N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ H16 FBVDDQ_20 PEX_IOVDDQ_12 AN28
FBVDDQ_21 PEX_IOVDDQ_13 Under GPU(below 150mils)
H18
H19 FBVDDQ_22 +3VS_VGA
H20 FBVDDQ_23
FBVDDQ_24

.1U_0402_16V7K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
N13P@ H21 AH12 +PEX_PLLHVDD RV138 1 @ 2 0_0402_5%
FBVDDQ_25 PEX_PLL_HVDD

CV70

CV74

CV73
H22 1 1 1
H23 FBVDDQ_26
H24 FBVDDQ_27
H8 FBVDDQ_28 AG12 +PEX_SVDD3V3
H9 FBVDDQ_29 PEX_SVDD_3V3 2 2 2
rise 1.5v system source voltage to 1.55-1.57V L27 FBVDDQ_30
FBVDDQ_31
N13P@ N13P@ N13P@ Place near balls +1.05VS_VGA
M27 LV2 N13P@
N27 FBVDDQ_32 AG26 +PEX_PLLVDD +PEX_PLLVDD 120mA 2 1
FBVDDQ_33 PEX_PLLVDD

.1U_0402_16V7K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
P27
C FBVDDQ_34 C

CV65

CV66
CV3
R27 1 1 1 BLM18PG121SN1D_0603
T27 FBVDDQ_35
FBVDDQ_36 +3VS_VGA
120ohms @100MHz (ESR=0.18)
T30 J8
T33 FBVDDQ_37 VDD33_0 K8
FBVDDQ_38 VDD33_1 Place near balls Place near GPU 2 2 2
V27 L8 RV5
W27 FBVDDQ_39 VDD33_2 M8 +VDD33 2 1 N13P@
FBVDDQ_40 VDD33_3

.1U_0402_16V7K

.1U_0402_16V7K

4.7U_0603_6.3V6K
W30 N13P@ N13P@
+1.5VS_VGA FBVDDQ_41

1U_0402_6.3V6K
CV109

CV111

CV293

CV75
W33 1 1 1 1 0_0603_5%
Y27 FBVDDQ_42 N13P@
FBVDDQ_43 AH8 +IFPAB_PLLVDD1 RV40 2 10K_0402_5%
IFPAB_PLLVDD AJ8 RV48 1 @ 2 1K_0402_1%
IFPAB_RSET 2 2 2 2
Place near balls
2 RV141 @1 FB_VDDQ_SENSE
10_0402_5% AG8 +IFPAB_IOVDD 1 RV65 2 10K_0402_5% N13P@ +VDD33
@ IFPA_IOVDD AG9 N13P@ N13P@ N13P@ N13P@
IFPB_IOVDD Inc 2pcs 0.1u

.1U_0402_16V7K

.1U_0402_16V7K
2 RV142 1 FB_VSS_SENSE F1
FB_VDDQ_SENSE following DG

CV303

N13P@ CV304
10_0402_5% N13P@ 1 1
AF7 +IFPC_PLLVDD 1 RV42 2 10K_0402_5%
+1.5VS_VGA IFPC_PLLVDD

N13P@
F2 AF8 RV43 2 @ 1 1K_0402_1%
FB_GND_SENSE IFPC_RSET
AF6 +IFPC_IOVDD 1 RV44 2 10K_0402_5% 2 2
1 2 J27 IFPC_IOVDD
RV6 N13P@ 40.2_0402_1% FB_CAL_PD_VDDQ
CALIBRATION PIN DDR3 AG7 +IFPD_PLLVDD 1
N13P@
RV45 2 10K_0402_5%
1 2 H27 IFPD_PLLVDD AN2 RV46 1 @ 2 1K_0402_1%
RV8 N13P@ 42.2_0402_1% FB_CAL_PU_GND IFPD_RSET
FB_CAL_x_PD_VDDQ 40.2Ohm AG6 +IFPD_IOVDD 1
N13P@
RV47 2 10K_0402_5%
1 2 H25 IFPD_IOVDD
RV9 N13P@ 51.1_0402_1% FB_CAL_TERM_GND
FB_CAL_x_PU_GND 42.2Ohm AB8 +IFPEF_PLLVDD1
N13P@
RV72 2 10K_0402_5%
IFPEF_PLVDD AD6 1 RV50 2 1K_0402_1%
IFPEF_RSET
FB_CAL_xTERM_GND 51.1Ohm Place near balls AC7
N13P@
N13P@
IFPE_IOVDD AC8 +IFPE_IOVDD1 RV73 2 10K_0402_5%
IFPF_IOVDD
B N13P@ B

+3VS to +3VS_VGA
N13P-PES-A1_FCBGA908

N13P@ +3VS +3VS_VGA

J10
@
1 2
1 2

JUMP_43X79
+5VALW
QV5 CV57
LP2301ALT1G_SOT23 10U_0603_6.3V6M

D
R1109 @ N13P@ 3 1 2 1
0_0402_5% R1103 N13P@

1
2 1 100K_0402_5%
<10,42,46,51,52,53,54> SUSP#
N13P@

G
2

2
RV205 RV206
DGPU_PWR_EN# 1 2 470_0603_5%
10K_0402_5% @

1 2
1
D

CV241
R1104 N13P@ 1 D

.1U_0402_16V7K
2 1 2 Q128 RV207 @
<18,23> DGPU_PWR_EN
G 2N7002_SOT23 2 2 1 DGPU_PWR_EN#
0_0402_5% S N13P@ QV6 @ G

3
2
N13P@ S 10K_0402_5%

3
1
2N7002_SOT23

R1105

.1U_0402_16V7K
CV242
100K_0402_5% 1
N13P@

2
A A
@
2

Security Classification
2011/10/27
Compal Secret Data
2012/10/27 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13X-POWER
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 25 of 60
5 4 3 2 1
 5 4 3 2 1

U65F

Part 6 of 7
A2 D2
AA17 GND_0 GND_100 D31
AA18 GND_1 GND_101 D33
AA20 GND_2 GND_102 E10 U65G +VGA_CORE
AA22 GND_3 GND_103 E22 +VGA_CORE
AB12 GND_4 GND_104 E25
AB14 GND_5 GND_105 E5 Part 7 of 7 V17
AB16 GND_6 GND_106 E7 AA12 VDD_56 V18
AB19 GND_7 GND_107 F28 AA14 VDD_0 VDD_57 V20
AB2 GND_8 GND_108 F7 AA16 VDD_1 VDD_58 V22
AB21 GND_9 GND_109 G10 AA19 VDD_2 VDD_59 W 12
D
A33 GND_10 GND_110 G13 AA21 VDD_3 VDD_60 W 14 D
AB23 GND_11 GND_111 G16 AA23 VDD_4 VDD_61 W 16
AB28 GND_12 GND_112 G19 AB13 VDD_5 VDD_62 W 19
AB30 GND_13 GND_113 G2 AB15 VDD_6 VDD_63 W 21
AB32 GND_14 GND_114 G22 AB17 VDD_7 VDD_64 W 23
AB5 GND_15 GND_115 G25 AB18 VDD_8 VDD_65 Y13
AB7 GND_16 GND_116 G28 AB20 VDD_9 VDD_66 Y15
AC13 GND_17 GND_117 G3 AB22 VDD_10 VDD_67 Y17
AC15 GND_18 GND_118 G30 AC12 VDD_11 VDD_68 Y18
AC17 GND_19 GND_119 G32 AC14 VDD_12 VDD_69 Y20
AC18 GND_20 GND_120 G33 AC16 VDD_13 VDD_70 Y22
AA13 GND_21 GND_121 G5 AC19 VDD_14 VDD_71
AC20 GND_22 GND_122 G7 AC21 VDD_15
AC22 GND_23 GND_123 K2 AC23 VDD_16 U1
AE2 GND_24 GND_124 K28 M12 VDD_17 XVDD_1 U2
AE28 GND_25 GND_125 K30 M14 VDD_18 XVDD_2 U3
GND_26 GND_126 VDD_19 XVDD_3

POWER
AE30 K32 M16 U4
AE32 GND_27 GND_127 K33 M19 VDD_20 XVDD_4 U5
AE33 GND_28 GND_128 K5 M21 VDD_21 XVDD_5 U6
AE5 GND_29 GND_129 K7 M23 VDD_22 XVDD_6 U7
AE7 GND_30 GND_130 M13 N13 VDD_23 XVDD_7 U8
AH10 GND_31 GND_131 M15 N15 VDD_24 XVDD_8
AA15 GND_32 GND_132 M17 N17 VDD_25
AH13 GND_33 GND_133 M18 N18 VDD_26 V1
AH16 GND_34 GND_134 M20 N20 VDD_27 XVDD_9 V2
AH19 GND_35 GND_135 M22 N22 VDD_28 XVDD_10 V3
AH2 GND_36 GND_136 N12 P12 VDD_29 XVDD_11 V4
AH22 GND_37 GND_137 N14 P14 VDD_30 XVDD_12 V5
AH24 GND_38 GND_138 N16 P16 VDD_31 XVDD_13 V6
C AH28 GND_39 GND_139 N19 P19 VDD_32 XVDD_14 V7 C
AH29 GND_40 GND_140 N2 P21 VDD_33 XVDD_15 V8
AH30 GND_41 GND_141 N21 P23 VDD_34 XVDD_16
AH32 GND_42 GND_142 N23 R13 VDD_35
GND
AH33 GND_43 GND_143 N28 R15 VDD_36 W2
AH5 GND_44 GND_144 N30 R17 VDD_37 XVDD_17 W3
AH7 GND_45 GND_145 N32 R18 VDD_38 XVDD_18 W4
AJ7 GND_46 GND_146 N33 R20 VDD_39 XVDD_19 W5
AK10 GND_47 GND_147 N5 R22 VDD_40 XVDD_20 W7
AK7 GND_48 GND_148 N7 T12 VDD_41 XVDD_21 W8
AL12 GND_49 GND_149 P13 T14 VDD_42 XVDD_22
AL14 GND_50 GND_150 P15 T16 VDD_43
AL15 GND_51 GND_151 P17 T19 VDD_44 Y1
AL17 GND_52 GND_152 P18 T21 VDD_45 XVDD_23 Y2
AL18 GND_53 GND_153 P20 T23 VDD_46 XVDD_24 Y3
AL2 GND_54 GND_154 P22 U13 VDD_47 XVDD_25 Y4
AL20 GND_55 GND_155 R12 U15 VDD_48 XVDD_26 Y5
AL21 GND_56 GND_156 R14 U17 VDD_49 XVDD_27 Y6
AL23 GND_57 GND_157 R16 U18 VDD_50 XVDD_28 Y7
AL24 GND_58 GND_158 R19 U20 VDD_51 XVDD_29 Y8
AL26 GND_59 GND_159 R21 U22 VDD_52 XVDD_30
AL28 GND_60 GND_160 R23 V13 VDD_53
AL30 GND_61 GND_161 T13 V15 VDD_54 AA1
AL32 GND_62 GND_162 T15 VDD_55 XVDD_31 AA2
AL33 GND_63 GND_163 T17 XVDD_32 AA3
AL5 GND_64 GND_164 T18 XVDD_33 AA4
AM13 GND_65 GND_165 T2 XVDD_34 AA5
AM16 GND_66 GND_166 T20 XVDD_35 AA6
AM19 GND_67 GND_167 T22 XVDD_36 AA7
AM22 GND_68 GND_168 AG11 XVDD_37 AA8
B
AM25 GND_69 GND_169 T28 XVDD_38 B
AN1 GND_70 GND_170 T32
AN10 GND_71 GND_171 T5
AN13 GND_72 GND_172 T7
AN16 GND_73 GND_173 U12 N13P-PES-A1_FCBGA908
AN19 GND_74 GND_174 U14
AN22 GND_75 GND_175 U16
GND_76 GND_176 N13P@
AN25 U19
AN30 GND_77 GND_177 U21
AN34 GND_78 GND_178 U23
AN4 GND_79 GND_179 V12
AN7 GND_80 GND_180 V14
AP2 GND_81 GND_181 V16
AP33 GND_82 GND_182 V19
B1 GND_83 GND_183 V21
B10 GND_84 GND_184 V23
B22 GND_85 GND_185 W 13
B25 GND_86 GND_186 W 15
B28 GND_87 GND_187 W 17
B31 GND_88 GND_188 W 18
B34 GND_89 GND_189 W 20
B4 GND_90 GND_190 W 22
B7 GND_91 GND_191 W 28
C10 GND_92 GND_192 Y12
C13 GND_93 GND_193 Y14
C19 GND_94 GND_194 Y16
C22 GND_95 GND_195 Y19
C25 GND_96 GND_196 Y21
C28 GND_97 GND_197 Y23
C7 GND_98 GND_198 AH11
A A
GND_99 GND_199 C16
GND_OPT W 32
GND_OPT

N13P-PES-A1_FCBGA908 Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title
N13P@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13-VGA CORE, GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 26 of 60
5 4 3 2 1
 5 4 3 2 1

FBA_D[0..63] FBA_MA[15..0] <28,29> FBC_D[0..63] FBC_MA[15..0] <30,31>

<28,29> FBA_D[0..63] <30,31> FBC_D[0..63]
FBA_BA[2..0] <28,29> FBC_BA[2..0] <30,31>

U65C
U65B
Part 3 of 7
Part 2 of 7 FBC_D0 G9 D13 FBC_CS0#_L
FBB_D0 FBB_CMD0 FBC_CS0#_L <30>
FBA_D0 L28 U30 FBA_CS0#_L FBC_D1 E9 E14
FBA_D0 FBA_CMD0 FBA_CS0#_L <28> FBB_D1 FBB_CMD1
FBA_D1 M29 T31 FBC_D2 G8 F14 FBC_ODT_L
FBA_D1 FBA_CMD1 FBB_D2 FBB_CMD2 FBC_ODT_L <30>
FBA_D2 L29 U29 FBA_ODT_L FBC_D3 F9 A12 FBC_CKE_L
FBA_D2 FBA_CMD2 FBA_ODT_L <28> FBB_D3 FBB_CMD3 FBC_CKE_L <30>
FBA_D3 M28 R34 FBA_CKE_L FBC_D4 F11 B12 FBC_MA14
FBA_D3 FBA_CMD3 FBA_CKE_L <28> FBB_D4 FBB_CMD4
FBA_D4 N31 R33 FBA_MA14 FBC_D5 G11 C14 FBC_RST#
D FBA_D4 FBA_CMD4 FBB_D5 FBB_CMD5 FBC_RST# <30,31> D
FBA_D5 P29 U32 FBA_RST# FBC_D6 F12 B14 FBC_MA9
FBA_D5 FBA_CMD5 FBA_RST# <28,29> FBB_D6 FBB_CMD6
FBA_D6 R29 U33 FBA_MA9 FBC_D7 G12 G15 FBC_MA7
FBA_D7 P28 FBA_D6 FBA_CMD6 U28 FBA_MA7 FBC_D8 G6 FBB_D7 FBB_CMD7 F15 FBC_MA2
FBA_D8 J28 FBA_D7 FBA_CMD7 V28 FBA_MA2 FBC_D9 F5 FBB_D8 FBB_CMD8 E15 FBC_MA0
FBA_D9 H29 FBA_D8 FBA_CMD8 V29 FBA_MA0 FBC_D10 E6 FBB_D9 FBB_CMD9 D15 FBC_MA4
FBA_D10 J29 FBA_D9 FBA_CMD9 V30 FBA_MA4 FBC_D11 F6 FBB_D10 FBB_CMD10 A14 FBC_MA1
FBA_D11 H28 FBA_D10 FBA_CMD10 U34 FBA_MA1 FBC_D12 F4 FBB_D11 FBB_CMD11 D14 FBC_BA0
FBA_D12 G29 FBA_D11 FBA_CMD11 U31 FBA_BA0 FBC_D13 G4 FBB_D12 FBB_CMD12 A15 FBC_WE#
FBA_D12 FBA_CMD12 FBB_D13 FBB_CMD13 FBC_WE# <30,31>
FBA_D13 E31 V34 FBA_WE# FBC_D14 E2 B15 FBC_MA15
FBA_D13 FBA_CMD13 FBA_WE# <28,29> FBB_D14 FBB_CMD14
FBA_D14 E32 V33 FBA_MA15 FBC_D15 F3 C17 FBC_CAS#
FBA_D14 FBA_CMD14 FBB_D15 FBB_CMD15 FBC_CAS# <30,31>
FBA_D15 F30 Y32 FBA_CAS# FBC_D16 C2 D18 FBC_CS0#_H
FBA_D15 FBA_CMD15 FBA_CAS# <28,29> FBB_D16 FBB_CMD16 FBC_CS0#_H <31>
FBA_D16 C34 AA31 FBA_CS0#_H FBC_D17 D4 E18
FBA_D16 FBA_CMD16 FBA_CS0#_H <29> FBB_D17 FBB_CMD17
FBA_D17 D32 AA29 FBC_D18 D3 F18 FBC_ODT_H
FBA_D17 FBA_CMD17 FBB_D18 FBB_CMD18 FBC_ODT_H <31>
FBA_D18 B33 AA28 FBA_ODT_H FBC_D19 C1 A20 FBC_CKE_H
FBA_D18 FBA_CMD18 FBA_ODT_H <29> FBB_D19 FBB_CMD19 FBC_CKE_H <31>
FBA_D19 C33 AC34 FBA_CKE_H FBC_D20 B3 B20 FBC_MA13
FBA_D19 FBA_CMD19 FBA_CKE_H <29> FBB_D20 FBB_CMD20
FBA_D20 F33 AC33 FBA_MA13 FBC_D21 C4 C18 FBC_MA8
FBA_D21 F32 FBA_D20 FBA_CMD20 AA32 FBA_MA8 FBC_D22 B5 FBB_D21 FBB_CMD21 B18 FBC_MA6
FBA_D22 H33 FBA_D21 FBA_CMD21 AA33 FBA_MA6 FBC_D23 C5 FBB_D22 FBB_CMD22 G18 FBC_MA11
FBA_D23 H32 FBA_D22
FBA_D23
FBA_CMD22
FBA_CMD23
Y28 FBA_MA11 FBC_D24 A11 FBB_D23
FBB_D24
FBB_CMD23
FBB_CMD24
G17 FBC_MA5 Mode D - Mirror Mode Mapping
MEMORY INTERFACE

FBA_D24 P34 Y29 FBA_MA5 FBC_D25 C11 F17 FBC_MA3

MEMORY INTERFACE B
FBA_D25 P32 FBA_D24 FBA_CMD24 W31 FBA_MA3 FBC_D26 D11 FBB_D25 FBB_CMD25 D16 FBC_BA2
FBA_D26 P31 FBA_D25 FBA_CMD25 Y30 FBA_BA2 FBC_D27 B11 FBB_D26 FBB_CMD26 A18 FBC_BA1
FBA_D27 P33 FBA_D26 FBA_CMD26 AA34 FBA_BA1 FBC_D28 D8 FBB_D27 FBB_CMD27 D17 FBC_MA12
FBA_D27 FBA_CMD27 FBB_D28 FBB_CMD28 DATA Bus
FBA_D28 L31 Y31 FBA_MA12 FBC_D29 A8 A17 FBC_MA10
FBA_D29 L34 FBA_D28 FBA_CMD28 Y34 FBA_MA10 FBC_D30 C8 FBB_D29 FBB_CMD29 B17 FBC_RAS# Address
FBA_D29 FBA_CMD29 FBB_D30 FBB_CMD30 FBC_RAS# <30,31> 0..31 32..63
FBA_D30 L32 Y33 FBA_RAS# FBC_D31 B8 E17
FBA_D30 FBA_CMD30 FBA_RAS# <28,29> FBB_D31 FBB_CMD31
FBA_D31 L33 V31 FBC_D32 F24 FBx_CMD0 CS0#_L
FBA_D32 AG28 FBA_D31 FBA_CMD31 FBC_D33 G23 FBB_D32
FBA_D33 AF29 FBA_D32 FBC_D34 E24 FBB_D33
FBA_D33 FBB_D34 FBx_CMD1
FBA_D34 AG29 FBC_D35 G24 C12
FBA_D35 AF28 FBA_D34 R32 FBC_D36 D21 FBB_D35 FBB_CMD_RFU0 C20
FBA_D35 FBA_CMD_RFU0 FBB_D36 FBB_CMD_RFU1 FBx_CMD2 ODT_L
FBA_D36 AD30 AC32 FBC_D37 E21
C FBA_D37 AD29 FBA_D36 FBA_CMD_RFU1 +1.5VS_VGA FBC_D38 G21 FBB_D37 +1.5VS_VGA C
FBA_D37 FBB_D38 FBx_CMD3 CKE_L
FBA_D38 AC29 FBC_D39 F21
FBA_D39 AD28 FBA_D38 FBC_D40 G27 FBB_D39 G14 RV60 1 @ 2 60.4_0402_1%
FBA_D39 FBB_D40 FBB_DEBUG0 FBx_CMD4 A14 A14
A

FBA_D40 AJ29 R28 RV58 1 @ 2 60.4_0402_1% FBC_D41 D27 G20 RV61 1 @ 2 60.4_0402_1%
FBA_D41 AK29 FBA_D40 FBA_DEBUG0 AC28 RV59 1 @ 2 60.4_0402_1% FBC_D42 G26 FBB_D41 FBB_DEBUG1
FBA_D41 FBA_DEBUG1 FBB_D42 can be unstuff by default FBx_CMD5 RST RST
FBA_D42 AJ30 can be unstuff by default FBC_D43 E27
FBA_D43 AK28 FBA_D42 FBC_D44 E29 FBB_D43
FBA_D43 FBB_D44 FBx_CMD6 A9 A9
FBA_D44 AM29 FBC_D45 F29 D12 FBC_CLK0
FBA_D44 FBB_D45 FBB_CLK0 FBC_CLK0 <30>
FBA_D45 AM31 R30 FBA_CLK0 FBC_D46 E30 E12 FBC_CLK0# FBx_CMD7 A7 A7
FBA_D45 FBA_CLK0 FBA_CLK0 <28> FBB_D46 FBB_CLK0_N FBC_CLK0# <30>
FBA_D46 AN29 R31 FBA_CLK0# FBC_D47 D30 E20 FBC_CLK1
FBA_D46 FBA_CLK0_N FBA_CLK0# <28> FBB_D47 FBB_CLK1 FBC_CLK1 <31>
FBA_D47 AM30 AB31 FBA_CLK1 FBC_D48 A32 F20 FBC_CLK1# FBx_CMD8 A2 A2
FBA_D47 FBA_CLK1 FBA_CLK1 <29> FBB_D48 FBB_CLK1_N FBC_CLK1# <31>
FBA_D48 AN31 AC31 FBA_CLK1# FBC_D49 C31
FBA_D48 FBA_CLK1_N FBA_CLK1# <29> FBB_D49
FBA_D49 AN32 FBC_D50 C32 FBx_CMD9 A0 A0
FBA_D50 AP30 FBA_D49 FBC_D51 B32 FBB_D50
FBA_D51 AP32 FBA_D50 FBC_D52 D29 FBB_D51 F8
FBA_D51 FBB_D52 FBB_WCK01 FBx_CMD10 A4 A4
FBA_D52 AM33 K31 FBC_D53 A29 E8
AL31 FBA_D52 FBA_WCK01 L30 C29 FBB_D53 FBB_WCK01_N A5
FBA_D53
FBA_D53 FBA_WCK01_N
FBC_D54
FBB_D54 FBB_WCK23 FBx_CMD11 A1 A1
FBA_D54 AK33 H34 FBC_D55 B29 A6
FBA_D55 AK32 FBA_D54 FBA_WCK23 J34 FBC_D56 B21 FBB_D55 FBB_WCK23_N D24
FBA_D55 FBA_WCK23_N FBB_D56 FBB_WCK45 FBx_CMD12 BA0 BA0
FBA_D56 AD34 AG30 FBC_D57 C23 D25
FBA_D57 AD32 FBA_D56 FBA_WCK45 AG31 FBC_D58 A21 FBB_D57 FBB_WCK45_N B27
FBA_D57 FBA_WCK45_N FBB_D58 FBB_WCK67 FBx_CMD13 WE# WE#
FBA_D58 AC30 AJ34 FBC_D59 C21 C27
FBA_D59 AD33 FBA_D58 FBA_WCK67 AK34 FBC_D60 B24 FBB_D59 FBB_WCK67_N
FBA_D59 FBA_WCK67_N FBB_D60 FBx_CMD14 A15 A15
FBA_D60 AF31 FBC_D61 C24
FBA_D61 AG34 FBA_D60 +1.05VS_VGA +FB_PLLAVDD FBC_D62 B26 FBB_D61
FBA_D61 FBB_D62 FBx_CMD15 CAS# CAS#
FBA_D62 AG32 Place close to BGA FBC_D63 C26 D6
FBA_D63 AG33 FBA_D62 J30 FBB_D63 FBB_WCKB01 D7
FBA_D63 FBA_WCKB01 200mA FBB_WCKB01_N FBx_CMD16 CS0#_H
J31 BLM18PG330SN1D_0603 FBC_DQM0 E11 C6
FBA_DQM0 P30 FBA_WCKB01_N J32 1 2 +FB_PLLAVDD FBC_DQM1 E3 FBB_DQM0 FBB_WCKB23 B6
FBA_DQM0 FBA_WCKB23 FBB_DQM1 FBB_WCKB23_N FBx_CMD17
FBA_DQM1 F31 J33 LV3 FBC_DQM2 A3 F26
FBA_DQM2 F34 FBA_DQM1 FBA_WCKB23_N AH31 FBC_DQM3 C9 FBB_DQM2 FBB_WCKB45 E26
FBA_DQM2 FBA_WCKB45 FBB_DQM3 FBB_WCKB45_N FBx_CMD18 ODT_H
FBA_DQM3 M32 AJ31 N13P@ FBC_DQM4 F23 A26
B FBA_DQM4 AD31 FBA_DQM3 FBA_WCKB45_N AJ32 FBC_DQM5 F27 FBB_DQM4 FBB_WCKB67 A27 B
FBA_DQM4 FBA_WCKB67 FBB_DQM5 FBB_WCKB67_N FBx_CMD19 CKE_H
FBA_DQM5 AL29 AJ33 FBC_DQM6 C30
FBA_DQM6 AM32 FBA_DQM5 FBA_WCKB67_N FBC_DQM7 A24 FBB_DQM6
FBA_DQM6 FBB_DQM7 FBx_CMD20 A13 A13
FBA_DQM7 AF34
FBA_DQM7 RV66 10K_0402_5% FBC_DQS0 D10
FBB_DQS_WP0 FBx_CMD21 A8 A8
FBA_DQS0 M31 E1 FB_CLAMP 2 @ 1 FBC_DQS1 D5
FBA_DQS1 G31 FBA_DQS_WP0 FB_CLAMP FBC_DQS2 C3 FBB_DQS_WP1
FBA_DQS_WP1 +FB_PLLAVDD FBB_DQS_WP2 FBx_CMD22 A6 A6
FBA_DQS2 E33 FBC_DQS3 B9
FBA_DQS3 M33 FBA_DQS_WP2 CV106 .1U_0402_16V7K FBC_DQS4 E23 FBB_DQS_WP3 H17
FBA_DQS_WP3 FBB_DQS_WP4 FBB_PLL_AVDD +FB_PLLAVDD FBx_CMD23 A11 A11
FBA_DQS4 AE31 K27 1 2 FBC_DQS5 E28

.1U_0402_16V7K
FBA_DQS_WP4 FB_DLL_AVDD FBB_DQS_WP5

CV108
FBA_DQS5 AK30 N13P@ FBC_DQS6 B30 1 FBx_CMD24 A5 A5
FBA_DQS6 AN33 FBA_DQS_WP5 FBC_DQS7 A23 FBB_DQS_WP6
FBA_DQS_WP6
Place close to ball FBB_DQS_WP7
FBA_DQS7 AF33 FBx_CMD25 A3 A3
FBA_DQS_WP7 U27 FBC_DQS#0 D9
FBA_PLL_AVDD +FB_PLLAVDD FBB_DQS_RN0 2
FBA_DQS#0 M30 FBC_DQS#1 E4 FBx_CMD26 BA2 BA2
22U_0805_6.3V6M
.1U_0402_16V7K

FBA_DQS_RN0 FBB_DQS_RN1
CV107

CV110

FBA_DQS#1 H30 FBC_DQS#2 B2 N13P@

1U_0402_6.3V6K

FBA_DQS_RN1 1 1 1 FBB_DQS_RN2
CV39

FBA_DQS#2 E34 FBC_DQS#3 A9 FBx_CMD27 BA1 BA1

FBA_DQS#3 M34 FBA_DQS_RN2 H26 FBC_DQS#4 D22 FBB_DQS_RN3
FBA_DQS#4 AF30 FBA_DQS_RN3 FB_VREF FBC_DQS#5 D28 FBB_DQS_RN4
FBA_DQS_RN4 2 2 2 FBB_DQS_RN5
Place close to ball FBx_CMD28 A12 A12
FBA_DQS#5 AK31 FBC_DQS#6 A30
FBA_DQS#6 AM34 FBA_DQS_RN5 N13P@ N13P@ N13P@ FBC_DQS#7 B23 FBB_DQS_RN6
FBA_DQS_RN6 FBB_DQS_RN7 FBx_CMD29 A10 A10
FBA_DQS#7 AF32
FBA_DQS_RN7
FBx_CMD30 RAS# RAS#
Place close to ball Place close to BGA
N13P-PES-A1_FCBGA908 N13P@
N13P-PES-A1_FCBGA908 N13P@

<30,31> FBC_DQM[7..0]
<28,29> FBA_DQM[7..0] <30,31> FBC_DQS[7..0]
A <28,29> FBA_DQS[7..0] <30,31> FBC_DQS#[7..0] A
<28,29> FBA_DQS#[7..0] 30ohms (ESR=0.01) Bead
P/N;SM010007W00

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13X-MEM Interface
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 27 of 60
5 4 3 2 1
 5 4 3 2 1

FBA_D[0..63] <27,29>
Memory Partition A - Lower 32 bits FBA_MA[15..0] <27,29>

FBA_BA[2..0] <27,29>
UV3 UV4
FBA_DQM[7..0] <27,29>
+1.5VS_VGA +FBA_VREF0 M8 E3 FBA_D4 +FBA_VREF0 M8 E3 FBA_D19
VREFCA DQL0 VREFCA DQL0 FBA_DQS[7..0] <27,29>
D
H1 F7 FBA_D1 H1 F7 FBA_D20 D
VREFDQ DQL1 F2 FBA_D7 VREFDQ DQL1 F2 FBA_D17
DQL2 DQL2 FBA_DQS#[7..0] <27,29>
1

FBA_MA0 N3 F8 FBA_D0 FBA_MA0 N3 F8 FBA_D21 Group2 (IN1)

RV79 FBA_MA1 P7 A0 DQL3 H3 FBA_D6 FBA_MA1 P7 A0 DQL3 H3 FBA_D16
A1 DQL4 Group0 (IN3) A1 DQL4
FBA_MA2 P3 H8 FBA_D3 FBA_MA2 P3 H8 FBA_D23
1.1K_0402_1% FBA_MA3 N2 A2
A3
DQL5
DQL6
G2 FBA_D5 FBA_MA3 N2 A2
A3
DQL5
DQL6
G2 FBA_D18 Mode D - Mirror Mode Mapping
N13P@ FBA_MA4 P8 H7 FBA_D2 FBA_MA4 P8 H7 FBA_D22
2

+FBA_VREF0 FBA_MA5 P2 A4 DQL7 FBA_MA5 P2 A4 DQL7

FBA_MA6 R8 A5 FBA_MA6 R8 A5
A6 A6 DATA Bus
1

CV118

FBA_MA7 R2 D7 FBA_D29 FBA_MA7 R2 D7 FBA_D10

0.01U_0402_16V7K

1 A7 DQU0 A7 DQU0
RV68 FBA_MA8 T8 C3 FBA_D25 FBA_MA8 T8 C3 FBA_D15 Address 0..31 32..63
FBA_MA9 R3 A8 DQU1 C8 FBA_D28 FBA_MA9 R3 A8 DQU1 C8 FBA_D8
1.1K_0402_1% FBA_MA10 L7 A9 DQU2 C2 FBA_D26 FBA_MA10 L7 A9 DQU2 C2 FBA_D13
2 A10/AP DQU3 A10/AP DQU3 Group1 (TOP) FBx_CMD0 CS0#_L
FBA_MA11 R7 A7 FBA_D31 Group3 (BOT) FBA_MA11 R7 A7 FBA_D9
2

N13P@ FBA_MA12 N7 A11 DQU4 A2 FBA_D24 FBA_MA12 N7 A11 DQU4 A2 FBA_D12

A12 DQU5 A12 DQU5 FBx_CMD1
FBA_MA13 T3 B8 FBA_D30 FBA_MA13 T3 B8 FBA_D11
N13P@ FBA_MA14 T7 A13 DQU6 A3 FBA_D27 FBA_MA14 T7 A13 DQU6 A3 FBA_D14
A14 DQU7 A14 DQU7 FBx_CMD2 ODT_L
FBA_MA15 M7 FBA_MA15 M7
A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA
FBx_CMD3 CKE_L
FBA_BA0 M2 B2 FBA_BA0 M2 B2 FBx_CMD4 A14 A14
FBA_BA1 N8 BA0 VDD D9 FBA_BA1 N8 BA0 VDD D9
FBA_CLK0 FBA_BA2 M3 BA1 VDD G7 FBA_BA2 M3 BA1 VDD G7
BA2 VDD BA2 VDD FBx_CMD5 RST RST
K2 K2
VDD K8 VDD K8
VDD VDD FBx_CMD6 A9 A9
2

N1 N1
RV80 FBA_CLK0 J7 VDD N9 FBA_CLK0 J7 VDD N9
<27> FBA_CLK0 CK VDD CK VDD FBx_CMD7 A7 A7
C 160_0402_1% FBA_CLK0# K7 R1 FBA_CLK0# K7 R1 C
<27> FBA_CLK0# CK VDD CK VDD
N13P@ FBA_CKE_L K9 R9 FBA_CKE_L K9 R9 FBx_CMD8 A2 A2
<27> FBA_CKE_L CKE/CKE0 VDD CKE/CKE0 VDD
1

FBx_CMD9 A0 A0
FBA_CLK0# FBA_ODT_L K1 A1 FBA_ODT_L K1 A1
<27> FBA_ODT_L ODT/ODT0 VDDQ ODT/ODT0 VDDQ
FBA_CS0#_L L2 A8 FBA_CS0#_L L2 A8 FBx_CMD10 A4 A4
<27> FBA_CS0#_L CS/CS0 VDDQ CS/CS0 VDDQ
FBA_RAS# J3 C1 FBA_RAS# J3 C1
<27,29> FBA_RAS# RAS VDDQ RAS VDDQ
FBA_CAS# K3 C9 FBA_CAS# K3 C9 FBA_ODT_L FBx_CMD11 A1 A1
<27,29> FBA_CAS# CAS VDDQ CAS VDDQ
FBA_WE# L3 D2 FBA_WE# L3 D2
<27,29> FBA_WE# WE VDDQ WE VDDQ
E9 E9 FBx_CMD12 BA0 BA0
VDDQ F1 VDDQ F1 FBA_CKE_L
FBA_DQS0 F3 VDDQ H2 FBA_DQS2 F3 VDDQ H2
DQSL VDDQ DQSL VDDQ FBx_CMD13 WE# WE#
FBA_DQS3 C7 H9 FBA_DQS1 C7 H9
DQSU VDDQ DQSU VDDQ

2
FBx_CMD14 A15 A15
RV67 RV76
FBA_DQM0 E7 A9 FBA_DQM2 E7 A9 10K_0402_5% 10K_0402_5% FBx_CMD15 CAS# CAS#
FBA_DQM3 D3 DML VSS B3 FBA_DQM1 D3 DML VSS B3 N13P@ N13P@
DMU VSS E1 DMU VSS E1 FBx_CMD16 CS0#_H

1
VSS G8 VSS G8
FBA_DQS#0 G3 VSS J2 FBA_DQS#2 G3 VSS J2
DQSL VSS DQSL VSS FBx_CMD17
FBA_DQS#3 B7 J8 FBA_DQS#1 B7 J8
DQSU VSS M1 DQSU VSS M1
VSS VSS FBx_CMD18 ODT_H
M9 M9
VSS P1 VSS P1
VSS VSS FBx_CMD19 CKE_H
FBA_RST# T2 P9 FBA_RST# T2 P9
<27,29> FBA_RST# RESET VSS RESET VSS
T1 T1 FBx_CMD20 A13 A13
L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
B FBx_CMD21 A8 A8 B
1

1
J1 B1 J1 B1 FBx_CMD22 A6 A6
NC/ODT1 VSSQ NC/ODT1 VSSQ
1

RV78 RV77 L1 B9 RV69 L1 B9

10K_0402_5% J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1
243_0402_1% NC/CE1 VSSQ 243_0402_1% NC/CE1 VSSQ FBx_CMD23 A11 A11
N13P@ N13P@ L9 D8 N13P@ L9 D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 FBx_CMD24 A5 A5
2

2
VSSQ E8 VSSQ E8
2

VSSQ F9 VSSQ F9
VSSQ VSSQ FBx_CMD25 A3 A3
G1 G1
VSSQ G9 VSSQ G9
VSSQ VSSQ FBx_CMD26 BA2 BA2
96-BALL 96-BALL FBx_CMD27 BA1 BA1
SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96 FBx_CMD28 A12 A12
X76@ X76@
FBx_CMD29 A10 A10
+1.5VS_VGA UV3 SIDE +1.5VS_VGA UV4 SIDE FBx_CMD30 RAS# RAS#
.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
CV119

CV120

CV121

CV123

CV162

CV161

CV159

CV134

CV129

CV160

CV133

CV132

CV164

CV136

CV163

CV137

CV135

CV157

CV155

CV138

CV142

CV143

CV144

CV158
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

@ @ @ @ @ @ @
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2011/10/27 Deciphered Date 2012/10/27

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13X-VRAM A Lower
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 28 of 60
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Upper 32 FBA_D[0..63] <27,28>

bits UV5 UV6

FBA_MA[15..0] <27,28>
+1.5VS_VGA
FBA_BA[2..0] <27,28>
+FBA_VREF1 M8 E3 FBA_D36 +FBA_VREF1 M8 E3 FBA_D63
H1 VREFCA DQL0 F7 FBA_D34 H1 VREFCA DQL0 F7 FBA_D58
VREFDQ DQL1 VREFDQ DQL1 FBA_DQM[7..0] <27,28>
1 F2 FBA_D37 F2 FBA_D60
RV70 FBA_MA0 N3 DQL2 F8 FBA_D35 FBA_MA0 N3 DQL2 F8 FBA_D59
A0 DQL3 A0 DQL3 FBA_DQS[7..0] <27,28>
D FBA_MA1 P7 H3 FBA_D39 Group4 (IN1) FBA_MA1 P7 H3 FBA_D61 Group7 (IN3) D
1.1K_0402_1% FBA_MA2 P3 A1 DQL4 H8 FBA_D32 FBA_MA2 P3 A1 DQL4 H8 FBA_D56
A2 DQL5 A2 DQL5 FBA_DQS#[7..0] <27,28>
N13P@ FBA_MA3 N2 G2 FBA_D38 FBA_MA3 N2 G2 FBA_D62
2

+FBA_VREF1 FBA_MA4 P8 A3 DQL6 H7 FBA_D33 FBA_MA4 P8 A3 DQL6 H7 FBA_D57

FBA_MA5 P2 A4 DQL7 FBA_MA5 P2 A4 DQL7
A5 A5 Mode D - Mirror Mode Mapping
1

CV178
FBA_MA6 R8 FBA_MA6 R8
0.01U_0402_16V7K

1 A6 A6
RV82 FBA_MA7 R2 D7 FBA_D45 FBA_MA7 R2 D7 FBA_D55
FBA_MA8 T8 A7 DQU0 C3 FBA_D42 FBA_MA8 T8 A7 DQU0 C3 FBA_D51
1.1K_0402_1% N13P@ FBA_MA9 R3 A8 DQU1 C8 FBA_D46 FBA_MA9 R3 A8 DQU1 C8 FBA_D54
2 A9 DQU2 A9 DQU2 DATA Bus
N13P@ FBA_MA10 L7 C2 FBA_D41 Group5 (TOP) FBA_MA10 L7 C2 FBA_D49
2

FBA_MA11 R7 A10/AP DQU3 A7 FBA_D47 FBA_MA11 R7 A10/AP DQU3 A7 FBA_D52 Address

A11 DQU4 A11 DQU4 Group6 (BOT) 0..31 32..63
FBA_MA12 N7 A2 FBA_D43 FBA_MA12 N7 A2 FBA_D50
FBA_MA13 T3 A12 DQU5 B8 FBA_D44 FBA_MA13 T3 A12 DQU5 B8 FBA_D53
A13 DQU6 A13 DQU6 FBx_CMD0 CS0#_L
FBA_MA14 T7 A3 FBA_D40 FBA_MA14 T7 A3 FBA_D48
FBA_MA15 M7 A14 DQU7 FBA_MA15 M7 A14 DQU7
A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA
FBx_CMD1
FBx_CMD2 ODT_L
FBA_BA0 M2 B2 FBA_BA0 M2 B2
FBA_BA1 N8 BA0 VDD D9 FBA_BA1 N8 BA0 VDD D9
BA1 VDD BA1 VDD FBx_CMD3 CKE_L
FBA_CLK1 FBA_BA2 M3 G7 FBA_BA2 M3 G7
BA2 VDD K2 BA2 VDD K2
VDD VDD FBx_CMD4 A14 A14
K8 K8
VDD VDD
2

N1 N1 FBx_CMD5 RST RST

RV83 FBA_CLK1 J7 VDD N9 FBA_CLK1 J7 VDD N9
<27> FBA_CLK1 CK VDD CK VDD
160_0402_1% FBA_CLK1# K7 R1 FBA_CLK1# K7 R1 FBx_CMD6 A9 A9
<27> FBA_CLK1# CK VDD CK VDD
N13P@ FBA_CKE_H K9 R9 FBA_CKE_H K9 R9
<27> FBA_CKE_H CKE/CKE0 VDD CKE/CKE0 VDD
FBx_CMD7 A7 A7
1

C C
FBA_CLK1# FBA_ODT_H K1 A1 FBA_ODT_H K1 A1 FBx_CMD8 A2 A2
<27> FBA_ODT_H ODT/ODT0 VDDQ ODT/ODT0 VDDQ
FBA_CS0#_H L2 A8 FBA_CS0#_H L2 A8
<27> FBA_CS0#_H CS/CS0 VDDQ CS/CS0 VDDQ
FBA_RAS# J3 C1 FBA_RAS# J3 C1 FBx_CMD9 A0 A0
<27,28> FBA_RAS# RAS VDDQ RAS VDDQ
FBA_CAS# K3 C9 FBA_CAS# K3 C9
<27,28> FBA_CAS# CAS VDDQ CAS VDDQ
FBA_WE# L3 D2 FBA_WE# L3 D2 FBx_CMD10 A4 A4
<27,28> FBA_WE# WE VDDQ WE VDDQ
E9 E9
VDDQ F1 VDDQ F1
VDDQ VDDQ FBx_CMD11 A1 A1
FBA_DQS4 F3 H2 FBA_DQS7 F3 H2
FBA_DQS5 C7 DQSL VDDQ H9 FBA_DQS6 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ FBx_CMD12 BA0 BA0
FBx_CMD13 WE# WE#
FBA_DQM4 E7 A9 FBA_DQM7 E7 A9
FBA_DQM5 D3 DML VSS B3 FBA_DQM6 D3 DML VSS B3
DMU VSS DMU VSS FBx_CMD14 A15 A15
E1 E1
VSS G8 VSS G8
VSS VSS FBx_CMD15 CAS# CAS#
FBA_DQS#4 G3 J2 FBA_DQS#7 G3 J2
FBA_DQS#5 B7 DQSL VSS J8 FBA_DQS#6 B7 DQSL VSS J8
DQSU VSS DQSU VSS FBx_CMD16 CS0#_H
M1 M1
FBA_CKE_H VSS M9 VSS M9
VSS VSS FBx_CMD17
P1 P1
FBA_RST# T2 VSS P9 FBA_RST# T2 VSS P9
<27,28> FBA_RST# RESET VSS RESET VSS FBx_CMD18 ODT_H
FBA_ODT_H T1 T1
L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS FBx_CMD19 CKE_H
FBx_CMD20 A13 A13
1

1
RV84 RV87 J1 B1 J1 B1
10K_0402_5% 10K_0402_5% RV86 L1 NC/ODT1 VSSQ B9 RV85 L1 NC/ODT1 VSSQ B9
B NC/CS1 VSSQ NC/CS1 VSSQ FBx_CMD21 A8 A8 B
N13P@ N13P@ 243_0402_1% J9 D1 243_0402_1% J9 D1
N13P@ L9 NC/CE1 VSSQ D8 N13P@ L9 NC/CE1 VSSQ D8
NCZQ1 VSSQ NCZQ1 VSSQ FBx_CMD22 A6 A6
E2 E2
2

2
VSSQ E8 VSSQ E8
VSSQ VSSQ FBx_CMD23 A11 A11
F9 F9
VSSQ G1 VSSQ G1
VSSQ VSSQ FBx_CMD24 A5 A5
G9 G9
VSSQ VSSQ
FBx_CMD25 A3 A3
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD26 BA2 BA2
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
X76@ X76@ FBx_CMD27 BA1 BA1
FBx_CMD28 A12 A12
+1.5VS_VGA UV5 SIDE +1.5VS_VGA UV6 SIDE
FBx_CMD29 A10 A10
FBx_CMD30 RAS# RAS#
.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
CV145

CV174

CV296

CV301

CV291

CV302

CV299

CV290

CV300

CV297

CV298

CV165

CV177

CV170

CV166

CV172

CV179

CV173

CV169

CV180

CV167

CV171

CV168

CV175
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

@ @ @ @ @ @ @
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@

A A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2011/10/27 Deciphered Date 2012/10/27

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13X-VRAM A Upper
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 29 of 60
5 4 3 2 1
 5 4 3 2 1

FBC_D[0..63] <27,31>
Memory Partition C - Lower 32 bits FBC_MA[15..0] <27,31>

FBC_BA[2..0] <27,31>

FBC_DQM[7..0] <27,31>
+1.5VS_VGA UV7 UV8
FBC_DQS[7..0] <27,31>
+FBB_VREF0 M8 E3 FBC_D4 +FBB_VREF0 M8 E3 FBC_D16
VREFCA DQL0 VREFCA DQL0 FBC_DQS#[7..0] <27,31>
1
D
H1 F7 FBC_D3 H1 F7 FBC_D21 D
RV111 VREFDQ DQL1 F2 FBC_D7 VREFDQ DQL1 F2 FBC_D18
FBC_MA0 N3 DQL2 F8 FBC_D0 N3 DQL2 F8
A0 DQL3 Group0 (IN3)FBC_MA0 A0 DQL3
FBC_D17
1.1K_0402_1% FBC_MA1 P7 H3 FBC_D5 FBC_MA1 P7 H3 FBC_D20 Group2 (IN1)
N13P@ FBC_MA2 P3 A1 DQL4 H8 FBC_D1 FBC_MA2 P3 A1 DQL4 H8 FBC_D23 Mode D - Mirror Mode Mapping
2

+FBB_VREF0 FBC_MA3 N2 A2 DQL5 G2 FBC_D6 FBC_MA3 N2 A2 DQL5 G2 FBC_D19

FBC_MA4 P8 A3 DQL6 H7 FBC_D2 FBC_MA4 P8 A3 DQL6 H7 FBC_D22
A4 DQL7 A4 DQL7
1

CV202

FBC_MA5 P2 FBC_MA5 P2 DATA Bus

0.01U_0402_16V7K

1 A5 A5
RV115 FBC_MA6 R8 FBC_MA6 R8
FBC_MA7 R2 A6 D7 FBC_D28 FBC_MA7 R2 A6 D7 FBC_D8 Address
A7 DQU0 A7 DQU0 0..31 32..63
1.1K_0402_1% FBC_MA8 T8 C3 FBC_D27 FBC_MA8 T8 C3 FBC_D15
N13P@ 2 FBC_MA9 R3 A8 DQU1 C8 FBC_D31 FBC_MA9 R3 A8 DQU1 C8 FBC_D11 FBx_CMD0 CS0#_L
2

N13P@ FBC_MA10 L7 A9 DQU2 C2 FBC_D25 FBC_MA10 L7 A9 DQU2 C2 FBC_D12

FBC_MA11 R7 A10/AP DQU3 A7 FBC_D29 R7 A10/AP DQU3 A7
A11 DQU4 Group3 (BOT)FBC_MA11 A11 DQU4
FBC_D9 Group1 (TOP) FBx_CMD1
FBC_MA12 N7 A2 FBC_D24 FBC_MA12 N7 A2 FBC_D13
FBC_MA13 T3 A12 DQU5 B8 FBC_D30 FBC_MA13 T3 A12 DQU5 B8 FBC_D10
A13 DQU6 A13 DQU6 FBx_CMD2 ODT_L
FBC_MA14 T7 A3 FBC_D26 FBC_MA14 T7 A3 FBC_D14
FBC_MA15 M7 A14 DQU7 FBC_MA15 M7 A14 DQU7
A15/BA3 A15/BA3 FBx_CMD3 CKE_L
+1.5VS_VGA +1.5VS_VGA
FBx_CMD4 A14 A14
FBC_BA0 M2 B2 FBC_BA0 M2 B2
FBC_BA1 N8 BA0 VDD D9 FBC_BA1 N8 BA0 VDD D9
BA1 VDD BA1 VDD FBx_CMD5 RST RST
FBC_CLK0 FBC_BA2 M3 G7 FBC_BA2 M3 G7
BA2 VDD K2 BA2 VDD K2
VDD VDD FBx_CMD6 A9 A9
K8 K8
VDD VDD
2

310mA N1 N1 FBx_CMD7 A7 A7
RV89 FBC_CLK0 J7 VDD N9 FBC_CLK0 J7 VDD N9
<27> FBC_CLK0 CK VDD CK VDD
C 160_0402_1% FBC_CLK0# K7 R1 FBC_CLK0# K7 R1 FBx_CMD8 A2 A2 C
<27> FBC_CLK0# CK VDD CK VDD
N13P@ FBC_CKE_L K9 R9 FBC_CKE_L K9 R9
<27> FBC_CKE_L CKE/CKE0 VDD CKE/CKE0 VDD
FBx_CMD9 A0 A0
1

FBC_CLK0# FBC_ODT_L K1 A1 FBC_ODT_L K1 A1 FBx_CMD10 A4 A4

<27> FBC_ODT_L ODT/ODT0 VDDQ ODT/ODT0 VDDQ
FBC_CS0#_L L2 A8 FBC_CS0#_L L2 A8
<27> FBC_CS0#_L CS/CS0 VDDQ CS/CS0 VDDQ
FBC_RAS# J3 C1 FBC_RAS# J3 C1 FBx_CMD11 A1 A1
<27,31> FBC_RAS# RAS VDDQ RAS VDDQ
FBC_CAS# K3 C9 FBC_CAS# K3 C9
<27,31> FBC_CAS# CAS VDDQ CAS VDDQ
FBC_WE# L3 D2 FBC_WE# L3 D2 FBx_CMD12 BA0 BA0
<27,31> FBC_WE# WE VDDQ WE VDDQ
E9 E9
VDDQ F1 VDDQ F1
VDDQ VDDQ FBx_CMD13 WE# WE#
FBC_DQS0 F3 H2 FBC_DQS2 F3 H2 FBC_ODT_L
FBC_DQS3 C7 DQSL VDDQ H9 FBC_DQS1 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ FBx_CMD14 A15 A15
FBC_CKE_L FBx_CMD15 CAS# CAS#
FBC_DQM0 E7 A9 FBC_DQM2 E7 A9
FBC_DQM3 D3 DML VSS B3 FBC_DQM1 D3 DML VSS B3
DMU VSS DMU VSS FBx_CMD16 CS0#_H
E1 E1
VSS VSS

1
G8 G8 RV117 RV116 FBx_CMD17
FBC_DQS#0 G3 VSS J2 FBC_DQS#2 G3 VSS J2 10K_0402_5% 10K_0402_5%
FBC_DQS#3 B7 DQSL VSS J8 FBC_DQS#1 B7 DQSL VSS J8 N13P@ N13P@
DQSU VSS DQSU VSS FBx_CMD18 ODT_H
M1 M1
VSS M9 VSS M9
VSS VSS FBx_CMD19 CKE_H

2
P1 P1
FBC_RST# T2 VSS P9 FBC_RST# T2 VSS P9
<27,31> FBC_RST# RESET VSS RESET VSS FBx_CMD20 A13 A13
T1 T1
L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS FBx_CMD21 A8 A8
B B
FBx_CMD22 A6 A6
1

1
J1 B1 J1 B1
NC/ODT1 VSSQ NC/ODT1 VSSQ
1

RV91 RV90 L1 B9 RV88 L1 B9 FBx_CMD23 A11 A11

10K_0402_5% J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1
243_0402_1% NC/CE1 VSSQ 243_0402_1% NC/CE1 VSSQ
N13P@ N13P@ L9 D8 N13P@ L9 D8 FBx_CMD24 A5 A5
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
2

2
VSSQ E8 VSSQ E8 FBx_CMD25 A3 A3
2

VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ VSSQ FBx_CMD26 BA2 BA2
G9 G9
VSSQ VSSQ
FBx_CMD27 BA1 BA1
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD28 A12 A12
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
X76@ X76@ FBx_CMD29 A10 A10
FBx_CMD30 RAS# RAS#
+1.5VS_VGA UV7 SIDE +1.5VS_VGA UV8 SIDE
.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
CV191

CV183

CV199

CV189

CV205

CV188

CV190

CV206

CV181

CV182

CV185

CV194

CV192

CV203

CV195

CV184

CV197

CV186

CV187

CV198

CV200

CV201

CV204

CV193
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

@ @ @ @ @ @ @
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ A
N13P@ N13P@ N13P@ N13P@ N13P@

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2011/10/27 Deciphered Date 2012/10/27

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13X-VRAM C Lower
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 30 of 60
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Upper 32 bits FBC_D[0..63] <27,30>

FBC_MA[15..0] <27,30>

FBC_BA[2..0] <27,30>
UV9 UV10

+1.5VS_VGA FBC_DQM[7..0] <27,30>

+FBB_VREF1 M8 E3 FBC_D39 +FBB_VREF1 M8 E3 FBC_D60
H1 VREFCA DQL0 F7 FBC_D33 H1 VREFCA DQL0 F7 FBC_D57
VREFDQ DQL1 VREFDQ DQL1 FBC_DQS[7..0] <27,30>
D
F2 FBC_D38 F2 FBC_D63 D
1 FBC_MA0 N3 DQL2 F8 FBC_D32 FBC_MA0 N3 DQL2 F8 FBC_D58
A0 DQL3 A0 DQL3 FBC_DQS#[7..0] <27,30>
RV120 FBC_MA1 P7 H3 FBC_D36 Group4 (IN1) FBC_MA1 P7 H3 FBC_D61 Group7 (IN3)
FBC_MA2 P3 A1 DQL4 H8 FBC_D35 FBC_MA2 P3 A1 DQL4 H8 FBC_D56
1.1K_0402_1% FBC_MA3 N2 A2 DQL5 G2 FBC_D37 FBC_MA3 N2 A2 DQL5 G2 FBC_D62
N13P@ FBC_MA4 P8 A3 DQL6 H7 FBC_D34 FBC_MA4 P8 A3 DQL6 H7 FBC_D59
Mode D - Mirror Mode Mapping
2

+FBB_VREF1 FBC_MA5 P2 A4 DQL7 FBC_MA5 P2 A4 DQL7

FBC_MA6 R8 A5 FBC_MA6 R8 A5
A6 A6
1

CV229
FBC_MA7 R2 D7 FBC_D47 FBC_MA7 R2 D7 FBC_D54 DATA Bus
0.01U_0402_16V7K

1 A7 DQU0 A7 DQU0
RV127 FBC_MA8 T8 C3 FBC_D43 FBC_MA8 T8 C3 FBC_D51
FBC_MA9 R3 A8 DQU1 C8 FBC_D46 FBC_MA9 R3 A8 DQU1 C8 FBC_D55 Address
A9 DQU2 A9 DQU2 0..31 32..63
1.1K_0402_1% N13P@ FBC_MA10 L7 C2 FBC_D42 FBC_MA10 L7 C2 FBC_D49
N13P@ 2 FBC_MA11 R7 A10/AP DQU3 A7 FBC_D40 FBC_MA11 R7 A10/AP DQU3 A7 FBC_D52
Group5 (TOP) Group6 (BOT) FBx_CMD0 CS0#_L
2

FBC_MA12 N7 A11 DQU4 A2 FBC_D45 FBC_MA12 N7 A11 DQU4 A2 FBC_D50

FBC_MA13 T3 A12 DQU5 B8 FBC_D44 FBC_MA13 T3 A12 DQU5 B8 FBC_D53
A13 DQU6 A13 DQU6 FBx_CMD1
FBC_MA14 T7 A3 FBC_D41 FBC_MA14 T7 A3 FBC_D48
FBC_MA15 M7 A14 DQU7 FBC_MA15 M7 A14 DQU7
A15/BA3 A15/BA3 FBx_CMD2 ODT_L
+1.5VS_VGA +1.5VS_VGA
FBx_CMD3 CKE_L
FBC_BA0 M2 B2 FBC_BA0 M2 B2
FBC_BA1 N8 BA0 VDD D9 FBC_BA1 N8 BA0 VDD D9
BA1 VDD BA1 VDD FBx_CMD4 A14 A14
FBC_BA2 M3 G7 FBC_BA2 M3 G7
FBC_CLK1 BA2 VDD K2 BA2 VDD K2
VDD VDD FBx_CMD5 RST RST
K8 K8
VDD N1 VDD N1
VDD VDD FBx_CMD6 A9 A9
2

FBC_CLK1 J7 N9 FBC_CLK1 J7 N9
<27> FBC_CLK1 CK VDD CK VDD
RV129 FBC_CLK1# K7 R1 FBC_CLK1# K7 R1 FBx_CMD7 A7 A7
<27> FBC_CLK1# CK VDD CK VDD
C 160_0402_1% FBC_CKE_H K9 R9 FBC_CKE_H K9 R9 C
<27> FBC_CKE_H CKE/CKE0 VDD CKE/CKE0 VDD
N13P@ FBx_CMD8 A2 A2
1

FBC_ODT_H K1 A1 FBC_ODT_H K1 A1 FBx_CMD9 A0 A0

<27> FBC_ODT_H ODT/ODT0 VDDQ ODT/ODT0 VDDQ
FBC_CLK1# FBC_CS0#_H L2 A8 FBC_CS0#_H L2 A8
<27> FBC_CS0#_H CS/CS0 VDDQ CS/CS0 VDDQ
FBC_RAS# J3 C1 FBC_RAS# J3 C1 FBx_CMD10 A4 A4
<27,30> FBC_RAS# RAS VDDQ RAS VDDQ
FBC_CAS# K3 C9 FBC_CAS# K3 C9
<27,30> FBC_CAS# CAS VDDQ CAS VDDQ
FBC_WE# L3 D2 FBC_WE# L3 D2 FBx_CMD11 A1 A1
<27,30> FBC_WE# WE VDDQ WE VDDQ
E9 E9
VDDQ F1 VDDQ F1
VDDQ VDDQ FBx_CMD12 BA0 BA0
FBC_DQS4 F3 H2 FBC_DQS7 F3 H2
FBC_DQS5 C7 DQSL VDDQ H9 FBC_DQS6 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ FBx_CMD13 WE# WE#
FBx_CMD14 A15 A15
FBC_DQM4 E7 A9 FBC_DQM7 E7 A9
FBC_DQM5 D3 DML VSS B3 FBC_DQM6 D3 DML VSS B3
DMU VSS DMU VSS FBx_CMD15 CAS# CAS#
E1 E1
VSS G8 VSS G8
VSS VSS FBx_CMD16 CS0#_H
FBC_DQS#4 G3 J2 FBC_DQS#7 G3 J2
FBC_DQS#5 B7 DQSL VSS J8 FBC_DQS#6 B7 DQSL VSS J8
DQSU VSS DQSU VSS FBx_CMD17
FBC_ODT_H M1 M1
VSS M9 VSS M9
VSS VSS FBx_CMD18 ODT_H
P1 P1
FBC_CKE_H FBC_RST# T2 VSS P9 FBC_RST# T2 VSS P9
<27,30> FBC_RST# RESET VSS RESET VSS FBx_CMD19 CKE_H
T1 T1
L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS FBx_CMD20 A13 A13
1

RV118 RV119
B 10K_0402_5% 10K_0402_5% FBx_CMD21 A8 A8 B
1

1
N13P@ N13P@ J1 B1 J1 B1
RV123 L1 NC/ODT1 VSSQ B9 RV128 L1 NC/ODT1 VSSQ B9
NC/CS1 VSSQ NC/CS1 VSSQ FBx_CMD22 A6 A6
243_0402_1% J9 D1 243_0402_1% J9 D1
2

N13P@ L9 NC/CE1 VSSQ D8 L9 NC/CE1 VSSQ D8

NCZQ1 VSSQ NCZQ1 VSSQ FBx_CMD23 A11 A11
E2 N13P@ E2
2

2
VSSQ E8 VSSQ E8
VSSQ VSSQ FBx_CMD24 A5 A5
F9 F9
VSSQ G1 VSSQ G1
VSSQ VSSQ FBx_CMD25 A3 A3
G9 G9
VSSQ VSSQ
FBx_CMD26 BA2 BA2
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD27 BA1 BA1
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
X76@ X76@ FBx_CMD28 A12 A12
FBx_CMD29 A10 A10
+1.5VS_VGA UV9 SIDE +1.5VS_VGA UV10 SIDE FBx_CMD30 RAS# RAS#
.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
CV209

CV227

CV213

CV233

CV226

CV207

CV230

CV220

CV221

CV228

CV225

CV210

CV208

CV223

CV211

CV222

CV212

CV231

CV224

CV214

CV215

CV217

CV218

CV232
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

@ @ @ @ @ @ @
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ N13P@ A
N13P@ N13P@ N13P@ N13P@ N13P@ N13P@

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2011/10/27 Deciphered Date 2012/10/27

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13X-VRAM C Upper
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 31 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS_VGA
Physical Logical Logical Logical Logical
Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]

2
RV92 @ RV93 RV94 RV121 @ RV122 @ ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
45.3K_0402_1% 45.3K_0402_1% 10K_0402_1% 20K_0402_1% 20K_0402_1%
N13P@ N13P@ STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]

1
STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
<24> STRAP0 STRAP0
D <24> STRAP1 STRAP1 STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0] D
<24> STRAP2 STRAP2
<24> STRAP3 STRAP3 STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
<24> STRAP4 STRAP4
STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
2 CHANGE_GEN3

2
@ RV95 RV96 RV97 @ RV124 @ RV125 @
45.3K_0402_1% 45.3K_0402_1% 10K_0402_1% 4.99K_0402_1% 10K_0402_1% Pull-up to
N13P@ Resistor Values Pull-down to Gnd
+3VS_VGA
1

1
5K 1000 0000
ZZZ ZZZ
10K 1001 0001
15K 1010 0010
20K 1011 0011
Samsung Samsung
S2GP@ S1GM@ 25K 1100 0100
X7634138L01 X7634138L05
30K 1101 0101
ZZZ ZZZ
+3VS_VGA 35K 1110 0110
45K 1111 0111

Hynix Hynix
C H2GP@ H1GM@ C
2

X7634138L02 X7634138L06
2

RV98
4.99K_0402_1% RV99 @ RV100 @ ZZZ ZZZ
@ 30K_0402_1% 4.99K_0402_1%
1

SUB_VENDOR 3GIO_PADCFG XCLK_417

1

<24> ROM_SI ROM_SI

<24> ROM_SO ROM_SO
<24> ROM_SCLK ROM_SCLK Samsung Samsung 0 No VBIOS ROM 3GIO_PADCFG[3:0] 0 277MHz (Default)
S1GP@ S512M@
X7634138L03 X7634138L07
2

1 BIOS ROM is present (Default) 0110 Notebook Default 1 Reserved

2

RV101 ZZZ ZZZ

X76 20K_0402_1% RV102 RV103
X76@ 10K_0402_1%
N13P@
15K_0402_1%
N13P@ FB_0_BAR_SIZE SLOT_CLK_CFG
1

0 Reserved 0 GPU and MCH don't share a common reference clock

Hynix Hynix
10/11 Updated for NVIDIA update. H1GP@ H512M@
X7634138L04 X7634138L08 1 Reserved 1 GPU and MCH share a common reference clock (Default)
For N13P-GL strap table X76
2 256MB (Default) SMBUS_ALT_ADDR VGA_DEVICE
GPU Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK
3 Reserved 0 0x9E (Default) 0 3D Device (Class Code 302h)
128M* 16* 8 Samsung (2Gb) R R R R R R
N13P-GL 900 MHz 2GB K4W2G1646C-HC11 PU 45K PD 45K PU 45K n/a n/a PD 45K PD 10K PD 15K
B B
128M* 16* 8 Hynix (2Gb) R R R R R R 1 0x9C (Multi-GPU usage) 1 VGA Device (Default)
N13P-GL 900 MHz 2GB H5TQ1G63DFR-11C PU 45K PD 45K PU 45K n/a n/a PD 35K PD 10K PD 15K
USER Straps
64M* 16* 8 Samsung (1Gb) R R R R R R
N13P-GL 900 MHz 1GB K4W1G1646G-BC11 PU 45K PD 45K PU 45K n/a n/a PD 20K PD 10K PD 15K User[3:0]
64M* 16* 8 Hynix (1Gb) R R R R R R
N13P-GL 900 MHz 1GB H5TQ1G63DFR-11C PU 45K PD 45K PU 45K n/a n/a PD 15K PD 10K PD 15K
1000-1100 Customer defined

10/11 Updated for NVIDIA update. PEX_PLL_EN_TERM

0 Disable (Default)

1 Enable

PCIE_MAX_SPEED
0 Limit to PCIE Gen1

1 PCIE Gen 2/3 Capable

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13X_MISC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 32 of 60
5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT CMOS Camera

+LCDVDD +5VALW +3VS
+3VS
W=60mils
(20 MIL) (20 MIL)
1 CMOS@ +3VS_CMOS
Q83

1
R400 R401 C513
D 150_0603_1% 100K_0402_5% 4.7U_0603_6.3V6K PMV65XP_SOT23-3~D R4953 D
0_0603_5%
2

D
3 1 +3VS_CMOS_R 1 2
R403 1 CMOS@ 1

2
1

3
D 220K_0402_5%
S
CMOS@
G
2 1 2 2 Q80 C518 C519

G
2
Q79 G PMV65XP_SOT23-3~D 0.1U_0402_16V4Z 10U_0603_6.3V6M
2N7002_SOT23 S R435 CMOS@ 2 2 CMOS@
1
D
W=60mils

1
1
C515 150K_0402_5%
0.1U_0402_16V4Z

OUT
<42> CMOS_ON#
2 +LCDVDD +LCDVDD_CONN
L29 1
2
<17> PCH_ENVDD IN 1 2 C520

GND
0.1U_0402_16V4Z
Q81 DTC124EK FBMA-L11-201209-221LMA30T_0805 2
CMOS@
1

DTC124EKAT146_SC59-3 1 1

3
C516 C517
@ R408 4.7U_0603_6.3V6K
100K_0402_5% 0.1U_0402_16V4Z
2 2
2

+3VS

C C

R717 0_0402_5% 1
1 2 R433 @ VGA LCD/PANEL BD. Conn.
4.7K_0402_5%
2

BKOFF# 1 2 DISPOFF# +LEDVDD B+

<42> BKOFF#
D4 @
1

CH751H-40PT_SOD323-2 1 R813 2
R716 1 1 0_0805_5%
10K_0402_5% C539
680P_0402_50V7K C541
@ 4.7U_0805_25V6-K
2

2 2

R538 0_0402_5%
1 2
<17> PCH_ENBKL ENBKL <42>
+LCDVDD_CONN
+3VS_CMOS +LEDVDD
+3VS
2

CMOS JLVDS1
B R438 1 2 B
100K_0402_5% USB20_N5 3 1 2 4
<18> USB20_N5 3 4 1
<18> USB20_P5 USB20_P5 5 6
7 5 6 8 @ C540
(60 MIL)
1

LVDS_A0# 9 7 8 10 680P_0402_50V7K
<17> LVDS_A0# 9 10 2
LVDS_A0 11 12
<17> LVDS_A0 11 12
13 14
LVDS_A1# 15 13 14 16
<17> LVDS_A1# 15 16
LVDS_A1 17 18 INVPWM 0_0402_5% 2 R430 1
<17> LVDS_A1 17 18 PCH_PWM <17>
19 20 DISPOFF#
LVDS_A2# 21 19 20 22 0_0402_5% 2 R431 1
<17> LVDS_A2# 21 22 EC_INVT_PWM <42>
LVDS_A2 23 24 @
<17> LVDS_A2 23 24
25 26 EDID Pull high at chipset/VGA side
LVDS_ACLK# 27 25 26 28 EDID_CLK
<17> LVDS_ACLK# 27 28 EDID_CLK <17>
LVDS_ACLK 29 30 EDID_DATA EDID_DATA <17>
<17> LVDS_ACLK 31 29 30 32 LVDS_B2#
31 32 LVDS_B2# <17>
LVDS_B0 33 34 LVDS_B2
<17> LVDS_B0 33 34 LVDS_B2 <17>
LVDS_B0# 35 36
<17> LVDS_B0# 35 36
LVDS_B1# 37 38 LVDS_BCLK
<17> LVDS_B1# 37 38 LVDS_BCLK <17>
LVDS_B1 39 40 LVDS_BCLK#
<17> LVDS_B1 39 40 LVDS_BCLK# <17>
41 42
GND GND
ACES_87142-4041
A A
ME@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS/CAMERA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 33 of 60
5 4 3 2 1
 A B C D E

D73
@
3 6 GREEN
I/O2 I/O4

2 5 +5VS
GND VDD

1 1
RED 1 4 BLUE
I/O1 I/O3

AZC099-04S.R7G_SOT23-6
+5VS
D10
+CRT_VCC
CRT Connector
F1
2 1 1 2 +CRT_VCC_F
1
RB491D_SC59-3
FCM1608CF-121T03 0603 1.1A_6V_SMD1812P110TF C521
1 2 RED
<17> DAC_RED
L30 W=40mils 2
0.1U_0402_16V4Z

FCM1608CF-121T03 0603
1 2 GREEN
<17> DAC_GRN
L31
FCM1608CF-121T03 0603
1 2 BLUE
<17> DAC_BLU

C522

C523

C524

C525

C526

C527
L32 JCRT1 ME@

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
1

1
6
1 1 1 1 1 1
PAD T66 NC11 11
10/27 change to 0402 footprint
R445 R443 R446 RED 1
150_0402_1% 150_0402_1% 150_0402_1% 7
2 2 2 2 2 2 CRT_DDC_DAT_CONN 12
2

2
GREEN 2
8 16
CLOSE TO CONN JVGA_HS 13
G
17
BLUE 3 G
9

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
1

1
JVGA_VS 14

C537

C538

C535

C536
4
2 10 2
+CRT_VCC CRT_DDC_CLK_CONN 15
R448
5

2
1 2 1
1 C528 CONTE_80431-5K1-152

C529 1K_0402_5% 100P_0402_50V8J

2
0.1U_0402_16V4Z
2
1
5

FCM1608CF-121T03 0603 9/21 EMI request

OE#
P

2 4 CRT_HSYNC_1 1 2 JVGA_HS
<17> CRT_HSYNC A Y L33
0ohm and mount
G

U23
SN74AHCT1G125DCKR_SC70-5 1
3

@
D8
C530 @
10P_0402_50V8J JVGA_VS 3 6 JVGA_HS
+CRT_VCC 2 I/O2 I/O4
R451
1 2
1 2 5 +5VS
GND VDD
C531 1K_0402_5%
0.1U_0402_16V4Z
2 CRT_DDC_CLK_CONN 1 4 CRT_DDC_DAT_CONN
I/O1 I/O3
5

FCM1608CF-121T03 0603
OE#
P

2 4 CRT_VSYNC_1 1 2 JVGA_VS AZC099-04S.R7G_SOT23-6

3 <17> CRT_VSYNC A Y 3
L34
G

U24 1
SN74AHCT1G125DCKR_SC70-5
3

@ C532
10P_0402_50V8J
2

+CRT_VCC
+3VS
1

Pull high at chipset/VGA side R456 R457

5

2.2K_0402_5% 2.2K_0402_5%
2

<17> CRT_DDC_DATA 4 3 CRT_DDC_DAT_CONN

2N7002DW -T/R7_SOT363-6
2

Q62B

<17> CRT_DDC_CLK 1 6 CRT_DDC_CLK_CONN

1 1
4
2N7002DW -T/R7_SOT363-6 @ @ 4
Q62A C533 C534
100P_0402_50V8J 68P_0402_50V8K
2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 34 of 60
A B C D E
 5 4 3 2 1

+5VS
W=40mils +5VS_HDMI
+5VS RB491D_SC59-3 F2 HDMI@
+3VS D13 HDMI@ 1.1A_6VDC_FUSE
2 1+HDMI_5V 1 2 +5VS_HDMI

2
1

2
R482 @ C543
D R485 0_0805_5% HDMI@ D
1M_0402_5% Q93 D14 @ 0.1U_0402_16V4Z 2
HDMI@ HDMI@ BAT54S-7-F_SOT23-3

1
2
G
2N7002H_SOT23-3

1
TMDS_B_HPD 3 1
<17> TMDS_B_HPD

2
2
HDMI@ R483 R484 HDMI@
R488 2.2K_0402_5% 2.2K_0402_5%
20K_0402_5%

1
HDMI@
HDMI_CLK+_CONN C992 1 2 4.7P_0402_50V JHDMI1

1
@ HDMI_DET 19
HDMI_CLK-_CONN C993 1 2 4.7P_0402_50V 18 HP_DET
+5VS_HDMI +5V
@ 17
HDMI_TX0+_CONN C994 1 2 4.7P_0402_50V HDMIDAT_R 16 DDC/CEC_GND
@ HDMICLK_R 15 SDA
HDMI_TX0-_CONN C995 1 2 4.7P_0402_50V 14 SCL
@ 13 Reserved
HDMI_TX1+_CONN C996 1 2 4.7P_0402_50V HDMI_CLK-_CK R465 1 @ 2 11NH +-5% 0402 HDMI_CLK-_CONN 12 CEC 20
<17> HDMI_CLK-_CK CK- G1
@ 11 21
<17> HDMI_CLK+_CK CK_shield G2
HDMI_TX1-_CONN C997 1 2 4.7P_0402_50V HDMI_CLK+_CKR464 1 @ 2 11NH +-5% 0402 HDMI_CLK+_CONN 10 22
C CK+ G3 C
@ HDMI_TX0-_CK R467 1 @ 2 11NH +-5% 0402 HDMI_TX0-_CONN 9 23
+3VS <17> HDMI_TX0-_CK D0- G4
HDMI_TX2+_CONN C998 1 2 4.7P_0402_50V <17> HDMI_TX0+_CK 8
@ HDMI_TX0+_CK R466 1 @ 2 11NH +-5% 0402 HDMI_TX0+_CONN 7 D0_shield
HDMI_TX2-_CONN C999 1 2 4.7P_0402_50V HDMI_TX1-_CK R469 1 @ 2 11NH +-5% 0402 HDMI_TX1-_CONN 6 D0+
<17> HDMI_TX1-_CK D1-
@ <17> HDMI_TX1+_CK 5
D1_shield
2

HDMI_TX1+_CK R468 1 @ 2 11NH +-5% 0402 HDMI_TX1+_CONN 4

R783 HDMI_TX2-_CK R471 1 @ 2 11NH +-5% 0402 HDMI_TX2-_CONN 3 D1+
<17> HDMI_TX2-_CK D2-
0_0402_5% 2
<17> HDMI_TX2+_CK D2_shield
HDMI_TX2+_CK R470 1 @ 2 11NH +-5% 0402 HDMI_TX2+_CONN 1
D2+
1

SUYIN_100042GR019M23DZL
12/06 Update back to ME@
Pull up R for PCH OR VGA SIDE
common mode choke.
SM070000K00
Q63A
HDMI@ L35 HDMI@
2

2N7002DW-T/R7_SOT363-6 HDMI_CLK+_CK 1 2 HDMI_CLK+_CONN

1 2
1 6 HDMICLK_R 680 +-5% 8P4R
<17> HDMICLK_NB
HDMI_CLK-_CK 4 3 HDMI_CLK-_CONN HDMI_CLK-_CONN 5 4
4 3
5

HDMI_CLK+_CONN 6 3
WCM-2012-900T_4P HDMI_TX1-_CONN 7 2
B 4 3 HDMIDAT_R HDMI_TX1+_CONN 8 1 SD309680080 B
<17> HDMIDAT_NB
L36 HDMI@
Q63B HDMI_TX0+_CK 1 2 HDMI_TX0+_CONN RP5 HDMI@ S ROW RES 1/16W 680 +-5% 8P4R
HDMI@ 1 2
2N7002DW-T/R7_SOT363-6 680 +-5% 8P4R
HDMI_TX0-_CK 4 3 HDMI_TX0-_CONN HDMI_TX0-_CONN 5 4
4 3 HDMI_TX0+_CONN 6 3
WCM-2012-900T_4P HDMI_TX2-_CONN 7 2
HDMI_TX2+_CONN 8 1
HDMIDAT_R L37 HDMI@ +3VS
HDMI_TX1+_CK 1 2 HDMI_TX1+_CONN RP6 HDMI@
1 2

1
D
HDMICLK_R 2
HDMI_TX1-_CK 4 3 HDMI_TX1-_CONN G
4 3 Q95
S

3
WCM-2012-900T_4P HDMI@
3

2N7002H_SOT23-3
D11 @ L38 HDMI@
PJDLC05_SOT23-3 HDMI_TX2+_CK 1 2 HDMI_TX2+_CONN
1 2

HDMI_TX2-_CK 4 3 HDMI_TX2-_CONN
4 3
WCM-2012-900T_4P
A A
1

Security Classification Compal Secret Data Compal Electronics,Ltd.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title
HDMI CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 35 of 60
5 4 3 2 1
 A B C D E

Mini-Express Card for WLAN/WiMAX(Half)

+3VS_WLAN +3VALW +1.5VS_CONN

+3VS 80mil +3VS_WLAN

J6 1 1 1 1

@
C548@ C547
1
Mini-Express Card(WLAN/WiMAX) 1

@
1 2 4.7U_0603_6.3V6K 0.1U_0402_16V4Z C544 C545 @
1 2 +1.5VS 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2
1 @ 2 JUMP_43X79
<19,40> PCH_BT_ON#
R4965 0_0402_5% 0_0402_5% JWLAN1
PCIE_WAKE# 1 R514 2 1 2
<16,37,45> PCIE_WAKE# WAKE# 3.3V
<40> BT_ACTIVE BT_ACTIVE 1 R497 2 @ 3 4
R4964 1 2 0_0402_5% BT_DISABLE#_R 0_0402_5% 5 NC GND 6 +1.5VS_CONN
<19> BT_DISABLE# 7 NC 1.5V 8
<15> CLKREQ_WLAN# LPC_FRAME#_R
9 CLKREQ# NC 10 LPC_AD3_R
11 GND NC 12 LPC_AD2_R
<15> CLK_PCIE_WLAN1# 13 REFCLK- NC 14 LPC_AD1_R
<15> CLK_PCIE_WLAN1 REFCLK+ NC
15 16 LPC_AD0_R
PCI_RST#_R 17 GND NC 18
CLK_PCI_DB 19 NC GND 20 1 R498 2 0_0402_5%
NC NC PCH_WL_OFF# <18>
21 22
23 GND PERST# 24 1 R499 2 @ 0_0402_5% PLT_RST# <18,23,37,42,45>
<15> PCIE_PRX_DTX_N2 PERn0 +3.3Vaux +3VALW
25 26 1 R500 2 0_0402_5% +3VS
<15> PCIE_PRX_DTX_P2 27 PERp0 GND 28
29 GND +1.5V 30 1 R501 2 @ 0_0402_5%
GND SMB_CLK SMB_CLK_S3 <12,13,15>
31 32 1 R502 2 @ 0_0402_5%
<15> PCIE_PTX_C_DRX_N2 PETn0 SMB_DATA SMB_DATA_S3 <12,13,15>
33 34
<15> PCIE_PTX_C_DRX_P2 PETp0 GND
35 36
+3VS_WLAN 37 GND USB_D- 38 USB20_N10 <18>
NC USB_D+ USB20_P10 <18>
39 40
41 NC GND 42 R503 2 @ 1 0_0402_5%
43 NC LED_WWAN# 44 R504 2 @ 1 0_0402_5% WLAN_LED#
100_0402_1% 45 NC LED_WLAN# 46
NC
R505 47 NC LED_WPAN# 48
1 2 49 NC +1.5V 50
<42,43> EC_TX NC GND
1 2 51 52
<42,43> EC_RX NC +3.3V
R506
100_0402_1% 53 54 Reserve for SW mini-pcie debug card.
GND GND
Series resistors closed to KBC side.
TAITW_PFPET0-AFGLBG1ZZ4N0

2
For EC to detect ME@ LPC_FRAME#_R R508 1 @ 2 0_0402_5% LPC_FRAME#
LPC_FRAME# <14,42>
2 R507 LPC_AD3_R R509 1 @ 2 0_0402_5% LPC_AD3 2
debug card insert. 100K_0402_5% LPC_AD2_R R510 1 @ 2 0_0402_5% LPC_AD2
LPC_AD3 <14,42>
LPC_AD2 <14,42>
LPC_AD1_R R511 1 @ 2 0_0402_5% LPC_AD1
LPC_AD1 <14,42>
LPC_AD0_R R512 1 @ 2 0_0402_5% LPC_AD0

1
1 2 LPC_AD0 <14,42>
PCI_RST#_R R513 @ 0_0402_5% PLT_RST#
CLK_PCI_DB CLK_PCI_DB <18>

Every power trace need:

+CHGRTC_R
W=20mils
For GreenCLK generate CLK:
+3VLP +3VLP Mount: All parts in this page except
GCLK@ 1
U68 GCLK244@ Swing Level RES (Marked "*")
CG2
NA: PD108,
0.1U_0402_16V4Z

2 +1.05VS +3V_LAN +3VS_VGA

+RTCBATT
Y1,R98,C180,C181,
SLG3NB244VTR
1 Y2,R169,C196,C197,
1

CG3 GCLK@ Y6,C968,C969

1

+3V_LAN 22U_0603_6.3V6M
0_0402_5%

1
0_0402_5%

2
GCLK274@
RG9

CG4
RG11

2.2U_0402_6.3V6M
RG8 0_0402_5%
2

U68 2 GCLK@
2

1 10 14
CG6 VBAT VDD_RTC_OUT
GCLK@ 1 15
0.1U_0402_16V4Z

3
CG5 +V3.3A 3
GCLK274@

GCLK@ 2 2 1 +3VS_GCLK 2
1
0.1U_0402_16V4Z

CG7 CG1 VDD 9 GCLK_32K_R RG1 1 2 0_0402_5% GCLK_32K

2 32kHz GCLK@
GCLK_32K <14> PCH_32.768K
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2 GCLK@ VGA_GCLK 11
VDDIO_27M 27MHz
12 GCLK_27MHZ_R RG2 1 2 33_0402_5%
GCLK274@
GCLK_27MHZ
GCLK_27MHZ <23> NV_GPU
+3V_LAN 8
VDDIO_25M_A 25MHz_A
6 GCLK_LAN_25MHZ_R RG3 1
GCLK@
2 33_0402_5% GCLK_LAN_25MHZ
GCLK_LAN_25MHZ <37> LAN
3 5 RG4 1 2 33_0402_5% GCLK_PCH_25MHZ
PCH_GCLK
VDDIO_25M_B 25MHz_B
GCLK_PCH_25MHZ_R
GCLK@
GCLK_PCH_25MHZ <15> PCH_25M
GreenCLK_XTALI 1
Y8 GreenCLK_XTALO 16 XTAL_IN
XTAL_OUT
Close to GCLK
GND1
GND2
GND3

GND4

4 3
NC OSC
1 2
OSC NC
Reserved for Swing Level adjustment
33P_0402_50V8J

33P_0402_50V8J

SLG3NB274VTR_TQFN16_2X3
4
7
13

17

1 25MHZ_20PF_FSX3M-25.M20FDO 1
GCLK274@
CG8
GCLK@
GCLK@ CG9
GCLK@ ( Close GCLK side )
2 2
@
GCLK_27MHZ RG5 *1 2 0_0402_5%
9/22 from 15pF
@
GCLK_LAN_25MHZ RG6 *1 2 0_0402_5%

@
GCLK_PCH_25MHZ RG7 *1 2 0_0402_5%

4 4

Security Classification
2011/10/27
Compal Secret Data
2012/10/27 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card/Green CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 36 of 60
A B C D E
 5 4 3 2 1

Atheros request can't disable LAN power

+3VALW +3V_LAN

Layout Notice : Place as close +LX

J18 chip as possible. Close together
1 2 L77 L78 SWR@
1 2 R1357 L74 SWR@
+1.1_DVDDL 1 2 0_0402_5% +LX_R 1 2 +LX FBMA-L11160808601LMA10T_2P FBMA-L11160808601LMA10T_2P
JUMP_43X79

1000P_0402_50V7K
1 2 1 2

10U_0603_6.3V6M
4.7UH_SIA4012-4R7M_20% +1.1_AVDDL_L +1.1_AVDDL +1.1_DVDDL

0.1U_0402_16V4Z
@

@ C935

C936

C937

0.1U_0402_16V4Z

1U_0402_6.3V4Z

4.7U_0603_6.3V6K
D 1 1 D
Q130

C967

C980

C317
LP2301ALT1G_SOT23 Note: Place Close to LAN chip 1 1 1
2 2 L39 DCR< 0.15 ohm

D
3 1
Rate current > 1A
2 2 2

G
2
R4977
LAN_PWR_ON# 1 2
<42> LAN_PWR_ON#
10K_0402_5%

C1001
1 Place close to Pin34

.1U_0402_16V7K
Close to
Pin40
2
Vendor recommand reseve the
PU resistor close LAN chip

R525 1 2 4.7K_0402_5% U41 8162@ +3V_LAN

+3V_LAN
@ R1367
<18,23,36,42,45> PLT_RST#
PLT_RST# SA000050E00_S IC AR8161-AL3A-R QFN 40P E-LAN CTRL +AVDDH_AVDD3.3 1 2 0_0402_5%
SA000052J10_S IC AR8162-AL3A-R QFN 40P E-LAN CTRL
AR8162-AL3A-R

0.1U_0402_16V4Z

1U_0402_6.3V4Z
H --> Overclocking mode

C948

C949
L --> Not overclocking mode 1 1
C C

U41 GIGA@
Place Close to Chip 2 2
C946 1 2 .1U_0402_16V7K PCIE_PRX_C_DTX_N1 29 38 ACTIVITY
LDO Mode
<15> PCIE_PRX_DTX_N1 TX_N LED_0 ACTIVITY <38>
39 LAN_LINK#
C947 1 2 .1U_0402_16V7K PCIE_PRX_C_DTX_P1 30
Atheros LED_1 23 LAN_CLK_SEL 2 1 LAN_LINK# <38>
LAN_LINK# 2 1
<15> PCIE_PRX_DTX_P1 TX_P LED_2
AR8151/AR8161 R4958 @ 10K_0402_5% R4959 10K_0402_5% Place close to Pin16
36 LDO@
<15> PCIE_PTX_C_DRX_N1 RX_N 12 MDI0-
TRXN0 MDI0- <38>
35 11 MDI0+
<15> PCIE_PTX_C_DRX_P1 RX_P TRXP0 15 MDI0+ <38>
MDI1-
TRXN1 MDI1- <38>
32 14 MDI1+
<15> CLK_PCIE_LAN# 33 REFCLK_N TRXP1 18 MDI1+ <38>
MDI2-
<15> CLK_PCIE_LAN REFCLK_P TRXN2 MDI2- <38>
17 MDI2+
TRXP2 MDI2+ <38>
PLT_RST# 2 21 MDI3-
PERST# TRXN3 20 MDI3- <38>
@ MDI3+
R1369 1 2 0_0402_5% PCIE_WAKE#_R 3 TRXP3 MDI3+ <38> Place Close to PIN1
<16,36,45> PCIE_WAKE# W AKE#
<42> LAN_WAKE# R1370 1 2 0_0402_5%
25 10 LAN_RBIAS 1 2 +3V_LAN
R521 1 2 4.7K_0402_5% 26 SMCLK RBIAS R1371 2.37K_0402_1%
+3V_LAN SMDATA
Place Close to PIN1
@ 28 1 +3V_LAN
NC VDD33

1000P_0402_50V7K
27

10U_0603_6.3V6M

10U_0603_6.3V6M
0.1U_0402_16V4Z

1U_0402_6.3V4Z
Vendor recommand reseve the TESTMODE 1 1 1 1

2
@
PU resistor close LAN chip 40 +LX
LX +LX

C950

C951

C952

C953

C954
LAN_XTALO 7

1
@ LAN_XTALI_R 8 XTLO R1372 30K_0402_1% 2 2 2 2
R520 1 2 4.7K_0402_5% XTLI 5 +1.7_VDDCT 1 2
+3V_LAN VDDCT/ISOLAN +3VS
B B
<15> CLKREQ_LAN#
4
CLKREQ# 24
DVDDL/PPS 37 +1.1_DVDDL
+1.1_AVDDL 13 DVDDL_REG/DVDDL
+1.1_AVDDL 19 AVDDL +2.7_AVDDH
+1.1_AVDDL 31 AVDDL 16 +AVDDH_AVDD3.3
+1.1_AVDDL_L 34 AVDDL AVDDH/AVDD33 22 +2.7_AVDDH
+1.1_AVDDL 6 AVDDL AVDDH 9 +2.7_AVDDH
AVDDL_REG/AVDDL AVDDH_REG
1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z
C956

C957

C958

C959

C960
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1 1 1 1 C961

C962

C963

C964

C965
41 1 1 1 1 1
GND

2 2 2 2 2 AR8161-AL3A-R_QFN40_5X5
2 2 2 2 2

Near
Near Near Near Near Pin9 Near Near
Pin13 Pin19 Pin31 Pin6 Pin22 Pin37

C981 @ 5P_0402_50V8
1 2 LAN_XTALI CRYSTAL@
<15> PCH_LAN_48M
LAN_XTALI R1373 1 2 0_0402_5% LAN_XTALI_R
Y6 LAN_XTALO C988 5P_0402_50V8
4 3 GCLK_LAN_25MHZ 1 2
A
Place Close to C968 NC OSC <36> GCLK_LAN_25MHZ
A

1 2 GCLK@
OSC NC
15P_0402_50V8J

15P_0402_50V8J

3.3V : Enable switching regulator 1 25MHZ_20PF_FSX3M-25.M20FDO 1

C968

C969

0V : Disable switching regulator

Security Classification Compal Secret Data Compal Electronics, Inc.
2 2 2011/10/27 2012/10/27 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN-AR8151/8161
Size Document Number Rev
12/29, Y6 changes to SJ10000E800 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
S CRYSTAL 25MHZ 10PF +-20PPM 7V25000014
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 37 of 60
5 4 3 2 1
 5 4 3 2 1

MDI3+
T1,T2 P/N to SP050007K00
MDI3-
T2
2
@ C970 MDI3+ 1 16 MDO3+ R4966 2 8162@ 1 0_0402_5%
<37> MDI3+ TD+ TX+
0.1U_0402_16V4Z MDI3- 2 15 MDO3- R4967 2 8162@ 1 0_0402_5%

10
<37> MDI3- TD- TX-

6
7
8
9
3 14 MCT0
D 1 4 CT CT 13 D

6
7
8
9
10
11 5 NC NC 12
GND CT 6 NC NC 11 MCT0
RCLAMP3304N.TCT_SLP2626P10-10 1 CT CT
MDI2+ 7 10 MDO2+ R4968 2 8162@ 1 0_0402_5%
D69 @ <37> MDI2+ RD+ RX+
5
4
3
2
1
C972 MDI2- 8 9 MDO2- R4969 2 8162@ 1 0_0402_5%
<37> MDI2- RD- RX-
@ 0.1U_0402_16V4Z EMI Request
5
4
3
2
1
2
BOTHHAND_NS0013LF
GIGA@ R1376 C973
MDI2- 1 2 MCT0_1 1 2

MDI2+ 75_0603_5% 10P_0603_50V

T1
2
Place Close to T2 C974 MDI0+ 1 16 MDO0+
<37> MDI0+ TD+ TX+
MDI1- @ 0.1U_0402_16V4Z MDI0- 2 15 MDO0- 2 1
<37> MDI0- 3 TD- TX- 14 MCT0 DL1 LSE-200NX3216TRLF_1206-2
1 4 CT CT 13 @
MDI1+ 5 NC NC 12
6 NC NC 11 MCT0 Reserve gas tube for EMI go rural solution
1 CT CT
MDI1+ 7 10 MDO1+ Place Close to T1,T2
<37> MDI1+ 8 RD+ RX+ 9
@ C975 MDI1- MDO1-
<37> MDI1- RD- RX-
0.1U_0402_16V4Z
10
6
7
8
9

2
C C
BOTHHAND_NS0013LF
6
7
8
9
10

11
GND
RCLAMP3304N.TCT_SLP2626P10-10 SWR or LDO Mode Update For ESD request, 10/26 update reserved
D68 @
5
4
3
2
1
5
4
3
2
1

LDO@
2 1 0_0402_5% D74
R4960 @
JRJ1 CHASSIS_GND 2
MDI0- R4961 2 SWR@ 1 0_0402_5% 12 1
Green LED- MCT0_1 3
MDI0+ LAN_LINK# R4962 2 LDO@ 1 220_0402_5% 11
<37> LAN_LINK# Green LED+ 16
Place Close to T1 PJDLC05_SOT23-3
220_0402_5% MDO3- 8 SHLD2
2 1 PR4- 15
+3V_LAN SHLD1
1 R1378 MDO3+ 7
@ SWR@ PR4+
For EMI request, 10/27 update reserved
C978 MDO1- 6
470P_0402_50V7K PR2- @
2 MDO2- 5 R4971 2 1 0_0402_5%
PR3- @
MDO2+ 4 R4972 2 1 0_0402_5%
PR3+ @
B MDO1+ 3 R4973 2 1 0_0402_5% B
PR2+ @
MDO0- 2 R4974 2 1 0_0402_5%
PR1- 14
For ESD surge, Modify R1443 near to LAN chip side. SHLD2
MDO0+ 1
R1443 PR1+ 13
ACTIVITY 2 1 10 SHLD1 @
<37> ACTIVITY Yellow LED- CHASSIS_GND C989 1 2 470P_0603_50V8J
220_0402_5% 9
Yellow LED+ C990 1 2 0.1U_0603_25V4Z
1 LIYO_101007-08203-033
@ C991 1 2 1U_0603_25V6
C979 +3V_LAN ME@
470P_0402_50V7K
2
CHASSIS_GND

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN_Transformer
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 38 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS REMOTE1+
Close to VRAM
D D
Close U27 1

1
C

1
REMOTE1+ @ C586 2 Q97
+3VS R540 100P_0402_50V8J B MMST3904-7-F_SOT323-3
1 Close to DDR 10K_0402_5%
2 E N13P@

3
C587 @ REMOTE1-
2200P_0402_50V7K U27

2
N13P@ 2 REMOTE1-

1 10 EC_SMB_CK2
VDD SMCLK EC_SMB_CK2 <15,23,42>
REMOTE1+ 2 9 EC_SMB_DA2
REMOTE2+ 2
DP1 SMDATA EC_SMB_DA2 <15,23,42>
REMOTE2+
near PL402
1 REMOTE1- 3 8 1
DN1 ALERT#

1
C590 C
C588 @ 0.1U_0402_16V4Z REMOTE2+ 4 7 @ C589 2 Q98 @
2200P_0402_50V7K 1 DP2 THERM# 100P_0402_50V8J B MMST3904-7-F_SOT323-3
2 REMOTE2- REMOTE2- 5 6 2 E

3
DN2 GND REMOTE2-

EMC1403-2-AIZL-TR_MSOP10
REMOTE1,2+/-:
C Address 1001_101xb Trace width/space:10/10 mil
C

Trace length:<8"

CPU VGA_L VGA_R

H1 H2 H3
HOLEA HOLEA HOLEA H4 H5 H19
HOLEA HOLEA HOLEA FD1 FD2 FD3 FD4

1
H_3P8 H_3P8 H_3P8
H_3P3 H_3P3 H_3P0

A C

B FAN1 Conn M/B

L
㨊⚻⫼
R
M/B ⚻⫼ 月役桐㇯ ⚻⫼ B

H6 H7 H8 H9 H10 H11 H12 H13 H17 H18 H14

+5VS HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA H15 H16 HOLEA HOLEA HOLEA
HOLEA HOLEA
JFAN1
2 R581 1 1
1

1
0_0603_5% 2 1
<42> EC_TACH

1
3 2
<42> EC_FAN_PWM 3
4
5 4 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_3P0X4P5N H_3P0X4P0N H_5P5N H_3P0N H_3P3
2 G5
6
C591 G6
10U_0603_6.3V6M ACES_85205-04001 B
1 ME@
2P8 * 8pcs E

A A

Security Classification Compal Secret Data Compal Electronics,Ltd.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title
Fintek-Thermal IC/FAN/screw
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 39 of 60
5 4 3 2 1
 A B C D E F G H

BT MODULE CONN SATA HDD Conn.

JHDD1
1
SATA_ITX_DRX_P0 2 GND
<14> SATA_ITX_DRX_P0 RX+
<14> SATA_ITX_DRX_N0 SATA_ITX_DRX_N0 3
4 RX-
SATA_DTX_C_IRX_N0 C596 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N0 5 GND
<14> SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 C597 1 2 0.01U_0402_16V7K SATA_DTX_IRX_P0 6 TX-
<14> SATA_DTX_C_IRX_P0 7 TX+
GND

1 1
R632 BT@ C709 BT@
100K_0402_5% 0.1U_0402_16V4Z
1 2 1 2 8
<19,36> PCH_BT_ON# 3.3V
9
+3VS 3.3V
+3VS_BT 10
11 3.3V
+3VS 12 GND
0_0603_5% 13 GND
R583 BT@ 14 GND
30mils 5V

D
3 1 +3VS_BT_R 2 1 1 R550 2 +5V_HDD 15
+5VS 5V
1 0_0805_5% 16
Q104 0.1U_0402_16V4Z 17 5V
PMV65XP_SOT23-3~D C712 18 GND

G
2
BT@ BT@ 19 Reserved
2 +5V_HDD +3VS 20 GND 23
JBT1 21 12V GND 24
1 22 12V GND
2 1 12V
2 1 1 1 1 1 1
<18> USB20_P13 USB20_P13 3 @ SUYIN_127043FB022G278ZR
USB20_N13 4 3 C598 C599 C600 @ C601 @ C602 C603
<18> USB20_N13 4
BTON_LED:NC 5 7 1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0402_6.3V6K 10U_0603_6.3V6M 10U_0603_6.3V6M 0.1U_0402_16V4Z
BT_ACTIVE 6 5 G1 8 2 2 2 2 2 2 ME@
<36> BT_ACTIVE 6 G2
ACES_87213-0600G
ME@

2
ODD Power Control 2

@ J9
1 2
1 2 +5V_ODD

+5VALW +5VS JUMP_43X79

SATA ODD FFC Conn.
JODD1
S

3 1
1 SATA_ITX_C_DRX_P2 C605 1 2 0.01U_0402_16V7K SATA_ITX_DRX_P2_15 1
<14> SATA_ITX_C_DRX_P2 1
1

Q99 @ <14> SATA_ITX_C_DRX_N2 SATA_ITX_C_DRX_N2 C606 1 2 0.01U_0402_16V7K SATA_ITX_DRX_N2_15 2

@ PMV65XP_SOT23-3~D C604 3 2
G
2

R568 R552 @ @ 0.1U_0402_16V4Z SATA_DTX_C_IRX_N2 C618 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N2_15 4 3

10K_0402_5% 10K_0402_5% 2 <14> SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 C617 1 2 0.01U_0402_16V7K SATA_DTX_IRX_P2_15 5 4
<14> SATA_DTX_C_IRX_P2 1 2 ODD_DETECT# 6 5
1
2

1 R675 2 @ R710 @ 0_0402_5% +5V_ODD 7 6

100K_0402_5% C608 check 8 7
1

10U_0603_6.3V6M ODD_DA# 9 8
@ 1 <18,42> ODD_DA# 9
@ 2 10
OUT

C607 10
0.01U_0402_16V7K +3VS 1 R555 2 11
2 2 10K_0402_5% 12 GND
<19> ODD_EN IN GND
GND

Q100 ACES_87056-01001-001
DTC124EKAT146_SC59-3
3

@
ME@

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD/BT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 40 of 60
A B C D E F G H
 5 4 3 2 1

CX20671
High Definition Audio Codec SoC
With Integrated Class-D Stereo
Amplifier.
An integrated 5 V to 3.3 V Low-dropout
voltage regulator (LDO).
An integrated 3.3 V to 1.8V Low-dropout
voltage regulator (LDO).
D D

+3VS

1
HDA_RST_AUDIO#
+3VS
HDA_SYNC_AUDIO
EMI R351 @
4.7K_0402_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z
4.7U_0603_6.3V6K
1 1 1 HDA_SDOUT_AUDIO

2
C579

C580

C581
+LDO_OUT_3.3V 1 R515 2 HDA_BITCLK_AUDIO HDA_RST_AUDIO#
0_0402_5%

1U_0402_6.3V6K
+3VS 2 2 2
1

0.1U_0402_16V4Z

0.1U_0402_16V4Z
4.7U_0603_6.3V6K
@
@ 1 1 1 1 AVDD_3.3 pinis output of 1 1 1 1 C641 @

0.1U_0402_16V4Z
4.7U_0603_6.3V6K

C584

C585

C625

C592
1 1 internal LDO. NOT connect

C582

C583

C575

C576

C577

C578
100P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J
to external supply. 2
2 2 2 2 2 2 2 2
2 2 @ @ @ @
Layout Note:Path from +5VS to LPWR_5.0
RPWR_5.0 must be very low
resistance (<0.01 ohms)
R527 0_0402_5%
ESD Reserve
+3VS
1 2

1U_0402_6.3V6K

0.1U_0402_16V4Z
+5VS
+3VALW
1R528 @ 2 0_0402_5% 1 1

C593

C623

0.1U_0402_16V4Z
4.7U_0603_6.3V6K
+5VS
1 1 Sense resistors must be

C638

C631
10 mils connected same power

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2 2
1 1 1 1 that is used for VAUX_3.3

C632

C594

C595

C628
@

10U_0603_6.3V6M

0.1U_0402_16V4Z
2 2
1 1

C626

C634
@ @
2 2 2 2 R458 1 2 5.11K_0402_1% +3VS
C Port B C

0.1U_0402_16V4Z
2 2 SENSE_A R491 1 2 20K_0402_1% MIC_JD
MIC_JD <43> Port A

18

28
26
27
29
1

7
2
3
1 2 39.2K_0402_1%

C620
U25 R494 PLUG_IN PLUG_IN <43>

VAUX_3.3
VDD_IO

DVDD_3.3
FILT_1.8

FILT_1.65

AVDD_3.3
AVDD_5V
AVDD_HP
@ Please bypass caps very close to device.
12 2
LPWR_5.0 15
HDA_RST_AUDIO# 9 RPWR_5.0 17
<14> HDA_RST_AUDIO# RESET# CLASS-D_REF EXT_MIC_L_CR R4946 3.3K_0402_5% +MICBIASB
HDA_BITCLK_AUDIO 5 EXT_MIC_R_CR R4947 3.3K_0402_5%
<14> HDA_BITCLK_AUDIO BIT_CLK
HDA_SYNC_AUDIO 8 36 SENSE_A
<14> HDA_SYNC_AUDIO SYNC SENSE_A
R495 1 2 33_0402_5% 6
<14> HDA_SDIN0 SDATA_IN
HDA_SDOUT_AUDIO 4 2.2U_0603_6.3V6K
<14> HDA_SDOUT_AUDIO SDATA_OUT 35 EXT_MIC_R_C C621 1 2 R517 100_0402_1% EXT_MIC_R
PORTB_R EXT_MIC_R <43>
34 EXT_MIC_L_C C622 1 2 R4948 100_0402_1% EXT_MIC_L External MIC
PORTB_L EXT_MIC_L <43>
33 +MICBIASB
PC_BEEP 10 B_BIAS 2.2U_0603_6.3V6K
EAPD active low PC_BEEP
0=power down ex AMP 32 +MICBIASC
C_BIAS 31 MIC_INR
1=power up ex AMP @ PORTC_R 30 MIC_INL
0_0402_5% 1 2 R519 CX_GPIO0 38 PORTC_L Internal MIC
<42> EAPD 2 1 GPIO0/EAPD#
37
<42> EC_MUTE# GPIO1/SPK_MUTE#
0_0402_5% R496 23 R481 1 2 39_0402_5%
PORTA_R HP_OUTR <43>
22 R493 1 2 39_0402_5% Headphone
PORTA_L HP_OUTL <43>
40
1 DMIC_CLK 24
DMIC_1/2 NC Changed from 15ohm to 39ohm
25 for "POP"noise.
NC 39
SPK_L2+ 11 NC
SPK_L1- 13 LEFT+
LEFT- 21
Internal SPEAKER AVEE 19
SPK_R2+ 16 FLY_P 20 1 2

4.7U_0603_6.3V6K
0.1U_0402_16V4Z
SPK_R1- 14 RIGHT+ FLY_N C635 1U_0402_6.3V6K
RIGHT- 1 1

C629

C609
Short GND and GNDA on
GND

B GND1 & GND2 on layout B

@
R516 @ CX20671-21Z_QFN40_6X6 2 2
41

1 2
0_0402_5%

GND GNDA

PC Beep
1 2
EC Beep <42> BEEP#
C619 0.1U_0402_16V4Z

R492
1 2PC_BEEP1 1 2 PC_BEEP
ICH Beep <14> HDA_SPKR
C612 0.1U_0402_16V4Z 33_0402_5%
1

@
R480 Place close to Codec chip
10K_0402_5%
EMI Request: SM01001678L
2

+MICBIASC close to Codec JSPK1 ME@

SPK_R1- L41 1 2 0_0603_5% SPK_R1-_CONN 1
SPK_R2+ L42 1 2 0_0603_5% SPK_R2+_CONN 2 1
1

SPK_L1- L43 1 2 0_0603_5% SPK_L1-_CONN 3 2

R518 SPK_L2+ L46 1 2 0_0603_5% SPK_L2+_CONN 4 3
4
2.2K_0402_5%
5
wide 30MIL

2
A 6 GND1 A

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
2

MIC1 GND2
1 1 1 1
1 C633 1 2 2.2U_0603_6.3V6K

C610

C627

C624

C611
MIC_INTERNAL MIC_INR ACES_88231-04001
2 GNDA
1 1 MIC_INL EMI Request
WM-64PCY_2P 2 2 2 2 @ D70 D71 @
0.1U_0402_16V4Z

0.1U_0402_16V4Z

1
45@ TVNST52302AB0 C/C SOT523 TVNST52302AB0 C/C SOT523
2 2
C636

C640

Security Classification Compal Secret Data Compal Electronics, Inc.

@ @ 2011/10/27 2012/10/27 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CX20671 Codec
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 41 of 60
5 4 3 2 1
 +3VALW
+3VLP

+3VALW Vcc 3.3V +/- 5%

L44
FBM-11-160808-601-T_0603 100K +/- 5%
1 1 1 1 1 1
+EC_VCCA R694

0.1U_0402_16V4Z
C653

0.1U_0402_16V4Z
C654

0.1U_0402_16V4Z
C662

0.1U_0402_16V4Z
C655

1000P_0402_50V7K
C657

1000P_0402_50V7K
C658
1 2
+3VALW +EC_VCCA
1 1 Board ID R695 VAD_BID min V AD_BID typ VAD_BID max
C659
C656 2 2 2 2 2 2
0 0 0 V 0 V 0 V MP

111
125
0.1U_0402_16V4Z 1000P_0402_50V7K U31

67
22
33
96
9
1 2 2 ECAGND 2
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V PVT
L45

EC_VDD0

EC_VDD/AVCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC

EC_VDD/VCC
FBM-11-160808-601-T_0603 18K +/- 5%
2 0.436 V 0.503 V 0.538 V DVT
3 33K +/- 5% 0.712 V 0.819 V 0.875 V EVT
1 21
<19> GATEA20 2 GATEA20/GPIO00 GPIO0F 23 BEEP#
<19> KBRST# KBRST#/GPIO01 BEEP#/GPIO10 BEEP# <41>
3 26 NOVO#
<14> SERIRQ SERIRQ GPIO12 NOVO# <43>
4 27 ACOFF +3VS +3VALW
<14,36> LPC_FRAME# LPC_FRAME# ACOFF/GPIO13 ACOFF <49>
LPC_AD3 5
<14,36> LPC_AD3

2
LPC_AD2 7 LPC_AD3
<14,36> LPC_AD2 PWM Output

1
LPC_AD1 8 LPC_AD2 63 BATT_TEMP N13P@
<14,36> LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_TEMP <48>
LPC_AD0 10 LPC & MISC 64 VGA_IMVP_IMON 2 R758 1 0_0402_5% R694
<14,36> LPC_AD0 LPC_AD0 GPIO39 GPU_IMON <54>
2 1 2 1 65 R588 100K_0402_5%
ADP_I/GPIO3A ADP_I <48,49>
@ C660 22P_0402_50V8J @ R589 10_0402_5% 12 AD Input 66 10K_0402_5%
<18> CLK_PCI_EC

1
13 CLK_PCI_EC GPIO3B 75 BRDID @ BRDID
<18,23,36,37,45> PLT_RST#

2
1 2 EC_RST# 37 PCIRST#/GPIO05 GPIO42 76 EC_FAN_PWM
+3VALW IMVP_IMON <55>

2
R590 47K_0402_5% EC_SCI# 20 EC_RST# IMON/GPIO43
<19> EC_SCI# EC_SCII#/GPIO0E
2 BATT_LEN# 38 R695
<48> BATT_LEN# GPIO1D 68 33K_0402_5%
C661 DAC_BRIG/GPIO3C 70 +5VALW
0.1U_0402_16V4Z EN_DFAN1/GPIO3D 71
DA Output

1
1 KSI0 55 IREF/GPIO3E 72 +3VALW
KSI1 56 KSI0/GPIO30 CHGVADJ/GPIO3F
KSI2 57 KSI1/GPIO31 EC_MUTE# 1 R593 2 10K_0402_5%
KSO[0..15] KSI3 58 KSI2/GPIO32 83 R594
<43> KSO[0..15] KSI3/GPIO33 EC_MUTE#/GPIO4A EC_MUTE# <41>
KSI4 59 84 USB_ON# USB_ON# 1 2
KSI[0..7] KSI4/GPIO34 USB_EN#/GPIO4B USB_ON# <44,45> +5VS
KSI5 60 85
<43> KSI[0..7] KSI6 61 KSI5/GPIO35 CAP_INT#/GPIO4C 86 10K_0402_5%
KSI6/GPIO36 PS2 Interface EAPD/GPIO4D EAPD <41>
KSI7 62 87 TP_CLK TP_CLK R591 1 2 4.7K_0402_5%
KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK <43>
+3VALW KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <43>
R595 1 2 47K_0402_5% KSO1 KSO1 40 TP_DATAR592 1 2 4.7K_0402_5%
@ KSO2 41 KSO1/GPIO21
R597 1 2 47K_0402_5% KSO2 KSO3 42 KSO2/GPIO22 97 CPU1.5V_S3_GATE
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 CPU1.5V_S3_GATE <10,53>
@ KSO4 43 98 VGA_AC_DET
KSO4/GPIO24 WOL_EN/GPXIOA01 VGA_AC_DET <23,54>
KSO5 44 99 BATT_TEMP 1 2
KSO6 45 KSO5/GPIO25 Int. K/B HDA_SDO/GPXIOA02 109 NTC_V_R 2 R750 1 0_0402_5%
ME_FLASH <14>
+3VALW C663 100P_0402_50V8J
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 NTC_V <48>
ACIN 1 2
+3VALW KSO7/GPIO27 SPI Device Interface
+3VS KSO8 47 C664 100P_0402_50V8J
R600 KSO9 48 KSO8/GPIO28 119 PCH_PWR_EN PCH_PWR_EN 2 R599 @1 100K_0402_5% 1 2
KSO9/GPIO29 SPIDI/GPIO5B PCH_PWR_EN <46,48>
1 2 EC_SMB_CK1 KSO10 49 120 R522 @ 4.7K_0402_5%
2.2K_0402_5% KSO11 50 KSO10/GPIO2A SPIDO/GPIO5C 126
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58
R604 KSO12 51 128
R601 R602 1 2 EC_SMB_DA1 KSO13 52 KSO12/GPIO2C SPICS#/GPIO5A
2.2K_0402_5% KSO14 53 KSO13/GPIO2D
2.2K_0402_5% 2.2K_0402_5%
KSO15 54 KSO14/GPIO2E 73
KSO15/GPIO2F ENBKL/GPIO40 ENBKL <33>
KSO16 81 74
EC_SMB_CK2 <43> KSO16 KSO17 82 KSO16/GPIO48 PECI_KB930/GPIO41 89 LAN_PWR_ON#
<43> KSO17 KSO17/GPIO49 FSTCHG/GPIO50 LAN_PWR_ON# <37>
EC_SMB_DA2 90 BATT_CHG_LED#
BATT_CHG_LED#/GPIO52 BATT_CHG_LED# <43>
1 1 91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# <43>
@ @ EC_SMB_CK1 77 GPIO 92
<48,49> EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 PWR_LED# <43> +3VLP
C665 C666 EC_SMB_DA1 78 93 BATT_LOW_LED#
<48,49> EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_LOW_LED# <43>
100P_0402_50V8J 100P_0402_50V8J EC_SMB_CK2 79 SM Bus 95 SYSON
2 2 <15,23,39> EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON <45,46,51>
EC_SMB_DA2 80 121
<15,23,39> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 VR_ON <55>

1
127 PM_SLP_S4# <16> KB9012A2 work around
PM_SLP_S4#/GPIO59 R4945 @
47K_0402_5% VR_HOT# 1 R737 2 H_PROCHOT# <6,48>
<55> VR_HOT#
6 100 0_0402_5%
<16> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# <16>
+3VS 14 101 EC_LID_OUT#
<16> PM_SLP_S5# EC_LID_OUT# <19>

2
PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04

1
EC_SMI# 15 102 Turbo_V D
<19> EC_SMI# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 Turbo_V <48>
16 103 H_PROCHOT#_EC R757 2 1 0_0402_5% H_PROCHOT#_EC 2 1
<33> CMOS_ON# GPIO0A H_PROCHOT#_EC/GPXIOA06 PROCHOT <48>
1

RF_LED# 17 104 MAINPWON_EC 1 R4978 2 G

<43> RF_LED# GPIO0B VCOUT0_PH/GPXIOA07 MAINPWON <48,50>
18 GPO 105 BKOFF# 0_0402_5% @ Q37 S C493
BKOFF# <33>

3
R605 ODD_DA# 19 GPIO0C BKOFF#/GPXIOA08 106 PBTN_OUT# 2N7002H_SOT23-3 47P_0402_50V8J
<18,40> ODD_DA# GPIO0D GPIO PBTN_OUT#/GPXIOA09 PBTN_OUT# <16> 2
10K_0402_5% EC_INVT_PWM 25 107 PCH_APWROK <16>
<33> EC_INVT_PWM EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10
EC_TACH 28 108 SA_PGOOD <52>
<39> EC_TACH
2

EC_TACH EC_PME# 29 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11

EC_TX 30 EC_PME#/GPIO15
<36,43> EC_TX EC_TX/GPIO16
EC_RX 31 110 ACIN
<36,43> EC_RX EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN <16,49>
PCH_PWROK 32 112 EC_ON +3VALW
<16> PCH_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON <43,50>
EC_FAN_PWM 34 114 ON/OFF# <43>
<39> EC_FAN_PWM SUSP_LED#/GPIO19 ON/OFF/GPXIOD03
NUM_LED# 36 GPI 115 LID_SW#
<43> NUM_LED# LID_SW# <43>

2
2 1 NUM_LED#/GPIO1A LID_SW#/GPXIOD04 116 SUSP#
SUSP#/GPXIOD05 SUSP# <10,25,46,51,52,53,54>
@ R608 117 PCH_HOT#_R R792 2 @ 1 0_0402_5%
GPXIOD06 PCH_HOT# <15>
10K_0402_5% 118 PECI_KB9012 1 2 R606
PECI_KB9012/GPXIOD07 H_PECI <6,19>
AGND/AGND

R611 EC_RTCX1 122 R669 43_0402_1% 10K_0402_5%

2 1 123 XCLKI/GPIO5D
GND/GND
GND/GND
GND/GND
GND/GND

SUSCLK_R 124 +V18R

<16> SUSCLK

1
0_0402_5% XCLKO/GPIO5E V18R
1
GND0
1

C667 R609
1

4.7U_0603_6.3V6K 2 1
R740 C93 2 LAN_WAKE# <37>
11
24
35
94
113

69

100K_0402_5% 20P_0402_50V8 0_0402_5%

2

2 R610 1
2

KB9012QF A3 LQFP 128P_14X14

ECAGND

EMC Request 0_0402_5% @

EC_RTCX1 SYSON EC_PME# 1 3

S
PCI_PME# <18>

C492
1 2 SUSCLK_R Q102 @

.1U_0402_16V7K
R120 @ 2N7002_SOT23

G
2
10M_0402_5% 1 +3VALW
PN : SA00004OB20 S IC KB9012QF A3 LQFP 128P KB CONTROLLER @

2
32.768KHZ_12.5PF_9H03200413
1

4
18P_0402_50V8J

Y5
OSC

OSC

1 1
C347 @ C367 @
@ 18P_0402_50V8J
NC

NC

2 2
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title
check
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & EC I/O Port
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 42 of 60
 KSI[0..7]
INT_KBD Conn. the same wtih G770
KSI[0..7] <42>
JKB1 ME@
KSO[0..17] KSO16 C693 1 2 @ 100P_0402_50V8J KSI1 1
KSO[0..17] <42> 2 1
KSI7
KSO17 C692 1 2 @ 100P_0402_50V8J KSI6 3 2
KSO9 4 3
KSO2 C668 1 2 @ 100P_0402_50V8J KSO1 C669 1 2 @ 100P_0402_50V8J KSI4 5 4
KSI5 6 5
KSO15 C670 1 2 @ 100P_0402_50V8J KSO7 C671 1 2 @ 100P_0402_50V8J KSO0 7 6
KSI2 8 7
KSO6 C672 1 2 @ 100P_0402_50V8J KSI2 C673 1 2 @ 100P_0402_50V8J KSI3 9 8
KSO5 10 9
KSO8 C674 1 2 @ 100P_0402_50V8J KSO5 C675 1 2 @ 100P_0402_50V8J KSO1 11 10
KSI0 12 11
KSO13 C676 1 2 @ 100P_0402_50V8J KSI3 C677 1 2 @ 100P_0402_50V8J KSO2 13 12
KSO4 14 13
KSO12 C678 1 2 @ 100P_0402_50V8J KSO14 C679 1 2 @ 100P_0402_50V8J KSO7 15 14
KSO8 16 15
KSO11 C680 1 2 @ 100P_0402_50V8J KSI7 C681 1 2 @ 100P_0402_50V8J KSO6 17 16
KSO3 18 17
KSO10 C682 1 2 @ 100P_0402_50V8J KSI6 C683 1 2 @ 100P_0402_50V8J KSO12 19 18
KSO13 20 19
KSO3 C684 1 2 @ 100P_0402_50V8J KSI5 C685 1 2 @ 100P_0402_50V8J KSO14 21 20
KSO11 22 21
KSO4 C686 1 2 @ 100P_0402_50V8J KSI4 C687 1 2 @ 100P_0402_50V8J KSO10 23 22
KSO15 24 23
KSI0 C688 1 2 @ 100P_0402_50V8J KSO9 C689 1 2 @ 100P_0402_50V8J KSO16 25 24
EC DEBUG PORT <42>
<42>
KSO16
KSO17
KSO17 26 25
KSO0 C690 1 2 @ 100P_0402_50V8J KSI1 C691 1 2 @ 100P_0402_50V8J 27 26
28 27
29 28 31
30 29 GND 32
CONN PIN define need double check Reserve for ESD. 30 GND
JP3
1 ACES_88514-3001
+3VALW 1
2
<36,42> EC_TX 2
3
<36,42> EC_RX 4 3
4
Power Bottom Board Conn. 8pin
ACES_85205-0400
ME@
Card Reader/Audio Jack SB CONN
+5VALW

JPWRB1
1
2 1
<42> NUM_LED# 2
3 JCR1
<42> CAPS_LED# 3
<42> PWR_LED# 4 HP_OUTL 1
+3VLP +3VALW 4 <41> HP_OUTL 1
5 HP_OUTR 2
ON/OFF switch +3VALW
NOVO_BTN#
ON/OFFBTN#
6
7
5
6
<41> HP_OUTR
<41> PLUG_IN PLUG_IN 3
4
2
3

2
+3VLP 8 7 EXT_MIC_L 5 4
8 <41> EXT_MIC_L 5
R642 EXT_MIC_R 6
<41> EXT_MIC_R 6
R532@ 100K_0402_5% 9 <41> MIC_JD MIC_JD 7
2

SMT1-05_4P SW3 @ 100K_0402_5% 10 GND 8 7

2

1 3 GND +3VS USB20_P11 2 R4954 1 0_0402_5% USB20_P11_C 9 8

1
<18> USB20_P11 9
R701 D26 USB20_N11 2 R4955 1 0_0402_5% USB20_N11_C 10
Power Button 2 4 100K_0402_5% R535 @ NOVO# 2
<18> USB20_N11
11 10
<42> NOVO# 11
100K_0402_5% 1 NOVO_BTN# 12
1

3 NOVO_BTN# ON/OFFBTN# ACES_88058-080N 13 12

6
5

R725 EMI 14 GND

1000P_0402_50V7K
3

2
R720 ON/OFF# 1 2 ME@ WCM-2012-900T_4P GND
TOP Side J11

1
DAN202UT106_SC70-3 USB20_N11 4 3

C987
0_0402_5% D24 USB20_N11_C ACES_88058-120N
1 2 1 2 51_ON# 1 2 4 3
PJSOT24C 3P C/A SOT-23
@ 0_0402_5% R722 @ @ ME@

2
SHORT PADS 0_0402_5% USB20_P11 1 2 USB20_P11_C
Bottom Side 1 2

1
L81 @
3 ON/OFF#
1 ON/OFF# <42>
ON/OFFBTN#
2 51_ON#
51_ON# <47>
D23 @
DAN202UT106_SC70-3
1

D
EC_ON 2
<42,50> EC_ON
G
Q106 @ S
3
2

2N7002_SOT23-3
R639 @
10K_0402_5%
1

+5VS
To TP/B Conn.

JTP1 ME@ LED B/D Conn,

C696
8 +3VALW JLED1
0.1U_0402_16V4Z 7 GND 1
GND +5VALW 1
2
+3VALW 2
6 R617 +5VS 3
TP_CLK 5 6 1 2 LID_SW# 4 3
<42> TP_CLK 5 <42> LID_SW# 4
TP_DATA 4 5
<42> TP_DATA 4 5
1 1 3 100K_0402_5% 6
3 <42> PWR_LED# 6
SW/L 2 7
2 <42> BATT_LOW_LED# 7
@ C697 C698 @ SW/R 1 <42> BATT_CHG_LED# 8
100P_0402_50V8J 100P_0402_50V8J 1 RF_LED# 9 8
2 2 <42> RF_LED# 9
ACES_88058-060N <14> HDD_LED# 10
3

SW/L 11 10
C490

C491
.1U_0402_16V7K

.1U_0402_16V7K

SW/R 12 11
1 1 12
13 15
@ D15 14 13 G1 16
PSOT24C_SOT23-3 @ @ 14 G2
2 2 ACES_85202-1405L
1

ME@

pin 1 2 3 4 5 Security Classification Compal Secret Data Compal Electronics, Inc.

2011/10/27 2012/10/27 Title
14 VDD CLK DAT L R GND
Issued Date Deciphered Date ROM/KBD/PWR/CR/LED/TP Conn.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 43 of 60
 A B C D E

1 1
Left Ext.USB Conn.

+USB_VCCB
+5VALW
+USB_VCCB JUSB3
+USB_VCCB
W=80mils 1 5
Left USB PORT X1 VCC GND1
1
C983 1 USB20_N1 R4951 2 @ 1 0_0402_5% USB20_N1_C 2 6
+ <18> USB20_N1 D- GND2
U66
1 8 220U_6.3V_M C984 USB20_P1 R4952 2 @ 1 0_0402_5% USB20_P1_C 3 7
GND VOUT <18> USB20_P1 D+ GND3
C985 0.1U_0402_16V4Z 2 7 470P_0402_50V7K
2 1 3 VIN VOUT 6 6.3ĭ * 5.9 2 2 4 8
VIN VOUT GND GND4

2
4 5 USB_OC0# SF000001500
<42,45> USB_ON# EN FLG USB_OC0# <18>
G547I2P81U_MSOP8 OCTEK_USB-04APEB
ME@
1 USB20_N1 4 3 USB20_N1_C
C986 4 3

2
@ 1000P_0402_50V7K 2
USB20_P1 1 2 USB20_P1_C
2 1 2 D72 @

1
L80 WCM-2012-900T_4P PJDLC05_SOT23-3

Update to SM070001S00 for EMI request

Right Ext.USB Cable Conn.

3 3

JUSB4
+5VALW +USB_VCCA 8
+USB_VCCA 7 GND
RIGHT USB PORT X1 GND
+USB_VCCA
W=80mils 6
5 6
1 5
U67 C732 1 USB20_N9 R870 2 @ 1 0_0402_5% USB20_N9_C 4
1 8 + <18> USB20_N9 3 4
USB20_P9 R871 2 @ 1 0_0402_5% USB20_P9_C
GND VOUT <18> USB20_P9 3
C731 0.1U_0402_16V4Z 2 7 220U_6.3V_M C733 2
2 1 3 VIN VOUT 6 470P_0402_50V7K 1 2
VIN VOUT 1

2
USB_ON# 4 5 USB_OC4# 2 2
<42,45> USB_ON# EN FLG USB_OC4# <18> 6.3ĭ * 5.9 ACES_88058-060N
G547I2P81U_MSOP8 SF000001500 ME@
WCM-2012-900T_4P
1 USB20_P9 4 3 USB20_P9_C
C730 4 3
@ 1000P_0402_50V7K
USB20_N9 1 2 USB20_N9_C
2 1 2 D28 @

1
L67 PJDLC05_SOT23-3

4
Update to SM070001S00 for EMI request 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB ext. ports
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 44 of 60
A B C D E
 5 4 3 2 1

+1.05VDD
+1.5V to +1.05V Transfer @ D27 @ D30 D22
@
D31
@
+5VALW +1.5V +5VALW +1.05V

EU3@
U52 U3RXDN1 9   1 U3RXDN1 U3RXDN2 9   1 U3RXDN2 U2DN1 3 6 U2DP2 3 6
I/O2 I/O4 I/O2 I/O4
1U_0402_6.3V6K

10U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

C799

.1U_0402_16V7K

C802

.1U_0402_16V7K

C797

.1U_0402_16V7K

C798

0.01U_0402_16V7K

C805

0.01U_0402_16V7K

C800

0.01U_0402_16V7K

C803

0.01U_0402_16V7K

C806

0.01U_0402_16V7K

C808

0.01U_0402_16V7K
EU3@
+1.5V
C863

C864

C796

C794
1 1 6 1 1 1 1 1 1 1 1 1 1 1 U3RXDP1 8   2 U3RXDP1 U3RXDP2 8   2 U3RXDP2
5 VCNTL 3
VIN VOUT U3TXDN1 7 
9 4  4 U3TXDN1 U3TXDN2 7   4 U3TXDN2 2 5 +5VALW 2 5 +5VALW
+5VALW VIN VOUT GND VDD GND VDD
2 2 SYSON 8 2 2 2 2 2 2 2 2 2 2 2 U3TXDP1 6   5 U3TXDP1 U3TXDP2 6   5 U3TXDP2
EN

10U_0603_6.3V6M

EU3@

EU3@

EU3@

EU3@

EU3@

EU3@

EU3@

EU3@

EU3@

EU3@

EU3@
2 1 7 2 1 R1149 2

GND
POK FB

C886 EU3@
EU3@ R1150 5.11K_0402_1% 10K_0402_1% 1  3  3 1 4 U2DP1 1 4 U2DN2
I/O1 I/O3 I/O1 I/O3

1
EU3@ EU3@
APL5930KAI-TRG_SO8 R1151 8 8

1
D 32.4K_0402_1% AZC099-04S.R7G_SOT23-6 AZC099-04S.R7G_SOT23-6 D
EU3@ 2
Vout=0.8(1+10K/32.4K)
YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9
1.042 ~ 1.0469 ~ 1.0519V For EMI request

2
+3V +3V +3AVDD Close to U32.3 Close to U32.25
Spec: 0.9975 ~ 1.05 ~ 1.1025 L60 EU3@
1 2
FBMA-L11-201209-221LMA30T_0805

C887

10U_0603_6.3V6M

C816

.1U_0402_16V7K

C817

.1U_0402_16V7K

C809

0.01U_0402_16V7K

C810

0.01U_0402_16V7K

C811

0.01U_0402_16V7K

C812

0.01U_0402_16V7K

C813

0.01U_0402_16V7K

C888

10U_0603_6.3V6M

C821

.1U_0402_16V7K

C825

0.01U_0402_16V7K

C823

.1U_0402_16V7K

C827

1 1
нϯs>tƚŽнϯsdƌĂŶƐĨĞƌ
2 2
0.01U_0402_16V7K
Update to SM070001S00 for EMI request
1 1 1 1 1 1 1 1 1 1 1
Intel_PCH_USB2.0
1 R728 2
0_0402_5%
@
2 2 2 2 2 2 2 2 2 2 2
WCM-2012-900T_4P

EU3@

EU3@

EU3@

EU3@

EU3@

EU3@

EU3@

EU3@

EU3@

EU3@

EU3@

EU3@

EU3@
R730
+3VALW +3V 2 IU3@ 1 U2DN2_L 1 2 U2DN2
<18> USB20_N3 1 2
0_0402_5%
U30 EU3@ R640
0.2A 2 IU3@ 1 U2DP2_L 4 3 U2DP2
+1.05V <18> USB20_P3 4 3
3 1 0_0402_5%
4 VIN VOUT 5 L55
<42,46,51> SYSON VIN/CE VOUT 1 R721 2

2
2 0_0402_5% @
GND R766
RT9701-PB_SOT23-5 0_0603_5%
+3V EU3@ +1.05VDD +3AVDD 1 R742 2 @
0_0402_5% +USB3_VCCA

1
U32 Intel_PCH_USB3.0
EU3@ R709 WCM-2012-900T_4P
W=80mils
2 IU3@ 1 U3RXDN2_L 1 2 U3RXDN2 LP2

25
12

22

34

43

21

30

33

39

42
<18> USB3_RX4_N

3
1 2

9
0_0402_5%
+3V +3V R714 JUSB2

AVDD33

AVDD33
VDD33

VDD33

VDD33

VDD33

VDD10

VDD10

VDD10

VDD10

VDD10

VDD10

VDD10
2 IU3@ 1 U3RXDP2_L 4 3 U3RXDP2 1
C <18> USB3_RX4_P 4 3 VBUS C
10/11 Corrected. 0_0402_5% U2DN2 2
2

L54 U2DP2 3 D-
R1187 1 EU3@ 1 R743 2 4 D+
<15> CLK_PCIE_USB30 PECLKP GND
EU3@ 10K_0402_5% 2 37 U3TXDP2_R C844 1 2 .1U_0402_16V7K U3TXDP2_L 0_0402_5% @ U3RXDN2 5
<15> CLK_PCIE_USB30#
2

Q125 EU3@ EU3@ PECLKN U3TXDP2 EU3@ U3RXDP2 6 SSRX- 10

G

SSM3K7002FU_SC70-3 .1U_0402_16V7K2 1 C835 PCIE_PRX_C_DTX_P4 4 38 U3TXDN2_R C846 1 2 .1U_0402_16V7K U3TXDN2_L 1 R636 2 @ 7 SSRX+ GND 11
1

<15> PCIE_PRX_DTX_P4 PETXP U3TXDN2 GND GND

1 3 .1U_0402_16V7K2 1 C834 PCIE_PRX_C_DTX_N4 5 45 U2DN2_R R774 2 1 0_0402_5% U2DN2_L 0_0402_5% U3TXDN2 8 12
<16,36,37> PCIE_WAKE# <15> PCIE_PRX_DTX_N4 PETXN U2DM2 SSTX- GND
PCIE_WAKE#_USB3 EU3@ EU3@ U3TXDP2 9 13
D

7 44 U2DP2_R R776 2 EU3@ 1 0_0402_5% U2DP2_L C850 IU3@ WCM-2012-900T_4P SSTX+ GND
<15> PCIE_PTX_C_DRX_P4 PERXP U2DP2
8 40 U3RXDP2_R R772 2 EU3@ 1 0_0402_5% U3RXDP2_L 1 2 U3TXDN2_L 1 2 U3TXDN2 OCTEK_USB-09EAEB
<15> PCIE_PTX_C_DRX_N4 PERXN U3RXDP2 <18> USB3_TX4_N 1 2
.1U_0402_16V7K ME@
1 10/20 add 10k pu 41 U3RXDN2_R R763 2 EU3@ 1 0_0402_5% U3RXDN2_L
+3V U3RXDN2 1 2 U3TXDP2_L 4 3 U3TXDP2
+3V <18> USB3_TX4_P 4 3
C837 EU3@ PLT_RST#_USB3 47 .1U_0402_16V7K
1 R4970 2 PCIE_WAKE#_USB3 48 PERSTB R1161 EU3@ C848 IU3@ L53
1000P_0402_50V7K PEWAKEB
2 10K_0402_5% CLKREQ_USB3 10 17 OCI2B 1 2 10K_0402_5%
EU3@ PECREQB OCI2B 19 OCI1B 1 2 10K_0402_5% 1 R638 2
OCI1B R1162 EU3@ 0_0402_5% @
UPD720202K8-701-BAA_QFN48_7X7 18
EU3@ SMIB 46 PPON2 20
<18> SMIB SMIB PPON1
1 R747 2 PLT_RST#_USB3 10/14 R1172 modify to 300K
<18,23,36,37,42> PLT_RST#
430K_0402_5% Intel_PCH_USB2.0
10/14 R747 modify to 430K +3V R1172 1 EU3@ 2 300K_0402_5% 11 1 R563 2 @
PONRSTB 28 U3TXDP1_R C843 EU3@ 1 2 .1U_0402_16V7K U3TXDP1_L 0_0402_5%
1
C832 to 1U. U3TXDP1

1U_0402_6.3V6K
1 2
D67 1 2
C894
C832 SPI_CLK_USB 15 29 U3TXDN1_R C845 EU3@ 1 2 .1U_0402_16V7K U3TXDN1_L WCM-2012-900T_4P
1 SPISCK U3TXDN1
1U_0402_6.3V6K 1SS355TE-17_SOD323-2 SPI_CS_USB# 14 36 U2DN1_R R759 2 EU3@ 1 0_0402_5% U2DN1_L 2 R741 1 U2DP1_L 1 2 U2DP1
2 SPICSB U2DM1 <18> USB20_P2 1 2
EU3@ EU3@ USB_SO_SPI_SI 16 IU3@
USB_SI_SPI_SO 13 SPISI 35 U2DP1_R R754 2 EU3@ 1 0_0402_5% U2DP1_L 0_0402_5%
2 SPISO U2DP1 31 U3RXDP1_R R760 2 EU3@ 1 0_0402_5% U3RXDP1_L 2 IU3@ 1 U2DN1_L 4 3 U2DN1
U3RXDP1 <18> USB20_N2 4 3
R755
EU3@ 32 U3RXDN1_R R762 2 EU3@ 1 0_0402_5% U3RXDN1_L 0_0402_5% L51
B +3V +3V USB3_XT1 24 U3RXDN1 1 R562 2 @ B
USB3_XT2 23 XT1 0_0402_5%
XT2
2

R1152 EU3@ 1 R564 2 @ +USB3_VCCA

1

EU3@ 27 26 1 2 Intel_PCH_USB3.0 0_0402_5%

EU3@ R745 EU3@ R1180 IC(L) RREF
Q121 10K_0402_5% 100_0402_1% 1.6K_0402_1% R773 WCM-2012-900T_4P

GND
LP1
2

SSM3K7002FU_SC70-3 2 IU3@ 1 U3RXDN1_L 1 2 U3RXDN1

G

W=80mils
1

<18> USB3_RX3_N 1 2
0_0402_5%
2

1 3 CLKREQ_USB3 Y7 R739 JUSB1

49
<15> CLKREQ_USB30# 1 2 2 IU3@ 1 U3RXDP1_L 4 3 U3RXDP1 1
D

<18> USB3_RX3_P 4 3 VBUS

1 0_0402_5% U2DN1 2
24MHZ_12PF_X5H024000DC1H L50 U2DP1 3 D-
C836 1 R561 2 @ 4 D+
1 EU3@ 1 GND
1000P_0402_50V7K C897 C898 0_0402_5% U3RXDN1 5
2 12P_0402_50V8J 15P_0402_50V8J U3RXDP1 6 SSRX- 10
EU3@ SSRX+ GND
EU3@ EU3@ W=80mils 1 R565 2 @ 7 11
2 2 0_0402_5% U3TXDN1 8 GND GND 12
+5VALW +USB3_VCCA .1U_0402_16V7K U3TXDP1 9 SSTX- GND 13
C849 IU3@ WCM-2012-900T_4P SSTX+ GND
C704 U35 1 2 U3TXDN1_L 1 2 U3TXDN1 OCTEK_USB-09EAEB
<18> USB3_TX3_N 1 2
10/14 Modify to +3V from +3VALW .1U_0402_16V7K 1 8 ME@
1 2 2 GND VOUT 7
3 VIN VOUT 6 1 2 U3TXDP1_L 4 3 U3TXDP1
VIN VOUT <18> USB3_TX3_P 4 3
+3V +3V +3V USB_ON# 4 5 USB_OC1#
<42,44> USB_ON# EN FLG USB_OC1# <18>
C847 IU3@ L49
for DFT G547I2P81U_MSOP8 for DFT .1U_0402_16V7K 1 R546 2 @
0_0402_5%
2

2
10K_0402_5%
R1177

1 EU3@
C895 2A/Active Low 1 Place TX AC coupling Cap (C843~C850). Close to connector
EU3@ .1U_0402_16V7K R1175 R1176 1
EU3@ 10K_0402_5% 47K_0402_5% C736 + C735
A 2 EU3@ 220U_6.3V_M 470P_0402_50V7K A
1

U53 EU3@ 6.3ĭ * 5.9

8 1 SPI_CS_USB# SF000001500 2 2
7 VCC CS# 2 USB_SI_SPI_SO
SPI_CLK_USB 6 HOLD# SO 3
USB_SO_SPI_SI 5 SCK WP# 4
SI GND
AT25F512AN-10SU-2.7_SO8~D
Security Classification Compal Secret Data Compal Electronics, Inc.
12/07 update to SA00002AA00 Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0/Left USB Ports
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 05, 2012 Sheet 45 of 60
5 4 3 2 1
 A B C D E

+5VALW TO +5VS
+3VALW TO +3VS +3VALW TO +3VALW(PCH AUX Power) 11/28 @
+5VALW +5VS +3VALW +3VS
U38
U39
DMN3030LSS-13_SOP8L-8 DMN3030LSS-13_SOP8L-8 +3VALW @ +3V_PCH
PJ1
8 1 8 1
1 7 2 1 1 1 7 2 1 1 2 1

1
6 3 C723 6 3
C720 5 C721 C722 5 C724 C725 JUMP_43X118
1 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V6K R644 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V6K R645 EVT short PJ1, U40 @ 1
2 2 2 470_0603_5% 2 2 2 470_0603_5%
9/22 NA

4
@ @ U40

1 2

1 2
DMN3030LSS-13_SOP8L-8
+VSB D +VSB D @ 8 1

1
2 SUSP 2 SUSP 1 7 2 1
1

1
G G C782 6 3
R646 S Q107 S Q108 5 C780 @ R777

3
150K_0402_5% 2N7002_SOT23 R647 2N7002_SOT23 10U_0603_6.3V6M 1U_0402_6.3V6K 470_0603_5%
@ 470K_0402_1% @ 2 @ 2 @
1

1 2
2

2
5VS_GATE 2 R649 15VS_GATE_R C783 D

2
+VSB 10U_0603_6.3V6M 2 PCH_PWR_EN#
1 1
1

1
D D R650 2 @ G
82K_0402_5%

1
SUSP 2 Q110 C726 SUSP 2 Q111 0_0402_5% C727 S Q118

3
G 2N7002_SOT23 0.01U_0402_25V7K G 2N7002_SOT23 0.01U_0402_25V7K 2N7002_SOT23
2 @ 2 @ R778 @
S S 9/22 NA
3

1
470K_0402_1%

2
1

1
D R779
PCH_PWR_EN# 2 Q120 0_0402_5% C781
G 2N7002_SOT23 0.01U_0402_25V7K
@ S @ @ 2

1
+1.5V to +1.5VS
+1.8VS +1.5V +1.05VS +0.75VS

+1.5V Q8 +1.5VS
1

1
PMV65XP_SOT23-3~D +5VALW

D
2 R655 R656 R659 R658 3 1 2

1
470_0603_5% 470_0603_5% 470_0603_5% 22_0603_5% 1 1 1

1
@ @ @
1 2

1 2

1 2

1 2
C717 C718 C719 R780 @

G
2
D D D D 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V6K R643 100K_0402_5%
2 SUSP 2 SYSON# 2 SUSP 2 SUSP 2 2 2 470_0603_5%

2
G G G G @

2
S Q113 S Q114 S Q116 S Q115 PCH_PWR_EN#
3

3
2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23

1
@ @ @ +3VALW D

1
2 SUSP D
G PCH_PWR_EN 2 @
<42,48> PCH_PWR_EN

1
S Q109 G

3
For Intel S3 Power Reduction. 2N7002_SOT23 Q124 S

3
1
100K_0402_5% @ 2N7002_SOT23
R648
R781

2
2 R651 1 1.5VS_GATE 100K_0402_5%
+RTCVCC +5VALW +5VALW Q112

2
1

1
D 0_0402_5%
SUSP# 2 C728 C729
2

G 0.1U_0402_25V6

2
Check R652 @ @ 2N7002_SOT23S

3
220K_0402_5% R653 R654 0.1U_0402_25V6
100K_0402_5% 100K_0402_5%
+1.5V to +1.5VS_VGA Transfer
1

SUSP SYSON#
<10,53,54> SUSP
1

Q117 +1.5V +1.5VS_VGA

1

DTC124EKAT146_SC59-3 @ Q119
OUT

DTC124EKAT146_SC59-3
OUT

3 SYSON 2 J12 @ 3
2
<42,45,51> SYSON IN 300mil(7.2A) 2 1
GND

0,25,42,51,52,53,54> SUSP# IN 2 1
1 1
GND

JUMP_43X118 C851
C856 10U_0603_6.3V6M
3
1

10U_0603_6.3V6M AO4430: Rdson: 5.5mohm @ VGS=10V N13P@

3

2 2
R1110 @ AO4304L_SO8
100K_0402_5% N13P@ U49 N13P@ 300mil(7.2A)
8 1
2

7 2
6 3

2
5 1 1
C854 R1101 @
9/27 BOM Structure 1
C853 0.1U_0402_16V4Z 470_0603_5%

4
change to N13P@ C852
10U_0603_6.3V6M 2
10U_0603_6.3V6M
2

1
2
+5VALW 2
R4963 N13P@ N13P@
+VSB N13P@ 0_0402_5%
1

@
R1102 10K_0402_5%

1
R1107 2 1

1
100K_0402_5% D @
N13P@ N13P@ @ Q127 2 2 R790 1 DGPU_PWROK#
2

1
2N7002_SOT23 G 0_0402_5%
DGPU_PWROK# Q126 C855 S
DGPU_PWROK# <54>

3
R1106 2N7002_SOT23 0.1U_0402_25V6

2
1

1
0_0402_5% D N13P@ D N13P@ 2 R791 @1 SUSP
2 1 2 Q129 DGPU_PWROK# 2 R782 1 2 0_0402_5%
<19,54> DGPU_PWROK
G 2N7002_SOT23 N13P@ 0_0402_5% G
N13P@ S N13P@ S
3

3
4 4
1

SUSP 2 R789 @1
0_0402_5%
R1108
100K_0402_5%
@
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 46 of 60
A B C D E
 5 4 3 2 1

DC030006J00 VIN

PF101 PL101
7A_24VDC_429007.WRML SMB3025500YA_2P
4 APDIN 1 2 APDIN1 1 2
4
3
3

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
2
2

1
D 1 D
1
4602-Q04C-09R 4P P2.5

2
PC101

PC102

PC103

PC104
JDCIN1 ME@

VIN
Unpop for KB9012

2
@
PD103
LL4148_LL34-2

@ PD104 PJ101

1
LL4148_LL34-2 @ JUMP_43X39 51ON-1
C
BATT+ 2 1 1
1 2
2 C

1
@ PR118 @ PR119
PQ104 68_1206_5% 68_1206_5%
TP0610K-T1-GE3_1P_SOT23-3
@PR120
@ PR120 @

2
200_0603_5%
CHGRTCP 1 2 51ON-2 3 1
VS
0.22U_0603_25V7K

@
1

@
2

1
PC112

PR123 @ PC113
100K_0402_1% 0.1U_0603_25V7K
1

2
@ PR124
2

22K_0402_1%
1 2 51ON-3
+3VLP <43> 51_ON#
2

PR127 RTCVREF
1

0_0402_5%
@ PU102 @ PR128
200_0603_5%
1

APL5156-33DI-TRL_SOT89-3
3.3V
2

3 2 CHGRTCIN
VOUT VIN
1

@ GND PC115
B PC114 @ 1U_0805_25V6K B
10U_0603_6.3V6M 1
2

+CHGRTC
- JRTC2 + PR131
560_0603_5%
PR132
560_0603_5%
PD109
RB751V-40_SOD323-2
2 1 1 2 1 2 2 1 +RTCBATT

@ MAXEL_ML1220T10 +CHGRTC_R 1 2
RTCVREF
PD108
RB751V-40_SOD323-2

RTC Battery

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR DCIN / Vin Detector /Pre-charge
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C38-G series Chief River Schematic0.1
Date: Thursday, January 05, 2012 Sheet 47 of 60
5 4 3 2 1
 5 4 3 2 1

VMB2 VMB
PF201 PL201
JBATT1 12A_65V_451012MRL SMB3025500YA_2P
1 1 2 1 2
1 2 BATT+
2 3 EC_SMCA
3 4 EC_SMDA
4 5
5

1
D 6 D
6

1
7 PC201 PC202
7

100_0402_1%

100_0402_1%
8 1000P_0402_50V7K 0.01U_0402_25V7K
ADP_I need to write Charge Options Register (0x12H)=> bit6=1

2
GND 9
GND PR201

PR202
TYCO_1775789-1
2

2
ME@ 0: IOUT is the 20x current amplifier output <default @ POR>
1: IOUT is the 40x current amplifier output

For KB930 --> Keep PU201 circuit

PH1 under CPU botten side :
(Vth = 0.825V)
EC_SMB_CK1 <42,49> CPU thermal protection at 93 +-3 degree C
For KB9012 (Red square) --> Remove PU201 circuit, but keep PR206
Recovery at 56 +-3 degree C
EC_SMB_DA1 <42,49> PH201, PR205, PR211,PQ201,PR208,PR212
1 2
+3VALW
VL
PR203
6.49K_0402_1%
+3VLP
<42,49> ADP_I

21.5K_0402_1%
90W(DIS) : 4.42K

1
4.42K_0402_1%

12.7K_0402_1%
1

PR207
1 2
BATT_TEMP <42> A/D 65W(UMA) : 402 ohm <Bom structure>

PR205

PR206
PR204

1
10K_0402_5% @
PC203 +3VS <BOM Structure>

2
0.1U_0603_16V7K PU201

2
1 8 NTC_V_1
VCC TMSNS1 <Bom Structure>

100K_0402_1%
C <BOM Structure> 2 7 OTP_N_002 2 1 C
GND RHYST1

PR208
PR209
3 6 Turbo_V_1 10K_0402_1%
<6,42,49> H_PROCHOT# OT1 TMSNS2

0_0402_5%
PR210

100K_0402_1%_TSM0B104F4251RZ
4 5 ADP_OCP_2 1 2 @

1
OT2 RHYST2

PH201
PQ201

2
D

10K_0402_1%
0_0402_5%
PR229

PR227
G718TM1U_SOT23-8 27.4K_0402_1%

PR211
2 ADP_OCP_1
90W(DIS) : 27.4K

OTP_N_003
G
S SSM3K7002FU_SC70-3 65W(UMA) : 5.11K @

2
2

1
PR212 PR228
0_0402_5% 47K_0402_1%
<42> PROCHOT 1 2 2 1 1 2
@
MAINPWON <42,50>
PR230 +3VALW
PR213 0_0402_5% 1 2
<Bom Structure>

1
0_0402_5%
PR232
47K_0402_1%
@

<42>
NTC_V

2
<42>
Turbo_V
<Bom structure>

+3VLP

B B

P2
PQ205
+3VLP +3VALW
0.01U_0402_25V7K

TP0610K-T1-GE3_1P_SOT23-3
1

PC204

3 1
B+ +VSBP
2

VMB2

100K_0402_1%

0.22U_0603_25V7K
PR214 PR215
2

1
100K_0402_1% 100K_0402_1%

1
PR216

PC205
PR217 PR218 <BOM Structure>
2

768K_0402_1% 10M_0402_5% PC206

1

1 2 0.1U_0603_25V7K

2
BATT_OUT <49>
PR219

2
10K_0402_1% PR220
8

1 2 PQ202 VL 22K_0402_1%
1

3 D 2N7002KW_SOT323-3 1 2
P

+ 1 2
O
2

PR221 2 G
-
G
2

221K_0402_1% PU202A S PR222

3

LM393DG_SO8 100K_0402_1%
4

+3VLP PR224 @
1

PQ203 1K_0402_5% D PJ201

1

D 2N7002KW_SOT323-3 1 2 2 PQ204 @ JUMP_43X39

2 1 2 <50> SPOK 1 2
G 2N7002W-T/R7_SOT323-3
2VREF_8205 +VSBP 1 2 +VSB
2

1U_0402_6.3V6K

G S
3
1

PC207

PR223 PR226 S PR231

3

10K_0402_1% 100K_0402_1% 1K_0402_5%

2 1 1 2
2

RTCVREF <50> PCH_PWR_EN

1

A PR225 A
10K_0402_1%
@

<42> BATT_LEN#

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-BATTERY CONN/OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C38-G series Chief River Schematic0.1
Date: Thursday, January 05, 2012 Sheet 48 of 60
5 4 3 2 1
 5 4 3 2 1

P3
B+ Need EC write ChargeOption() bit[8]=1
P2
Setting (ACP to PHASE Rising Threshold)=1350mV(min)
PQ301 PQ302
AO4407A_SO8 AO4423L_SO8
8 1 1 8 PR302
VIN 7 2 2 7 0.01_1206_1% CHG_B+
6 3 3 6
SH00000AA00
5 5 1 4 1 2 PQ303
PL301 AO4407A_SO8
2 3 1UH_PCMB061H-1R0MS_7A_20% 1 8

4
2 7
3 6

@ 10U_0805_25V6K

@ 10U_0805_25V6K

2200P_0402_50V7K
PQ304 5

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
D D
1 2
47K_0402_5%
1

2
200K_0402_1%
0.1U_0603_25V7K

PC307

4
1
PR301

PC302

PC315

PC303

PC305

PC306
DTA144EUA_SC70-3 PC304 DISCHG_G

PC301

PR303
5600P_0402_25V7K

1
PR304
47K_0402_1%
2

2
2 1 2

2
ACN VIN

2ACOFF-1

1SS355_SOD323-2
2
1

ACP PR305

1DISCHG_G-1
10K_0402_1%
1

2
PD301
P2-1 PR306

0.1U_0603_25V7K

1
2 200K_0402_1%
PQ305 PQ306

1
+3VALW PC308 PC309 DTC115EUA_SC70-3

1
DTC115EUA_SC70-3
PR307 <50> ACPRN 1 2 2 1 PD302
3

20K_0402_1% 1SS355_SOD323-2
1 2 0.1U_0603_25V7K 2 1 2
6

PQ308
1

D
150K_0402_1%

2N7002KW _SOT323-3 PC310 PQ309

PR308

PQ307A 2
2 BATT_OUT <48>
2N7002KDW -2N_SOT363-6 G 0.1U_0603_25V7K P2 2N7002W -T/R7_SOT323-3

1
D

0.1U_0603_25V7K
S
3

2 1 2 PACIN
1

1
PC311
VIN @ @ G

10K_0402_5%

10K_0402_5%
S

3
2

2
390K_0603_1%

2
1
P2-2

PR315

PR316

10_1206_5%
2

5
6
7
8
C C
PR314
2N7002KDW-2N_SOT363-6

2
5

PQ310
PR319

AO4466L_SO8
3
PQ307B

<BOM Structure>

CMPOUT

ACP
CMPIN
ACOK

ACN
1

1
PR318 <42,48> ADP_I
2

47K_0402_1% PR317 21

1
PACIN 1 2 5 1 2 6 TP 4
PACIN ACDET PC313
64.9K_0603_1% PC312 20 BQ24727VCC 1 2
SH000005Z80
4

PC323 1 2 7 VCC PL302

ACON IOUT
1 2 10UH_PCMB104T-100MS_6A_20% PR320

3
2
1
1U_0603_25V6K
1

PQ311 100P_0603_50V8 19 0.01_1206_1%

PHASE
DTC115EUA_SC70-3 0.1U_0603_25V7K
<42,48> EC_SMB_DA1
8
SDA
PU301
1 2 1 4
BATT+
BQ24727RGRR_VQFN20_3P5X3P5 LX_CHG CHG
PR321 18 DH_CHG
HIDRV

5
6
7
8
1 2ACOFF-12 9 2 3
<42> ACOFF SCL SA000051W00

1
<42,48> EC_SMB_CK1

PQ312
10K_0402_5% PR324 PC314

AO4466L_SO8

4.7_1206_5%
PR322
PR323 2.2_0603_5% 0.047U_0603_16V7K
1

1 2 10 17 BST_CHG 1 2 2 1 SRP SRN

10U_0805_25V6K

10U_0805_25V6K
ILIM BTST
1

16251_SN
PR325 +3VALW 316K_0402_1%
PD303
3

PR326 4

LODRV
0_0402_5%

1
16 2 1

PC316

PC317
100K_0402_1%

GND
SRN

SRP
REGN

BM
2N7002KW_SOT323-3
2

2
PQ313 RB751V-40_SOD323-2

680P_0603_50V7K
1 12

13

14

15
11

3
2
1
1

1
D

PC319
10_0603_5%
6.8_0603_5%

2
2 BQ24727VDD

PR328
PC318
<48> BATT_OUT
PR327
G 1U_0603_25V6K

2
S
3

2
2

PC320 DL_CHG
B 0.1U_0603_25V7K B
2 1

CHGVADJ=(Vcell-4)/0.10627
1

Vcell CHGVADJ

1
PC321 @
4V 0V 0.1U_0603_25V7K PC322
2

2 0.1U_0603_25V7K
4.2V 1.882V
4.35V 3.2935V
BQ24727VDD

CC=0.25A~3A PR337
10K_0402_1%
1

IREF=1.016*Icharge 1 2
ACIN <16,42>
PR336
IREF=0.254V~3.048V PR335 10K_0402_1%
47K_0402_1%
VCHLIM need over 95mV PACIN
2

1 2

ACPRN <50> PR339

2
12K_0402_1%
2

PQ316

A DTC115EUA_SC70-3 A
3

For disable pre-charge circuit.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C38-G series Chief River Schematic
Date: Thursday, January 05, 2012 Sheet 49 of 60

5 4 3 2 1
 5 4 3 2 1

Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO

2VREF_8205 PJ402
+3VALW P 2 1 +3VALW
2 1
@ JUMP_43X118

1U_0603_10V6K
D D

1
PJ403

PC401
+5VALW P 2 1 +5VALW

2
2 1
@ JUMP_43X118

PR401 PR402
13K_0402_1% 30K_0402_1%
1 2 1 2

PR403 PR404
RT8205_B+ 20K_0402_1% 19.6K_0402_1% RT8205_B+
1 2 1 2
PJ401 Typ: 175mA
B+ 2 1 +3VLP
0.1U_0603_25V7K

2 1

ENTRIP2

ENTRIP1
@ JUMP_43X118
PC405

PR405 PR406
2200P_0402_50V7K

2200P_0402_50V7K
0.1U_0603_25V7K

0.1U_0603_25V7K
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

130K_0402_1% 66.5K_0402_1%
1 2 1 2
PC402

PC410
4.7U_0805_10V6K
1

1
PC403

PC404

PC406

PC407

PC408

PC409
2

1
8
7
6
5

5
6
7
8
4

3
PU401
2

2
PC411

ENTRIP2

ENTRIP1
FB2

FB1
TONSEL

REF
1
C PQ401 C

TPC8065-H_SO8
25

PQ402
AO4466L_SO8 P PAD

2
4 4
7 24
VO2 VO1 SPOK <48>
8 23 PR408 PC413
PR407 VREG3 PGOOD 2.2_0603_5% 0.1U_0603_25V7K
1
2
3

3
2
1
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2
2.2_0603_5% BOOT2 BOOT1
PL401 PC412 UG_3V 10
VFB=2.0V 21 UG_5V PL402
4.7UH +-20% PCMC063T-4R7MN 5.5A 0.1U_0603_25V7K UGATE2 UGATE1 3.3UH_PCMB064T-3R3MS_7A_20%
1 2 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP PHASE2 PHASE1
1

8
7
6
5

1
LG_3V 12 19 LG_5V
4.7_1206_5%

4.7_1206_5%
LGATE2 LGATE1

5
6
7
8
PQ403
PR409

PR410
SKIPSEL
AO4712L_SO8

VREG5

PQ404
GND

VIN

NC
RT8205EGQW _W QFN24_4X4

EN
1 1 1
2

2
4 @
+ PC415 4 PC424 + + PC417

13

14

15

16

17

18
1

1
150U_B2_6.3VM_R35M PR411 150U_V_6.3VM_R18 150U_V_6.3VM_R15

TPC8A03-H_SO8
680P_0603_50V7K

499K_0402_1%

680P_0603_50V7K
2 1 2 2 2
PC418

PC419
2

1
2
3

2
B+

3
2
1
1
100K_0402_1%

1U_0603_10V6K
VL

1
PC420

1
PR412

PC421
Typ: 175mA

4.7U_0805_10V6K
B B

2
ENTRIP1 ENTRIP2
2

2
For KB9012 RT8205_B+
<42,43> EC_ON
6

PR418

1
2.2K_0402_5% PQ405B
2 1 PQ405A 2N7002KDW -2N_SOT363-6

0.1U_0603_25V7K
2N7002KDW -2N_SOT363-6 2 5 2VREF_8205 +3.3VALWP OCP(min)=5.81A

2
PC422
+5VALWP OCP(min)=8.44A
1

<42,48> MAINPWON PR413

0_0402_5%
2 1

PR414
100K_0402_1%
2 1
VL
1
2N7002W-T/R7_SOT323-3

PR415
1

200K_0402_1% D
9> ACPRN 2 1 2 1 2 2
PQ407

PQ406
G VS DTC115EUA_SC70-3
S PR416
40.2K_0402_1%

4.7U_0603_6.3V6M
3

A A
1

100K_0402_1%
1

1
PR417

PC423

@ @
3
2

<42,43> EC_ON
2

2
PQ408
DTC115EUA_SC70-3
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/01/25 Deciphered Date 2012/07/11 Title
@ @

For KB9012 3VALWP/5VALWP

3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
@
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C38-G series Chief River Schematic
Date: Thursday, January 05, 2012 Sheet 50 of 60
5 4 3 2 1
 A B C D

PJ501
1.5V_B+ 2
2 1
1 B+

2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
5
6
7
8
@ JUMP_43X118

1
PC502

PC503

PC504

PC505
PQ501
TPC8065-H_SO8

2
4

3
2
1
1
PR503 PC506 PL501 1

100K_0402_1% PU501 2.2_0603_5% 0.22U_0603_16V7K 1UH_PCMC063T-1R0MN_11A_20%

PR505
1
PGOOD VBST
10 BST_1.5V 1 2BST_1.5V-1 1 2 1 2 +1.5VP
PR501 2 1 2 9 DH_1.5V
0_0402_5% TRIP DRVH
1 2 3 8 LX_1.5V

4.7_1206_5%
EN SW

1
<42,45,46> SYSON

PR504 @
1

5
6
7
8
4 7
VFB V5IN +5VALW
2
+
47K_0402_5%
PQ502 PC507

.1U_0402_16V7K
<BOM Structure>

1
PC501 @
PR502

1 PR5062 5 6 DL_1.5V 220U_D2_4VY_R15M +1.5VP OCP(min)=15.6A

RF DRVL

1
PC508

2
470K_0402_1% 11 1U_0603_10V6K 2
PR507

2
TP 4 PJ502

1000P_0603_50V7K
1

PC509 @
1 2 TPS51212DSCR_SON10_3X3 2 1
2 1

1
VFB=0.7V
@ JUMP_43X118
11.5K_0402_1%

1
TPC8A03-H_SO8

3
2
1

2
PJ503 +1.5V
PR508 +1.5VP 2 1
10K_0402_1% 2 1
@ JUMP_43X118

2 2

3 3

PU502 PL503
4

PJ505 1UH_PH041H-1R0MS_3.8A_20%
2 1 1.8VSP_VIN 10 2 1.8VSP_LX 1 2
+5VALW
PG

2 1 PVIN LX +1.8VSP
@ JUMP_43X118 9 3

68P_0402_50V8J
PVIN LX
1

1
680P_0603_50V7K 4.7_1206_5%
1

1
PC510 8 PC511
SVIN
PR509

22U_0805_6.3VAM PR510
6 20K_0402_1%
2

2
5 FB

22U_0805_6.3VAM

22U_0805_6.3VAM
1 2

EN

1
PJ504
NC

NC
TP

2 1

PC513

PC514
FB=0.6Volt +1.8VSP +1.8VS
2 1
<10,25,42,46,52,53,54> SUSP#
PC512

PR511
11

2
1 2 EN_1.8VSP @ JUMP_43X118
2

0_0402_5%
0.1U_0402_10V7K
2

PC515 @

SY8033BDBC_DFN10_3X3
1

PR512 <BOM Structure> 1.8VSP max current=4A

1M_0402_5%
1.8VSP_FB
2
1

4
PR513 4

10K_0402_1%
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-+1.5VP/+1.8VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C38-G series Chief River Schematic
Date: Thursday, January 05, 2012 Sheet 51 of 60
A B C D
 5 4 3 2 1

+3VS PR601
1K_0402_5%
2 1
VID [0] VID[1] VCCSA Vout PJ602
+VCC_SAP

100K_0402_5%
0 0 0.9V H_VCCSA_VID1 <10> +VCCSAP 2
2 1
1 +VCCSA

1
TDC 4.2A
@ JUMP_43X118

PR602
0 1 0.8V Peak Current 6A
1 0 0.725V OCP current 7.2A

2 +VCCSA_PWRGD
H_VCCSA_VID0 <10>
1 1 0.675V
PR603
<42> SA_PGOOD
1K_0402_5%
output voltage adjustable network 2 1
D D
The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that

+VCCSA_VID0
+VCCSA_VID1
+5VALW

+VCCSA_PWRGD
VCCSA VID is 00 prior to VCCIO stability.

1U_0603_10V6K
2

PC601
PR604 PR605
10_0402_1% 0_0402_5%

1
2 1 +VCCSA_EN 1 2
+V1.05S_VCCP_PWRGOOD <53>
PC602
2.2U_0603_10V7K
1 2

18

15

14
17

13
16
PU601
PR606 PC603

VID1

VID0

EN
V5DRV

V5FILT

PGOOD
0_0603_5% 0.22U_0603_16V7K
12 +VCCSA_BT 1 2+VCCSA_BT_1 1 2
19 BST PL601
PGND 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
SW
11 +VCCSA_PHASE 1 2 +VCCSAP
20
PGND

22U_0805_6.3V6M

22U_0805_6.3V6M

0.1U_0402_10V7K
1
10

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
2200P_0402_50V7K
SW
2200P_0402_50V7K

21 PR607 @ @ @ @
0.1U_0603_25V7K

2
PGND
10U_0805_6.3V6M

10U_0805_6.3V6M
4.7_1206_5%

PC605

PC606

PC608

PC609

PC611

PC612
TPS51461RGER_QFN24_4X4 9

PC607

PC610
22 SW
PC614

1 2 2

1
2

VIN
PC613

PC615

PC616

1
23 SW PC604
1

2 1 1 VIN 1000P_0603_50V7K
PJ601 7

2
+3VALW 2
2 1
1 +VCCSA_PWR_SRC +VCCSA_PWR_SRC 24
VIN
SW

C @ JUMP_43X118 25 C

COMP

MODE
TP

SLEW

VOUT
VREF
GND
1

6
@ PR608
2 1

33K_0402_5%
PC617 PR609
2 1 100_0402_5%
2 1
0.22U_0402_10V6K

0.01U_0402_25V7K
2
2 1 2 1
PR611

PC619
PC618 PR610 0_0402_5%

1
3300P_0402_50V7K 5.1K_0402_1% 2 1
+VCCSA_SENSE <10>
PJ603
+3VS +V1.05S_VCCPP_B+ 2 1
2 1 B+
@ JUMP_43X118

2200P_0402_50V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
5
6
7
8

0.1U_0402_25V6
1

1
PQ601

PC621
2

TPC8037-H_SO8

PC620

PC622

PC623
@ PR612

2
100K_0402_5% PC624 @
0.22U_0603_16V7K 4
1 PR613 2 1 2
1

@ 0_0603_5%
<53> +V1.05S_VCCP_PWRGOOD
PU602 @ @ @ @ @
1 10 BST_+V1.05S_VCCPP @

3
2
1
@ PR614 PGOOD VBST
1 2 TRIP_+V1.05S_VCCPP 2 9 UG_+V1.05S_VCCPP @ PL602
TRIP DRVH 1UH_PCMC063T-1R0MN_11A_20%
66.5K_0402_1%
@ PR615 EN_+V1.05S_VCCPP 3 8 SW_+V1.05S_VCCPP 1 2
B
0_0402_5% EN SW +V1.05S_VCCPP B
1 2 FB_+V1.05S_VCCPP 4 7 +V1.05S_VCCPP_5V
<10,25,42,46,51,53,54> SUSP# VFB V5IN +5VALW 1
RF_+V1.05S_VCCPP 5 6 LG_+V1.05S_VCCPP
1

5
6
7
8

1
RF DRVL @ + PC631
1

@ PC625 11 PQ602 @ 220U_D2_4VY_R15M

0.1U_0402_16V7K TP @ PC626 PR617
2

TPS51212DSCR_SON10_3X3 1U_0603_6.3V6M 4.7_1206_5% 2

2

0.1U_0402_10V7K
2
@ PR616 4 +V1.05S_VCCPP PJ604 +V1.05S_VCCP
@ @ 2 1

PC627
470K_0402_1%

1
PC628 2 1
2

1
@ JUMP_43X118
TPC8A03-H_SO8 1000P_0603_50V7K
3
2
1

PC629 PR618
@ @
2 1 2 1

PR619 1000P_0402_50V7K 1.2K_0402_1%

PR620
@ 4.32K_0402_1% @ 0_0402_5%
2 1 2 1
VCCIO_SENSE <9,53>
+3VS

VCCP_PWRCTRL = "High" , Vo = 1.05V (SNB)

2

@
2

@ PR621 PR622 VCCP_PWRCTRL = "Low" , Vo = 1V (IVB)

10K_0402_1% 71.5K_0402_1% @ PR623
100K_0402_5%
1

1
SSM3K7002FU_SC70-3

@ PR624
1

D 0_0402_5%
PQ603

A 2 2 1 A
VCCP_PWRCTRL <10>
G
S
3

.01U_0402_16V7K

@
2
1

@ PR625
PC630

100K_0402_5%
@
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR +VCCSAP/1.0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C38-G series Chief River Schematic
Date: Thursday, January 05, 2012 Sheet 52 of 60
5 4 3 2 1
 5 4 3 2 1

+1.5V

1
PJ701

1
D JUMP_43X79 D
@

2
2
PU701
PJ702
pu701vin 1
VIN NC
8 +3VALW
+0.75VSP 2 1 +0.75VS
PC702 2 7 2 1
GND NC

1
4.7U_0805_6.3V6K
JUMP_43X79

1
3 6 PC703
PR702 VREF VCNTL @

2
@ PR720 1K_0402_1% 4 5 1U_0603_10V6K
10K_0402_1% VOUT NC
9
CPU1.5V_S3_GATE 1 2

2
PQ701 TP PJ703
2N7002W -T/R7_SOT323-3 APL5336KAI-TRL_SOP8P8 2 1
2 1
PR703 @ JUMP_43X118

.1U_0402_16V7K
+0.75VSP

1
49.9K_0402_1% D +1.05VS_VCCPP PJ704 +1.05VS

10U_0603_6.3V6M
2 1
<10,46,54> SUSP 1 2 2

PC704
1K_0402_1%

10U_0603_6.3V6M
2 1

1
PC705

PC706
G

2
S PR704 @ JUMP_43X118

0.1U_0402_10V7K

2
1
PC701

2
PJ605 @ +V1.05S_VCCP
+1.05VS 2 1
2 1
C JUMP_43X118 C
PJ606 @
2 1
2 1
JUMP_43X118

PR710 Ivy Bridge CPU ES2 Using

1,52,54> SUSP# 60.4K_0402_1%
1 2
+1.05VS_VCCPP OCP(min)=20.75A
@ 10K_0402_1%

+3VS
2

.1U_0402_16V7K
<bom structure>
1
PR709

PC707

100K_0402_1%
2

PJ705
100K_0402_1%
1

1.05VS_B+ 2 1

2200P_0402_50V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
2 1
B+
2
PR705

0.1U_0402_25V6
2

@ JUMP_43X118
PR706

1
PC719

PC717
PR715

5
0_0402_5% PR713 PC710

PC714

PC718
<52> +V1.05S_VCCP_PW RGOOD 1 2 2.2_0603_5% 0.1U_0603_25V7K PQ702
1

2
1
BST_1.05VS_VCCP 2 1 2
1

<Bom Structure>
10.7K_0402_1%

PR717
14

13
17

16

15

PU702 2 1 4
EN
PAD

BST
PGOOD

MODE
2
PR707

2.2_0402_5%
1 12 LX_1.05VS_VCCP TPCA8065-H_PPAK56-8-5 PL701
0.1U_0402_25V6

3
2
1
B VREF SW 1.0UH +-20% PCMC104T-1R0MN 20A B
<BOM Structure>
+1.05VS_VCCPP
1

VSSIO_SENSE_L 2 1
12K_0402_1%
1

<9>
PC708

2 11 DH_1.05VS_VCCP
2

REFIN DH
2

1
PR708

1000P_0603_50V7K 4.7_1206_5%
5
PC720
TPS51219RTER_QFN16_3X3 PQ703

PR712
0.01UF_0402_25V7K 1
1

PR718
3 10 DL_1.05VS_VCCP

330U_2.5V_M_LESR9M
2 1 GSNS DL +
1

PC709
TPCA8057-H_PPAK56-8-5
4
0_0402_1% 4 9 2
<BOM Structure> VSNS V5 +5VALW
COMP

1
PGND
TRIP

GND

3
2
1

PC715
<BOM Structure>

2
PC712
5

PR716
1

1 2 1 2
75K_0402_1%

PR714
1

PC713
<9,52> VCCIO_SENSE 1 2 @ 10_0402_5% 0.01UF_0402_25V7K 1U_0603_10V6K
2

10_0402_1%
PR711

2
2

<BOM Structure> PC716

1000P_0402_50V7K
1

PR719
A A
1 2

10_0402_1%
2

PC721
1000P_0402_50V7K
Compal Secret Data Compal Electronics, Inc.
1

Security Classification
<BOM Structure>
Issued Date 2010/01/25 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR +1.05VS_VCCPP/+0.75VSP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C38-G series Chief River Schematic
Date: Thursday, January 05, 2012 Sheet 53 of 60
5 4 3 2 1
 A B C D

+3VS_VGA

10K_0402_5% +1.05VS +1.05VS_VGA PJ806

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
2 1
+5VALW +1.05VS 2 1 +1.05VS_VGA
8 1
2

2
7 2 @ JUMP_43X118

2
6 3 @

1
PC867 5 PC868 PC869 PR838
10U_0805_10V6K 470_0603_1% +VGA_B+

2
2
TPC8A03-H_SO8 PQ807 10U_0805_10V6K 1U_0603_10V6K PJ801
PR853

PR852

PR864

PR854

PR855

PR856

PR857

PR858

PR859

PR860

PR861

PR862
1

2
PR840 @ PR851 2 1 B+

1
PQ808 0_0402_5% 2 1
20K_0402_1%
PR839 2N7002KW_SOT323-3
@ 1 2 @ JUMP_43X118
DGPU_PWROK# <46>
GPU_VID5

GPU_VID4

GPU_VID3

GPU_VID2

GPU_VID1

GPU_VID0

GPU_VID5

GPU_VID4

GPU_VID3

GPU_VID2

GPU_VID1

GPU_VID0

1
100K_0402_5% D

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6

2200P_0402_50V7K
1
1 2 2 1 2 SUSP
SUSP <10,46,53>

1
PC870 G

1
@ @ @ @ @ @ PR848 PR849 @

PC801

PC803

PC804
S

3
0_0402_5% 0.1U_0603_25V7K 0_0402_5%

PC802
2
1 1
1 2
<46> DGPU_PWROK# PQ809

2
1
D 2N7002KW_SOT323-3

5
1 2 2
PD808
<10,46,53> SUSP SUSP
G PQ801
RB751V-40_SOD323-2
RB751V-40_SOD323-21 2 PR841 @ S
N13P-GL:0.95V(VID5~0=101100)

3
0_0402_5%
PR802
147K_0402_1% N13M-GE:0.9V(VID5~0=110000) 4
<18> NVDD_PWR_EN 1 2VRON_VGA
PD809
1 2 PR804 PC805
RB751V-40_SOD323-2 2.2_0603_5% 0.22U_0603_10V7K TPCA8065-H_PPAK56-8-5

3
2
1
@ BOOT2_VGA 2 1 BOOT2_2_VGA 1 2

GPU_VID5

GPU_VID4

GPU_VID3

GPU_VID2

GPU_VID1

GPU_VID0
<23>

<23>

<23>

<23>

<23>

<23>
1 PR803 2 PL803
<10,25,42,46,51,52,53> SUSP# @0_0402_5% 2@ PR863 1 UGATE2_VGA 0.36UH_VMPI1004AR-R36M-Z03_30A_20%
47K_0402_5%
<10,25,42,46,51,52,53> DPRSLPVR_VGA 1 2 PHASE2_VGA 1 4
+VGA_COREP

2
PR805
10K_0402_1% PC806 .1U_0402_16V7K PR801 PQ802 PQ803 LF2_VGA 2 3 V2N_VGA
<BOM Structure>

5
1 2 DPRSLPVR_VGA 0_0402_5%

10K_0402_1%
3.65K_0805_1%
1

1
TPCA8059-H_PPAK56-8-5

TPCA8057-H_PPAK56-8-5
+3VS @ PR806 PR810

PR808
1 1

GPU_VID6
1

330U_D2_2.5V_Y

330U_D2_2.5V_Y
1.91K_0402_1% 1_0402_1%

PR809
1 2 CLK_ENABLE#_VGA PR807 + +

PC807

PC808
LGATE2_VGA 4 4

2
1

@4.7_1206_5%

2
PR811 2 2

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

SNUB2_VGA
1.91K_0402_1%

PR842

PR843

PR844

PR845

PR846

PR847
VSUM-_VGA

3
2
1

3
2
1
@
2

VSUM+_VGA ISEN2_VGA
<19,46> DGPU_PWROK

1
+3VS_VGA 1 2 PR812 <BOM Structure>
100K_0402_5%

1
@ PR873 +3VS 1 2
0_0402_5% PC809
@680P_0402_50V7K

2
2
PSI#_VGA PR813
147K_0402_1%
+VGA_CORE Under VGA Core 2

@ PR870
100K_0402_5%
2 1 +VGA_CORE Near VGA Core

1
1 2 PC871
+3VS
1U_0603_10V6K
37
36
35
34
33
32
31
40

38
39

1 2 PU801

2
<23,42> VGA_AC_DET
VID6
VID5
VID4
VID3
VID2
VID1
VID0
CLK_EN#

VR_ON
DPRSLPVR

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
PSI#_VGA
RBIAS_VGA

PR869 @

47U_0805_4V
<BOM2 Structure>
22U_0805_6.3V6M

22U_0805_6.3V6M

4.7U_0805_6.3V6K
1

1
0_0402_5% 30

PC811

PC812

PC813

PC814

PC815

PC816

PC817

PC818
1

1
BOOT2 29

PC819

PC820

PC821

PC822
1 UGATE2 28

2
2 PGOOD PHASE2 27

2
PR871 470K_0402_5%_TSM0B474J4702RE 3 PSI# VSSP2 26 PR814 2
1 2 1 2 4 RBIAS LGATE2 25 VCCP_VGA 1 2
VR_TT# VCCP +5VS
5 24 0_0402_5%
4.02K_0402_1% PH802 VW_VGA 6 NTC PWM3 23
COMP_VGA 7 VW LGATE1 22
FB_VGA 8 COMP VSSP1 21

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K
1 2ISEN3_VGA 9 FB PHASE1
1

1
ISEN3
UGATE1

10 PC824

PC825

PC826

PC827

PC828

PC829

PC830

PC831

PC832

PC833

PC834

PC835
BOOT1
ISUM+

ISEN2
ISEN1

ISUM-
VSEN

IMON

PC823 1U_0603_10V6K
8.06K_0402_1%

VDD
RTN
1000P_0402_50V7K

VIN

22P_0402_50V8J 41
@249K_0402_1%

2
2

<BOM Structure> AGND

PC836

ISL62883CHRTZ-T_TQFN40_5X5
PR816

PR817

11
12
13
14
15
16
17
18
19
20

PR818
2

499_0402_1% PC837
1 2FB1_VGA1 2 <BOM Structure>
<BOM Structure>
<BOM Structure>
<BOM Structure>
<BOM Structure>
ISUM-_VGA
1

VDD_VGA
RTN_VGA

390P_0402_50V7K
PC838 PR820 PR819 @ 0_0402_5%

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

@0.1U_0402_10V7K

@0.1U_0402_10V7K

@0.1U_0402_10V7K
100P_0402_50V8J 1.15K_0402_1% @ PR815 IMON_VGA 1 2 @
+5VS

1
1 2 1 2 0_0402_5% VSEN_VGA

PC839

PC840

PC841

PC842

PC843

PC844

PC845

PC846
1 2 PR821 0_0402_5% PR865 0_0402_5%
11.3K_0402_1%

+5VS
2
0.047U_0402_16V7-K

VIN_VGA 1 2 1 2 PJ802

2
1

For 15W one phase GPU_IMON <42> 2 1

PC874

PR850

ISEN2_VGA +VGA_B+ 2 1
1 2FB2_VGA1 2 PR823 <BOM Structure>
ISEN1_VGA 1_0402_5% @ JUMP_43X118
2

3
PC847 PR822 1 2 +VGA_B+ +VGA_COREP PJ803 +VGA_CORE 3
0.22U_0402_10V6K

0.22U_0402_10V6K

1
1

150P_0402_50V8J 33K_0402_1% 2 1
+5VS
1

2 1
PC848

PC849

PC850

PC851
1U_0603_10V6K

0.22U_0603_25V7K

PR824 VSSSENSE_VGA <24> @ JUMP_43X118

68K_0402_1%

2200P_0402_50V7K
2

BOOT1_VGA

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
2

5
PQ804

1
PC852

PC853

PC854

PC855
2

2
UGATE1_VGA 4
VSUM+_VGA
VSUM-_VGA
1 2
@82.5_0402_5%

+VGA_COREP
PR827 PC856
1

PR825 2.2_0603_5% 0.22U_0603_10V7K TPCA8065-H_PPAK56-8-5

PR826

3
2
1
1

10_0402_5% 2 1 BOOT1_1_VGA 1 2
2.61K_0402_1%

PL804
PR828

0.36UH_VMPI1004AR-R36M-Z03_30A_20%
<24> VCCSENSE_VGA 1 2
2

PHASE1_VGA 1 4
+VGA_COREP
2

PR829
VSUM_VGA_N001

0.22U_0603_10V7K

0.022U_0603_25V7K
1

0_0402_5% PQ806 LF1_VGA 2 3

<BOM V1N_VGA
Structure>

5
NTC_VGA

PC857 PQ805
1

1
330P_0402_50V7K
PC858

PC859

10K_0402_1%
3.65K_0805_1%
2

1
PR831
1 1

330U_D2_2.5V_Y

330U_D2_2.5V_Y
TPCA8057-H_PPAK56-8-5
PR833
2

PR830 1_0402_1% + +

PR832

PC860

PC861
@0.01U_0402_25V7K

LGATE1_VGA 4 4
@330P_0402_50V7K

2
1

TPCA8059-H_PPAK56-8-5
@4.7_1206_5% @
PC863

PC864

11K_0402_1%

2
1

PC862 PH801 2 2
PR834

PR835 1000P_0402_50V7K 10K_0402_1%_TSM0A103F34D1RZ

SNUB1_VGA
0_0402_5%
2

3
2
1

3
2
1
1 2 <BOM Structure> @ VSUM-_VGA
<24> VSSSENSE_VGA
2

Layout Note: VSUM+_VGA

PR836 PR837 Place near Phase1 Choke ISEN1_VGA
10_0402_5% 1K_0402_1%

1
4
For N13M-GE(15W without turbo) 1 2 1 2 4

VSUM-_VGA
PC865
@:PR806,PR812,PC823,PC848,PC849,PR832, @680P_0402_50V7K

2
PC801,PC802,PQ801,PQ802,PQ803,PR804,
PC805,PC803,PR808,PR809,PR810,PC807,
PC804
1

PC866
POP:PR815,PC803 0.1U_0402_16V7K
2

PR816->120K(SD034120380)
PR820->1.69K(SD00000JB80)
PR822->22K(SD034220280)
Security Classification Compal Secret Data Compal Electronics, Inc.
PR837->866(SD034866080) Issued Date 2008/09/15 Deciphered Date 2012/07/11 Title
PC858->0.1uF(SE026104M80)
PC859->0.068uF(SE026683K80) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR - VGA_COREP
PR850->22.1K(SD034221280) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C38 Chief River Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 05, 2012 Sheet 54 of 60
A B C D
 5 4 3 2 1

PC902

1200P_0402_50V7K
1 PR901 2 FBA3 1 2 PC901 1 2

680P_0402_50V7K
D PUT COLSE D

75K_0402_1%
10_0402_1% 0.033u_0402_16V7K .1U_0402_16V7K
TO GT

1
PR903 1 PR904 2

PC903

PC904

PR905
TRBSTA# 1 PR9022 FBA1 1 2 PH901 Inductor
2P: 24K 24.9K_0402_1% PR906 PC906

1
1
8.06K_0402_1% 806_0402_1% 220K_0402_5%_ERTJ0EV224J CSCOMPA 1 2 DROOPA 1 2 CSREFA
1P: 24.9K

2
PC905 PR908 PC907 PC908 2 PR9071 NTC_PH203 1K_0402_1% 1000P_0402_50V7K

2
0.033u_0402_16V7K 1 2 FBA2 1 2 1 2 165K_0402_1%
10_0402_1% 2P: 1.65K
680P_0402_50V7K PR910 22P_0402_50V8J PC909
1 PR9092 1 2 COMPA1 1 2 1P: 1K
1K_0402_1% 5.11K_0402_1% 1800P_0402_50V7K CSREFA
PC910 TSENSEA

2
1 PR9122 SWN1A 0.047U_0402_16V7K

2P: 21.5K 63.4K_0603_1% PR913 6.98K_0402_1%

1
CSP1A 1 2
1P: 15.8K SWN1A <56>

2
15.8K_0402_1%
PR937

CSCOMPA
1 2 PC911
<10> VCC_AXG_SENSE

2
8.25K_0402_1%
1PR914
0_0402_5% 1000P_0402_50V7K

1
PC912 PH904

PR915
PR954 1000P_0402_50V7K
CSREFA <56>

1
1 2 100K_0402_1%_TSM0B104F4251RZ
<10> VSS_AXG_SENSE
0_0402_5% PC914

1
CSP2A
CSP1A
1 2

TRBSTA#

DROOPA

CSSUMA

TSENSEA
COMPA
IMONA
FBA
.1U_0402_16V7K

DIFFA

ILIMA
+V1.05S_VCCP

PR918 2P: 36K

1 2 PUT COLSE
26.1K_0402_1% 1P: 26.1K

60

58

52

46
57

49
48
47
56
61

59

51
53
55
54

50
+5VS 1 PR9192 PU901 TO V_GT
C C
2_0603_5% HOT SPOT

VSNA

DIFFA

DROOPA

TSNSA
CSREFA
FBA

CSP2A
CSP1A
VSPA

CSCOMPA
PAD

COMPA

ILIMA

CSSUMA
TRBSTA#

IOUTA
6132_PWMA
PC915
1 2 6132_VCC
.1U_0402_16V7K

.1U_0402_16V7K

1 45 PR921 PC918
2.2U_0603_10V7K 2 VCC PWMA 44 BSTA1 1 2 BSTA1_11 2
VDDBP BSTA +5VS
130_0402_1%

54.9_0402_1%

PR920 3 43 2.2_0603_5% 0.22U_0603_25V7K

VRDYA HGA HG1A <56>
1

PR922 2

1 2VR_ON_CPU 4 42
<42> VR_ON EN SWA SW1A <56>
PR923

PC916 PC917 0_0402_5% VR_SVID_DAT1 5 41 PC919

SDIO LGA LG1A <56>
VR_SVID_ALRT# 6 40 BST2 1 PR9242 BST2_1 1 2 2Phase: @
2

PR927 PR925 VR_SVID_CLK 7 ALERT# BST2 39 2.2_0603_5% 0.22U_0603_25V7K

SCLK HG2 HG2 <56> 1Phase: install

1
0_0402_5% 95.3K_0402_1% 1 2 VBOOT 8 38 Option for
SW2 <56>
1

1 PR926 2VR_SVID_DAT1 1 2 10K_0402_1% ROSC_CPU 9 VBOOT NCP6132AMNR2G_QFN60_7X7 SW2 37 PC920 PR928

<9> VR_SVID_DAT ROSC LG2 LG2 <56> 1 phase GFX
CPU_B+ 1 2 VRMP 10 36 6132P_VCCP 1 PR9302 1 2 0_0402_5%
<9> VR_SVID_ALRT# VRMP PVCC
VR_HOT# 11 35 0_0402_5% 2.2U_0603_10V7K
<9> VR_SVID_CLK VRHOT# PGND
0.01U_0402_25V7K

PR929 1K_0402_1% VGATE 12 34

LG1 <56> +5VS

2
VRDY LG1
1

13 33 CSP2A
+V1.05S_VCCP VSN SW1 SW1 <56>
PC921 14 32 PC922
+3VS VSP HG1 HG1 <56>
DIFF_CPU 15 31 BST1 1 PR9312 BST1_1 1 2

CSCOMP
2

DIFF BST1

TRBST#
2.2_0603_5% 0.22U_0603_25V7K

DROOP

CSSUM

DRVEN
CSREF
1

COMP

TSNS
CSP3
CSP2
CSP1

PWM
IOUT
ILIM
1

PR932 @

FB
75_0402_1% PR933 +5VS
10K_0402_5%

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
3P: 73.2K
2

1 PR9342
<42> VR_HOT#
2

2P: 41.2K
COMP_CPU

1
FB_CPU 41.2K_0402_1% Option for 3Phase: @
TRBST#
<16> VGATE
PR936 2 phase CPU PR935

DROOP

TSENSE
2 ILIM_CPU
1 2 VSN 3P: 22p 0_0402_5% 2Phase: install
<9> VSSSENSE 6132_PWM
1

0_0402_5%
IMON

PC923 2P: 10p

2
PR938 1000P_0402_50V7K CSP3
2

1 2 VSP PC924
<9> VCCSENSE
PR939 12.4K_0402_1%

0_0402_5% 1 2
.1U_0402_16V7K CSP2 1 PR9412
SWN2 <56>
IMVP_IMON

B 6.98K_0402_1% B

2
PC926 CSP1 PC927 TSENSE

1
3P: 330p 1 PR940 2 2 1 CSP2 0.047U_0402_16V7K @
1

1K_0402_1% CSP3 PR960

2P: 1000p 22P_0402_50V8J 6.98K_0402_1%

2
<BOM Structure>

1
PR942 PC928 PR943 PC929 3P: 21K CSREF
1 2FB_CPU1 1 2 2 1COMP_CPU1 2 1
PR944 PC930 49.9_0402_1% 6.04K_0402_1% 2P: 12.4K CSP1 1 PR9452
SWN1 <56>

8.25K_0402_1%
1 2FB_CPU3 1 2 680P_0402_50V7K 1800P_0402_50V7K 6.98K_0402_1%

PR946 1

2
10_0402_1% <BOM Structure> 3P: 6.04K
CSCOMP

CSREF <56>
2

1
0.033u_0402_16V7K PC931 @ PH902
PR947 PR948 2P: 4.32K PC932 0.047U_0402_16V7K PR961
TRBST# 1 2 FB_CPU2 1 2 1000P_0402_50V7K 3P: 1500p 6.98K_0402_1% 100K_0402_1%_TSM0B104F4251RZ
1

2
0.033u_0402_16V7K

1
2P: 1200p
1

8.06K_0402_1% 806_0402_1% 3P: 2200p CSREF

PC933 2P: 3300p CSSUM

2

3P: 348 3P: 3.65K PC934

1 2
2P: 1.21K 2P: 9.53K 1200P_0402_50V7K 1 PR9492 SWN1
24.9K_0402_1%

130K_0603_1% PUT COLSE

2

.1U_0402_16V7K

TO VCORE
PC935

3P: 23.7K 1 2 PC936 1 PR9512 SWN2

PR950

680P_0402_50V7K 130K_0603_1% HOT SPOT

1

2P: 24.9K
1 PR952 2NTC_PH201 1 PR953 2
1

75K_0402_1%
PR955 PC937 165K_0402_1%
CSCOMP 1 2 DROOP 1 2 CSREF PH903
PUT COLSE
1K_0402_1% 1000P_0402_50V7K 2 1
3P: 806 TO VCORE
Phase 1 220K_0402_5%_ERTJ0EV224J
2P: 1K
A Inductor A

<42> IMVP_IMON

Security Classification
2009/12/01
Compal Secret Data
2012/07/11 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CPU_CORE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom C38-G series Chief River Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 05, 2012 Sheet 55 of 60
5 4 3 2 1
 5 4 3 2 1

CPU_B+ CPU_B+

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
B+

0.1U_0402_25V6

0.1U_0402_25V6
2200P_0402_25V7K

2200P_0402_25V7K
5

5
PL901
PQ901 FBMA-L11-453215-121LMA90T_1812 PQ902

1
1 2

PC938

PC939

PC940

PC941

PC942

PC943

PC944

PC946
CPU_B+
1 1

2
4 4
<55> HG1 + + <55> HG2
+VCC_CORE
PC950 PC947 +VCC_CORE
100U_25V_M
100U_25V_M
PL902 2 2
TPCA8065-H_PPAK56-8-5 <BOM Structure>
<BOM Structure> TPCA8065-H_PPAK56-8-5

3
2
1

3
2
1
D D
0.36UH_VMPI1004AR-R36M-Z03_30A_20% PL903
<BOM Structure>
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1 4 1 4
<55> SW1 <55> SW2 <BOM Structure>

1
2 3 2 3

5
PR956 PQ904 PR957
PQ903 4.7_1206_5% 4.7_1206_5%

2
PR958
4 V1N_CPU2 1 4 V2N_CPU 2 PR959 1 CSREF
<55> LG1 CSREF <55> <55> LG2

1SNUB_CPU1

SNUB_CPU2
10_0402_1%
10_0402_1%

TPCA8057-H_PPAK56-8-5

3
2
1

3
2
1
SWN1 <55> SWN2 <55>
TPCA8057-H_PPAK56-8-5 <BOM Structure>
PC948
<BOM Structure>

1
680P_0603_50V7K PC949

2
680P_0603_50V7K

2
C C

QC 45W CPU DC 35W CPU

VID1=0.9V VID1=1.05V
IccMax=94A IccMax=53A
Icc_Dyn=66A Icc_Dyn=43A
Icc_TDC=52A Icc_TDC=36A
R_LL=1.9m ohm R_LL=1.9m ohm
OCP~110A OCP~65A

CPU_B+
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6

2200P_0402_25V7K

B B
1

1
PC957

PC958

PC959

PC960
2

2
5

PQ907

4
<55> HG1A
PL905

TPCA8065-H_PPAK56-8-5
+VCC_GFXCORE_AXG
3
2
1

0.36UH_VMPI1004AR-R36M-Z03_30A_20%
<BOM Structure>
1 4
<55> SW1A <BOM Structure>
1

2 3
5

PQ909 PR967
V1N_GFX

4.7_1206_5%
2

4
5> LG1A
SNUB_GFX1

TPCA8057-H_PPAK56-8-5 2 PR971 1
3
2
1

CSREFA <55>
<BOM Structure>
10_0402_1%
1

PC968
680P_0603_50V7K SWN1A <55>
2

A A

QC 45W GT2 DC 35W GT2

VID1=1.23V VID1=1.23V
IccMax=46A IccMax=33A
Icc_Dyn=37A Icc_Dyn=20.2A Security Classification Compal Secret Data Compal Electronics, Inc.
Icc_TDC=38A Icc_TDC=21.5A Issued Date 2009/12/01 Deciphered Date 2012/07/11 Title

R_LL=3.9m ohm R_LL=3.9m ohm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CPU_CORE
Size Document Number Rev
OCP~55A OCP~40A AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C38-G series Chief River Schematic
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 05, 2012 Sheet 56 of 60
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE Below is 458544_CRV_PDDG_0.5 Table 5-8.

+VCC_CORE +VCC_GFXCORE_AXG
1 1 1 1 1
5 x 22 ȝF (0805)
PC1
PC2 PC3 PC4 PC5
Socket Bottom 5 x (0805) no-stuff
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM +VCC_GFXCORE_AXG sites

D
7 x 22 ȝF (0805) D

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Socket Top 2 x (0805) no-stuff
sites

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 @ 1 1 1

PC12

PC13

PC14

PC15

PC16

PC17

PC18

PC19
@
PC6 PC7 PC8 PC9 PC10 PC11
10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM
2 2 2 2 2 2 2 2 2 2 2 2 2 2
+V1.05S_VCCP
+VCC_CORE +V1.05S_VCCP

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 @ @ @ @

PC25

PC26

PC27

PC28

PC29

PC30

PC31

PC32

PC33

PC34

PC35
PC20 PC21 PC22 PC23 PC24
2 2 2 2 2 2 2 2 2 2 2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 1 1 @ 1 1 1 1 1 1
2 2 2 2 2

PC36

PC37

PC38

PC39

PC40

PC41

PC42

PC43
2 2 2 2 2 2 2 2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 1 1 1 1
1 1 1 1 1 @ @ @

PC49

PC50

PC51

PC52

PC53

PC54

PC55

PC56
PC44 PC45 PC46 PC47 PC48
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M <BOM Structure> 2 2 2 2 2 2 2 2
2 2 2 2 2 @
1 1 1

330U_D2_2.5V_Y_R9M

330U_D2_2.5V_Y_R9M

330U_2V_M_X_LESR6M
PC57

PC58

PC60
+ + +
C C

2 3 2 3 2 3
1 1 1

330U_D2_2VM_R9M

330U_D2_2.5V_Y_R9M

330U_D2_2.5V_Y_R9M
1 1 1 1 1

PC66

PC67

PC68
@ + + +
PC61 PC62 PC63 PC64 PC65
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2 2 3 @ 2 3 2 3 @

1 1 1 1
@ @ <BOM Structure> <BOM Structure>
PC69 PC70 PC71 PC72
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2

+VCC_CORE

1 1
+ PC73 + PC74

330U_D2_2.5V_Y_R9M 330U_D2_2.5V_Y_R9M
B 2 3 2 3 B

1 1
+ PC77 + PC78

330U_2V_M_X_LESR6M 330U_D2_2.5V_Y_R9M
2 3 2 3

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/09/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR - PROCESSOR DECOUPLING
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C38-G series Chief River Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 05, 2012 Sheet 57 of 60
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9HUVLRQFKDQJHOLVW3,5/LVW 3DJHRI

IRU3:5
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To facilitate EA test P54 Change net name of pin 1 of PR825 from +VGA_CORE to +VGA_COREP 2011/10/19 DVT

D D

 Sense VSSIO_SENSE_L net close to IC P53 Add PR718 2011/10/19 DVT

 CPU controller compensation RC tunning P55 Change PC904, PC907, PC908, PC909, PC926, PC928, PR929, PC936 and PR943 2011/10/19 DVT


EMI request P51 Change PR503 2011/10/19 DVT


Back to Back MOS change P49 Change PQ302 2011/12/06 PVT


Sense VSSIO_SENSE_L change according to FAE P53 Add PR719 and PC721. Change PR718 and PR714 2011/12/06 PVT


Add IC G718 P48 Change PR205 to 4.42k (90W) and PR210 to 27.4k (90W) 2011/12/06 PVT

 EC_ON RC change P50 Change PR418 from 10k to 2.2k 2011/12/06 PVT

C C

Unpop PR224 and add PR231 by HW request P48 Unpop PR224 and add PR231 2011/12/21 PVT


Change CPU&GFX compensation RC by FAE recommendation P55 PR902, PR903, PR947, PR948, PC901, PC905, PC929, PC930 and PC933 2011/12/21 PVT


Change charger's choke from 4.7u to 10u P49 PL302 2011/12/21 PVT







B B






A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/06 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C38-G series Chief River Schematic0.1
Date: Thursday, January 05, 2012 Sheet 58 of 60
5 4 3 2 1
 5 4 3 2 1

COMPAL CONFIDENTIAL
MODEL NAME: Power Sequence Block Diagram
PCB NAME: LA-7981P
D REVISION: D

DATE: 2011/07/13 10

PCH_PWROK
AC A1
MODE VIN +3V_PCH

V V
A2 A3 B5 +5V_PCH

VV
PU301 A5 3

V
PU401

V
B+
+3VALW B7 3 3
BATT BATT V 10
+5VALW
MODE
B1
B2
B+ B4 V PCH_PWROK
V SYS_PWROK 15 14 VGATE

V
EC 4
PQ2 11
PCH_RSMRST#_R PM_DRAM_PWRGD

V
V
V V PCH
B3 A5 B7 5 12
PBTN_OUT# H_CPUPWRGD
CPU

V V
13 SVID

V
C C
51ON# EC_ON
PM_SLP_S3#
PM_SLP_S4# PLT_RST# 16
PM_SLP_S5#
A4 B6 PM_SLP_SUS# 6
DGPU_PWROK

V
V
ON/OFF

SYSON 7 SYSON#

V
+1.5V
PU501

DGPU_PWR_EN
SUSP#,SUSP 8

(DIS)

V
PU601 U38
8b
B +VCC_SA +5VS B

(DIS)

V
V
PU702 U39
8a
+V1.05S +3VS DGPU

V
V
V

PU602 Q8
+V1.05S_VCCP +1.5VS

PU701

V
SA_PGOOD 8a +0.75VS

13 SVID
VR_ON 9 PU901
V

+VCC_CORE
A A

14 VGATE

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 59 of 60
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A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/27 Deciphered Date 2012/10/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7983P
Date: Thursday, January 05, 2012 Sheet 60 of 60
5 4 3 2 1