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NAME:

ID NO:

BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI


I SEMESTER 2011-2012
CS G562/CS G524 ADVANCED ARCHITECTURE & PERFORMANCE EVALUATION
ADVANCED COMPUTER ARCHITECTURE
TEST I (CLOSE BOOK)
TIME: 50 Min. 03/10/11 MM: 25

Q1. The (imaginary) move memory/register (movmr) instruction is like a move instruction except that it
moves contents of a register to another register as well as to a memory location. The R-type format is
used, as shown below.
movmr (rd),(rs),(rt) # Memory[R[rt]] R[rs];
# R[rd]R[rs]

The multicycle datapath from lecture appears below. Show what changes are needed to support movmr.
You should only add wires and muxes to the datapath; do not modify the main functional units
themselves (the memory, register file, and ALU). Use minimum number of cycles for your
implementation. Do not lengthen the clock cycle. Assume that everything besides the ALU, Memory and
Register File is instantaneous.

1
Complete this finite state machine diagram for the movmr instruction. Control values not shown in each
stage are assumed to be 0.

Op = movmr

[10]

Q2.To perform jump to a function call, implement jmem instruction in the single-cycle datapath shown
below. The format of jmem instruction is shown below.

jmem (rt), offset(rs) # [R[rt] PC+4;


# PC Memory[R[rs]+offset]

Show what changes are needed to support jmem instruction. You should only add wires and muxes to the
datapath; do not modify the main functional units themselves (the memory, register file and ALU). Your
solution should not lengthen the clock cycle. Assume that the ALU, Memory and Register file all take
2ns, and everything else is instantaneous.

2
On the diagram below, write (next to the signal’s name) values of all non-0 control signals required for
the jmem instruction.
[6]

Q3.The design team for a simple, single-issue processor is choosing between a pipelined or non-pipelined
implementation. Here are some design parameters for the two possibilities: [4]
Parameter Pipelined version Non Pipelined Version
Clock rate 500MHz 350MHz
CPI for ALU instructions 1 1
CPI for control instructions 2 1
CPI for memory instructions 2.7 1

(a) For a program with 20% ALU instructions, 10% control instructions and 70% memory instructions,
which design will be faster? Give a quantitative CPI average for each case.

(b) If the number of control instructions remain fixed at 10%, then what should be the minimum % of
ALU instructions such that the Pipelined version is faster than the non pipelined version?

3
Q3. A RISC Processor having a five stage pipeline as discussed in class is used. The Pipeline hardware
detects all possible data hazards and stalls the pipeline when necessary for correct program behavior. For
such a Processor draw cycle by cycle execution schedule in the pipeline for the following program for one
iteration of the loop through this pipeline. [5]

Destination Source
LOOP: ADD R2, R2, R1
ADD R3, R2,R1
LW R1, $(R3)
SUB R3, R3, R1
SW $(R3) R2
BNEZ R3 LOOP

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