VLSI Interview Questions

1) What is the transistor model used in your VLSI project?

2) What are the types of transistors used in VLSI Design?
3) What are the MOSFET terminals?
4) Explain about Body Effect.
5) Why we connect PMOS to Power Supply & NMOS to GND in CMOS inverter?
6) Draw the NMOS Inverter Circuit & Characteristics Curve.
7) Draw the PMOS Inverter Circuit & Characteristics Curve.
8) Draw the CMOS Inverter Circuit
a) Characteristics Curve.
b) Explain its operation.
c) Explain its operation with GND & Vi = +5v
d) Explain its operation with GND = -5v & Vi = +5v.
e) What is the operation of PMOS & NMOS in CMOS inverter?
9) Realize the NAND & NOR logic gates using NMOS & CMOS logics.
10) Difference between NMOS & PMOS.
11) Difference between NMOS & CMOS.
12) Difference between PMOS & CMOS.
13) What are the parameters (or) desire factors for designing the NMOS, PMOS & CMOS
Inverter?
14) How will you choose W & L (Aspect Ratio) for NMOS, PMOS & CMOS Circuits? Any
relationship between them.
15) What is meant by Threshold voltage?
16) What is meant by Static?
17) Difference between Static & Dynamic CMOS.
18) What is meant by Static Power dissipation?
19) What is meant by Dynamic Power dissipation?
20) Write the equation for the Dynamic Power dissipation in NMOS, PMOS & CMOS
Circuit?
21) Draw the characteristic equation & curve for the diode.
22) What is the VT for various types of diodes?
23) What is the VT for various types of diodes made by different materials?
24) 0.7 v VT for = ?
25) What is meant by VLSI Modeling & Devices?
26) Draw the NOR gate & OR gate using NAND gates only & explain its operation.
27) Draw the XOR gate & truth table.
28) Draw an inverter circuit using XOR gate.
29) What is meant by Convolution?
30) Tell about 2 (or) 3 projects done by you.
31) How to define Embedded Systems?
32) What is meant by Forward & Reverse Bias?
33) ?

In reverse bias, also the same

condition (or) …… ? Why?

? ?

Curve start with 0 (or) after some level;

For what purpose?

?
34) It is same for Zener diode (or) ….. ?
35) If you are a corporate trainer, how do you explain about VLSI to your Unknown students
(or) staffs?
36) What is the temperature value for Si & Ge?
37) Why high frequency is not used in Si based IC?
38) What is the material used for the high frequency IC?
39) Tell about λ rules.
40) Tell the λ value:

Contact ?

Metal ?
41) What are the types of memory? (Volatile & Non-Volatile)
42) Draw a basic SRAM & DRAM cell.
43) What is the difference between SRAM & DRAM? Explain in detail.
44) What types of current flows & leakage currents in the Semi-Conductor? (Drift &
Diffusion Currents)Explain in detail & Write the equation & derive it fully.
45) Relationship between the Ohm’s law & Drift and Diffusion Current. Explain in detail
with mathematic equations.
46) Draw a J-K Flip-Flop & convert it to D Flip-Flop. Write the truth table.
47) What is the meaning of “ > ” in Flip-Flop clock signal? (Edge Triggering)
48) Explain the operation of D & T Flip-Flop in detail.
49) Why do you offer Ph.D; Not preferring the research associates.

50) What is the output of the circuit:

D Q

CLK

51) What is meant by Matrix?

52) Define the rank of the matrix.
53) How to find the rank of the matrix?
54) Why ECC uses elliptic curve & why it is called elliptic?
55) What is Pass Transistor?
56) Explain the “Bad 1”.

WORNG

57) What are the types of FPGA? (Xilinx, Altera…)

58) What is inside in Xilinx FPGA?
If a full adder circuit implemented in Xilinx FPGA means, where the user’s datas are
stored?
In Xilinx FPGA, logic gates & multiplexers are not used for user programs.
59) What is meant by LUT?
60) Why LUT is used?
61) Realize the full adder circuit using LUT.
62) Explain about your academic project.
63) Fill the following details in your career.

S.No. Subjects Name Book Name Author Name

64) Write 2 X 3 matrix.

65) What are the elements of matrix?
66) What is meant by Linear Difference equation?
67) Write one example for linear difference equation.

What is Variable & Constant?

68) What is meant by Determinant?
69) How to find Determinant?
70) How to find determinant for (2 X 3) or (3 X 2) matrix?
71) What is a determinant of matrix [ A ] or single row?
72) How many non-repeated even 3 – digit numbers in 0, 1, 2 …9?
73) Draw the TCP-IP reference layers
(a) Where is the Data Link Layer?
(b) PPP – where used?
(c) What is the difference between Connection – Oriented Protocols & Connection-less
Protocols?
74) Write a C program for [ 8 ] [ 8 ] chess / checkers program, traverse towards white in
diagonal.
75) In 64 ! of binary digits, how many trialing 0’s (LSB 0’s).
76) Check the code in A [1000] [1000]. Matrix transpose.
77) D Flip-Flop Using NOR Latches
This circuit utilizes three interconnected RS latch circuits, as shown. This
example uses NOR gates, but NAND gates can easily be used to perform the same
function.
The two input latch circuits essentially store the D and D' signals separately,
and apply those stored signals to the output latch. While the CLK input is a logic 0,
changes to the D input can only affect the state of the lower gate of the lower input
latch circuit. The other gates are locked into their output states by their other
interconnections.
When CLK goes to logic 1, it inherently forces the outputs of the two middle
input gates to logic 0. This effectively isolates the output latch from any input
changes. Note that at this time, one or the other of the two input latches will be in an
illegal state, depending on the state of the D input. This illegal state overrides the
latching action of that input circuit.
Now, when CLK falls to logic 0, whichever input latch was in an illegal state will
abruptly resume its latching action, and will at once control the state of the output latch.
In this manner, the circuit is still an edge-triggered flip-flop that will take on the state of
the D input at the moment of the falling clock edge.
78) What is the output of AND gate in the circuit below, when A and B are as in waveform?
Tp is the gate delay of respective gate.

79) Identify the circuit below, and its limitation.

80) What is the current through the resistor R1 (Ic)?

81) What is the function of a D flip-flop, whose inverted output is connected to its input?
82) Design a circuit to divide input frequency by 2.
83) Design a divide-by-3 sequential circuit with 50% duty cycle.
84) Design a divide-by-5 sequential circuit with 50% duty cycle.
85) What are the different types of adder implementations?
86) Referring to the diagram below, briefly explain what will happen if the propagation delay
of the clock signal in path B is much too high compared to path A. How do we solve this
problem if the propagation delay in path B can not be reduced?

87) Draw a Transmission Gate-based D-Latch.

88) Give the truth table for a Half Adder. Give a gate level implementation of it.
89) What is the purpose of the buffer in the circuit below is it necessary/redundant to have a
buffer?

90) What is the output of the circuit below, assuming that value of 'X' is not known?

91) Design an OR gate from 2:1 MUX.

92) Consider a circular disk as shown in the figure below with two sensors mounted X, Y and
a blue shade painted on the disk for an angle of 45 degree. Design a circuit with
minimum number of gates to detect the direction of rotation.

93) Design an XOR gate from 2:1 MUX and a NOT gate
94) What is the difference between a LATCH and a FLIP-FLOP?

Latch is a level sensitive device while flip-flop is an edge sensitive device.

Latch is sensitive to glitches on enable pin, whereas flip-flop is immune to glitches.
Latches take fewer gates (also less power) to implement than flip-flops.
Latches are faster than flip-flops.

95) Design a 2 bit counter using D Flip-Flop.

96) What are the two types of delays in any digital system?
97) Design a D Flip-Flop from two latches.

98) Design a Transparent Latch using a 2:1 Mux.

99) Design a 4:1 Mux using 2:1 Muxes and some combo logic.

100) What is metastable state? How does it occur?

101) What is metastability?
102) Design a 3:8 decoder.
103) Design a FSM to detect sequence "101" in input sequence.
104) Convert NAND gate into Inverter, in two different ways.
105) Design a D and T flip flop using 2:1 mux; use of other components not allowed,
just the mux.
106) Design a divide by two counter using D-Latch.
107) Design D Latch from SR flip-flop.
108) Define Clock Skew, Negative Clock Skew, Positive Clock Skew.
109) What is Race Condition?
110) Design a 4 bit Gray Counter.
111) Design 4-bit Synchronous counter, Asynchronous counter.
112) Design a 16 byte Asynchronous FIFO.
113) What is the difference between an EEPROM and a FLASH?
114) What is the difference between a NAND-based Flash and a NOR-based Flash?
115) You are given a 100 MHz clock. Design a 33.3 MHz clock with and
without 50% duty cycle.
116) Design a Read on Reset System?
117) Which one is superior: Asynchronous Reset or Synchronous Reset? Explain.
118) Design a State machine for Traffic Control at a Four point Junction.
119) What are FIFO's? Can you draw the block diagram of FIFO? Could you modify it to
make it asynchronous FIFO?
120) How can you generate random sequences in digital circuits?

121) Two capacitors are connected in parallel through a switch. C1= 1uF, C2= 0.25uF.
Initially switch is open, C1 is charged to 10V. What happens if we close the switch? No
loss in the wires and capacitors. 

122) You have 2 switches to control the light in the long corridor. You want to be able to
turn the light on entering the corridor and turn it off at the other end. Do the wiring
circuit.
123) This question is based on the previous one, but there are 3 switches that can turn on and
off a light in the room. How to wire them up?
124) What will be the voltage level between the 2 capacitors?
The Vcc = 10v DC.

125) Suppose, you work on a specification for a system with some digital parameters. Each
parameter has Min Typ and Max colomns. In what column would you put a Setup time
and a Hold time?

126) Design a simple circuit based on combinational logic to double the output frequency. 

127) 8bit ADC with parallel output converts input signal into digital numbers. You have to
come up with the idea of a circuit that finds MAX of every 10 numbers at the output of
the ADC.

128) Implement comparator that compares two 2-bit numbers A and B. The comparator
should have 3 outputs:  A > B, A < B, A = B. Do it two ways:
- using combinational logic;
- using multiplexers. Write HDL code for your schematic at RTL and gate level.
129) You have 8 bit ADC clocking data out every 1mS.  Design a system that will sort the
output data and keep a statistics   how often each binary number appears at the output of
ADC.
130) What types of flip-flops do you know?
131) Implement D- latch from
- RS flip flop;
- multiplexer.
132) How to convert D-latch into JK-latch and JK-latch into D-latch? 
133) You have two counters to 16, built from neg. edge D- FF. First circuit is synchronous
and second is "ripple" (cascading). Which circuit has a less propagation delay?
134) What is the difference between flip-flop and latch? 
Write an HDL code for their behavioral models.
135) Describe the operation of DAC? What are the most important parameters of DAC?
Do we really need both INL and DNL to estimate linearity? 
136) Compare briefly all types of ADC that you know.
137) How will the output signal of an ideal integrator look like after
- a positive pulse is applied to the input;
- a series of 10 positive pulses?
138) How to design a divide-by-3 counter with equal duty cycle?
139) For an 8-bit flash A/D converter with an input range from 0V to 2.55V, describe what
happens when the input voltage changes from 1.27V to 1.28V
140) Your system has CPU, ALU and two 8bit registers. There is no external memory. Can
you swap the contence of the registers ?
141) Convert D-latch into divider by 2. 
142) What is the max clock frequency the circuit can handle? 
T_setup= 6nS 
 T_hold = 2nS 
T_propagation = 10nS 
143) For ATE engineers (semiconductor test):
Draw a shmoo plot of two parameters: Clock period Tclk and setup time Tsetup.
144) For chip design/test/product engineers :
An IC device draws higher current when temperature gets:
- higher
- lower

145) The circle can rotate clockwise and back. Use minimum hardware to build a circuit to
indicate the direction of rotating.

146) I swapped 2 transistors in CMOS inverter (put n-transistor at the top and p-transistor at
the bottom). Can this circuit work as a non-inverting buffer?

147) To enter the office people have to pass through the corridor. Once someone gets into
the office the light turns on. It goes off when noon is present in the room. There are two
 registration sensors in the corridor.  Build a state machine diagram and design a circuit to
control the light.

148) Draw a transistor schematic of NOR gate, it's layout and a cross section of the layout.
149) The silicon of a new device has memory leak. When all "0" are written into RAM, it
reads back all "0" without any problem. When all "1" are written, only 80% of memory
cells are read back correctly. What can be possibly the problem with the RAM?
150) A voltage source with internal impedance Z_source = 50 OHm is connected to a
transmission line with Z = 50 OHm. Z_load is also 50 OHm.
The voltage source generates a single voltage step 1V.
What will be the voltage level on the load:
a)  2V , because the reflected signal will be in-phase with the incident signal;
b)  0.33V , because the voltage is devided between Z_source , Z_load and Z_transm.line;
c)  0.5V , because the voltage is devided between Z_source and Z_load.

151) Design a FIFO 1 byte wide and 13 words deep. The FIFO is interfacing 2 blocks with
different clocks. On the rising edge of clk the FIFO stores data and increments wptr. On
the rising edge of clkb the data is put on the b-output, the rptr points to the next data to be
read. If the FIFO is empty, the b-output data is not valid. When the FIFO is full the
 existing data should not be overridden. When rst_N is asserted, the FIFO pointers are
asynchronously reset.

module fifo1 (full,empty,clk,clkb,ain,bout,rst_N)

output [7:0] bout;
input [7:0] ain;
input clk,clkb,rst_N;
output empty, full;
reg [3:0] wptr, rptr; ----

endmodule

152) Design a COMBINATIONAL circuit that can divide the clock frequency by 2.
153) Design a 2bit up/down counter with clear using gates. (No verilog or vhdl)
154) We have a circular wheel with half painted black and the other half painted white.
There are 2 censors mounted 45 degree apart at the surface of this wheel( not touching
the wheel) which give a "1" for black and "0" for white passing under them. Design a
circuit to detect which way the wheel is moving. Can not assume any fixed position for
start.
155) We have a FIFO which clocks data in at 100 MHz and clocks data out at 80 MHz. On
the input there is only 80 data in any order during each 100 clocks. In other words, a 100
input clock will carry only 80 data and the other twenty clocks carry no data (data is
scattered in any order). How big the FIFO needs to be to avoid data over/under-run.
156) Instead of specifying SETUP and HOLD time, can we just specify a SETUP time for '1'
and a SETUP time for '0'?
157) When will you use a latch and a flip-flop in a sequential design?
158) Design a 1-bit full adder using a decoder and 2 "or" gates?
159) You have a circuit operating at 20 MHz and 5 volt supply. What would you do to
reduce the power consumption in the circuit- reduce the operating frequency of 20 MHz
or reduce the power supply of 5Volts and why?
160) In an nmos transistor, how do the current flows from drain to source in saturation
region when the channel is pinched off?
161) In a SRAM circuit, how do you design the pre-charge and how do you size it?
162) In a PLL, what elements (like XOR gates or Flip-flops) can be used to design the phase
detector?
163) While synthesis of a design using synopsis design compiler, why do you specify input
and output delays?
164) What difference do you see in the timing reports for a propagated clock and an ideal
clock?
165) What is time borrowing related to Static timing analysis in Primetime?
166) Explain why & how a MOSFET works.

167) Explain the various MOSFET Capacitances & their significance

168) Draw a CMOS Inverter. Explain its transfer characteristics

169) Explain sizing of the inverter

170) How do you size NMOS and PMOS transistors to increase the threshold voltage?

171) What is Noise Margin? Explain the procedure to determine Noise Margin

172) Give the expression for CMOS switching power dissipation

173) Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes

(a) with increasing Vgs

(b) with increasing transistor width
(c) considering Channel Length Modulation
174) What is Body Effect?
175) Describe the various effects of scaling

176) Give the expression for calculating Delay in CMOS circuit

177) What happens to delay if you increase load capacitance?

178) What happens to delay if we include a resistance at the output of a CMOS circuit?

179) What are the limitations in increasing the power supply to reduce delay?
180) How does Resistance of the metal lines vary with increasing thickness and increasing
length?

181) You have three adjacent parallel metal lines. Two out of phase signals pass through the
outer two metal lines. Draw the waveforms in the center metal line due to interference.
Now, draw the signals if the signals in outer metal lines are in phase with each other

182) What happens if we increase the number of contacts or via from one metal layer to the
next?

183) Draw a transistor level two input NAND gate. Explain its sizing

(a) considering Vth

(b) for equal rise and fall times

184) Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate
later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one
would you place near the output?
185) Draw the stick diagram of a NOR gate. Optimize it

186) For CMOS logic, give the various techniques you know to minimize power
consumption.

187) What is Charge Sharing? Explain the Charge Sharing problem while sampling data
from a Bus.

188) Why do we gradually increase the size of inverters in buffer design? Why not give the
output of a circuit to one large inverter?

189) In the design of a large inverter, why do we prefer to connect small transistors in
parallel (thus increasing effective width) rather than lay out one transistor with large
width?

190) Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2
input Multiplexer. You can expect any simple 2 or 3 input gates)
191) Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its
stick diagram

192) Why don’t we use just one NMOS or PMOS transistor as a transmission gate?

193) For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD,
give the output for a square pulse input going from 0 to VDD

194) Draw a 6-T SRAM Cell and explain the Read and Write operations

195) Draw the Differential Sense Amplifier and explain its working. Any idea how to size
this circuit? (Consider Channel Length Modulation)

196) What happens if we use an Inverter instead of the Differential Sense Amplifier?

197) Draw the SRAM Write Circuitry

198) Approximately, what were the sizes of your transistors in the SRAM cell? How did you
arrive at those sizes?

199) How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM’s
performance?

200) What’s the critical path in a SRAM?

201) Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of
Clock signal?

202) Give a big picture of the entire SRAM Layout showing your placements of SRAM
Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers

203) In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines?
Why?

204) How can you model a SRAM at RTL Level?

205) What’s the difference between Testing & Verification?

206) For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0
and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some
redundant logic)

207) What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do
you avoid Latch Up?

208) Dynamic Power dissipation increases.

209) Resistance is directly proportional to length and inversely proportional to area. So
higher metals has lesser resistance. Increasing L increases the resistance.
210) Increase in contact resistance.
211) NMOS passes clean zero and a bad one while PMOS passes clean 1 and bad zero
(Hint: Vt loss)
212) Paretic Tx act as tyristors. Chances of triggering this thyristor.
Put sufficient well contacts.
213) Capacitor stores the energy in terms of current. It allows the A.C. signals & blocks the

D.C. signal, because of its property:

214) Inductor stores the energy in terms of magnetic field,

215) In Analog Circuits, BJT acts an amplifier.

216) In Digital Circuits, single BJT acts as a “TRANSISTOR” in digital NOT gate circuit.
217) TTL gate IC’s starts with the number “74”.
218) Any Flip Flop without Clock, called LATCH.
219) Single bit register called ”Flip Flop”