Amplifiers with Improved Efficiency

Doherty Amplifier
Outphasing (LINC or Chireix) Amplifier
Envelope Tracking Amplifier
Envelope Elimination & Restoration Amplifier
 Strategies for Reduction of DC Power For
Low output Power Operation

Iout
Iout

Vout Vout
V1 V2 V3
Vary bias current according to
Instantaneous power Vary bias current and voltage according to
“Dynamic biasing” Instantaneous power
“Envelope tracking and EER”
Iout

Vary load impedance according to

Instantaneous power
“Doherty and Chireix”

Vout
 Envelope Tracking (ET) Technique

• Envelope Amplifier provides dynamic drain voltage

• Maximizes PA efficiency by keeping RF transistor
closer to saturation for all envelope amplitudes

DC Drain voltage Dynamic Drain Voltage

Supply tracks envelope
of RF signal

Voltage
Envelope Envelope
Detector Amplifier

0
Time

RF RF RF
Signal Amplifier Signal Out
In

In Envelope Tracking, PA is quasi-linear.

Input signal contains envelope and phase information.
 Benefit of ET Architecture (1)

Efficiency
For ET system
Efficiency

Vcc3 Vcc2 Vcc1

Vcc4
Vcc5

Pout (dBm)

ET System Maximizes Efficiency Vs Power

By Adjusting Power Supply Voltage (Vcc or Vdd)
 Class B Amplifier Efficiency

Notation change:
here Vo=Vdd
 Class B Amplifier Efficiency

Notation change:
here Vo=Vdd
Also,
In ET, try to keep Pout within 1-2 dB overdrive PA
of Poutmax (65-80%) all the time somewhat
Envelope & Power Supply Benefit of ET Architecture (2)

Envelope & Power Supply

Voltage (normalized)

Voltage (normalized)
Constant Supply Voltage Envelope Tracking

Red: overvoltage

Extra power dissipation is overvoltage*current

Envelope Elimination and Restoration (EER) Technique

DYNAMICALLY VARYING
DRAIN VOLTAGE

Voltage
AMPLITUDE signal DC SUPPLY

0 VDD
AMPLIFIER
DRAIN Time
VOLTAGE

PHASE signal (…. and Restoration)

RF POWER Output
0
TRANSISTOR signal

saturated at
all times
 Envelope and Phase Signals in EER
• EER separates the CDMA signal into two new signals
(Signal Decomposition):

AMPLITUDE signal (Envelope)

Contains AM of
0
WCDMA signal CDMA signal

Baseband signal, DC to ~30MHz

0
EER
PHASE signal (Envelope Elimination)

WCDMA signal is both 0 Contains PM of

Amplitude and Phase CDMA signal
Modulated
Phase modulated carrier at RF
Earl McCune
 Comparison of EER and ET

ET EER
DYNAMICALLY VARYING
DRAIN VOLTAGE
DC Drain voltage

Voltage
tracks AMPLITUDE signal DC SUPPLY
Supply envelope of
RF signal
0 VDD
Envelope Envelope AMPLIFIER
Detector Amplifier DRAIN Time
VOLTAGE

0 (…. and Restoration)

PHASE signal

RF RF RF RF POWER Output
Signal Amplifier Signal 0 TRANSISTOR signal
In Out

saturated
at all
times
 Comparison of EER and ET

60
Output PWR
efficiency
50

ET
Output Power (W), Efficiency (%)
40
Operating
Range EER
30
Operating
Point
20

Traditional PA
Operating 10
Range
0
0 0.5 1 1.5 2 2.5 3 3.5
Input power (W)
 EER / ET Comparison
Potentially highest efficiency
Requires very accurate dynamic supply
EER Input drive power is greater
Leakage of input signal to output is a problem for low
output drive
Phase signal has very broad bandwidth
Time alignment of phase, envelope very critical

Very good efficiency achievable

ET Dynamic supply accuracy requirements are reduced
Input drive power is modest
Leakage of input signal to output is not a problem
Requires linearization

ET and EER are two limiting cases of a family of architectures,

where the "RF input" is chosen to be in-between a) constant
envelope; and b) envelope equal to that of desired signal
Envelope and Phase Spectra for WCDMA Signal
Much of power is close to DC
Bandwidth is greater than signal bandwidth

PSD of Phase signal

Magnitude (dB)
30
20
10
0
-10
-20
-30
-40
-50
-60
-20 -15 -10 -5 0 5 10 15 20
Frequency offset (MHz)

Considerable expansion of bandwidth

For phase signal!
 Range of System Designs
Bridging Classical EER and Classical ET

RF input envelope
Classical EER
RF input envelope is
optimized to achieve
trajectory with highest
efficiency and
linearity

Signal envelope
Burden of achieving accurate output
envelope is placed jointly on RF stage and on
dynamic power supply
EER / ET Advantages
•High efficiency
•Excellent thermal management for transistor
•Broad tunable bandwidth

EER / ET Challenges
•Vdd amplifier must be low cost, high efficiency, broad
bandwidth, high voltage
•RF stage must operate well over wide Vdd range
•Gain of RF stage tends to be lower (device in
compression to get high efficiency)
 PA Efficiency Can Be Very High With ET
ET PA with Dual Switcher / HVHBT PA

Efficiency

Probability

PDF
WCDMA
6.6 dB PAPR
Pout=67W
Record

CE Gain PAE RF PA Envelope Amplifier

65.6% 12.3dB 61.7% 82% 80%

Measurement of “Instantaneous” Efficiency of PA
During Modulation
Envelope Amp Digitizing
oscilloscope
Env
signal Idd(t)
Current
amplifier
Vdd(t)

coupler
RF RF PA
signal
Vi Vo
 Experimental Envelope Tracking Amplifier
Complex system including
RF stage, analog/digital dynamic power
supply, digital predistortion, up and down-
converters

DC
Drain Modulator
Predistortion
ET/EER and

DC/DC
Envelope
DAC
DSP

I
RF
Q Upcon
WCDMA Output
DAC PA
Drivers Final stage High Power
Downcon
RF Stage
ADC

F= 2.1 GHz
 Constraint on Overall Efficiency
Both RF PA and dynamic power supply must be optimized

Composite Efficiency =

Vdd amplifier efficiency

X
RF stage efficiency
 Representative Envelope Amplifiers
Basestation unit: >250W peak output power, 3- 30V
low cost, off-the shelf components

Many other examples ! CMOS IC

 Buck Dc-Dc Converter
Vbat d Iind / dt = Vind / L
Vh Vout
Iind

Vh Vbat time
Isw

-Vd
time
Vind time
Vbat-Vout
Idiode
time
-Vd-Vout
time
Efficiency can be high (85-95%)
Losses due to I2R & CV2 fsw (best to operate at low fsw)
 Envelope Tracking on Different Time Scales

No tracking
Useful for power
Vdd(t) Fast tracking
variations on
power control
Signal time scale
(critical for
time handset power
amplifiers)
No tracking

Slow tracking Not suited to

EER, only ET

time
 Frequency Response Considerations

Envelope spectrum Phase spectrum

Power Spectral Density (dB/bin)

Cumulative
distribution

Frequency (MHz)

Signal BW=4MHz

Most of envelope power is at DC!

Portions of envelope power extend well beyond 2-3*BW
Accurate envelope over 2-3*BW required for full fidelity
Strategies for Providing Efficient Broadband Supply Voltage

Video amplifier

Dc-dc converter
Current Source
Voltage Source Low BW
High BW Eff > 90%
Eff = 50% VDC
VDC
Current
Envelope Sense g
Signal
s d

Switcher
Linear
Stage
Stage

RF Power Transistor Drain Bias

Envelope Amplifier: Overall Efficiency ~ 85%

BW = 50 MHz
 Current Source
Voltage Source Low BW
High BW Eff > 90%
Envelope Amplifier VDC
Eff = 50% VDC

Architecture Envelope
Signal
Current
Sense
s
g

Switcher
Linear
Stage
Stage

RF Power Transistor Drain Bias

Envelope Amplifier: Overall Efficiency ~ 85%

BW = 50 MHz
 Design Example: CMOS Envelope Amplifier
for LTE Handset Applications VDD

M5

Switching
Anti-shoot L
Through &
Gate

Stage
Drivers c
M6

Linear Stage
M3 M2
Rsen

Env_in
id
Sense & Control
OTA

ia OP AMP

M4 M1

R1 R2 To PA

Vout
2V/div

Vin 0.15um CMOS

0.5V/div
M. Hassan et al
Time (100ns/div) RFIC 2011
Envelope-Tracking Amplifier CMOS & SOS Power Amplifier

Overall
efficiency
reaches 50% !!

Band 13 (782 MHz)

10MHz LTE signal 16 QAM, PAPR=6.6dB

CSICS 2012
 ET PA with Dual Switcher / HVHBT PA

Before DPD
Efficiency After DPD

After
Memory
Mitigation*

Probability

PDF

WCDMA [dBc] ACPR1 ACPR2 NRMSE

6.6 dB PAPR Before DPD -35.4 -45.5 6.8%

Pout=67W After ML DPD -45.3 -50.7 2.4%

After Memory -55.5 -60.2 0.7%
Record mitigation

CE Gain PAE RF PA Envelope Amplifier

65.6% 12.3dB 61.7% 82% 80%

Qualcomm RF 360