EE4410 – Project

ECG Signal Acquisition System

XU Yong Ping
Dept of Electrical and Computer Engineering
Email: elexuyp@nus.edu.sg

EE4410 – Integrated circuit and system design – Xu YP 1

Outline
1. Module organization
2. Project Introduction
3. A-to-D Conversion Basics
4. Successive Approximation ADC
5. Band-gap reference
6. Noise analysis

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1. Module organization
„ Aims
Through the design of a prototype IC chip
„ To provide the opportunity for students to apply
fundamentals and theory to the real life problems
„ To improve students’ analytical and problem solving
skills
„ Expose students to commercial integrated circuit
design flows and teamwork
„ To introduce mixed-signal circuit design, in particular,
ADCs and DACs

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How to study in this module?

„ Try to apply what you have learned before and in this module to
the practical problems in the project. Many modules you studied
before are relevant to this project.
„ Although the design tool (such as Cadence) is very powerful,
always remember to pay attention to and understand the
underlying principles
„ “Try and error” with the powerful design tools is not a good
approach to carry out the design. Only use the design software to
assist your analysis.
„ Literature research helps you understand the existing methods and
techniques, as well as their limitations. Try not to copy what
people have done, but understand their approaches and
limitations, and see if you can come up with better ideas to
overcome their limitations, and hence improve the performance.
„ There are many ways to design and realize the same function.
Analog and mixed-signal IC designers need to be innovative.

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Lectures and Labs (1)
Semester 1:
Familiarization
with EDA tools Chip design

2 weeks 11 weeks

4 ~ 5 weeks

Tape-out

Start Lecture (2hrs/wk) Laboratory (4hrs/wk)

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Lectures and Labs (2)

Semester 2:
1. Chip design presentation Testing the
2. Chip test preparation fabricated chip Report writing

2-3 weeks 8 weeks 2 week

2-3 weeks
Design presentation
Presentation from each group Assessment

Start Lecture (2hrs/wk) Laboratory (3hrs/wk)

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2. Project introduction

„ Scope
„ Specifications
„ Project schedule and execution
„ Assessment
„ Refer to the handout for more details

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The scope
„ ECG (Electrocardiogram) signal acquisition system

Low noise Lowpass Successive Approx.

Sample
Amplifier ADC
filter &hold
Vin,ECG +
LPF S /H ADC Dout
-

Bias Voltage
circuit Reference

„ Recommendation for system partition

„ Low noise amplifier and LPF (one student)
„ ADC and S/H (two students)
„ Bandgap reference (one student)

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Specifications
„ System and analog
„ Technology: 0.35-μm CMOS
„ System supply voltage: 3V
„ System bandwidth: 0.5 – 150Hz
„ Amplifier gain: 200
„ Input referred noise: <10 μV (0.5-150Hz)
„ Input signal amplitude: up to 5 mVp-p
„ Common-mode input range: ±0.5V
„ DC offset rejection: > ±50 mV
„ CMRR (instrum. amplifier): > 50dB
„ Power consumption: As low as possible
„ ADC
„ Resolution: 10 bits
„ Sampling frequency 500Hz
„ Output format: Binary coded
„ DNL and INL: < 2 LSB
„ Load capacitance: 2.5pF@ADC output
„ With on-chip reference
„ End of conversion (EOC)
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Schedule and execution

„ Week 0
„ Introduction to module and project
„ Grouping and lab schedule
„ Week 1 – 6
„ Lectures and chip design (lab)
„ Week 7 – 11
„ Chip design (lab)

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Assessment

„ Individual
„ Subsystem design 35%
„ Subsystem performance 20%
„ Chip design presentation 10%
„ Team
„ Overall chip design 15%
„ Overall chip performance 15%
„ Report writing 5%

EE4410 – Integrated circuit and system design – Xu YP 11

3. A-to-D conversion

„ Qantization
„ Sample & hold
„ Anti-aliasing filter

vin n
Sample
Anti-aliasing
&hold
Quantization vo

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Quantization and noise
Quantization noise:
Analog input Digital output
3-bit ADC ADC
Theoretical ADC Vin Dout
transfer characteristic
111
Center point A full scale (FS) analog signal is converted
110 Midstep Value
into 2n discrete levels which correspond to
Digital output code

101 n digital bits. Hence one LSB (Step width)

for an n-bit ADC is
100
FS
011 Practical ideal 1LSB =
ADC transfer 2n − 1
010 characteristic
For 2n >>1,
001 1LSB value (Step width)
FS FS
1LSB = ≈ =Δ
000
0 1 2 3 4 5 6 7 (FS)
Analog input
2n − 1 2n
where Δ is the quantization step size,
Δ = 1 LSB.
Quantization Error

+1/2 LSB
The quantization error is bounded between
Analog input ±0.5LSB, that is
0 1 2 3 4 5 6 7
Δ Δ
-1/2 LSB
− ≤ eq (n) ≤
2 2
EE4410 – Integrated circuit and system design – Xu YP 13

Signal-to-quantization noise ratio

Quantization noise power: Signal-to-quantization noise ratio:

If assuming that eq(n) is equally distributed (equal Assuming that the signal is a full-scale sinusoidal
probability density) over the range of (-Δ/2, Δ/2), as wave with an amplitude of A, the signal power for
shown below, an n-bit ADC is

P(e) A2 (FS 2 )2
Ps = =
1/Δ 2 2
The signal-to-quantization noise ratio (SQNR) is

e Ps
−Δ/2 0 Δ/2 SQNR(dB) = 10 ⋅ lg
Pn
and is not correlated with the signal, the ⎡⎛ A2 ⎞ ⎛ Δ2 ⎞⎤
quantization noise power (the variance) is = 10 ⋅ lg ⎢⎜⎜ ⎟⎟ ⎜ ⎟⎥
⎜ 12 ⎟
⎣⎝ 2 ⎠ ⎝ ⎠⎦

Pn = σ e2 =
Δ2
e 2 p (e)de =
1 Δ2 2
e de =
Δ2 ⎡ (FS 2)2
≈ 10 ⋅ lg ⎢
(FS 2 ) ⎤⎥
n 2

∫ ∫
Δ −Δ 2 ⎣⎢ ⎦⎥
−Δ 2 12 2 12
≈ 6.02n + 1.76dB

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Sampling and aliasing
xa(t) – Continuous-time signal with bandwidth of B
xa (t) |Xa (ω)|
ms(t) – Periodic sampling function.
xo(t) – Sampled version of xa(t), xo(t)=xa(t).ms(t)

fs = ωs/2π - Sampling frequency.

t -> ω
Ts = 1/fs - Sampling interval and τ – sampling period
2πB’
Sampling theorem:
t ω
-2πB 0 2πB For xa(t) to be reconstructed from its sampled version,
ms (t) τ ∞
xo(t), fs must satisfy
ms (t ) =
Ts
∑m e n
jnω s t
|Ms (ω)|
n = −∞ f s ≥ 2B
1 t -> ω
Aliasing occurs when the above relationship is not
satisfied.

t ω τ ∞
⎛ nπτ ⎞
2π/ωs 0 ωs 2ωs 3ωs X o (ω) = ∑m X n a ( ω − nω s ) mn = Sa⎜⎜ ⎟⎟
τ Ts n = −∞ ⎝ TS ⎠
xo (t) |Xo (ω)|
Sample ωs
≥ 2 B (No aliasing)
2π
xa (t) xo (t) ωs
< 2 B ' (Aliasing occurred)
2π

ms (t)
t ω
0 ωs 2ωs 3ωs

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A/D converter specifications

‰ DC specifications (Static errors)

‰ Gain error
‰ Offset error
‰ Differential nonlinearity error (DNL)
‰ Integral nonlinearity error (INL)
‰ Dynamic specifications
‰ Signal-to-noise and distortion ratio
‰ Dynamic range
‰ Spurious free dynamic range
‰ Effective resolution bandwidth and effective number
of bit (ENOB)

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Gain and offset errors
Gain error (-1 ¾ LSB)

3-bit ADC 3-bit ADC

111 111
Actual ADC Ideal ADC
110 transfer 110 transfer
characteristic characteristic

Digital output code

Digital output code

101 101

100 100

011 Ideal ADC 011

transfer Actual ADC
010 010
characteristic transfer
001 characteristic
001

000 000
0 1 2 3 4 5 6 7 (FS) 0 1 2 3 4 5 6 7 (FS)
Analog input Analog input

The gain error is the difference between its actual Offset error (¾ LSB)
and ideal FS value. It may be expressed in terms
of LSB or in the percentage of the FS value. In The offset error is defined as the amount of the
this example, the gain error is negative. analog value shifted from zero when the digital
output code is zero. It may be expressed in terms
For the actual ADC transfer characteristic, the full of LSB or in the percentage of the FS value.
scale point can be determined by either the
endpoint or the best fit line.
EE4410 – Integrated circuit and system design – Xu YP 17

Nonlinearity errors (DNL and INL)

3-bit ADC 3-bit ADC

111 111
Max. INL is ½ LSB.
110 Max. DNL is ¾ LSB. 110
Digital output code

½ LSB
Digital output code

101 101
½ LSB
100 100
¼ LSB
011 011
- ¼ LSB
¾ LSB
010 010
-¼ LSB ¼ LSB
001 001
½ LSB
¼ LSB
000 000
0 1 2 3 4 5 6 7 (FS) 0 1 2 3 4 5 6 7 (FS)
Analog input Analog input

The integral nonlinearity error (INL) is defined as

The differential nonlinearity error (DNL) is the deviation of the actual transfer function from the
defined as the difference between the actual step straight line that is determined by the endpoints or
width and the ideal value of 1 LSB from one the best fit line. The deviations are measured at the
adjacent level. It is often expressed in LSB or the transitions between the steps. The INL is expressed
percentage of the FS. in LSB or the percentage of the FS. Note that the
the offset and gain errors must be nullified before
INL is measured.
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 Signal-to-noise and distortion ratio

Power spectral density (dB) In this example, when the power spectral
density is used,
Signal tone
Ps
Spurious tones
SINAD(dB ) = 10 lg
Pn
S2
Harmonics
= 10 lg
H 22 + H 32 + N 2
Noise floor where

f H2 – the second harmonic component,

H3 - the third harmonic component,
Signal bandwidth N - the random noise, including the spurious
components.
Signal to noise and distortion ratio (SINAD or SNR)
The SINAD is defined as the ratio of the rms amplitude of
the maximum output signal to the rms value of the total
noise and harmonic distortion components over the
specified bandwidth of interest.

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Dynamic range and SFDR

Dynamic Range - DR Spurious Free Dynamic Range - SFDR
The dynamic range is specified as the The spurious free dynamic range is defined as the ratio
ratio of the rms value of the maximum of the rms amplitude of the maximum output signal to
range of an input sinusoidal signal to the the rms value of the peak spurious signal over the
rms value of the total noise and distortion specified bandwidth of interest.
at the output (over a specified signal
bandwidth of interest) when the same
input sinusoidal signal is present. It is Power spectral density (dB)
expressed in dB.
Signal tone
Note that in most cases, the DR is not 0dB
Spurious tones
equal to the maximum SINAD or SNR. SFDR
SNR Harmonics
120dB

Noise floor
DR Peak SNR

f
0dB Signal bandwidth
DR
Input amplitude
-120dB Max. input (0dB)

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Effective number of bits (ENOB) and
effective resolution bandwidth (ERBW)
Effective number of bits (ENOB): Effective resolution bandwidth (ERBW) [1]

Recall: ERBW is defined as the frequency at which the

ENOB is reduced by ½ LSB from its ENOB at dc.
SQNR(dB) = 6.02n + 1.76dB
If SINAD is used, the ERBW is the frequency at
which the SINAD is reduced by 3 dB from its value
n-bit resolution
at dc.

Ideal SNR when only quantization

ENOB (SINAD)
noise is considered

Measured SNR n
ENOB: n – 0.5 (-3dB)
SINAD(dB) − 1.76
ENOB(bit ) =
6.02

Effective resolution fin

0
ERBW
ENOB, in principle, contains the same information
as the SINAD.

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4. Successive approximation ADC

X = 13.7 (25)
0 32
Concept
(5-bit ADC)
ref1= 16

1. X > 16? No 0 < X < 16

0 "0" is assigned to bit 4 (MSB)
X 16

ref2 = 8

2. X > 8? Yes 8 < X < 16

8 X 16 "1" is assigned to bit 3

ref3 = 12
3. X > 12? Yes 12 < X < 16
12 X 16
"1" is assigned to bit 2

ref4 = 14
4. X > 14? No 12 < X < 14
X "0" is assigned to bit 1
12 14

ref5 = 13
5. X > 13? Yes 13 < X < 14 "1" is assigned to bit 0 (LSB) and the digital output is 01101.

~ 14 − 13
x = 13 + = 13.5 ⇒ Error = 13.5 − 13.7 = −0.2
2
14 − 13 1
Error (max) = ± = ±0.5 ⇒ ± LSB
2 2
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System architecture

Comparator
Vin,ana
S/H +
- Vref
CLK
Error

DAC Vin Final approx.

Vref

Dout 0.5Vref
1 0 1 1 0 0 1 Dout

CLK Register

SAR
S.Conv 0
1 2 3 4 5 6 7
# of successive approximation

SAR – Successive Approximation Register

EE4410 – Integrated circuit and system design – Xu YP 23

Successive approx. Register (SAR)

S.conv
Comparator
Vin,ana
S/H + k=0
-
CLK
k = k+1
Vref DAC
Bit(n-k) = 1 no
Dout yes
n - k = 0? E.conv

CLK Register yes

Vin > VDAC?

no
SAR
S.Conv
Bit(n-k) = 0

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Successive approx. Register (SAR)
Example:

*Johns & Martin, Analog Integrated Circuit Design, First edition, John Wiley & Sons, 1997

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Charging scaling DAC

Charge Scaling (Capacitor divider)

Capacitor array DAC

n
(Ctotal = 2 C) When the kth capacitor is switched to Vref
Vo
n-1
2C C C
2 C n-2 2k C
2 C
Vo = ⋅ Vref = 2 k − n ⋅ Vref
2n C
k = 1, 2, L ( n − 1)
Vref

Charge Scaling DAC

Vout
n-1
2 C 2C C C
n-2
2 C
n −1
2k C
Vout = ∑ Dk ⋅ Vref
k =0 2n C
Vref

Dn-1 Dn-2 D1 D0

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SA-ADC based on charge scaling

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Charge redistribution DAC

Charge redistribution (Charge sharing)

Discharge C array D2 = 1, D1,0 = 0

Vo
Vo
2C C C
2C C C S1 2C V ref
S1
Vo = ⋅ V ref =
4C 2

V ref V ref

D2 D1 D0 D2 D1 D0

D1 = 1, D2,0 = 0 D2,1 = 1, D0 = 0

Vo Vo

2C C C 2C C C
3V ref
S1 V ref S1 3C
Vo =
C
⋅ V ref = Vo = ⋅ V ref =
4C 4 4C 4
Vref
Vref

D2 D1 D0
D2 D1 D0

* D2 returns to 0, 2C is discharged. Vo is back to zero before D1 becomes 1.

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SA-ADC based on charge redistribution

reset
Capacitor array DAC
(Ctotal = 2nC) Vtop
Dbit,out
2n-1C 2C C C Comparator
2n-2C
from SAR

Vin
Vref

Operation: Reset Sampling Vin Conversion

Reset reset Sampling Vin

reset
VC = 0 Capacitor
array
Dbit,out Vin
Capacitor Dbit,out
array Comparator
VC Comparator
VC = −Vin
*Assume Vos = 0
EE4410 – Integrated circuit and system design – Xu YP 29

SA-ADC based on charge redistribution

(cont’d)
Conversion: reset

Capacitor array DAC

(Ctotal = 2nC) Vtop
Dbit,out
2n-1C 2C C C Comparator
2n-2C
from SAR

Vin
Vref

Vref
2
Vref
Vin
Vi ,comp = −Vin + >0
reset 2 reset
n-1 ⇒ Dn −1 = 0 n-2
2 C 2 C
Vi,comp Vi,comp
Vref Vref
Dn-1 Dn-1
n-2
n-1 Vin Vref 3(2 )C Vin Vref
2 C Comparator Comparator
2 4

Vref
Vi ,comp = −Vin + Vi ,comp = −Vin +
Vref
2 4
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Capacitance mismatch error
Assume that the unit capacitor, C, has a mismatch of ΔC.

Worst-cases INL:

( )
INL max = 2 n −1 C + ΔC max,INL − 2 n −1 ⋅ C = 2 n −1 ⋅ ΔC max,INL

C LSB
ΔC max,INL ≤ for INL <
2n 2

Worst-cases DNL:

DNLmax = ( 2 n − 1) ⋅ ΔC max,DNL

1 C LSB
ΔC max,DNL ≤ ⋅ for DNL <
2n − 1 2 2

EE4410 – Integrated circuit and system design – Xu YP 31

Reported successive approx. ADCs

[1]
[2]

[1] M. D. Scott, B.E. Boser, K. S. J. Pister, “An Ultralow-

[3]
Energy ADC for Smart Dust,” J. Solid State Circuit,
Vol. 38, pp. 1123-1129, July 2003.

[2] T. Yoshida, et al. “A 1V supply successive

approximation ADC with rail-to-rail input voltage range,”
Proc. ISCAS 2005, pp. 192-195, May. 2005

[3] L. S. Y. Wong, et al., “A Very Low Power CMOS Mixed-

Signal IC for Implantable Pacemaker Applications,”
ISSCC Dig. Tech.Papers, pp.318-319, Feb. 2004.

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Commercial Successive approx. ADCs
„ Resolution: 12b
„ Conv. Time: 1.6μS
„ Throughput: 100kSPS
„ Supply: +2.7 to 5.25V
„ Power dissipation:
0.9mW@100kSPS and 3V

„ Resolution: 10b
„ Conv. Time: 20μS
„ Supply: +5V and -12V
„ Power diss.: 325mW

EE4410 – Integrated circuit and system design – Xu YP 33

Comparator
Ideal comparator Non-ideal comparator
V0 V0
V0 V0
Vop+ Vop Vop
Low gain
+
Vin V0 High gain
- 0

Vin Vin
0
Vin = V+ − V− Vop- Vin
0
0 Vref
Minimum resolved Hysteresis
‰ Infinite gain ⎧Vop + ← (Vin > 0) ⎧Vop ← (Vin > Vref ) input voltage
V0 = ⎨ V0 = ⎨
‰ No hysteresis ⎩Vop − ← (Vin < 0) ⎩ 0 ← (Vin < Vref )
Effect of non-idealities:
V0 V0 Limited slew rate ‰ Low gain reduces the
resolution.
Vop Vop
‰ Non-zero offset
Vin ‰ Zero rise and Vin introduces error.
Vref fall time ‰ Hysteresis introduces
Vref
‰ No input offset Zero offset error, but increases the
Non-zero offset noise immunity.
t t ‰ Slew rate limits the
0 0 speed.

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High-gain amplifier as a comparator

In summary, a comarator should have

Setting time of the single-pole amplifier
‰ High gain
‰ High speed
|A(jω)|
‰ Low offset and hysteresis

Avo
Avo ⋅ ω3dB = ωu
High-gain Amplifier as a comparator Acl ⋅ ω3dB −cl = ωu
Acl=1/β

V0
0dB ω
Vop+ ω3dB ω3dB-cl ωu
+
Vin A V0
ideal low gain
-
Vin V0
high gain
ΔV0
AV = slope =
Vop- ΔVin Vfinal

Specified settling error

(% with respect to Vfinal)

High gain and high slew rate are required.

t
0 tsettle

EE4410 – Integrated circuit and system design – Xu YP 35

Linear settling time

Linear settling time: The output of the closed-loop amplifier is,
assuming that Vin (s) is a step signal,
ƒ The settling time is a small signal behavior
ωu
and can be obtained from the inverse v0 (s ) = vin (s )
Laplace transform of the transfer function. s + ω3dB −cl
ƒ A closed-loop amplifier is shown below. In time domain,
Assume that the opamp is compensated to a
single-pole response. v0 (t ) =
1
β
( )
1 − e −ω3 dB− clt vin (t )

β The settling time is Actual output

-
A(s)
−1 ⎛ v (t ) ⎞ − 1 ⎛ vin (t ) β − v0 (t ) ⎞
Vo(s) t settle = ln⎜1 − 0 ⎟= ln⎜ ⎟⎟
ω3dB ⎜⎝ vin (t ) β ⎟⎠ ω3dB ⎜⎝ vin (t ) β ⎠
Av 0
Open-loop: Av (s ) = (1) Expected output Settling error
1 + s ω3dB
For the settling error less than 1%,
V0 (s ) Av (s )
Closed-loop: Acl (s ) = = (2)
Vin (s ) 1 + βAv (s ) 4.6 4.6
t≈ or t≈
ω3dB −cl ωBW
Substitute (1) into (2),
ωu ωu
Acl (s ) = = (βAV 0 >> 1) ωBW = ω3db (Open-loop)
s + βωu s + ω3dB −cl = ω3dB-cl (Close-loop)
= ωu (Unity-gain)

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Nonlinear settling time – slew rate
„ Nonlinear settling is a large signal behavior. Small-signal model or analysis is
therefore not valid.
„ Transistors are operated in nonlinear regions (triode or cutoff)
„ The nonlinear settling time is determined by the slew rate
„ Slew rate indicates how fast the output signal reaches its final value under large
signal condition.

Vin -
I0 A2 Vo
+
- VC + I0 CL

M1 M2 CC
I0
- Vo
A2
I0 +
M3 M4 dVC dV0 dVC I
CC = I0 SR = = = 0
dt dt dt CC

gm 2 I 0 ⋅ ωu
Since ωu = SR ==
CC g m2

EE4410 – Integrated circuit and system design – Xu YP 37

Regenerative comparator
Regenerative latch
Regenerative latch and metastability:
Preamplifier
CL CL
+
A Latch V0
-

CLK
ΔVinitial/final

- Regenerative latch increases the speed of the

Latch time – the time required for the latch output to
comparator due to its positive feedback. reach a valid logic level.
- Preamplifier increases the resolution of the
comparator and reduces the ‘kick-back noise’. CL ⎛ ΔV final ⎞
tlatch = ln⎜ ⎟
Gm ⎜⎝ ΔVinitial ⎟⎠ (2.1)

Kick-back noise Gm is the transconductance of the inverter.

Vfinal
Drive + Regenerative
Vin A V0
circuit - latch
Valid logic high

CLK
Preamplifier
acts as a buffer Vinitial

Valid logic low

The ‘kick-back’ noise occurs when the latch is
reset. It disturbs the output of drive circuit
which may take long time to recover.
EE4410 – Integrated circuit and system design – Xu YP
tlatch
Metastability occurs when the valid logic level cannot be
Reached within the required time frame. To reduce metastability,
large Vinitial and high transconductance are required.
38

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Examples

Regenerative comparator 1
φ1 = 0 -> Track phase
The drain voltage of M12 and M13. is equal to VDD and Q
M12 M13 = 0. The drain voltage of M6 and M7 is ground.
Vibias M5 φ1 φ1
M14 M15
Q φ1 = 1 -> Latch phase
M2
Vip M1 Vin φ1 The drains of M6 and M7 are discharged initially through
Qn
D1 M10 M8 and M9. The discharge currents depend on the input
M11
signal. After the discharge starts, an ΔVinitial is
D2 M8 M9 developed across the latch and regenerative process
M3 M4 follows.
M6 M7

The diode connected transistors D1 and D2 -> limits the

Preamplifier Latch output swing and helps the overload recovery.

No static current in the latch, therefore, low power

consumption.

The bandwidth of the preamplifier may be limited due to

the high resistance at the output node.

Low kick-back noise.

EE4410 – Integrated circuit and system design – Xu YP 39

Examples (cont’d)

Regenerative comparator 2 Regenerative comparator 3

M8 M9 M4
Vbias M3 φ1 M6 M8 M9
M5 M7
To SR latch
M1 M2 φ2
Vin φ1
M1 M2 V0
Vin
M12 M12

M10 M11 M10 M11

Vbias M3

Preamplifier Latch
Preamplifier Latch

φ1 = 0 and φ2 = 1 -> Track phase Low power consumption as there is no static

Two output nodes are pulled to Vdd and M12 is on. current in track phase.
The RS latch holds the previous decision. The
differential current from the preamplifier (M1 and High kick-back noise coupled through the drain-
M2) causes a small ΔVinitial across M12. gate parasitic capacitance of M1 and M2.

φ1 = 1 and φ2 = 0 -> Latch phase. Comparator 3 has less kick-back noise, but slightly
The latch regenerates from ΔVinitial to a full digital high power consumption due to the static current
output. in the latch during track phase.

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Sample and hold circuits
Sample and hold

vin Sample vo
& hold

clk
Ideal Non-ideal
Vo Vo
Vin Vin

h
s s h
t3 t t
0 t1 t2 0

During the sample period, the output tracks the input.

Thus, it is also called “Track-and-hold”.

EE4410 – Integrated circuit and system design – Xu YP 41

Simplest S/H circuit

Clk
Input signal range:
vin vo NMOS: 0 ≤ Vin < VDD − VT
C
vdd

vdd vdd - vT
Vo
C

t
0
Vin
PMOS: VT < Vin ≤ Vdd

t GND
0
Clk GND vT

s h s h s
C
t
0

EE4410 – Integrated circuit and system design – Xu YP 42

21
On resistance of switch

Ron
1 NM OS
NMOS: Ron ,n = → ∞, when Vin = Vdd − VT
W
μ n Cox (VDD − Vin − Vth )
L

1 0 V DD − VT
PMOS: Ron , p = → ∞, when Vin = VT Vin
W Ron
μ n Cox (Vin − Vth )
L
PM OS

NMOS/PMOS: Ron , np = Ron , n Ron , p

0 VT Vin
Ron,np Ron,np High Ron
Complementary switch gives low Ron,
but requires Low voltage
- Complementary clock problem
- More chip area
- More leakage
0 VT Vdd − VT Vin 0 Vdd − VT = VT Vin
EE4410 – Integrated circuit and system design – Xu YP 43

Settling (Acquisition) time

V0
Ron actual
vin vo

h t h t h t h t

t
First-order settling:

⎛ v (t ) ⎞ ⎛ 1 ⎞
t settle = − Ron C ln ⎜⎜ 1 − 0 ⎟⎟ = Ron C ln ⎜⎜ ⎟⎟
⎝ v in (t ) ⎠ ⎝ settling error ,% ⎠
Fast settling requires small Ron and C
⎛ 1 ⎞
C ln ⎜⎜ ⎟⎟
or t settle = ⎝ settling error ,% ⎠
W Signal dependent
μ n C ox (Vclk − Vin − VT )
L
EE4410 – Integrated circuit and system design – Xu YP 44

22
S/H errors and remedies

„ Clock feedthrough
„ Charge injection
„ Droop (Voltage on holding capacitor)
„ Aperture time and error

EE4410 – Integrated circuit and system design – Xu YP 45

Clock feedthough

vdd
ΔV C gs
0
ΔV = VDD
Clk C gs + C L

Cgd Cgs
- Clock feedthrough is caused by parasitic capacitance
vin vo in MOSFET.
C - Independent of input voltage.
- Only introduces constant DC offset or Pedestal error.

Remedies:
vdd
vdd
- Use dummy transistor Clk Clk
0 0
- Use complementary switch
- Use differential structure Cgd Cgs Cgd/2 Cgs/2

vin vo
Δq Δq/2 Δq/2
C Dummy
transistor
(half size of the switch)

EE4410 – Integrated circuit and system design – Xu YP 46

23
Channel charge injection

vdd
Clk
Charges in the channel exit from source and drain, and
0
are injected onto signal source and the sampling
capacitor, causing an error in the voltage across the
vin vo capacitor.
Δq Δq C

1 WLC ox (V DD − Vin − Vth )

ΔV = ⋅
2 C
vin C
Signal dependent!

Assuming that half of the channel charge exits

n n from source or drain

P-sub

EE4410 – Integrated circuit and system design – Xu YP 47

Channel charge injection – cont’d

1 WLC ox (V DD − Vin − Vth ) ⎛ WLC ox ⎞ WLC ox (V DD − Vth )

V0 = Vin − ΔV = Vin − ⋅ = Vin ⎜ 1 − ⎟−
2 C ⎝ 2C ⎠ 2C

When consider body effect: (VSB = Vin)

⎛ WLC ox
V0 = Vin ⎜ 1 −
⎝ 2C
⎞ WLC ox
⎟−
⎠ 2C
[ (
V DD − Vth 0 + γ 2φB + VSB − 2φ B )]
⎛ WLC ox
= Vin ⎜ 1 −
⎝ 2C
⎞ WLC ox
⎟−
⎠ 2C
γ 2φB + Vin −
WLC ox
2C
(
VDD − Vth 0 + 2φ B )
[6]
Linear Non-linear DC offset

Signal dependent error causes distortion.

Remedies:
Same remedies for clock feedthrough can be used to reduce the charge injection.

EE4410 – Integrated circuit and system design – Xu YP 48

24
Droop

Droop – leakage of charge from the holding capacitor

Clk
vin
v0
CL RL
n n

P-sub Leakage

Leakage

EE4410 – Integrated circuit and system design – Xu YP 49

S/H circuits
Open-loop S/H circuits

WLC ox (V DD − Vin − Vth )

Clk 1
Clk Δq =
2
vin +
A vo vin vo
-
C
RL Δq Δq C

- Opamp voltage follower acts as a buffer for S/H circuit.

- High gain is required to ensure the virtual short at the inputs of the op-amp and
hence the accuracy of the S/H signal.
- Fast settling is required for the op-amp voltage follower.
- Since the non-dominant pole may not be far away from the unity gain frequency,
the follower is a second-order system and may have a slower settling than the
first-order system.
- Signal dependent charge injection exists

EE4410 – Integrated circuit and system design – Xu YP 50

25
Closed-loop S/H circuit -1
φ1

φ2

-
φ1 vo
- A
A +
vin +

Track
Hold
-
- (vin) A vo
- A vo +
A +
vin +
C
C

- Closed-loop with holding capacitor at the output of the op-amp

- The first op-amp can deliver large charging and discharging current and therefore, improve the speed.
- Hold phase is similar to the open-loop S/H.
- Signal dependent charge injection still exists

EE4410 – Integrated circuit and system design – Xu YP 51

Closed-loop S/H circuit - 2

φ1 C
-
+ φ2 A vo
A +
vin -

Track (φ 1) Hold (φ 2)
C
C -
- A vo
+ A vo +
A +
vin -

C
Signal dependent charge injection is eliminated Clk
Since one terminal of the switch is at ground or
Virtual ground.
-
WLC ox (V DD − Vth )
1
Δq = Δq +
2

EE4410 – Integrated circuit and system design – Xu YP 52

26
Bottom-plate sampling S/H circuit

φ1 φ1
SW1
φ2
vin vo vin vo
Δq1 Δq2 Δq 1 Δq 2=0
C t C
φ1
SW2 I c=0
φ2 φ2
t

- Clock φ2 is closed slightly earlier than φ1.

- Since there is no current path through the capacitor, Δq2 is zero and the charge on
C remains unchanged.
- The charge injection from SW2 to the bottom plate is signal-independent.
- Signal dependent charge injection is therefore eliminated.

EE4410 – Integrated circuit and system design – Xu YP 53

5. Band-gap reference

ƒ Outline
ƒ Bandgap voltage reference
ƒ PTAT current source
ƒ Design issues

EE4410 – Integrated circuit and system design – Xu YP 54

27
Bandgap voltage reference
Temperature independent voltage source

+
k1 Vref = k1V1 + k2V2

k2
V1 ∂V1 ∂T > 0
With properly chosen k1 and k2,
reference voltage, Vref, can be made
independent of the temperature, that
V1 has a positive V2 ∂V2 ∂T < 0
is,
temperature coefficient.
dVref ∂V1 ∂V
= k1 + k2 2 = 0
V2 has a negative dT ∂T ∂T
temperature coefficient

EE4410 – Integrated circuit and system design – Xu YP 55

Voltage source with negative TC

IC
kT
IC = I S e VBE VT
VT =
q
I0 − E g kT I0
I S = bT 4+ m e
T2 > T1
b – proportionality factor
Eg – bandgap energy of silicon
VBE
m = -3/2 VBE
VBE(T2) VBE(T1)

IC
VBE = VT ln At room temperature, T=3000K,
IS

∂VBE ∂VT I 0 VT ∂I S ∂VBE

= ln − ≈ −1.5 mV 0
K (Negative TC)
∂T ∂T I S I S ∂T ∂T T =3000 K

Eg
ln − (4 + m ) T − VT
VT I 0 V
=
T IS T kT 2
VBE − (4 + m )VT − E g q
= Note that the temperature coefficient of VBE depends on
T
the temperature.
where assumed that IC is constant and independent
of temperature.
EE4410 – Integrated circuit and system design – Xu YP 56

28
Voltage source with positive TC

ΔVBE = VBE1 − VBE 2

nI 0 I
= VT ln − VT ln 0
nI0 I0 I S1 IS 2
= VT ln n
+ ΔVBE -
∂VBE k Positive TC
= ln n
Q1 Q2 ∂T q

Assuming that two transistors are matched.

I0 ΔVBE = VBE 1 − VBE 2

I0 b I0 I
R ΔVBE
= VT ln − VT ln 0
a I S1 nI S 1
Vb = VBE1 = VT ln n
VBE1
Q1(AE) Q2 (n x AE)

EE4410 – Integrated circuit and system design – Xu YP 57

Bandgap voltage reference

R2
Vref = VT ln n + VT ln n + VBE 2
R3
R1 R2
⎛ R ⎞
b - = ⎜⎜1 + 2 ⎟⎟VT ln n + VBE 2 (1)
a + ⎝ R3 ⎠
+
R3
Vref (Positive TC) (Negative TC)
-
Q1(AE) Q2 (n x AE) ∂Vref ∂VBE 2 ⎛ R2 ⎞ VT
For zero TC of Vref, = + ⎜⎜1 + ⎟⎟ ln n = 0
∂T ∂T ⎝ R3 ⎠ T
⎛ R2 ⎞
or (
⎜⎜1 + ⎟⎟VT ln n = − VBE 2 − (4 + m )VT − E g q ) (2)
Va = Vb , R1 = R2 , Vref = VR2 + VR3 + VBE 2 ⎝ R3 ⎠

VR3 = VBE1 − VBE 2 = VT ln n (2) into (1),

Vref = (4 + m )VT + E g q
VBE1 − VBE 2 1
I R3 = = VT ln n
R3 R3
When T = 0,
R2
VR2 = I R2 ⋅ R2 = I R3 ⋅ R2 = VT ln n Vref = E g q Bandgap voltage reference
R3

EE4410 – Integrated circuit and system design – Xu YP 58

29
BJTs in CMOS technology

C E B

p+ p+ n+
Vertical PNP transistor n-well

p-substrate

C E B

p+ p+ p+ n+
Lateral PNP transistor n-well

p-substrate

EE4410 – Integrated circuit and system design – Xu YP 59

PTAT current source

ΔVBE VT ln n
IR = =
I0 R R
I0 b
R ΔVBE
a Proportional to absolute temperature (PTAT)
Vb = VBE1
Q1 Q2
VBE1 VDD
Area=A Area=nA

VGS +
−

A IR I 0 = IR
+
-

V DD − VGS a b PTAT current

V a − Vb =
A ΔV=0 R1
ΔVBE

Q1 Q2
Area=A Area=nA

EE4410 – Integrated circuit and system design – Xu YP 60

30
Bandgap voltage reference using PTAT

IR
+ R2
-

Vref V ref = I R 2 ⋅ R 2 + V BE 3 = VT ln n + V BE 3
R1
R1
R2
Q2(nxAE)
Q1(AE) Q3

Vref

R1
R2
Q2(nxAE)
Q1(AE) Q3

EE4410 – Integrated circuit and system design – Xu YP 61

Design issues

„ Collector current variation

„ Opamp offset
„ Feedback polarity
„ Start-up problem
„ Temperature dependence of reference
voltage

EE4410 – Integrated circuit and system design – Xu YP 62

31
Collector current variation

I0
I0 VT ln n
R ΔVBE=VTlnn IC = I R = PTAT
R

Q1(AE) Q2(nxAE)

∂VBE ∂VT I C ⎛ 1 ∂I S 1 ∂I C ⎞
= ln + VT ⎜⎜ − ⎟⎟
∂T ∂T IS ⎝ I S ∂T I C ∂T ⎠
∂VT I C VT ∂I S VT
= ln − +
∂T I S I S ∂T T
VBE − (3 + m)VT − Eq q
=
T

EE4410 – Integrated circuit and system design – Xu YP 63

Opamp offset
VDD

R1 R2
VGS +
b -
−
+
a +
+
R3 Vos
Vref A IR
-
+
-

+
Q1(AE) a b
Q2 (n x AE)
Vos R1
ΔVBE

Q1(AE) Q2(nxAE)
V R 3 = V BE 1 − V os − V BE 2 = VT ln n − V os

⎛ R ⎞
V ref = ⎜⎜ 1 + 2 ⎟⎟ (VT ln n − V os ) + V BE 2
⎝ R3 ⎠
IR =
1
(VT ln n + Vos )
R1

*The offset voltage may be a function of the temperature

EE4410 – Integrated circuit and system design – Xu YP 64

32
Feedback polarity

R2
R1 R2
b -
R3
a + b
+ -
R3 Vref
Vref 1/gm2 a
+
- 1/gm1
Q1(AE) Q2 (n x AE)
VBE2 R1
VBE1

Feedback coefficients:

R3 + 1 g m 2 1 g m1
βN = βP =
R3 + 1 g m 2 + R 2 R1 + 1 g m1

A (V BE 1 − V BE 2 − β PV BE 1 + β N V BE 2 )
V ref = Positive feedback if βP > βN
1 − A (β P − β N )

EE4410 – Integrated circuit and system design – Xu YP 65

Start-up problem

The circuit has two equilibrium points. It may not start operation
itself if all nodes have zero initial voltage

Rc

M6

R1
M5

Q1 Q2

Start-up circuit

EE4410 – Integrated circuit and system design – Xu YP 66

33
6. Noise analysis

‰ Noise definition
‰ Noise presentation in time domain
‰ Noise presentation in frequency domain
‰ Noise measures
‰ Noise models
‰ Example

EE4410 – Integrated circuit and system design – Xu YP 67

Noise definition

„ Any unwanted signals or interferences to

the desired signal can be considered as
noise.
„ Examples
„ Random interferences (thermal noise)
„ Toned interference (50/60Hz from main, dc
offset)
„ Spectral interference (flicker noise, aliasing)
„ Mixed interference (inter-modulation)
EE4410 – Integrated circuit and system design – Xu YP 68

34
Noise presentation in time-domain

(Referring to random noise)

Vn2,rms
Normalized noise power: Pn = = Vn2,rms
1Ω

noise
Pn = I n2, rms × 1Ω = I n2, rms
t

1 T 1 T
Average noise power: Pn ,av = Tlim
→∞ T ∫
0
vn2 (t )dt Pn ,av = lim
T →∞ T ∫
0
in2 (t )dt

1/ 2
⎡1 T ⎤
1/ 2
⎡ ⎤ 1
I n, rms = ⎢ ∫ in2 (t )dt ⎥
T
rms noise voltage or current:Vn,rms = ⎢T ∫0 vn (t )dt ⎥
2
⎣ ⎦ ⎣T 0 ⎦

T – Time during which the noise is observed

EE4410 – Integrated circuit and system design – Xu YP 69

Noise presentation in frequency-

domain

Mean squared value (total noise power):

∞ ∞
Vn2,rms = ∫0 Vn2 ( f )df I n2, rms = ∫0 I n2 ( f )df

V2n,rms(f ) and I2n,rms (f ) are the power spectral density (V2/Hz or A2/Hz)

Understand noise spectrum:

∞ Noise spectrum
Noise power

Vn2,rms = ∑ vn2 (n)Δf

n =1
Noise power

Resolution BW

1 2 3 4 5 6
n

EE4410 – Integrated circuit and system design – Xu YP 70

35
Equivalent noise bandwidth (1)

White noise

Vni(f ) H(s)
[
Vno ( f ) = H ( j 2πf ) V ( f )
2 2
ni ]
1/ 2
V2 nw

Filtered out

White noise f0 f

Single-pole transfer function

V2nw
1
f
0dB H ( j 2πf ) = 1/ 2
⎡ ⎛ f ⎞2 ⎤
⎢1 + ⎜⎜ ⎟⎟ ⎥
⎣⎢ ⎝ 0 ⎠ ⎥⎦
f
f0 f

The total output noise power is

V2nw V2nw
∞
Vnw2 V 2 πf
Vno2 ,rms = ∫ df = nw 0
0 1 + ( f f0 )
2
2 feq
f0 f f

π
Equivalent noise bandwidth: feq = f0
2
EE4410 – Integrated circuit and system design – Xu YP 71

Time vs frequency domain (1)

V
P

f3
f2
f1
f0
t
0

EE4410 – Integrated circuit and system design – Xu YP 72

36
Time vs frequency domain (2)

„ None of the signals cannot be identified

except for a slight DC offset.

„ It is quite different result if the signal is

observed in the frequency-domain through
Fourier Transformation (FFT). Its spectral
contents are clearly seen.

EE4410 – Integrated circuit and system design – Xu YP 73

Time vs frequency domain (3)

„ Phase difference between two signals can

be clearly seen in time domain.
„ However, in frequency domain, they are
almost identical.
„ Power spectrum does not convey the phase
information.

EE4410 – Integrated circuit and system design – Xu YP 74

37
Noise summation

Vno (t ) = Vn1 (t ) + Vn 2 (t ) (Vn1 and Vn2 are not correlated)

1 T
[Vn1(t ) + Vn 2 (t )]2dt
T ∫0
Vn1(t)
Vno2 ,rms =
Vn0(t)

2 T
Vn2(t)
= Vn21,rms + Vn22,rms + ∫ Vn1 (t ) ⋅Vn 2 (t )dt
T 0
= Vn21,rms + Vn22,rms

Vno ,rms = Vn21,rms + Vn22 ,rms

In0(t)
Similarly,
In1(t) In2(t)
, rms = I n1, rms + I n 2, rms
2 2 2
I no

I no ,rms = I n21,rms + I n22 ,rms

EE4410 – Integrated circuit and system design – Xu YP 75

Noise measures
Input referred noise (equivalent input noise)
v0
= Av
RS
In1
vin
Vs Vin In2 Vn2 V0
v0 Zin
= Av = Av ,ov
Zin
Vn1
vs Rs + Zin
Noise equivalent circuit: Input referred noise

RS Vn,rms RS

Vn,th Vni
Input In,rms Noiseless circuit Output Input Zin Noiseless Output Vno
Vs Vs circuit

Noisy circuit Noisy circuit

Vn,th – Thermal noise from the signal source

EE4410 – Integrated circuit and system design – Xu YP 76

38
Input referred noise (2)

RS Vn,rms RS

Vn,th In,rms Vni1 Zin Noiseless Vno Vni Vni1 Zin Noiseless
circuit circuit

Noisy circuit Noisy circuit

vn0 = Av ,ovvni
2

vni2 1 = (vn2,th + vn2,rms )

Zin 2
+ in2,rms Rs Zin
Rs + Zin
2

= Av vni1 = Av2 (vn2,th + vn2,rms )

Z in 2
2
vno + Av2in2,rms Rs Z in
Rs + Z in

2
vno
vni2 = 2
= vn2,th + vn2,rms + in2,rms Rs2 = 4kTRs Δf + vn2,rms + in2,rms Rs2
Av ,ov

EE4410 – Integrated circuit and system design – Xu YP 77

Signal-to-noise ratio (SNR)

Noise figure (NF)

Signal-to-noise ratio (SNR):

⎡P ⎤ ⎡V 2 ⎤ ⎡V ⎤
SNR(dB) = 10 log⎢ s ⎥ or SNR(dB) = 10 log⎢ s2,rms ⎥ = 20 log⎢ s,rms ⎥
⎣ Pn ⎦ V
⎣ n,rms ⎦ ⎣Vn,rms ⎦

Ps - signal power , Pn - total noise power

Noise figure (NF)

NF describes how much the noise has increased through the circuit under evaluation.

Total available output noise power

NF =
Output noise power due to thermal noise from the source only

⎛ A v ⎞ ⎛ v2 + v2 + i2 R2 ⎞
NF (dB) = 10 log
(SNR)i
NF ( dB ) = 10 log⎜⎜ v ,ov ni ⎟⎟ = 10 log⎜⎜ n ,th n ,rms2 n ,rms s ⎟⎟ > 1
(SNR)o
or
⎝ Av ,ov vn ,th ⎠ ⎝ vn ,th ⎠

EE4410 – Integrated circuit and system design – Xu YP 78

39
Noise models
Noise in resistors

Thermal or Johnson noise generated from a resistor

Noise spectral density: Vn2,r ( f ) = 4kTR

R
rms noise power in bandwidth Δf : Vnr2 ,rms = 4kTRΔf
Vn,r
rms noise voltage in bandwidth Δf: Vnr ,rms = 4kTRΔf
R - noiseless

4kT
I n2, r ( f ) =
R R
In,r
2
I nr , rms = 4kTΔf R I nr ,rms = (4kTΔf R )1/ 2

Thermal noise is a white noise

EE4410 – Integrated circuit and system design – Xu YP 79

kT/C noise

Noise equivalent circuit H(jw)

Vnr2 ( f ) = 4kTR
R
R C Vn20,rms Vnr(f) C Vn20,rms 1 jωC
H ( jω ) =
R + 1 jωC

1 ∞ 1 ∞ 4kTR ⋅ (1 RC )2 dω = kT
∫0 Vn (ω ) ⋅ H ( jω ) dω = ∫0
2
Vn20,rms = 2
kT/C
2π 2π ω + (1 RC )2
2 C
4kTR

Recalculate the total noise power using the equivalent noise bandwidth:
f0 feq
f

f0 =
1 π π 1 1
-3dB frequency: Equivalent noise bandwidth: f eq = f0 = =
2πRC 2 2 2πRC 4 RC

1 kT
Vn20, rms = 4kTR ⋅ f x = 4kTR ⋅ = Independent of R
4 RC C

EE4410 – Integrated circuit and system design – Xu YP 80

40
Diode

The noise source in a diode or PN junction is shot noise, caused by random passage of
individual charge carriers across a potential barrier. Shot noise is a random noise and white.

kT i(t) P(i)
rD = In,d (t)
qI D
rD In,D ID

t Idiode
ID

Noise spectral density: I n2,d ( f ) = 2qI D Vn2,d ( f ) = 2kTrD

rms noise power in bandwidth Δf : ,rms = 2 qI D Δf

2
I nd Vnd2 ,rms = 2kTrD Δf

EE4410 – Integrated circuit and system design – Xu YP 81

Bipolar transistor

The noise sources in a bipolar transistor include

• Shot noise in base and collector currents
• Flicker noise in base current
• Relates to the trapping and releasing of the carriers by energy states (such as surface
states) caused by the defects in the material.
• Thermal noise in base resistance
Vni
KI B 2qf cnr I B
I nf2 ( f ) = =
f f
Ini
+ 2
I nc ( f ) = 2qI C
2
I nb ( f ) = 2qI B
Input equivalent noise power spectral density:

I nc2 2qI C kT ⎛ 1 ⎞
vni2 = + 4kTrb = ⋅ + 4kTrb = 4kT ⎜⎜ + rb ⎟⎟
g m2 g m qI C ⎝ 2 gm ⎠
Vnb2 ( f ) = 4kTrb
I nc2 ⎛ KI IC ⎞
I ni2 = I nb
2
+ I nf2 + = 2q⎜⎜ I B + B + ⎟
β ( f ) 2 ⎟⎠
fcnr is correlated with the 1/f corner frequency
β ( f )2 ⎝ f
K is a constant related to the process

EE4410 – Integrated circuit and system design – Xu YP 82

41
MOS transistor (1)

The noise sources in a MOS transistor include

• Thermal noise in the channel resistance
• Flicker noise in the channel (arising from the gate-substrate interface)
• Induced gate noise
• Thermal noise in resistive polysilicon gate, drain and source
• Shot noise of junction leakage current
• Thermal noise due to distributed substrate resistance

Thermal noise on channel resistance*:

id2 ( f ) = 4kTg ch = 4kTγg m γ is a bias-dependent parameter

⎧ 1 Triode
⎪
γ = ⎨2 3 Strong − inversion
⎪1 2 Weak − inversion
⎩

*Christian C. Enz and Yuhua Cheng, “MOS transistor modeling for RF IC design,” IEEE Journal of Solid-State Circuits, vol. 35, pp. 186 - 201, February 2000.

EE4410 – Integrated circuit and system design – Xu YP 83

MOS transistor (2)

Flicker noise:
K – process-dependent constant
K W – channel width
Vnf2 ( f ) =
WLCox f L – channel length
Cox – unit gate capacitance

Input equivalent noise power spectral density:

Vnf2 ( f ) Vni2 ( f )
I d2 ( f )

1 K
Vni2 ( f ) = 4kTγ + *Only channel thermal noise and flicker
g m WLCox f noise are considered.

EE4410 – Integrated circuit and system design – Xu YP 84

42
MOS transistor (3)

Induced gate noise

- Thermal noise induced channel voltage fluctuation coupled to the gate through
gate oxide capacitance
- A gate noise current is induced G

ω 2Cgs2
2
ing = 4kTg ng g ng ≈ At strong inversion
5g m i2ng Gng C gs

Induced gate noise is only important at high frequency

S

EE4410 – Integrated circuit and system design – Xu YP 85

Operational amplifier

Noiseless
in-2

v n2 A
+

in+2

The noise sources in an operational amplifier can be modeled by

• An input equivalent voltage noise source
• Two input equivalent current noise sources
• For MOS operational amplifier, the two current sources can be ignored.

EE4410 – Integrated circuit and system design – Xu YP 86

43
Example 1 – Cascode amplifer (1)

A cascode amplifer is shown in the figure below. Calculate the total output noise power at dc
and the input-referred noise. Ignore the flicker noise and assume that gm1 = gm2 = gm, rds1 =
rds2 =rds, RL<<rds and gmrds>>1.

(1) Total noise power at DC

RL
(i) Equivalent circuit with all noise sources
vn3
v0
vn2 rds2
Vbias M2
vn1
vin M1 - vgs2
rds1 + gm2vgs2
vn1 RL vno
gm1vgs1 vn2 vn3

EE4410 – Integrated circuit and system design – Xu YP 87

Example 1 – Cascode amplifer (2)

= g m1 (rds1 rin 2 ) ≈
(ii) Calculate Vno1 due to Vn1 v gs 2 g m1
Av1a = =1
rds2 vn 1 gm 2

ix ⎛ v +v ⎞
vno1 = −⎜⎜ g m 2 vgs 2 + no gs 2 ⎟⎟ ⋅ RL
+ rds1 - gm2vgs2 + ⎝ rds 2 ⎠
vgs2 RL
vn1
vno1 (1 + g m 2 rds 2 )RL
gm1vn1 vno1
- + -
Av1b = = ≈ − g m 2 RL
vgs 2 rds 2 + RL
rin2
vno1
Av1 = = Av1a ⋅ Av1b ≈ − g m 2 RL
DC gain from Vn1 to Vn01: vn1
vx − ix RL
ix = g m 2 v x + Output noise power due to vn1:
rds 2

1 = Av1 ⋅ vn1 = ( g m RL ) ⋅ vn1

vx r + RL 1 2
vno 2 2 2 2
√
rin 2 = = ds 2 ≈ (RL << rds )
ix 1 + g m 2 rds 2 g m 2

EE4410 – Integrated circuit and system design – Xu YP 88

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Example 1 – Cascode amplifer (3)

⎛ v −v ⎞
(iii) Calculate Vno2 due to Vn2 vno 2 = −⎜⎜ g m vgs 2 + no 2 1 ⎟⎟ RL (E3)
⎝ rds ⎠
rds2
Substituting (E1) and (E2) into (E3),
+ vgs2 -
⎛R ⎞
+ + gm2vgs2
+ vno 2 ≈ −⎜⎜ L ⎟⎟ ⋅ vn 2 (g r >> 2 )
m ds
vn2 rds1 v1
RL vno2 ⎝ rds ⎠
- - -
v R
Av 2 = no 2 ≈ L
vn 2 rds
DC gain from Vn2 to Vno2 :

⎛ v −v ⎞
v1 = (g m rds vgs 2 + vno 2 ) (E1)
1
v1 = ⎜⎜ g m v gs 2 + no 2 1 ⎟⎟rds
⎝ rds ⎠ 2

vgs 2 = vn 2 − v1 = vn 2 − (g m rds vgs 2 + vno 2 )

1 Output noise power due to vn2:
2 2 2
vno 2 ⎛ RL ⎞ 2
2vn 2 − vno 2 = ⋅ = ⎜ ⎟
⎜ r ⎟ ⋅ vn 2 √
2 2
vgs 2 = vno 2 vn 2
⎝ ds ⎠
(E2) vn 2
2 + g m rds

EE4410 – Integrated circuit and system design – Xu YP 89

Example 1 – Cascode amplifer (4)

(iv) Calculate Vno3 due to Vn3 Substituting (E4) into (E5),

rds vn 3
vno 3 =
R ⎛ 1⎞ 1
RL 1 + L − ⎜⎜ g m + ⎟⎟ RL ⋅
rds ⎝ rds ⎠ g m rds
- +
rds vgs2 gm2vgs2
+ v ≈ vn 3
no3
vn3 -
+
-
vno 3
Av 3 = ≈1
vn 3
DC gain from Vn3 to Vno3 :

⎛ v +v ⎞ Output noise power due to vn2:

vgs 2 = −⎜⎜ g mvgs 2 + no 3 gs 2 ⎟⎟rds
⎝ rds ⎠ vno2 3 = vn23 √
vno 3
vgs 2 = −
2 + g m rds (E4)

⎛ v +v ⎞ R ⎛ 1⎞
vno 3 = vn 3 − ⎜⎜ g m v gs 2 + no 3 gs 2 ⎟⎟ RL = vn 3 − L vno 3 − ⎜⎜ g m + ⎟⎟ RLv gs 2 (E5)
⎝ rds ⎠ rds ⎝ rds ⎠

EE4410 – Integrated circuit and system design – Xu YP 90

45
Example 1 – Cascode amplifer (5)

(v) Total output noise power (2) The input-referred noise

2
vno = vno
2
1 + vno 2 + vno 3
2 2
vn20 vn20 4kTRL 2
vni2 = 2 = 2 ≈ + 4kT
2
vno1 2 vno 2 2
2
v
2
AV g m RL ( g m RL )2 3g m
= vn 1 + vn 2 + no 3 vn23
v n1 vn 2 vn 3
⎡ ⎛R ⎞ ⎤
2
From RL
= ⎢(g m RL ) + ⎜⎜ L ⎟⎟ ⎥ ⋅ 4kT
2 1
+ 4kTRL
2

⎢⎣ ⎝ ds ⎠ ⎥⎦
r 3 gm From input transistor

≈ (g m RL ) 4kT
2 1
+ 4kTRL
2

3 gm
Vno2 can actually be ignored.
⎛ 2 ⎞
= 4kTRL ⎜1 + g m RL ⎟
⎝ 3 ⎠

Since 2/3gmRL >> 1, the noise from the input transistor is the dominant noise source.

EE4410 – Integrated circuit and system design – Xu YP 91

Other reading materials

1. Johns and Martin, Analog Integrated Circuit Design, John
Wiley & Sons, 1997.
2. Razavi, Desing of Analog CMOS integrated circuits, McGraw
Hill, 2001.
3. Paul Gray, et al. Analysis and design of analog integrated
circuits, Fourth Edition, John Wiley & Sons, 2001
4. Allen & Holberg, CMOS Analog Circuit Design, Second
Edition, Oxford University Press, 2002
5. Jacob Baker, CMOS Circuit design, layout, and simulation,
2nd edition, Wiley, 2005.

EE4410 – Integrated circuit and system design – Xu YP 92

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