Sequential Circuit Design:

Part 2
• C2MOS Latch
• Two-phase clock generators
• Four-phase clocking
• Pipelining and NORA-CMOS
• TSPC logic

C2MOS Logic
• Goal: Make circuit operation independent of phase
overlap
• No need to worry about careful design of clock
phases, clock inversions, etc
• Really ingenious design!

1
Flip-flop insensitive to clock overlap
Modes of operation:
VDD VDD 1) Evaluate (Φ = 1)
Φ-section acts as inverter
M2 M6 Φ-section is in high-impedance
(hold) mode
M4 M8
2) Roles reversed for Φ = 0
Φ X Φ
Q
D CL1 CL2
Φ M3 Φ M7

M1 M5

Φ-section Φ-section
C2MOS master-slave negative edge-triggered D flip-flop
• Insensitive to clock overlap as long as clock rise and fall times are “small”

C2MOS avoids Race Conditions

Signal propagation requires pull-up followed by pull-down, or vice versa
VDD VDD VDD VDD

M2 M6 M2 M6

0 M4 0 M8
X X
D Q D Q
1 M3 1 M7

M1 M5 M1 M5

(1-1) overlap (0-0) overlap

Only pull-down networks are enabled Only pull-up networks are enabled

2
 C2MOS avoids Race Conditions

Caution: If clock has low rise/fall times, then both pMOS and
nMOS may conduct

Typically need rise/fall time at most five times clock

propagation delay

Pipelining
Register

Register

F G

Φ1 Φ2

• Common in high-speed designs

• Combinational logic (stages) separated by registers
• Alternating clock phases typically used
• Race may occur if clock phases overlap

3
 Pipelined Logic using C2MOS

VDD VDD VDD

In Φ Φ Φ
F G Out
Φ C1 Φ C2 Φ C3

NORA CMOS (NO RAce CMOS)

What are the cons traints on F and G?
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Example

VDD VDD VDD

Φ Φ
1
Φ Φ

Number o f s tatic invers io ns s ho uld be eve n

4
 NORA CMOS
• Targets implementation of fast, pipelined
datapaths using dynamic logic
• Combines C2MOS pipeline registers and np-
CMOS dynamic logic functional blocks
– Combinational logic can be a mixture of static and dynamic logic
– Latch and logic (feeding latch) are clocked in such a way that both
are simultaneously in either evaluation or hold (precharge)
– Block in evaluation during Φ=1 is a Φ-module, inverse is a Φ-
module
– Φ-modules and Φ-modules alternate

NORA CMOS Modules

VDD VDD VDD

Φ Φ
In1 PUN Φ Out
In2 PDN
In3
Φ
Φ-module
Φ Φ
Combinational logic Latch

VDD VDD VDD VDD

Φ In 4

In 1 Φ Out
In 2 PDN
In 3 Φ Φ-module
Φ In4

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5
 NORA Logic Modules
Operation Modes

Φ-block Φ-block
Logic Latch Logic Latch

Φ=0 Precharge Hold Evaluate Evaluate

Φ=1 Evaluate Evaluate Precharge Hold

11

Doubled C2MOS Latches

• Single clock (no inverse clock is needed)

• Requires redesign of C2MOS latch

12

6
 Doubled C2MOS Latches
VDD VDD VDD VDD

Q
D D
Φ Φ Φ Φ
Q

Doubled n-C2MOS latch Doubled p-C2 MOS latch

Φ = 1, latch in transparent, evaluate mode
Φ = 0, latch in hold mode, only pull-up
network active
Dual-stage approach: no races

13

Doubled C2MOS Latches:

Advantages
• No even-inversion constraints between two
latches, or between latch and a dynamic block
• Dynamic and static circuits can be mixed freely
• Logic functions can be included in the n-C2MOS
or p-C2MOS latches, or placed between them
• Disadvantage: More transistors per latch (six,
instead of four)

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7
 TSPC - True Single Phase Clock
Logic
VDD VDD VDD VDD

PUN

In
Static
Φ Φ Φ Φ
Logic Out

PDN

Including logic into Inserting logic between

the latch latches

15

Simplified TSPC Latch (Split-

Output)
VDD VDD VDD VDD

Q Q
D D
Φ Φ
A

Φ-latch Φ-latch
• Reduced area
• Voltage degradation at A
16

8
 Master-Slave Flip-flops
VDD VDD VDD VDD VDD VD D

φ φ
Y
D D
D X
φ φ φ φ
D
φ φ

(a) Positive edge-triggered D flip-flop (b) Negative edge-triggered D flip-flop

VDD VDD VDD

D D
φ φ

(c) Positive edge-triggered D flip-flop

using split-output latches

17

Two-Phase Clock Generator

Φin
Φ1

Φ2

• Considerations:
– Drive: added buffers
– Non-overlap: Two phases inverted with respect to each other
– Minimum skew
– Implement with NAND gates?

18

9
 Registers with Load/Enable
Inputs
Ld Φ1 Φ2

D C C C Q

Ld
C

Multiplexed
input

19

Registers with Load/Enable

Inputs
Φ 2

D Q
C C
C

Enable

Gated clock
Ld Φ1 C
Φ

Clock enable
Gnd
circuit

20

10
 Comments on Transmission
Gates
(Common Misconceptions)
Enable

Enabled
Φ Transmission gate used here as an AND gate
C
Φ

Clock enable
circuit Gnd

21

Comments on Transmission
Gates
(Common Misconceptions)
b
Transmission gate is not an AND gate
a C F = ab

b
Transmission gate network does not
a C serve as an OR gate
b F = a+b
a C

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