VLSI Signal Processing

Systems
Chih-Wei Liu
cwliu@twins.ee.nctu.edu.tw

VSP Lecture0 - Chih-Wei Liu 1

(cwliu@twins.ee.nctu.edu.tw)
 Course Information
• Lecture:
– Chih-Wei Liu 劉志尉 cwliu@twins.ee.nctu.edu.tw
–TEL: 5731685
–ED618
‧Teaching Assistants:
– 張仲華 chchang@twins.ee.nctu.edu.tw
– TEL: ext 54225
– ED412
‧Lecture notes: http://twins.ee.nctu.edu.tw

VSP Lecture0 - Chih-Wei Liu (cwliu@twins.ee.nctu.edu.tw) 2

 Course Information
• Reference
– Keshab K. Parhi, VLSI Digital Signal Processing
Systems – Design and Implementation, Wiely, 1999
• Project
– The project is an individual project
– Project type can be either theory/algorithm
development type or implementation type
– Project report is required to be submitted before the
end of this course
– At the last week of this course, project presentation
will take place in class
• Course Grade
– Home work and project report (50%)
– Midterm Exam. 25%
– Final Exam. 25%

VSP Lecture0 - Chih-Wei Liu (cwliu@twins.ee.nctu.edu.tw) 3

 What is VSP?
• This course will cover the most important methodologies for
designing custom or semi-custom VLSI systems for some
typical digital signal processing applications.
• In this course, you will learn how to map DSP algorithms into
VLSI efficiently. Several high-level algorithm and
architecture design techniques will be introduced that
enable joint optimization across the algorithmic,
architectural, and circuit domains
• Two examples…
– FIR filter
– Data format converter

VSP Lecture0 - Chih-Wei Liu (cwliu@twins.ee.nctu.edu.tw) 4

 4-Tap FIR Filter Example
• Mathematical description
y[n ]  h0 x[n ]  h1 x[n  1]  h2 x[n  2]  h3 x[n  3]
• How to realize a 4-tap FIR filter?
– Multiplier, adder, register, …
– Clock rate, chip area, power or energy?
• Block diagram representation

VSP Lecture0 - Chih-Wei Liu (cwliu@twins.ee.nctu.edu.tw) 5

 Remarks
Direct Form 4-tap FIR 10-bit Transposed Form
10-bit

20-bit 20-bit

1. TCritical=TM+TA
1. TCritical=TM+(N-1) TA, where N is the
2. High fan out causes high
number of taps
driving force and long word-
2. Short word-length delay elements
length delay elements
3. small silicon area and power
3. High speed but large silicon
consumption, but limited speed
area and power consumption
VSP Lecture0 - Chih-Wei Liu (cwliu@twins.ee.nctu.edu.tw) 6
 Data Format Converter
Example
• 3-by-3 Matrix transposition
input sequence: ABCDEFGHI
output sequence: ADGBEHCFI

Step 1: Lifetime analysis

Sample Tinput Tzlout Tdiff Toutput Life Period cycle
0 1 2 3 4 5 6 7 8 9 10 11 12
A 0 0 0 4 0 ~ 4 A
B 1 3 2 7 1 ~ 7 B
C 2 6 4 10 2 ~ 10 C
D 3 1 -2 5 3 ~ 5 D
E 4 4 0 8 4 ~ 8
E
F 5 7 2 11 5 ~ 11
F
G 6 2 -4 6 6 ~ 6
G
H 7 5 -2 9 7 ~ 9
8 8 0 12 8 H
I ~ 12
I
# live 1 2 3 4 4 4 4 4 4 3 2 1
1 2 3
VSP Lecture0 - Chih-Wei Liu (cwliu@twins.ee.nctu.edu.tw) 7
 cycle
0 1 2 3 4 5 6 7 8 9 10 11 12
A
B

Step 2: C
D

Forward-backward
E
F

register allocation
G
H
I
# live 1 2 3 4 4 4 4 4 4 3 2 1
1 2 3

cycle input R1 R2 R3 R4 output cycle input R1 R2 R3 R4 output

0 a 0 a
1 b a 1 b a
2 c b a 2 c b a
3 d c b a 3 d c b a
4 e d c b a a 4 e d c b a a
5 f e d c b d 5 f e d c b d
6 g f e c g 6 g f e b c g
7 h f e 7 h c f e b b
8 i h f e e 8 i h c f e e
9 i h f h 9 i h c f h
10 i 10 i f c c
11 i 11 i f f
12 i i 12 i i

VSP Lecture0 - Chih-Wei Liu (cwliu@twins.ee.nctu.edu.tw) 8

 Step 3: Hardware Architecture
output

input R1 R2 R3 R4

cycle input R1 R2 R3 R4 output

0 a
1 b a
2 c b a
3 d c b a
4 e d c b a a
5 f e d c b d
6 g f e b c g
7 h c f e b b
8 i h c f e e
9 i h c f h
10 i f c c
11 i f f
12 i i
VSP Lecture0 - Chih-Wei Liu (cwliu@twins.ee.nctu.edu.tw) 9
 Concluding Remarks
• The same mathematical derivation or
algorithm
• Different hardware architecture
– Area consideration
– Speed consideration
– Or, …
• We have to learn more about VLSI
signal processing techniques
VSP Lecture0 - Chih-Wei Liu (cwliu@twins.ee.nctu.edu.tw) 10
 Course Outline
• Overview
• Lec 01 : Pipelining & Retiming
– review of Pipelining & Retiming
• Lec 02: Unfolding Transformation
• Lec 03: Folding Transformation
– scheduling
• Case Study I : Programmable/Configurable DSP Architectures
• Lec 05: Systolic Arrays
• Lec 06: Algorithmic Strength Reduction
• Case Study II: FFT Processors
• Lec 08: Bit-Serial Architectures
• Lec 09: Redundant Arithmetic
• Lec 10: Numerical Strength Reduction
• Lec 11: Distributed Arithmetic

VSP Lecture0 - Chih-Wei Liu (cwliu@twins.ee.nctu.edu.tw) 11

 HW for Lec. 0
• 5-by-5 Matrix transposition

VSP Lecture0 - Chih-Wei Liu (cwliu@twins.ee.nctu.edu.tw) 12