EE529 EMBEDDED SYSTEMS

Assignment-9

Fast Fourier Transform (FFT) is an algorithm to compute the discrete Fourier transform (DFT) and it’s
inverse. Basically, the computational problem for the DFT is to compute the sequence {X(k)} {
of N complex-valued
valued numbers given another sequence of data {x(n)}
{ )} of length N, according to the
formula:

In general, the data sequence x(n plex valued. Similarly, The inverse discrete
n) is also assumed to be complex
Fourier Transform (IDFT) is given by:

Direct computation of the DFT is basically inefficient and happens in O(N2) primarily because it does not
exploit the symmetry and periodicity properties
prop of the phase factor (Twiddle factor) WN. In particular,
these two properties are:

Symmetry Property: WNk+N/2 = -WNk

Periodicity Property: WNk+N = WNk

Exploiting these, we get computationally efficient algorithms, known collectively as fast Fourier
Transform (FFT) working in computational complexity of O(N log N).

F by the divide and conquer approach

Consider the computation of the N = 8 point FFT approach. Divide the N-point
input sequence into two N/2-point
point data sequences f1(n) and f2(n), corresponding to the even-numbered
even and
odd-numbered samples of the input sequence x(n), respectively, that is,

f1(n) = x(2n)

f2(n) = x(2n +1)

Thus f1(n) and f2(n)) are obtained by decimating or dividing x(n)) by a factor of 2, and hence the resulting
FFT algorithm is called a decimation-in-time
decimation algorithm. Repeat the division recursively till you get
(x,N,s), where x is the input
sequences of 1 dimension. To do the recursion, define a function ditfft(x,N,s)
sequence, N is the number of samples and s is the step size. The equation of FFT can then be expressed
as:

X0, X1, X2………XN-1 <= ditfft(x,N,s)

(x,N,s) :where Xi is the FT of xi
Now, divide the sequence into two subsequences:

X0……N/2-1 <= ditfft(x,N/2,2s)

XN/2….N-1 <= ditfft(x,N/2,2s)

Now, loop K=0 to N/2-1

T = XK

XK = T + exp(-2jπK/N) * XK+N/2

XK+N/2 = T – exp(-2jπK/N) * XK+N/2

Compute the time complexity of FFT based on the above equation.

The FFT equation can be summarized

summari as:

Figure 1 explains this process in detail.

Fig 1: N=8 Point Decimation in Time FFT

For implementation on a reconfigurable

reconfig hardware like an FPGA, modular components are to be formed
which are to be mapped with the re required signals. The main unit is a component for doing the butterfly
formulations,
mulations, which essentially did the calculations depicted in Figure 2.
 Fig 2: Butterfly Component

It has been proven that FFT is a computationally intensive operation. To optimize its run time, we have to
systematically assess all the daughter processes that run underneath. Once their characteristics are
identified, we can divide the algorithm to run on an FPGA (hardware) and a processor (software)
simultaneously.. For an 8 point FFT
FFT,, it can be seen that the algorithm involves 3 stages (Figure 1). Stage 1
involves 4 complex multiplications (with WN0 = 1) and 8 complex summations (4 addition and 4
subtraction). The next stage too involves 4 complex multiplications, but this time the T Twiddle factor is
not of unit magnitude, and 8 summations. This is also true for stage 3. Hence we can conclude that the
major component of this implementation is the complex summation and multiplication.

The complex summation does not require a large execution time; it is the multiplication that forms the
bottleneck. Hence it is wise to shift multiplication from software and implement it on hardware. Also, it
has been found that if a task interacts with external signals or is a custom task, like multiplication with
Twiddle factors, it is suited for
or hardware implementation. Design the he complex multiplier using the
architecture shown in figure 3:

Fig 3: Schematic of complex multiplier

software co-design to implement FFT was as follows: the input sequence,

Implement the hardware-software
each number is 16 bits:: 8 bit real and 8 bit imaginary) will be stored on the
consisting 8 numbers, (each
processor (an Atmega16 microcontroller).
microcontroller) The addition and
nd subtraction for each stage will be done on the
ler. While the multiplication will be performed on the FPGA (a Nexys 2 Spartan 3E FPGA).
microcontroller.
The Twiddle factors will be pre-calculated
pre calculated and stored in the ROM of the FPGA. This forms one
multiplicand, the other is sent from the microcontroller to the FPGA. For this, this you may use the
ation protocol to enable the microcontroller and FPGA talk to each other
following communication other.
 microcontroller FPGA communication. The
Figure 4 shows the system architecture used to establish microcontroller-FPGA
communication protocol that you will employ will be a hybrid one, a mixture of a parallel and serial
(UART-Universal
Universal Asynchronous Receiver Transmitter) communication. The data from microcontroller
will be sent to the FPGA through the UART (serially). You may decide on tthe baud rate and fix
beforehand
and (since Atmega16 runs on 16 MHz while Spartan 3E on 50 MHz). z). Once data is received, it will
be multiplied with the pre-calculated
calculated twiddle factors and the product will be ready to be transmitted. This
value will be sent onn parallel transmission lines. An interrupt will also be generated. When this interrupt
is received on the microcontroller, the value on the microcontroller port, to which communication
commun lines
are connected, will be read and in turn stored in a variable.

Fig 4: System Architecture

Now perform the following experiments:

1. Compute the cycle count and time of computation of 8 point FFT.

2. co design of FFT.
Estimate the resources utilized on FPGA for the hardware software co-design
3. Estimate the power dissipation of the FFT system.
4. Repeat experiments 1,2 and 3 for complete hardware implementation of 8 point FFT.
5. ware implementation of 8 point FFT.
Repeat experiments 1,2 and 3 for complete software
6. Compare the results of complete hardware, complete software and hardware
hardware-software co-design
of FFT system.