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Important Concepts/Theory:-
A clock divider is usually a device takes an input clock that is used to produce an output
clock. The output clock frequency is function of the input clock frequency where the output
clock frequency is the result of the input frequency divided by an integer. It is an electronic
device that is capable of dividing the frequency of a given digital input pulse train by a fixed
integer value, n. It often consists of an n-stage counter, the output frequency at the nth stage
of counting being an nth submultiple of the input frequency.
Clock divider by 2
Design Analysis:-
Clock divider by 2
Codes:-
module clock_divider ( clk ,rst,out_clk );
output reg out_clk;
input clk ;
input rst;
always @(posedge clk)
begin
if (~rst)
out_clk <= 1'b0;
else
out_clk <= ~out_clk;
end
endmodule
Results/Discussion:-
1.Waveform:
2.Report Results
a.RTL Schematic:
b. Tech Schematic:
Clock divider by n
Codes:-
module clock_divider
#(
(clk,reset, clk_out);
input clk;
input reset;
output clk_out;
reg clk_track;
begin
if (reset)
begin
r_reg <= 0;
end
else if (r_nxt == N)
begin
r_reg <= 0;
end
else
end
endmodule
Results/Discussion:-
1.Waveform:
c. Area Report
Conclusion:
Verilog HDL code for Clock Divider has been implemented and their simulation with signals
has been tested.
Concept (A) 2
Implementation (B) 2
Performance (C) 2
Total 6