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VLSI Design
ECE 558/658 (Fall 2006):
Lecture #1
Wayne Burleson
UMASS Amherst - ECE Department
Email: burleson@ecs.umass.edu
Welcome
Who am I?
Who are you?
What's next?
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Copyright 2006 © Wayne Burleson
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Logistics
http://www.ecs.umass.edu/ece/vspgroup/burleson/co
urses/558/
Lecture
Outline
Refer to Lecture 1 notes.
http://www.ecs.umass.edu/ece/vspgroup/burleson/co
urses/558/lecture1.html
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Copyright 2006 © Wayne Burleson
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Questions?
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Copyright 2006 © Wayne Burleson
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MODULE
+
GATE
CIRCUIT
Vin Vout
DEVICE
G
SD
n+ n+
Adapted from Irwin & Nayaranan's Slides from PSU. Copyright 2002 J. Rabaey et al."
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Copyright 2006 © Wayne Burleson
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Copyright 2006 © Wayne Burleson
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Moore's
Law
By Gordon Moore, Intel's co-founder
# of transistors on a die
doubles every 1 to 2 years
From 1958 to 1994
? F (feature size) : 1/50
? D2 (die area): x170
? PE (packing efficiency - # of transistors per minimum feature area): x100
? N = D2xPE/F2 = 50E6!
No sign of slowing down!
? 2300 transistors, 1 MHz clock (Intel 4004) - 1971
? 16 Million transistors (Ultra Sparc III)
? 42 Million, 2 GHz clock (Intel P4) - 2001
? 140 Million transistor (HP PA-8500)
? "SoC" or System-on-chip
109
108
107 integrated
# transistors
106 circuit
invented
105 memory
104 CPU
103
102
101
100
1960 1970 1980 1990 2000 2010 year
Modern VLSI Design 3e: Chapter 1 Copyright ♥ 1998, 2002 Prentice Hall PTR
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Copyright 2006 © Wayne Burleson
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Recent
Chips
Intel Pentium 4 Sony Playstation II
? 42M transistors ? 128-bit CPU "Emotion Engine"
? 217 mm^2 die ? 0.18 micron process
? 0.18-micron process ? 300MHz, 6.2 GFLOPS, 3.2
2GHz clock Gbytes/second
?
• 10 floating point multiply-
Intel/HP Itanium 646 accumulators and 4 floating point
dividers
? 220M transistors
• 3x floating point performance of
? 465 mm^2 die 500 MHz PIII
? 0.18-micron process ? Graphic synthesizer cgip
? 1.2GHz clock ? 0.25 micron chip
Sparc III ? 42.7M transistors
? 90M transistors ? 16.8x16.8 mm^2 die
? 0.13-micron, 7-level metal copper ? 2560-bit datapath
process ? 48 Gbytes/sec memory bandwidth
? 64b, 1MB L2$ ? 75M polygons/sec, 2.4
Gpixels/sec
? 53W @ 1.3V, 1.1GHz
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Copyright 2006 © Wayne Burleson
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Adapted from Irwin & Nayaranan's Slides from PSU. Copyright 2002 J. Rabaey et al."
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Copyright 2006 © Wayne Burleson
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100
2X growth in 1.96 years!
Transistors (MT)
10
P6
Pentium® proc
1 486
386
0.1 286
8085 8086 Courtesy, Intel
0.01 8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year
Adapted from Irwin & Nayaranan's Slides from PSU. Copyright 2002 J. Rabaey et al."
100000
64,000
0.35-0.4 ∝m
16,000
10000 0.5-0.6 ∝m
4,000 encyclopedia
0.7-0.8 ∝m
1000 1,000
2 hrs CD audio
1.0-1.2 ∝m 30 sec HDTV
256
1.6-2.4 ∝m
100
64
page
10
1980 1983 1986 1989 1992 1995 1998 2001 2004 2007 2010
Year
Adapted from Irwin & Nayaranan's Slides from PSU. Copyright 2002 J. Rabaey et al."
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Copyright 2006 © Wayne Burleson
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100
Courtesy, Intel
Die size (mm)
P6
486 Pentium ® proc
10 386
286
8080 8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10 years
1
1970 1980 1990 2000 2010
Year
Adapted from Irwin & Nayaranan's Slides from PSU. Copyright 2002 J. Rabaey et al."
Clock Frequency
Lead
Lead microprocessors
microprocessors frequency
frequency doubles
doubles every
every 22 years
years
10000
P6
100
Pentium ® proc
486
10 8085 386
8086 286
1 8080
8008 Courtesy, Intel
4004
0.1
1970 1980 1990 2000 2010
Year
Adapted from Irwin & Nayaranan's Slides from PSU. Copyright 2002 J. Rabaey et al."
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Copyright 2006 © Wayne Burleson
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Power Dissipation
Lead
Lead Microprocessors
Microprocessors power
power continues
continues to
to increase
increase
100
P6
Pentium ® proc
Power (Watts)
10
486
8086 286
386
8085
1 8080
8008
4004
Courtesy, Intel
0.1
1971 1974 1978 1985 1992 2000
Year
Power
Power delivery
delivery and
and dissipation
dissipation will
will be
be prohibitive
prohibitive
Adapted from Irwin & Nayaranan's Slides from PSU. Copyright 2002 J. Rabaey et al."
1000 500W
Pentium® proc
100
286 486
10 8086 386
8085
8080
8008
1 4004
Power
Power delivery
delivery and
and dissipation
dissipation will
will be
be prohibitive
prohibitive
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
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Copyright 2006 © Wayne Burleson
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Power Density
10000
Rocket
Nozzle
Power Density (W/cm2)
1000
Nuclear
100 Reactor
8086
10 4004 Hot Plate P6
8008 8085 386 Pentium® proc
286 486
8080 Courtesy, Intel
1
1970 1980 1990 2000 2010
Year
Power
Power density
density too
too high
high to
to keep
keep junctions
junctions at
at low
low temp
temp
Adapted from Irwin & Nayaranan's Slides from PSU. Copyright 2002 J. Rabaey et al."
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Copyright 2006 © Wayne Burleson
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Why Scaling?
Technology shrinks by ~0.7 per generation
With every generation can integrate 2x more functions
on a chip; chip cost does not increase significantly
Cost of a function decreases by 2x
But ?
? How to design chips with more and more functions?
? Design engineering population does not double every two
years?
Hence, a need for more efficient design methods
? Exploit different levels of abstraction
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
10,000 100,000
Logic Transistor per Chip(M)
10,000,000 100,000,000
1,000 Logic Tr./Chip 10,000
1,000,000 10,000,000
Tr./Staff Month.
(K) Trans./Staff -Mo.
100
100,000 1,000
1,000,000
Complexity
Productivity
1,0001 10
10,000
x x
0.1
100 1
1,000
xx
x
21%/Yr. compound
xx Productivity growth rate
x
0.01
10 0.1
100
0.001
1 0.01
10
1989
1991
1993
1997
1999
2001
2003
2005
1981
1983
1985
1987
1995
2007
2009
Source: Sematech
Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."
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Copyright 2006 © Wayne Burleson
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1M transistors, 1
designer=5000 Team
60000 16 15 16
trans/month 18
50000 19
Each additional designer 40000 24 23
reduces for 100 30000
trans/month Months until completion
20000 43
So 2 designers produce 10000 Individual
4900 trans/month each
0 10 20 30 40
Number of designers
[Adapted from Embedded Systems Design: A Unified Hardware/Software Introduction. Copyright 2000 Vahid & Givargis]
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Copyright 2006 © Wayne Burleson
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