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fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2016.2531099, IEEE
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A 0.4 V, sub-nW, 8-bit 1 kS/s SAR ADC in 65 nm

CMOS for Wireless Sensor Applications
Prakash Harikumar, Student Member, IEEE, J Jacob Wikner, Member, IEEE,
and Atila Alvandpour, Senior Member, IEEE

Abstract—This paper presents an 8-bit, 1 kS/s successive

approximation register (SAR) analog-to-digital converter (ADC)
which is targeted at distributed wireless sensor networks powered
by energy harvesting. For such energy-constrained applications,
it is imperative that the ADC employs ultra-low supply voltages
and minimizes power consumption. The 8-bit, 1 kS/s ADC was
designed and fabricated in 65 nm CMOS and uses a supply
voltage of 0.4 V. In order to achieve sufficient linearity, a two-
stage charge-pump was implemented to boost the gate voltage of
the sampling switches. A custom-designed unit capacitor of 1.9 fF
was used to realize the capacitive DACs. The ADC achieves an
ENOB of 7.81 bits while consuming 717 pW and attains an FoM
of 3.19 fJ/conversion-step. The DNL and INL are 0.35 LSB and
0.36 LSB respectively. The core area occupied by the ADC is
only 0.0126 mm2 .
Index Terms—ADC, SAR, ultra-low-voltage.

Fig. 1. Block diagram of the proposed ADC.

I. I NTRODUCTION
IRELESS sensor networks (WSNs) are increasingly
W employed in a wide range of applications including
military surveillance and environmental monitoring. Soil mois-
ture measurement using WSNs is used for desertification stud-
ies, efficient management of water resources and to provide
adequate irrigation [1], [2]. To ensure long-term autonomous
operation, the WSN is powered by photovoltaic cells which
harvest ambient light energy. An energy storage element (e.g.
supercapacitor) acts as the reservoir for the harvested energy.
Small form-factors are required for the nodes to reduce cost
and simplify deployment. For mm-scale photovoltaic cells, the
output power can be as low as tens of nW [3]. Hence ultra-low
power consumption is paramount for the WSN electronics.
In this work, we present a 0.4 V, 8-bit, 1 kS/s SAR ADC
with sub-nW power consumption targeted at WSNs for soil-
moisture sensing. Under such ultra-low supply voltages and
low sampling rate, a formidable trade-off between the ON-
resistance and subthreshold leakage of the input sampling
switches occurs. Since traditional bootstrapping and charge-
pumps [4], [5] prove inadequate for the task, we have im-
plemented a two-stage charge-pump that generates > 2.5X
boosted gate control voltage for the input sampling switches
which have been designed to alleviate leakage. To minimize
the DAC power consumption and area without using additional
voltages and boosted switches, a binary-weighted capacitor
array with a low-value, custom-designed unit capacitor Cu is
The authors are with the Department of Electrical Engineering, Linköping
University, Linköping, Sweden e-mail: (prakash.harikumar@liu.se).
Copyright (c) 2015 IEEE. Personal use of this material is permitted.
However, permission to use this material for any other purposes must be
obtained from the IEEE by sending an email to pubs-permissions@ieee.org
used. This strategy allows Cu to be chosen in order to limit the
thermal noise and thus minimize SNR degradation. A dynamic
latch comparator which does not entail static power consump-
tion has been designed to achieve low input-referred noise.
To minimize leakage power, the SAR logic utilizes minimum-
sized high-VT H (HVT) devices. In measurement, the prototype
ADC achieves an ENOB of 7.81 bits at near-Nyquist input
while consuming 717 pW. The resulting FoM is 3.19 fJ/conv-
step and the core area occupied is only 0.0126 mm2 .
II. ADC A RCHITECTURE
The block diagram of the proposed ADC which utilizes
a supply voltage VDD = 0.4 V is shown in Fig. 1. The
ADC consists of differential binary-weighted capacitive DACs,
a dynamic latch comparator and synchronous SAR logic.
The differential inputs are sampled on the top-plate node
of the DAC capacitors using boosted sampling switches. For
such low supply voltages, top-plate sampling is advantageous
compared to bottom-plate sampling, since it helps to obviate
the increased number of boosted switches as well as the
associated power consumption. The DAC switches are simple
inverters which switch between the high and low reference
levels VREF = VDD and ground respectively. In order to
achieve full-range input sampling without the use of extra
voltages, top-plate sampling with MSB preset [6] has been
used.
III. C IRCUIT I MPLEMENTATION
The design details of the various circuit blocks in the ADC
are described in this section. All simulations in this work

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400
320
Voltage droop [µV]
240
160
80
0 −85
−80
0 5 10 15
PT corner number
Fig. 2. Voltage droop of S/H over process and temperature corners.
utilize process and temperature (PT) corners encompassing the
entire set of process-defined corners and a temperature range
[0◦ C +85◦ C].
A. Input Sampling Switch
When the sampling pulse is HIGH, the sampling switches
close and the inputs are sampled on the DAC capacitors. In
this work, the tracking phase of the sampling switch comprises
one clock cycle of a 10 kHz system clock. During the bit
cycling period, which comprises eight clock periods of the
system clock, the sampling switches are turned OFF (HOLD
phase) and will then suffer from significant leakage. The
leakage current causes a voltage droop in the held voltage
which eventually degrades the performance. In addition, the
subthreshold leakage current shows a nonlinear dependency
on the voltage VDS across the sampling switch which causes
harmonic distortion in the ADC [6].
In this work, transmission-gate (TG) switches utilizing HVT
devices and device stacking have been used for sampling the
inputs. Although this topology helps to mitigate leakage, it
entails an increase in the ON-resistance (RON ) of the MOS
switches. A conventional bootstrapped switch keeps VGS =
VDD providing low and almost-constant RON . However, this
method proves inadequate at VDD = 0.4 V necessitating the
use of on-chip charge pumps to generate a control voltage
higher than VDD . To achieve sufficiently low RON for the
TG switch, a two-stage charge pump was implemented to
generate the boosted control voltage for the TG switch. The
architectural details and functionality of the charge pump are
described in [7]. Figure 2 shows the voltage droop on the
sampled voltage at the end of the HOLD phase over the
entire set of PT corners. The maximum value of the voltage
droop is only 372 µV which corresponds to 0.12 LSB of
the ADC indicating that the effect of leakage is sufficiently
suppressed. It is worth mentioning that the plot in Fig. 2
includes the effect of charge injection. With a 6 dB margin,
a total harmonic distortion (THD) of −55.9 dB has been
targeted for the S/H circuit. The THD performance of the fully-
differential sampling switch was simulated using full-range
differential sinusoids at near-Nyquist frequency as inputs.
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−55
−60
−65
THD [dB]
−70
−75
−80
−90
20 0 5 10 15 20
PT corner number
Fig. 3. THD performance of input S/H over process and temperature corners.
Figure 3 plots the simulated, post-layout THD performance of
the switch over PT corners. To determine the impact of process
variations and device mismatch on the switch performance,
250 Monte Carlo (MC) simulations were performed on the
post-layout netlist of the sampling switch. From the Monte
Carlo simulation results, it is seen that µT HD =−73.8 dB and
σT HD = 3.75 dB.
B. Capacitive Array DAC
The capacitive array DAC plays a crucial role in deter-
mining the linearity, power consumption and area of the
SAR ADC. Although several energy-efficient DAC switching
schemes such as monotonic [8] and Vcm-based [9] have been
published, each has its disadvantages such as signal-dependent
comparator offset, and the need for an additional voltage and
switches respectively. Since the 8-bit ADC supply voltage
VDD = 0.4 V will eventually be generated by an energy
harvesting source, it is beneficial to avoid the generation of
a separate common-mode voltage and minimize the number
of boosted switches. In the 65 nm process design kit which
we have used, the minimum value of the capacitor is 10.5 fF.
Designing a capacitive DAC using these capacitors will be
wasteful in terms of area and power consumption as 10.5 fF
is much higher than the minimum value required to meet noise
and matching requirements of the 8-bit ADC. Hence custom-
designed capacitors with a much lower unit capacitor value Cu
are preferred. In order to limit the thermal noise power of the
sample-and-hold Pn,sample ≤ 0.03Pn,quant , where Pn,quant
is the quantization noise power of the ADC, the minimum
value of the unit capacitor required in a binary-weighted DAC
is 1.32 fF.
The structure of the custom-designed unit capacitor which
is modified from [10] is shown in Fig. 4. It uses metal layers
M2, M3, M4 and M5. The inner M4 plate as well as the three
inner M3 fingers constitute the top plate node. The outer M3
layer, the two M3 fingers connected to it as well as the M2
layer, outer M4 layer and the M5 layer form the bottom plate
node. The top plate is completely enclosed between the bottom
plates except for the routing paths. The custom-designed unit
capacitor combines the inter-layer capacitance and the lateral
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Fig. 4. Structure of the custom-designed unit capacitor. Fig. 5. Schematic of the dynamic latch comparator.

fringing capacitance. With Cu = 1.88 fF and an area of 4 µm2 ,

the unit capacitor has a capacitive density Kc = 0.47 fF/µm2 . A
partial common-centroid layout was adopted for the capacitive
array DAC and dummy unit capacitors were placed along the
periphery of the array. The total DAC capacitance (single side)
is Cdac ≈ 485 fF and the parasitic capacitance on the top-plate
node Ctop,p = 8.6 fF. Ctop,p attenuates the DAC output voltage
which reduces the swing available at the comparator input. In
this work, the attenuation factor Hdac,atten due to Ctop,p is
given by
Cdac
Hdac,atten = 1 − = 0.017, (1)
Cdac + Ctop,p Fig. 6. Schematic of the synchronous SAR logic.
which illustrates the diminished impact of Ctop,p on the
DAC output voltage. The area of each capacitive DAC is
44.5 µm × 44.5 µm. The DAC switches are simple inverters counter while those in the bottom row provide the control
that use HVT devices. signals for the DAC switches and store the comparison result
during successive clock cycles. The signal samp generated by
the leftmost DFF on the top row constitutes the sampling pulse
C. Dynamic Latch Comparator
for the ADC. It is provided as input to the charge pump to
The dynamic latch comparator [4] is shown in Fig. 5. The obtain the boosted gate control voltage. The signal setMSB
Reset node of the comparator is connected to the 10 kHz generated as (samp OR s2) is used to set the MSB to HIGH
system clock of the ADC. A succeeding SR latch consisting during the input sampling and MSB approximation clock
of cross-coupled NOR gates stores the output of the com- phases. Transmission-gate based DFFs with minimum-sized
parator for one full clock cycle. In order to ensure sufficient HVT devices have been implemented to achieve low power
comparison speed at VDD = 0.4 V, low-VT H (LVT) devices consumption and minimize leakage. The timing sequence for
have been used for the input differential pair and cross- the SAR logic is shown Fig. 7.
coupled inverters while HVT devices have been used for the Post-layout simulation of the ADC included transient noise
reset switches M5 and M6 . To mitigate comparator noise, and the entire set of I/O pad schematics. A source impedance
balanced capacitance has been added on the output nodes of of 50 Ω was included on the differential inputs VIP and
the comparator. In post-layout simulation over PT corners, VIN . Parasitic capacitance modeling the digital probes of the
the maximum value of comparator input-referred noise is oscilloscope were added to the output pins of the ADC. In
311.7 µV (RMS) corresponding to 0.1 LSB. Consequently the
comparator noise power Pn,comp = 0.12Pn,quant . Based on
MC simulations, the input-referred offset of the comparator
σof f set,comp = 9.8 mV.

D. SAR Logic
The ADC utilizes a synchronous SAR controller as shown
in Fig. 6. The D-FlipFlops (DFFs) in the top row act as a ring Fig. 7. Timing sequence for the synchronous SAR logic.

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0.5

µDNL [LSB]
0.25
0
−0.25
−0.5
0 50 100 150 200 250
code
0.5

µINL [LSB]
Fig. 8. Chip microphotograph and layout of the 8-bit SAR ADC. 0.25
0
−0.25
[+0.35, −0.35] −0.5
DNL [LSB]

0.5
0 50 100 150 200 250
0 code

−0.5 Fig. 10. Measured µDNL and µINL for seven ADC chips.

0 50 100 150 200 250

code
0.2
σDNL,max = 0.19 LSB
σDNL [LSB]
[+0.36, −0.36]
0.5
INL [LSB]

0 0.1

−0.5
0
0 50 100 150 200 250 0 50 100 150 200 250
code code
0.16
σINL,max = 0.13 LSB
σINL [LSB]

Fig. 9. Measured DNL and INL errors of the ADC.

0.08
post-layout simulation, the ADC achieved an ENOB of 7.92
bits at near-Nyquist input and VDD = 0.4 V while consuming 0
730 pW. The power breakdown of the ADC is 41.4% for the 0 50 100 150 200 250
digital logic, 27.9% for the comparator, 8.9% for the charge code
pump and input sampling switches, and 21.8% for the DAC.
Fig. 11. Measured σDNL and σINL for seven ADC chips.
IV. M EASUREMENT R ESULTS
The prototype SAR ADC with a core area of
105 µm × 112 µm was designed and fabricated in a 0
−20 SNDR = 48.81dB, ENOB = 7.82 bits
PSD [ dB ]

65 nm, 1-poly 7-metal (1P7M) CMOS process. The chip −40

THD = −60.4 dB, SFDR = 64.1 dB

microphotograph is shown in Fig. 8. Histogram test was −60

conducted to determine the static linearity performance of −80
the ADC. A full-scale differential sinusoid with near-DC −100
frequency and amplitude of 800 mVpp was applied to the −120
0 0.1 0.2 0.3 0.4 0.5
1 kS/s ADC. The plot of the DNL and INL error is shown Frequency [ f / fs ]
in Fig. 9. The peak DNL error is +0.35/−0.35 LSB and the 0
peak INL error is +0.36/−0.36 LSB. In order to ascertain −20
PSD [ dB ]

SNDR = 48.78 dB, ENOB = 7.81 bits

the statistical matching performance of the custom-capacitor −40 THD = −60.7 dB, SFDR = 64.5 dB

based DAC, the DNL and INL of seven prototype chips were −60
measured. The mean and standard deviation of the measured −80
−100
DNL and INL curves are shown in Fig. 10 and Fig. 11 −120
respectively. For the seven samples, the worst-case DNLmax 0 0.1 0.2 0.3 0.4 0.5
Frequency [ f / fs ]
and INLmax are both 0.4 LSB. The dynamic performance of
the ADC was measured using the tone test. Fig. 12 shows the
measured FFT spectrum of the 1 kS/s ADC for near-DC and Fig. 12. Measured FFT spectrum (2048-point) for the ADC at 1 kS/s with
near-DC and near-Nyquist inputs.
near-Nyquist input frequencies. The amplitude of the test tone

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2016.2531099, IEEE
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SNDR, SFDR [dB] has a current measurement resolution of 100 fA was utilized.
70 Multiple samples were measured and found to have almost the
65 same power consumption. The 1 kS/s ADC consumes 717 pW
60 SNDR at VDD = 0.4 V resulting in an FoM of 3.19 fJ/conversion-
55 SFDR step. Leakage power consumption of the ADC is 90 pW
50 which constitutes 12.6% of the total power consumption.
45 Table I summarizes the ADC performance and compares this
0 0.1 0.2 0.3 0.4 0.5
Normalized frequency fin/fs work with previously published SAR ADCs having similar
sampling rates. The FoM achieved by the proposed ADC is
50
very competitive and the power consumption is the lowest.
SNDR [dB]

49
V. C ONCLUSION
48
A sub-nW, 1 kS/s 8-bit SAR ADC has been presented. The
47 ultra-low power consumption of 717 pW and supply voltage of
1 2 3 4 5 6 7
Prototype number 0.4 V combined with a small area of 0.0126 mm2 make this
ADC an ideal choice for wireless sensor networks powered
by energy harvesting sources. The ADC achieves satisfactory
Fig. 13. Measured SNDR, SFDR vs. fin and SNDR for seven prototypes.
dynamic and static performance and maintains almost constant
SNDR over the entire signal bandwidth.
TABLE I
ADC P ERFORMANCE S UMMARY AND C OMPARISON .
ACKNOWLEDGMENT
Specification [11] [5] [4] [12] This work
Technology (nm) 350 65 65 65 65 The authors would like to thank Pavel Angelov and Dr. Dai
Supply voltage (V) 1 0.55 0.7 0.6 0.4 Zhang for useful technical discussions and Martin Nielsen-
Sample rate (kS/s) 1 20 1 1.1 1 Lönn for support during the measurements.
Resolution (bit) 12 10 10 10 8
DNL (LSB) 0.8 0.58 0.55 0.96 0.35
INL (LSB) 1.4 0.57 0.61 0.87 0.36 R EFERENCES
Power (nW) 230 206 3 1.1 0.717
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