An FPGA-Based Rapid Prototyping Platform For Variable-Speed Drives
Francesco Ricci Hoang Le-Huy
Dept. of Electrical and Computer Engineering
UniversitC Laval
Quebec, Canada
fricci@gel. ulaval.ca
Abstract - This paper presents a novel approach to the design and
implementation of controllers for variable-speed drives using
Simulink and FPGA software. A rapid prototyping ]platform
based on FPGA is proposed and described. The design procedure
using this platform is presented to illustrate the important steps.
An application example using a DTC induction motor drive is
presented and discussed.
1. INTRODUCTION
Variable-speed drives (VSD) are complex systems com-
posed of components of different nature: power converter,
electrical machine, and control system. Design and prototyping
of such systems require complex operations which are usually
time consuming. A common method to reduce the prolotyping
time for VSD is to use a rapid prototyping system baried on a
DSP board.
The conventional approach to design VSD controllers con-
sists in two main phases: simulation and implementation.
These two phases are usually carried out sequentially on two
different platforms. First, simulation is performed using a sys-
tem simulator (such as MATLABKimulink) to perfect the
design. The system can be then implemented on DSP tiy using
C code generated from the model.
If Field Programmable Gate Arrays (FPGA) are used instead
of DSP for controller implementation, it becomes possible to
shorten the design and prototyping time by using hardware
models in the simulation phase. Once debugged and optimized,
the simulated controller model can be converted directly into
implementable code for the FPGA. One debugging step can be
thus avoided.
Xilinx (an FPGA producer) designed a s o h a r e package
that enables the simulation of FPGA functions in Sirnulink
environment. The product is a Simulink Blockset, named Sys-
tem Generator, that can be used for both simulation and. imple-
mentation of FPGA. Therefore, the control algorithm needs to
be built only once. With this tool, the implemented algorithm
in the FPGA will act exactly like in the simulation without
compatibility problems.
Another important advantage of FPGAs is their capability of
parallel operation that can greatly increase the execution speed
of the control algorithm.
This paper presents a novel approach to the design and
implementation of controllers for variable-speed drives using
Simulink and FPGA soilware. A rapid prototyping platform
based on FPGA is proposed and described. The design proce-
dure using this platform is presented to illustrate the important
1 I56
Dept. of Electrical and Computer Engineering
Universitk Laval
Quebec, Canada
lehuy@gel. ulaval.ca
steps. An application example using a DTC induction motor
drive is presented and discussed.
11. APPROACHES FOR PROTOTYPING
VARIABLE-SPEED DRIVES
A prototyping system is required at every stage of the devel-
opment cycle for a VSD since it provides the designer an envi-
ronment and necessary tools to edit, compile, test, and debug
the control code under operating conditions similar to that of
the actual VSD. The complexity of a prototyping system
depends largely on that of the controller chip used.
Fig. 1 shows a general configuration of a typical VSD proto-
typing system which consists of two main sections: the power
system (power converter and motor) and the control system.
An interface, including acquisition system and power switch
drivers, is required to connect the control system to the power
system. A PC is usually used as development platform for sim-
ulation and code generation.
A typical design process of a VSD control system consists
of several steps as illustrated in the flow diagram shown in Fig.
2.
The design process can be divided into two successive
phases: simulation and implementation. During the simulation
phase, the VSD is modeled and simulated with the best accu-
racy possible to represent the operation of the drive under dif-
ferent operating conditions. The performance of the controller
is evaluated and some design iterations are required to opti-
Sensors
Power
Load
Converter Motor
Controller
--
PC
LE
I’
Fig. I Configuration of a typical VSD prololyping System

System requirements
SIMULATION Simulation
*
IMPLEMENTATION Performanceevaluation
Fig. 2 Typical design steps for a VSD control system.
mize its performance. The following phase is the implementa-
tion of the simulated controller on actual hardware to verify its
real-time performance.
In a conventional design approach, simulation and imple-
mentation phases are performed on two different platforms.
Simulation is usually done on workstation or PC using C pro-
grams or a system simulator (for example Simulink, Saber,
etc.). For the implementation phase, the controller C program
(which is directly written for the simulation and modified for
the implementation or automatically generated by a specialized
tool such as the Real-Time Workshop of Simulink) is modified
to suit the hardware. The compiled code is then downloaded to
the hardware (DSP or microcontroller board) for execution and
debugging. Some iterations between the simulation and imple-
mentation phases are required to fine tune the controller.
This approach tends to he somewhat lengthy due to the code
modification and adaptation required to move from the simula-
tion platform to the implementation platform.
It is possible to accelerate the design process by using a
unique platform for both simulation and implementation. This
paper proposes a novel approach to the design of controllers
for VSD in which both simulation and implementation are
based on Field-Programmable Gate Array (FPGA). In the sim-
ulation phase, the VSD controller is represented by hardware
models of the actual elements which will be implemented on
FPGA. In fact, the simulation model represents in every detail
the controller to he implemented in FPGA. When the debug-
ging has been completed, the simulated controller can be con-
verted directly into hardware without further debugging or
adaptation. This is the reason of the reduced design time that
this approach can provide as compared to conventional
approach where debugging is needed in both simulation and
implementation phases.
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Another advantage of the proposed approach concerns the
execution speed of the implemented controller. Since all opera-
tions in FPGAs are in parallel in hardware, the control algo-
rithm can be executed very fast and a high sampling rate can he
used for the controller. As a result, the complexity of the con-
trol algorithm is no longer a limiting factor for its implementa-
tion.
Ill. DESCRIPTION OF THE PROPOSED RAPID
PROTOTYPING PLATFORM
A block diagram of the proposed rapid prototyping platform
for VSD is shown in Fig. 3.
The power section consists of an induction motor driving a
DC motor which is used as mechanical load. The induction
motor is fed by a three-phase IGBT inverter.
The control system for the VSD is implemented in a FPGA
on the master hoard which is a XSV300 board (from XESS).
The communication between this board and the PC is achieved
by a standard parallel link.
A second FPGA board (XSV40 from XESS) is used as an
interface between the control section (Master board) and the
power section. The functions of this FPGA are to generate the
gate drive signals for the inverter IGBTs and to control the A-
to-D converter (THS1207 from Texas Instruments). The con-
figuration of this FPGA is programmed once and remains fixed
unless modifications of IiO signals are necessary.
The motor currents (I, and Ib) are detected by two Hall-
effect LEM current sensors. The motor voltages are reconsti-
tuted from the DC link voltage (measured by a Hall-effect
LEM voltage sensor) and the inverter switching signal.
The communication between the master and slave boards is
,
done through a high-speed bidirectional optical link (33 Mhitsi
s) that ensures the required galvanic isolation between the con-
trol system and the power converter. Two Agilent optical pro-
totyping kits (HFBR-0536) and 10 meters of plastic optic fiber
were used.
,
Load
sensor
Induction
DC link Three-phase DC Motor
Inverter
Motor
~ lGBT ~
Commands Measures
Bidirecfional
optical link
Parallel
Master
board (XV300)
Fig. 3 Proposed FPGA-based rapid prototyping platform far VSD,
 The software installed on the PC includes MATLPtBiSim-
ulink, Power System Blockset, Xilinx System Generat,Dr, Syn-
plicity, and Foundation. These programs are required though
the design process and briefly described below. Power circuit design
(Power System 81ockset)
* MATLAB/Simulink: Software tool for the modeling and
simulation of control algorithms
+
FPGA conlloller design
* Power System Blockset: Specialized Simulink blocks for (Xilinx System Generator)

-
the modeling and simulation of power systems
Xilinx System Generator: Library of Xilinx functional
blocks (in Sirnulink environment) representing various circuits
SIMULATION < t
Compiele VSD sirnulation
(Simulink)
in FPGAs. Xilinx SG is also an automatic VHDL code genera-
tor.
* Active-HDL: This software is required to connect the
developed algorithm to other parts of FPGA code (it is not , \

required if a standard interface is used) VHDL code lor

* Synplify: A VHDL synthesis software that converts cmmunicaVon Autmaticccde generatinn
(doneonce) (Xilinx Syslem Generator)
VHDL code into actual circuits. z I
P t i
* Foundation: A FPGA implementation software that gener-
ates the FPGA configuration file from the synthesized circuit. z Complete FPGA
Simulation (i needed)
Code fusion

* Visual C++: Programming software required for the devel-
opment of the communication program between the PC and the
FPGA hoard.
IV. VSD CONTROLLER DESIGN PROCEDURE USING
THE PROPOSED PROTOTYPING PLATFORhl
The steps in the design procedure for VSD controllers using
the proposed prototyping platform are illustrated in the flow
diagram in Fig. 4.
In the first step, the power system model (including the
power converter and electric motor) is built using the Power
System Blockset (PSB). The controller model is then built
(also in Simulink environment) using Xilinx System Generator
(SG)blocks that represent various functions implementable in
the FPGA. Some conventions must he used in the signals nam-
ing and dimensions so that the algorithm will fit with the
remainder of the FPGA code. SG blocks are like standard Sim-
d i n k blocks except that they can operate only in discrete-time
and fixed-point format. The user has a wide choice of standard
and pre-built functions and can also create herhis own func-
tions for particular applications.
Specials blocks that represent the A-to-D converters are
connected between the power circuit and the controller. In this
way; the controller is simulated in the exact conditions: of the
prototyping hoard.
The complete VSD model, including the power circuit and
the controller, can be then simulated in the same Simulink dia-
gram for debugging purpose.
When the controller performs as expected in simulation, a
VHDL representation of the controller can be generated using
a special block of the SG. Next, this VHDL representation has
to be connected to the remainder of the FPGA code like the
communication modules. With the use of a standard interface,
the designer can jump directly to the synthesis step. If more
flexibility is desired, a VHDL software (Active-HDL for
example) can be used to create external code needed by the
algorithm, or to modify the standard interface. A simula.tion of
+
z (Active-HDL)
W (
I
Y
a
Synlhesis and
implementation
3 (Xilinx tools)
I I
download in FPGA
Fig. 4 Design steps of a VSD controller using the proposed
rapid prololyping platform.
the complete FPGA code can be run so as to validate the modi-
fications.
Synthesis and implementation of the controller are the fol-
lowing steps. In the synthesis software (Synplify), the program
files to be compiled (the controller and the communications
code) and the FPGA used are specified. Then, the synthesis is
done with a single click. Implementation is then done using
Xilinx Foundation software that executes a script. These opera-
tions create a configuration file for the FPGA.
The last thing to do is write an interface between the user
and the FPGA in C language. A standard interface can be used
but a custom one can also be built. The FPGA uses registers to
store control algorithm’s measures, command and settings so
that only two simple communication functions (pre-built) are
needed.
In the case where control algorithm is to he modified, a new
iteration through these steps has to be done. Since many of the
previous steps have to be done only once, the new iteration will
take less time.
V. APPLICATION EXAMPLE - A DTC CONTROLLER
A DTC controller for an induction motor drive has been
designed using the proposed prototyping platform in order to
evaluate the performance of the approach. Fig. 5 shows a Sim-
ulink diagram that represents the drive system. The power sec-
tion on the top is built with PSB blocks. The controller is built

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 f
I I

Fig. 5 Simulink diagram representing the DTC induction motor drive

with Xilinx SG blocks. The four channels of the A-to-D con-
verter are represented by four special blocks on the right.
Fig. 6 shows the diagram of the DTC controller built
entirely with SG blocks. Each function on the original control
algorithm has been rewritten to he suited for FPGA. This pro-
cedure is usually straightforward because SG functions are rep-
licas of Simulink functions. However, in order to exploit the
full advantage of FPGAs, some functions in the control algo-
rithm have to be modified. For example, the operation arctan is
traditionally used in DSP implementation to determine the
rotor flux vector position. In an FPGA, this operation would
require a lot of silicon space so it was replaced by several com-
parisons which can he implemented using much less resources
on the FPGA. For sine or cosine functions, it is simpler to
implement using lookup tables in FPGAs.
Fig. 7 shows details of one of the controller sections, the
rotor flux estimator. It is composed of constant multipliers,
adders and integrators.
The DTC induction motor drive model (using PSB and SG
blocks) was first simulated. Fig. 8 shows the results (stator flux
and motor torque) obtained with Xilinx SG model compared to
that obtained with standard Simulink discrete-time model. A
slight difference was noted which is due to one time-step delay
in the ADC and also due to the fixed-point format (12 bits)
used in the FPGA. This difference is considered negligible and
does not affect the controller performance.

Fig. 6 Diagram ofthe DTCcontraller(built with Xilinx SG blocks)

1159
 Speed response
1150

- 1100

-p
E
P
1050
maL

1000

950
" ~ " , " , ' ~ " ~ R ~
O

0
o N I O "
- -
m ) V ) -

Time
C m

(6)

Fig. 7 Flux estimator Sirnulink diagram (using Xilinx blocks).

7 Torque r e s p o n s e 1
[: . .I
Flux:magnitude
. .............. . . . . . . . : I
~ :
................ . . . . .!... ........ ~ .7 9.00

,
............................. Simulinkkesult. .. i. .
J -
8.00

7 00
.... E
z
6.00
.l................ .............. 'I
+ 5.00
~ ,...... .............. .......

1
# J
.II ............................... .............. ............
4.00
,, . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- .-
!
~

. .
0- .e, 0-m 0-a ._.

3'00

Fig. 9 Experimental slep response of the DTC controller implementedan

the FPGA prototyping board.
and voltage measurements. Nevertheless, the system was able
to provide a speed static error of less than 1% for speeds from
400 rpm to 1800 rpm.
Fig. 9 shows the experimental DTC controller response to a
step change in speed reference (from 1000 rpm to 1100 rpm).
: PSB result. . . . . . Both speed and torque responses are smooth and do not present
...............
.- I-
i

.- ._
.......... :.
om,, ..m U_
large oscillations. The small ripple appearing on the speed sig-
nal is due to the noisy signal provided by the speed sensor. The
Fig. 8 Comparison between Xilinn SG and Sirnulink Simulation results controller dynamics agree well with theoretical predictions.
The obtained speed control accuracy (1%) is acceptable for
industrial applications.
The designed controller was implemented on the FPGA pro-
totyping board to control a 2-kW induction motor fed by an VI. CONCLUSION
IGBT PWM inverter.
The currents and voltage are sampled with a time period of 4 A novel approach to prototyping VSD has been proposed
ps. The FPGA was able to execute one cycle of calculations in and described. The obtained results have demonstrated that
0.2 ps but the controller operated with a sampling period of 48 FPGAs are well suited for implementation of complex motor
ps because the power converter can only switch at 20 kHz. control and estimation algorithms due to their very high execu-
tion speed which is made possible by the inherent parallel
Thus the command to the inverter was sent out at a rate of 48
operation in FPGAs.
PS. Since the FPGA's structure is completely configurable, the
The DTC controller was functional since the first time hut
the drive performance was not as good as in the simulations. prototyping platform can be readily modified to suit new
The actual motor torque was lower than the simulation value. requirements (addition of measured variables, modification of
After some investigation, it was found that this problem was communication system, modification of control configuration,
caused by a less accurate flux estimation due to noisy current

I I60
etc.). The modifications are done at high level (Xilinx SG
blocks and VHDL language).
In the proposed protolyping approach, the design time could
be reduced because of the accuracy of the simulation attainable
with Sirnulink and Xilinx System Generator at every operation
details of the FPGA. Most of the time, only one step of debug-
ging is required because the design in Sirnulink represents an
exact model of the actual device.
In the prototyping platform built in OUT laboratory, the mea-
surement section did not perform as well as expected. This is
due to the quality of the analog circuits forming the front end.
With the current advances in microelectronics, the capacity
of FPGAs is continually increased permitting VSD designers
to fully exploit their possibilities in the implementation of
complex advanced control algorithms.

REFERENCES
[l] Power Electronics and Variable Frequency Drives, edited
by Bimal K. Bose, IEEE Press, New York, 1997.
[2] Power System Blocbet For Use with Sirnulink, User’s
Guide, The Mathworks Inc., 2000.
[3] Xilinx Blockset Reference Guide, Xilinx Inc., 2001
[4] Virtex Platform FPGA Handbook, Xilinx Inc., 2000.
[5] R. D. Turney, C. Dick, D. B. Parlour, and J. Hwang, Mod-
eling and Implemenfution of DSE FPGA Solutions, Xilinx
Inc., 2000.
[6] G. Buja, D. Casadei, G. Serra, “Direct stator flux and
torque control of an induction motor: theoretical analysis
and experimental results,” IEEE IECON’98.

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