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Q. No. 1: Consider an inverter circuit that has FET Aspect Ratios of (𝑊𝐿)=6 and (𝑊𝐿)𝑝=8 in a process
where 𝑘𝑛′=150 𝜇𝐴/𝑉2, 𝑘𝑝′=62 𝜇𝐴/𝑉2, 𝑉𝑇𝑛=0.7𝑉 and 𝑉𝑇𝑛=−0.85𝑉, 𝑉𝐷𝐷=3.3𝑉 and total output
capacitance to be 𝐶𝑜𝑢𝑡=150𝑓𝐹.
b. What happens to maximum frequency when the aspect ratios are reduced to half i.e. 𝑊2 and 𝐿2
SOLUTION:
GIVEN:
𝑘𝑛*=150 𝜇𝐴/𝑉2
𝑘𝑝*=62 𝜇𝐴/𝑉2
𝑉𝑇𝑛=0.7𝑉
𝑉𝑇𝑛=−0.85𝑉
𝑉𝐷𝐷=3.3𝑉
𝐶𝑜𝑢𝑡=150𝑓𝐹.
Part a:
Rp=1/[Bn*(VDD – |VTp|)]
Rp=1/[(62*10-6)*(8)*(3.3-0.85)]
So,
Tp = Rp * Cout
Tp = 123.43 ps
tr = 2.2 Tp
tr = 2.2 * 123.43
tr = 271.55 ps
For the Fall Time,
Rn=1/[Bn*(VDD – VTn )]
Rn=1/[(150*10-6)*(6)*(3.3-0.70)]
Rn=427.35 ohms
Tn = Rn * Cout
Tn = 64.1 ps
tf = 2.2 Tn
tf = 2.2 * 64.1 ps
tf = 141 ps
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Q. No. 2: In our CMOS Circuits, at no load capacitance, prove why we have 𝑡𝑟0> 𝑡𝑓0. Support
your answer with proper derivations.
SOLUTION:
Cout = CFET + CL
We know that “CFET” represents the parasitic capacitances of the transistors while C L is the capacitance
with external load.
So,
tr = 2.2 * Rp * Cout
tf = 2.2 * Rn * Cout
Hence under no load condition i.e. CL is equal to zero the inverter drives its capacitances such that
Cout = CFET
So,
As we know that
*
Kn = un (eox/tox)
Kp*= up (eox/tox)
un > u p
So,
*
Kn > Kp*
Hence,
Bn > B p
* *
Because Bn = Kn *(W/L) while Bp = Kp *(W/L)
So,
Rn=1/[Bn*(VDD – VTn )]and Rp=1/[Bn*(VDD – |VTp|)] hence by the above conditions Bn > Bp so we can say that
Rp > R n .
Recalling the rise and fall time equations, which are as follows:
We can say that by above conditions seen through derivations that is Rp > Rn , hence tr0 > tf0 .
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𝑓= 𝑥∙(𝑦+𝑧)
Design its CMOS circuit highlighting all capacitances. Find “Worst Case” rise and fall times of the
function.
Solution:
_____
f = x+(y.z)
Tn = Rn * Cn + 2 Rn * Cout
tr = tro + αo CL
Tp = Rp*Cp +2RpCout
tr = to + ao * CL
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Q. No. 4: Design clocked CMOS logic for NAND and NOR gates. Also design layout of the C2MOS
designs.
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Q. No. 5:Revise lecture of inverter switching characteristic, and find the output capacitance (𝐶𝑜𝑢𝑡) of
first inverter, which is driving an inverter with 𝐶𝑖𝑛=32.4 𝑓𝐹, with 𝐶𝑀𝑂𝑆=52.34 𝑓𝐹.
Given:
𝐶𝑖𝑛=32.4 𝑓𝐹
𝐶𝑀𝑂𝑆=52.34 𝑓𝐹.
To Find:
Cout
Solution: