VLSI Design Verification and Testing Course Outline

Introduction
Course outline

 Part I: Introduction to VLSI testing

Mohammad Tehranipoor  Part II: Test methods

 Part III: Design for testability

Electrical and Computer Engineering
University of Connecticut

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VLSI Realization Process Present and Future*

Customer’s need 1997-2001 2003-2006 2009-2012

Determine requirements Feature size (micron) 0.25 - 0.15 0.13 - 0.10 0.07-0.05
Transistors/cm2 4 - 10M 18 - 39M 84-180
Write specifications Pin count 100 - 900 160 - 1475 260-2690
Clock rate (MHz) 200 - 730 530 - 1100 840-1830
Design synthesis and Verification
Power (Watts) 1.2 - 61 2 - 96 2.8-109
Test development
Fabrication
* SIA Roadmap, IEEE Spectrum, July 1999
Manufacturing test
ITRS
Chips to customer
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Present and Future Contract between design house and fab

vendor

What is happening to the test cost
 Automatic Test Equipment (ATE) cost
Design is complete and checked (verified)
 Test time
Fab vendor: How will you test it?
 Escape
Design house: I have checked it and …
 Yield loss
Fab vendor: But, how would you test it?

Compression
Design house: Why is that important?

At-speed testing
complete the story

New subtle defects

Power delivery issue
That is one reason for design-for-
 Source: IEEE D&T, Jan 2000 testability, test generation etc.

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1
 Contract between design … Verification v/s Testing
Hence: Definitions

“Test” must be comprehensive
Design synthesis:

It must not be “too long”
 Given an I/O function, develop a procedure to manufacture a
device using known materials and processes.
Issues:

Verification:

Model possible defects in the process
 Understand the process  Predictive analysis to ensure that the synthesized design,

Develop simulator and fault simulator when manufactured, will perform the given I/O function.

Develop test generator
Test:

Methods to quantify the test efficiency  A manufacturing step that ensures that the physical device,
 Fault coverage manufactured from the synthesized design, has no
manufacturing defect.

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Verification v/s Testing Need for testing

Verification
Verifies correctness of design.
Performed by simulation, hardware Two-part process:
emulation, or formal methods.
Performed once prior to
manufacturing.
Responsible for quality of design.
Testing
Verifies correctness of
manufactured hardware.
1. Test generation: software
process executed once during
design
2. Test application: electrical tests
applied to hardware
Test application performed on
“every” manufactured device.
Responsible for quality of devices.

Functionality issue
 Does the circuit (large or small) work?

Density issue
 Higher density ⇒ higher failure prob

Application issue
 Life critical applications

Maintenance issue
 Need to identify failed components

Cost of doing business

What does testing achieve?
 Discard only the “bad product”?

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Ideal Tests Real Tests

Based on analyzable fault models, which may not

Ideal tests detect all defects produced in the
manufacturing process.

Ideal tests pass all functionally good devices.

Very large numbers and varieties of possible
defects need to be tested.

Difficult to generate tests for some real defects.
Defect-oriented testing is an open problem.
map on real defects.

Incomplete coverage of modeled faults due to high
complexity.

Some good chips are rejected. The fraction (or
percentage) of such chips is called the yield loss.

Some bad chips pass tests. The fraction (or
percentage) of bad chips among all passing chips is
called the defect level.

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 Testing as Filter Process Level of testing (1)

Levels
Good chips Prob(pass test) = high Mostly  Chip
good Board
Prob(good) = y Pr 
o b
(fa ) chips System
pe 
il ca
t es Es
Boards put together
) =w (t
Fabricated lo lo
System-on-Chip (SoC)
)= w
chips st (Y
ie  System in field
te ld
ss Lo
( pa ss
Cost – Rule of 10
b )
ro It costs 10 times more to
Defective chips
P Mostly 
test a device as we move to
bad
Prob(bad) = 1- y Prob(fail test) = high higher level in the product
chips manufacturing process

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Level of testing (2) Costs of Testing

Other ways to define levels – these
Design for testability (DFT)
are important to develop correct  Chip area overhead and yield reduction
“fault models” and “simulation  Performance overhead
models”
 Transistor
Software processes of test
 Gate  Test generation and fault simulation
 RTL  Test programming and debugging
 Functional
Manufacturing test
 Behavioral  Automatic test equipment (ATE) capital cost
 Architecture  Test center operational cost

Focus: Chip level testing – gate
level design

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Cost of Manufacturing Test Roles of Testing

0.5-1.0GHz, analog instruments,1024 digital pins:
Detection: Determination of whether or not the
ATE purchase price device under test (DUT) has some fault.
 = $1.2M + 1,024 x $3,000 = $4.272M
Diagnosis: Identification of a specific fault that is

Running cost (five-year linear depreciation) present on DUT.
 = Depreciation + Maintenance + Operation
Device characterization: Determination and
 = $0.854M + $0.085M + $0.5M
correction of errors in design and/or test
 = $1.439M/year
procedure.

Test cost (24 hour ATE operation)
 = $1.439M/(365 x 24 x 3,600)

Failure mode analysis (FMA): Determination of
 = 4.5 cents/second manufacturing process errors that may have
caused defects on the DUT.

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3
 A Modern VLSI Device Course Outline
System-on-a-chip (SOC) Part I: Introduction

Basic concepts and definitions (Chapter 1)

DSP RAM
core ROM

Test process and ATE (Chapter 2)
Transmission
Data
Test economics and product quality
terminal medium
Inter- Mixed- (Chapter 3)
face signal
logic Codec
Fault modeling (Chapter 4)

Emergence of SoC has made test event more challenging and expensive

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Course Outline (Cont.) Course Outline (Cont.)

Part II: Test Methods Part III: DFT

Logic and fault simulation (Chapter 5)

Testability measures (Chapter 6)
Scan design (Chapter 14)

Combinational circuit ATPG (Chapter 7)
BIST (Chapter 15)

Sequential circuit ATPG (Chapter 8)
Boundary scan (Chapters 16)

Memory test (Chapter 9)

Delay test and IDDQ test (Chapters 12 and
13)

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