Design and Simulation Equivalent Model

of Floating Gate Transistor

Birinderjit Singh Kalyan*, Balwinder Singh**

*SVIET, Banur, **CDAC, Mohali
SVIET, Banur , CDAC, Mohali

Abstract: The [rrst Floating Gate Transistor (metal­ the control gate voltage, but also the source, drain and
insulator-metal-insulator structure) was proposed by Kahng bulk potentials.
and Sze in 1967 [I]. Using the floating gate voltage value,
capacitive coupling coefficients can be found out at different VFG= ac;V os+ aoVDS+ UsVs+ <laVs
bias conditions as required. Once these have been found out III. MODELING APPROACHES
for a particular technology, the values of the capacitances
The most common approach for modeling of floating
can be found out and implemented in the given model. The
charge present on the gate has to be calculated using the
gate memory cell is the capacitive coupling
transient models of hot electron programming and Fowler method[7].
nordheim tunneling. These can be incorporated and thus the
model can be extended to the transient conditions as weU. CONTROL GATE

The SPICE equivalent model is designed and Current

Voltage characteristics and Transfer characteristics are
comparatively analyzed.
Keywords: FGMOS: Floating Gate Metal Oxide
Semiconductor, FAMOS: Floating Gate Avalanche
Injection Metal Oxide Semiconductor, FLOTOX: Floating
Gate Thin Oxide.
I. INTRODUCTION
Electron tunneling mechanism was proposed to be
Figure.1 Schematic cross section of a Floating Gate Transistor
used for programming and erasing the proposed cell
using a thin insulator layer (having thickness less than The Floating gate potential is given by the equation(l)
5 nm). But fabrication of thin oxides was not possible Different methods have been devised in literature for
then. The first floating gate device with a thick gate
determination of coupling coefficients [30-38, 40].
oxide was introduced by Frohman Bentchowsky [2]. These methods can be classified into three categories:
It was called FAMOS (Floating Gate Avalanche
Injection Metal Oxide Semiconductor). Then i) Dummy cell approach [30-33]
FLOTOX (Floating Gate Thin Oxide) Memory cell ii) The Floating gate cell approach [34-38]
[3] and ETOX[4] structures were proposed. FLOTOX iii) A new method without using coupling
cell contained a thin oxide layer so that the coefficient approach [12]
programming and erasing was done by Fowler
Nordheim tunneling. i) Dummy cell approach: Dummy cell is
The combination of Hot Electron progr amming and nothing but a memory cell with its control gate and
floating gate 'shorted' to each other. The dummy or
Fowler Nordheim tunneling was used in ETOX
reference cell is used for comparison with the actual
(EPROM Tunnel Oxide) cell. It had a thin oxide
layer. cell. Since perfect matching cannot occur between the
two cells due to process variations, these methods are
II. MODELING OF FLOATING not very accurate. But they are relatively simple than
GATE methods using only the actual floating gate cell. The
methods using the dummy cell include:
The most common approach for modeling a floating (a) Linear Threshold Voltage Method
gate transistor is the capacitive coupling approach. (b) The Transconductance Technique
Using the capacitive coupling approach, the Floating (c) Subthreshold Slope Method
Gate potential comes out to be a fimction of not only

978-1-4673-6540-6/15/$3\.00 ({:)2015 IEEE

(a) Linear Threshold Voltage Method
In this technique, gate coupling coefficient is
calculated by taking the ratio of threshold voltages of
the dummy cell and the actual cell, respectively. The
equations used as given below:
VFG = aaVCO+UDVD+USVs+Q/CT (2)
Putting Vs and Q=O,unprogrammed threshold voltage
of the floating gate cell can be found out.
We have
VFG=aaVCO+UDVD (3)
The subthreshold conduction curves are obtained for
both the cells. The threshold voltage for the devices is
obtained at subthreshold at a current level of 100 nA
to prevent errors due to drain coupling effect in the
linear region. In the Figureure(2) Vta and Vtc
correspond to threshold voltages of the dwnmy cell
and the actual cell,respectively at 0.1 V drain bias.
aa=VJVtc (4)
Here Vta is the measured from the dummy cell and Vtc
from the actual cell.
Figure. 2 Subthreshold conduction curves for drain
biases of O.lV and 2V for a dummy cell (polyl)
and the actual cell (EPROM) with coupling
measurement points labeled.
The limitations of this method are:
(a) The charge in the floating gate is required to
be absent,which is not always the case.
(b) The flat band voltage terms have been
neglected that lead to errors in the floating gate
voltage estimation
(c) The devices are measured in subthreshold,
the coupling coefficient changes in the linear region.
(b) The Transconductance Technique
This technique uses the ratio of linear
transconductances of the actual and the reference
device, respectively, to estimate the control gate
coupling coefficient. Using this technique, ao has
been estimated using the expression:
In a MOSFET,the surface potential becomes constant
after the onset of inversion. Hence, the drain coupling
coefficient can be found out by taking ratio of the
transconductances. But when Cox is comparable to
inversion layer capacitance (for gate oxides less than
15nm), CAjJ/oV FG can no longer be neglected. This
method overestimates the value of ao
(c) Subthreshold Method
In this method, the ratios of subthreshold slopes
measured from the dummy cell and the actual cell is
used for estimating aa.
VFG= aa(V co-<Po)+ UD(VD-<j)D)+ us(Vs-<Ps)+ as(1jI-
<PB) + Q/CT (6)
Here <p's are flat band voltages. IJ' is the surface
potential. Under DC conditions, Q is constant.
Differentiating with respect to 1jI, we get
(iN Fd8ljl) YD.VS = aa(oVCd8ljl) VD.VS+ as (7)
The neglecting as Us UD come closer to each other.
Thus, the error in the control gate coupling coefficient
obtained with the expression used can be easily
measured.
ii) The Floating gate cell approach
There are a couple of methods using only the floating
gate cell [34-38] for measurement of coupling
coefficients out of which only two have been
discussed in detail.
(a) Method using shift in threshold voltage
during programming [8]
In this method,the control gate coupling coefficient is
found while programming the device at any bias
voltages. It uses shift in threshold voltage during
programming to measure aa. The Floating gate
voltage,VF is given by:
VF(t)=acV c + aoVD + usVs + UB VB + QF(t)/CT (8)
Vc, VD, VS, VB are voltages at control gate, drain,
source and substrate; t is the programming time; QF(t)
is the charge in the floating gate at t; CT is the total
capacitance.
Now,V-rn(t) = -QF(t) /CCF' then, VF(t)=acIVc- VTH(t)1 +
UDVD (9)
It is clear from equation (2.34) that if both VTH(t) and
VF(t) can be measured simultaneously at a fixed VD,
ac can be directly investigated.
(b) Method using a linear system of two
equations [35]
The two equations are obtained from the drain turn on
measurement and progr amming characteristics of the
cell in terms of UD and aa.
The drain current depends negligibly on drain voltage
in the subthreshold region. A constant drain current is
forced through the cell in weak inversion.
The slope of the curve comes out to be:
D= ac/UD (10)
For the second equation, the threshold voltage shift
L'lV T as a function of programming time (t) is
obtained. Then, the time derivative of L'lVT (t) with
respect to L'lVT itself is obtained.
Ia= CFdd L'lVT/dt) (11)
and
VFG=aaVca + UDVD - aaL'lV T (12)
(c) Method based on FN erase measurements
and Source/drain junction leakage measurements [36]
(d) Method based on dependence of high
threshold voltage on the hold time of the write pulse
[37]
(e) Bias and W/L dependence of coupling
coefficients [38,39]
All the methods discussed previously assume the
coupling coefficients to be constants at all bias
conditions. Those using dummy or reference cell use
various approximations and those using only the
measurements made on the actual cell also neglect the
dependence of the coupling coefficients on bias
conditions. The latter are complex, time consuming
and involve a lot of measurements.
iii) A new method without using coupling
coiffident approach
A new mathematical model has been proposed in [12]
that is able to reproduce the behavior of the floating
gate memory cell in every bias condition. It describes
an algorithm that is based on finding the zero of the
charge balance equation at the Floating Gate node.
This model incorporates a Voltage controlled voltage
source at the Floating gate node to initialize it to the
correct value of potential. A c code is implemented in
the Voltage controlled voltage source that is based on
finding the zero of the charge balance equation.
Figure. 3 Equivalent Model of the Floating Gate
memory cell, constituted by the CCG capacitor, the
MOS transistor equivalent to the dummy
EEPROM cell, and the voltage controlled voltage
source, VFG, connected between the source and the
floating gate [12].
The charge balance equation is described as:
Qa (VfG,Vs,VD,VB) = Cca (Vca-VFa) + QFG (13)
Qa is the charge on the Floating gate
Cca (Vca- VFa) denotes charge on the inter poly
capacitor.
Oro is the charge inflow/outflow during transient
conditions (program/erase) which is a constant during
dc conditions
F (VFG) = Qa (VFa) + Cca (Vca-V FG) - QFG (14)
Charge on the MOS gate Q a (VFG, V S, VD, VB) is
calculated using Phillips MMP compact model of
MOS transistor. F (V Fa) is found out to be monotonic
versus V Fa for all Vco,Vs,VD,VB combinations.
The flow diagram for the c code implemented in the
voltage controlled voltage source is shown in the
Figureure.
Figure. 4 Flow diagram illustrating the algorithm
adopted to find the zero of F, which has been
implemented in the C code to calculate VFG [12].
This model features many advantages compared to
previous ones:
(i) It is simple and easy to implement since it
uses SPICE circuit elements,is scalable
(ii) Its computational time is not excessive.
(iii) It is based on a new procedure that calculates
the floating gate voltage without using fixed
capacitive coupling coefficients, thus improving the
floating gate voltage estimate that is fundamental for
the correct modeling of cell operations.
(iv) Moreover,this model requires only the usual
parameters adopted for SPICE-like models of MOS
transistors plus the floating gate--control gate
capacitance, making it very attractive to industry as
the same parameter extraction procedure used for
MOS transistors can be directly applied.
IV. IMPLEMENTATION OF SPICE
EQUIVALENT MODEL
Implementation of the SPICE equivalent model was
done using Tanner tools. The SPICE equivalent
model proposed here is a hybrid of the two schemes:
The capacitive coupling approach and the method
proposed in [12] using the charge balance equation.
The capacitive coupling approach uses the following
model.
Figure. 5 Capacitive coupling approach
It uses a capacitive circuit to represent the equivalent
circuit for an FGMOS. an equation for finding the
Floating gate potential is obtained in equation(l).
Another method based on finding the zero of charge
balance equation at the Floating Gate node in [12],
Figure. 6 Compact model for an FGT proposed
A MOSFET is present and a capacitor is also present.
Since the floating gate node has been initialized to a
potential value explicitly, there is no problem of
solving the capacitive net, which SPICE like
simulators are unable to do.
The problem with this model is that in many
simulators, such provisions as embedding the code in
a voltage source do not exist. This model is slow
because the algorithm is repeated for all combinations
of bias conditions. Moreover, the charge on the
floating gate has to be calculated using the base
MOSFET model used. So, a thorough knowledge of
all the parameters of the model is required. The charge
calculation procedure cannot be implemented in a
simulator. For modeling of floating gate devices, the
accurate knowledge of floating gate voltage is
necessary which can be efficiently calculated by this
method for required bias conditions. Having
determined the floating gate voltage, the coupling
coefficients can be calculated using the equation (2)
Calculating the coupling coefficients since floating
gate potential value can be found for a particular
technology at the bias conditions during read,
program and erase. By using those values, the values
of the capacitors can be found out (the value of
interpoly capacitor is known). To handle the problem
of capacitive net, resistances have been incorporated
in parallel. The proposed model is as shown.
Figure. 7 SPICE equivalent model
The resistances do not affect the dc value at the
floating gate provided their values are such that the
product of resistances and capacitances (time
constant) is same for all the branches. This can be
directly verified as shown below;
Resistor_I, Resistor_2, Resistor_3 will be referred as
RCG,RS,and RD
Capacitor_1, Capacitor_2, Capacitor_3 will be
referred as CCG, CS,and CD
VoltageSource_l is VCG, VoltageSource_2 is VDS
The Floating gate potential is referred as VFG in
equation(I). This model also contains an input node
that can be defined as a dc voltage source in T-SPICE. states with W/L=O.25/lmlO.375/lm, inter poly
In case any charge is present on the Floating gate,it is capacitance ofO.8fF'.
modeled using this dc voltage source. This model can (i) Programmed State
be used for analog and digital circuits. The threshold voltage increases when programming is
done. Being in programmed state, this FGMOS
V. RESULTS transfer curve shows a high threshold voltage value as
The dc current voltage characteristics as well as dc compared to the one with erased state.
transfer characteristics have been plotted for an
FGMOS with W/L=O.25,.unlO.375/lm, inter poly
capacitance ofO.8fF' for both progr ammed and erased
states. The results obtained are accurate as compared
to the capacitive coefficient coupling methods
described earlier.
a) Current Voltage characteristics

(i) Programmed State

Figure. 10 Transfer characteristics for FGMOS in the

programmed state

(ii) Erase State

The transfer curve for the erased state shows a drop in

threshold voltage as compared to ones with
programmed state. When no charge is present on the
Figure. 8 I-V characteristics for FGMOS in the
floating gate,the threshold voltage is lower.
programmed state

(ii) Erased State

Figure. 11 Transfer characteristics for FGMOS in the

erased state
Figure. 9 I-V characteristics for FGMOS in the erased
state These curves can be compared to those obtained in
MATLAB using the I-V equations for FGMOS.
In this particular state, it has been assumed that the
These curves obtained using interconnection of
charge stored in the floating gate is zero. However,
components match reasonably accurately with those
this is not the case. A small amount of residual charge
obtained using mathematical model.
is always present on the floating gate that needs to be
modeled. The magnitude of current with same applied (iii) Programmed State
bias is more for the erased state as can be interpreted
from the graphs.

b) Transfer characteristics
The transfer characteristics also have been obtained
for an FGMOS for both programmed and erased
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application to memory devices," Bell System
Technical Journal,p. 1288,1967.
[2] Frohman Bentchkowsky D., "A fully decoded
2048-bit electrically programmable MOS-ROM,"