MT7623N Public Datasheet For Development Board v1.1 PDF

MT7623N
Datasheet for Development Board
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MT7623N Datasheetf o r
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Development Board
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Version: 1.1
Release date: 2019-9-18
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© 2019 MediaTek Inc.
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This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Specifications are subject to change without notice.
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Document Revision History
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Revision Date
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P Description
0.1
1.0
2017-03-27
2017-04-07
a n aJia Chen
Leon Chung
First released
Update ETHSYS, HIFSYS
1.1 2019-09-18
Ba n Steven Liu Update ETHSYS
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Table of Contents
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Contents
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Document Revision History .................................................................................................................. 2
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Table of Contents ................................................................................................................................... 3
List of Figures ...................................................................................................................................... 11
List of Tables ........................................................................................................................................ 12
1 GPIO............................................................................................................................................. 13
1.1 Introduction ......................................................................................................................... 13
1.2 Block Diagram .................................................................................................................... 13
1.3
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Aux Funtion......................................................................................................................... 13
1.4
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External Interrupt List ......................................................................................................... 59
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1.5
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GPIO Usage Tips ............................................................................................................... 63
Register Definition .............................................................................................................. 64
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Top Clock Generator ................................................................................................................ 225
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2.1
2.2
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Introduction ....................................................................................................................... 225
Feature list ........................................................................................................................ 225
2.3 Block Diagram .................................................................................................................. 225

2.3.1 Clock Architecture ............................................................................................ 225
2.3.2 Clock Multiplixer ............................................................................................... 226
2.4 Clock PLL ......................................................................................................................... 227
2.5 PLL Related Control ......................................................................................................... 228
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2.6 Clock Gating ..................................................................................................................... 228
2.7
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Frequency Meter .............................................................................................................. 229
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2.8
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Register Definition ............................................................................................................ 230
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2.9.1
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Programming Guide ......................................................................................................... 266
Clock Off ........................................................................................................... 266
Clock Switching ................................................................................................ 267
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2.9.3
2.9.4
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Switch AXI to 26MHz by SCPSYS ................................................................... 267
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Frequency Meter .............................................................................................. 267
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2.10 PLL Related Register Definition ....................................................................................... 268
Top Reset Generate Unit ......................................................................................................... 310
3.1
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Introduction ....................................................................................................................... 310
3.2
3.3 Ba n
Feature list ........................................................................................................................ 310
Block Diagram .................................................................................................................. 310
3.4 Register Definition ............................................................................................................ 311
3.5 Programming Guide ......................................................................................................... 317

3.5.1 TOPRGU Initial ................................................................................................. 317
3.5.2 Watchdog Timer ............................................................................................... 318
3.5.3 IRQ Mode ......................................................................................................... 318
3.5.4 CONNSYS Watchdog Timeout ........................................................................ 318
3.5.5
3.5.6
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Dual Mode Reset.............................................................................................. 318
DDR Protect ..................................................................................................... 319
3.5.7
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DDR Reserved Mode Reset ............................................................................. 319
4.1 l
Peripheral Controller ................................................................................................................ 320
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Introduction ....................................................................................................................... 320
4.2
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Feature list ........................................................................................................................ 320
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4.3 Block Diagram .................................................................................................................. 320
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4.4
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External Interrupt Controller ................................................................................................... 369
5.1 Introduction ....................................................................................................................... 369
5.2 Feature list ........................................................................................................................ 369
5.3 Block Diagram .................................................................................................................. 369
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System Interrupt Controller..................................................................................................... 416
6.1
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Introduction ....................................................................................................................... 416
6.2
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Feature list ........................................................................................................................ 416
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Block Diagram .................................................................................................................. 416
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6.4
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Programming Guide ......................................................................................................... 444
6.5.1
6.5.2
MCUSYS MTCMOS Sequence ........................................................................ 444
SW Flow ........................................................................................................... 445
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General-Purpose Timer............................................................................................................ 446
7.1
7.2 Ba n
Introduction ....................................................................................................................... 446
Feature list ........................................................................................................................ 446
7.3 Block Diagram .................................................................................................................. 447
8 UART .......................................................................................................................................... 471
8.1 Introduction ....................................................................................................................... 471
8.2
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Feature list ........................................................................................................................ 471
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8.3 Block Diagram .................................................................................................................. 472
8.4
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I2C .............................................................................................................................................. 489
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9.1 Introduction ....................................................................................................................... 489
9.2
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Feature list ........................................................................................................................ 489
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9.2.1 Manual Transfer Mode ..................................................................................... 489
9.3 Block Diagram .................................................................................................................. 490
10 Pulse-Width Modulator (PWM) ................................................................................................ 512
10.1 Introduction ....................................................................................................................... 512
10.2 Feature list ........................................................................................................................ 512
10.3 Block Diagram .................................................................................................................. 512
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SPI Interface Controller ........................................................................................................... 549
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11.1 Introduction ....................................................................................................................... 549
11.2 Feature list ........................................................................................................................ 549
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11.3 Block Diagram .................................................................................................................. 549
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11.5 Programming Guide ......................................................................................................... 555
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USB2.0 ....................................................................................................................................... 556
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12.1 Introduction ....................................................................................................................... 556
12.2 Feature list ........................................................................................................................ 556
12.3 Block Diagram .................................................................................................................. 557
12.4 USB MAC Register Definition ........................................................................................... 557

12.4.1 Function Address Register ............................................................................... 560
12.4.2 Power Management Register ........................................................................... 560
12.4.3 Tx Interrupt Status Register ............................................................................. 562
12.4.4 Rx Interrupt Status Register ............................................................................. 563
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12.4.5 Tx Interrupt Enable Register ............................................................................ 563
12.4.6
12.4.7
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Rx Interrupt Enable Register ............................................................................ 564
Common USB Interrupt Register ..................................................................... 565
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12.4.8
12.4.9
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Common USB Interrupt Enable Register ......................................................... 567
Frame Number Register ................................................................................... 568
12.4.10
12.4.11
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Endpoint Selection Index Register ................................................................... 568
USB Endpoint 0 FIFO Register ........................................................................ 568
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12.4.12 USB Endpoint n FIFO Register ........................................................................ 569
12.4.13
12.4.14
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Device Control Register ................................................................................... 569
PWRUPCNT Register ...................................................................................... 570
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12.4.15 Tx FIFO Size Register (Dynamic FIFO Sizing Only) ........................................ 570
12.4.16 Rx FIFO Size Register (Dynamic FIFO Sizing Only) ....................................... 571
12.4.17 Tx FIFO Address Register (Dynamic FIFO Sizing Only) ................................. 572
12.4.18 Rx FIFO Address Register (Dynamic FIFO Sizing Only) ................................. 573
12.4.19 HS_EOF1 Register........................................................................................... 574
12.4.20 FS_EOF1 Register ........................................................................................... 574
12.4.21 LS_EOF1 Register ........................................................................................... 575
12.4.22 RSTINFO Register ........................................................................................... 575
12.4.23 Rx Data Toggle Set/Status Register ................................................................ 575
12.4.24 Rx Data Toggle Enable Register ...................................................................... 577
12.4.25
12.4.26
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Tx Data Toggle Set/Status Register................................................................. 577
Tx Data Toggle Enable Register ...................................................................... 579
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12.4.28
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USB Level 1 Interrupt Status Register(Word Access) ..................................... 580
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USB Level 1 Interrupt Mask Register(Word Access) ....................................... 581
12.4.29
12.4.30
12.4.31
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USB Level 1 Interrupt Polarity Register(Word Access) .................................... 582
USB Level 1 Interrupt Control Register(Word Access) .................................... 582
EP0 Control Status Register ............................................................................ 583
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12.4.32
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EP0 Received bytes Register .......................................................................... 584
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NAK Limit Register ........................................................................................... 584
12.4.34
12.4.35
12.4.36
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CONFIGDATA .................................................................................................. 585
TXMAP Register ............................................................................................... 585
Tx CSR Register .............................................................................................. 586
12.4.37
12.4.38
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RXMAP Register .............................................................................................. 588
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RX CSR Register ............................................................................................. 589
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12.4.40
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Rx Count Register ............................................................................................ 591
TxType Register ............................................................................................... 591
TxInterval Register ........................................................................................... 592
12.4.42 RxType Register ............................................................................................... 592
12.4.43 RxInterval Register ........................................................................................... 593
12.4.44 Configured FIFO Size Register ........................................................................ 593
12.4.45 DMA Interrupt Status Register (Byte Access) .................................................. 594
12.4.46 DMA Limiter Register (Word Access) .............................................................. 594
12.4.47 DMA Configuration Register (Word Access) .................................................... 594
12.4.48 DMA Channel M Control Register (Word Access) ........................................... 595
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12.4.49 DMA Channel M Address Register (Word Access) ......................................... 596
12.4.50
12.4.51
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DMA Channel M Byte Count Register (Word Access) ..................................... 596
EPn RxPktCount Register (Word Access) ....................................................... 597
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Transmit Endpoint n Function Address (Word Access) ................................... 597
Transmit Endpoint n Hub/Port Address (Word Access) ................................... 598
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Receive Endpoint n Function Address (Word Access) .................................... 598
Receive Endpoint n Hub/Port Address (Word Access) .................................... 599
12.5.1
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12.5 USBQMU Register Definition ........................................................................................... 599
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Queue Control Registers (QCR0-QCR3) ......................................................... 599
12.5.2
12.5.3
12.5.4
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RX Queue Command and Status Registers (RQCSRn) .................................. 607
RX Queue Starting Address Registers (RQSARn) .......................................... 608
RX Queue Current Pointer Registers (RQCPRn) ............................................ 608
12.5.5 RX Timeout Register n (RQTRn) ..................................................................... 609
12.5.6 RX Queue Last Done Pointer Register n (RQLDPRn) ..................................... 609
12.5.7 Tx n Queue Command and Status Register (TQCSRn) .................................. 610
12.5.8 TX n Queue Starting Address Register (TQSARn) .......................................... 610
12.5.9 TX n Queue Current Pointer Register (TQCPRn) ............................................ 611
12.5.10 USB General Control and Status Register (USBGCSR) ................................. 611
12.5.11 USB Firmware Register 1 (USB_FW1) ............................................................ 614
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12.5.12 USB Firmware Register 2 (USB_FW2) ............................................................ 614
12.5.13
12.5.14
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TnQ USB Stream Constraint Register (T0QUSBSC) ...................................... 614
QMU Interrupt Status and Acknowledgement Register (QISAR) .................... 615
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12.5.16
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QMU Interrupt Mask Register (QIMR).............................................................. 616
QMU Interrupt Mask Clear Register (QIMCR) ................................................. 619
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QMU Interrupt Mask Set Register (QIMSR) ..................................................... 621
Device Software Interrupt Command Register (DSICR) .................................. 624
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12.5.19 GPD Done Interrupt on GPD IOC bit Disable Register (IOCDISR) ................. 624
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12.5.20
12.5.21
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QMU Hardware Version Register (QMU_HWVER) ......................................... 627
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TX Queue Empty Indication Register (TQEMIR) ............................................. 627
12.5.22
12.5.23
12.5.24
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TX Queue Empty Indication Mask Register (TQEMIMR) ................................. 628
TX Queue Empty Indication Mask Clear Register (TQEMIMCR) .................... 629
TX Queue Empty Indication Mask Set Register (TQEMIMSR) ........................ 630
12.5.25
12.5.26
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RX Queue Empty Indication Register (RQEMIR) ............................................ 632
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RX Queue Empty Indication Mask Register (RQEMIMR) ................................ 635
12.5.27
12.5.28
12.5.29
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RX Queue Empty Indication Mask Clear Register (RQEMIMCR) ................... 636
RX Queue Empty Indication Mask Set Register (RQEMIMSR) ....................... 636
RX Queue Error Indication Register (RQEIR) ................................................. 637
12.5.30 RX Queue Error Indication Mask Register (RQEIMR) ..................................... 640
12.5.31 RX Queue Error Indication Mask Clear Register (RQEIMCR) ........................ 643
12.5.32 RX Queue Error Indication Mask Set Register (RQEIMSR) ............................ 647
12.5.33 RX Endpoint Error Indication Register (REPEIR) ............................................ 651
12.5.34 RX Endpoint Error Indication Mask Register (REPEIMR)................................ 652
12.5.35 RX Endpoint Error Indication Mask Clear Register (REPEIMCR) ................... 654
12.5.36 RX Endpoint Error Indication Mask Set Register (REPEIMSR) ....................... 657
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12.5.37 TX Queue Error Indication Register (TQEIR) .................................................. 658
12.5.38
12.5.39
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TX Queue Error Indication Mask Register (TQEIMR) ...................................... 664
TX Queue Error Indication Mask Clear Register (TQEIMCR).......................... 666
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12.5.41
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TX Queue Error Indication Mask Set Register (TQEIMSR) ............................. 669
TX Endpoint Error Indication Register (TEPEIR) ............................................. 672
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TX Endpoint Error Indication Mask Register (TEPEIMR) ................................ 673
TX Endpoint Error Indication Mask Clear Register (TEPEIMCR) .................... 674
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12.5.44 TX Endpoint Error Indication Mask Set Register (TEPEIMSR) ....................... 675
12.5.45
12.5.46
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Device Software Interrupt Mask Register (DSIMR) ......................................... 676
Device Software Interrupt Mask Register (DSIMR) ......................................... 677
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12.5.47 Device Software Interrupt Mask Register (DSIMCR) ....................................... 677
12.5.48 Device Software Interrupt Mask Register (DSIMSR) ....................................... 677
13 MSDC Controller ....................................................................................................................... 679
13.1 Introduction ....................................................................................................................... 679
13.2 Feature list ........................................................................................................................ 679
13.3 Block Diagram .................................................................................................................. 680
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NAND Flash Interface ............................................................................................................... 838
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14.1 Introduction ....................................................................................................................... 838
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14.2 Feature list ........................................................................................................................ 838
14.3 Block Diagram .................................................................................................................. 839
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14.4 NFI Register Definition ..................................................................................................... 839
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14.5 NFIECC Register Definition .............................................................................................. 887
Infrared Receiver ...................................................................................................................... 924
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15.1 Introduction ....................................................................................................................... 924
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15.2 Feature list ........................................................................................................................ 924
15.3 Block Diagram .................................................................................................................. 924
16 HDMI Transmitter ..................................................................................................................... 952
16.1 Introduction ....................................................................................................................... 952
16.2 Feature list ........................................................................................................................ 952
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16.3 Block Diagram .................................................................................................................. 952
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MIPI TX..................................................................................................................................... 1016
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17.1 Introduction ..................................................................................................................... 1016
17.2 Feature list ...................................................................................................................... 1016
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17.3 Register Definition .......................................................................................................... 1016
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HIFSYS Control ....................................................................................................................... 1037
18.1 Introduction ..................................................................................................................... 1037
18.2 Feature List ..................................................................................................................... 1037
18.3 Block Diagram ................................................................................................................ 1037
19 PCie2.0..................................................................................................................................... 1044
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19.1 Introduction ..................................................................................................................... 1044
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19.2 Feature list ...................................................................................................................... 1044
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19.3 Block Diagram ................................................................................................................ 1045
19.3.1
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PCIe Subsys (MAC) ....................................................................................... 1045
19.4.1
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pcie_express_wrap ........................................................................................ 1045
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20
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USB3.0 ..................................................................................................................................... 1073
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20.1 Introduction ..................................................................................................................... 1073
20.2 Feature List ..................................................................................................................... 1073

20.2.1
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SSUSB Subsyss (MAC) ................................................................................. 1074
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20.3.1 ssusb2_xhci_exclude_port_csr ...................................................................... 1074
20.3.2 ssusb2_xhci_u2_port_csr .............................................................................. 1158
20.3.3 ssusb2_xhci_u3_port_csr .............................................................................. 1170
21 USB2.0 (in USB3.0) ................................................................................................................. 1181
21.1 Introduction ..................................................................................................................... 1181
21.2 Feature list ...................................................................................................................... 1181
21.3 Block Diagram ................................................................................................................ 1181
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ETHSYS Control ..................................................................................................................... 1185
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22.1 Description ...................................................................................................................... 1185
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22.2 Feature List ..................................................................................................................... 1185
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22.3 Block Diagram ................................................................................................................ 1185
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23
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Frame Engine .......................................................................................................................... 1190
23.1 Introduction ..................................................................................................................... 1190
23.2 Feature List ..................................................................................................................... 1190

23.2.1 PSE Features ................................................................................................. 1190
23.2.2 PDMA Features .............................................................................................. 1190
23.2.3 GMAC Features ............................................................................................. 1190
23.3 Block Diagram ................................................................................................................ 1191

23.3.1
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Frame Engine ................................................................................................. 1191
23.4.1
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Frame Engine MIB Counters .......................................................................... 1289
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List of Figures
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Figure 1-1: Block Diagram of GPIO ...................................................................................................... 13
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Figure 2-1: Block diagram of clock architecture .................................................................................. 226
Figure 2-2: Example of Clock Multiplixer ............................................................................................ 226
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Figure 2-3: PLL block diagram ............................................................................................................ 227
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Figure 2-4: ABIST FMETER structure ................................................................................................. 229
Figure 2-5: CKGEN FMETER structure .............................................................................................. 230
Figure 3-1: Block diagram of top reset generation unit ....................................................................... 310
Figure 4-1: Block diagram of Pericfg Controller .................................................................................. 320
Figure 5-1: Block diagram of external interrupt controller ................................................................... 369
Figure 6-1: System level block diagram of System Interrupt Controller ............................................. 417
Figure 6-2: Block diagram of system interrupt controller .................................................................... 417
Figure 6-3: MCUSYS MTCMOS Sequence ........................................................................................ 444
Figure 6-4: Software flow of MCUSYS MTCMOS Sequnce ............................................................... 445
Figure 7-1: Block diagram of GPT ...................................................................................................... 447
Figure 8-1: Block Diagram of UART.................................................................................................... 472
Figure 9-1: Block Diagram of I2C ........................................................................................................ 490
Figure 10-1: Generation procedure of PWM ....................................................................................... 512
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Figure 10-2: Block Diagram of PWM .................................................................................................. 512
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Figure 11-1: Pin connection between SPI master and SPI slave ....................................................... 549
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Figure 11-2: Block Diagram of SPI Controller ..................................................................................... 550
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Figure 11-3: SPI transmission formats ................................................................................................ 555
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Figure 12-1: Block Diagram of USB2.0 ............................................................................................... 557
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Figure 12-2: Block Diagram of USB2.0 QMU ..................................................................................... 557
Figure 13-1: Block Diagram of MSDC controller ................................................................................. 680
Figure 14-1: Block Diagram of NAND Flash Interface ........................................................................ 839
Figure 15-1: Block Diagram of IR Receiver ........................................................................................ 924
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Figure 16-1: Block Diagram of HDMI Transmitter ............................................................................... 952
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Figure 18-1.HIFSYS Block Diagram ................................................................................................. 1037
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Figure 19-1.PCIe Subsys Block Diagram ......................................................................................... 1045
Figure 20-1.SSUSB Host Architecture .............................................................................................. 1073
Figure 20-2.SSUSB Subsys Block Diagram ..................................................................................... 1074
Figure 22-1 ETHSYS sub-system control ......................................................................................... 1185
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List of Tables
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Table 1-1: Aux. Function Table of GPIO ................................................................................................ 13
Table 1-2. Reset Status of GPIOs ......................................................................................................... 39
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Table 1-3: Driving and pull control of GPIOs ......................................................................................... 44
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Table 1-4: IES control register mapping ................................................................................................ 53
Table 1-5: SMTcontrol register mapping ............................................................................................... 54
Table 1-6: Driving control register mapping .......................................................................................... 55
Table 1-7: External Interrupt List ........................................................................................................... 59
Table 1-8: EINT source usage notes ..................................................................................................... 63
Table 1-9: GPIO use MIPI-DSI Tx pin ................................................................................................... 63
Table 1-10: GPIO use I2S MCLK .......................................................................................................... 63
Table 2-1: PLL related control ............................................................................................................. 228
Table 2-2: Clock gating settings .......................................................................................................... 228
Table 7-1: Operation mode of GPT ..................................................................................................... 446
Table 8-1: UART Base Address Table ................................................................................................. 472
Table 12-1: USB20 Feature List .......................................................................................................... 556
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Table 13-1: MSDC Configuration Table ............................................................................................... 679
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Table 13-2: MSDC Base Address Table .............................................................................................. 680
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Table 19-1.PCIe Feature List ............................................................................................................ 1044
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1 GPIO
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1.1 Introduction
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By setting up the control registers, the MCU software can control the direction, output value and read
count.
1.2 Block Diagram

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the input values on these pins. The GPIOs are multiplexed with other functions to reduce the pin
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Below figure is the block diagram of GPIO. Each GPIO controls the auxlillary mode by programming
GPIO_MODE_SELx command register. Besides, the dedicated register bits can be set to 1 or 0 by
writing the bits of GPIO_MODE_SETx or GPIO_MODE_RESETx to 1.
GPIO_DIR, GPIO_DOUT and GPIO_PULLEN are also programmable by the same method of
GPIO_MODE.
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Ba n Figure 1-1: Block Diagram of GPIO
1.3 Aux Funtion

Below table is the aux. function of each GPIO, showing the mapping table of aux.name, mode number,
CU/CD(controllable pull-up and pull-down) and driving capability.
Table 1-1: Aux. Function Table of GPIO

Aux. Aux. PU/PD/
Name Aux.name Driving SMT
function type CU/CD
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PWRAP_SPI0_MI 0 GPIO0 IO CU,CD 2/4/6/8mA -
1
2
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PWRAP_SPIDO
PWRAP_SPIDI
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IO
IO
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
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3 - - CU,CD 2/4/6/8mA -
4
5
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R -
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CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
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6 - - CU,CD 2/4/6/8mA -
7 - - CU,CD 2/4/6/8mA -
PWRAP_SPI0_MO 0 GPIO1 IO CU,CD 2/4/6/8mA -
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Name
Aux.
function
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Aux.name
Aux.
type
PU/PD/
CU/CD
Driving SMT
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1 PWRAP_SPIDI IO CU,CD 2/4/6/8mA -
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2 PWRAP_SPIDO IO CU,CD 2/4/6/8mA -
3 - - CU,CD 2/4/6/8mA -
4 - - CU,CD 2/4/6/8mA -
5
6
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CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
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PWRAP_INT
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0
1
2
3
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GPIO2
PWRAP_INT
-
-
-
IO
I
-
-
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
-
-
-
-
-
4 - - CU,CD 2/4/6/8mA -
5 - - CU,CD 2/4/6/8mA -
6 - - CU,CD 2/4/6/8mA -
7 - - CU,CD 2/4/6/8mA -
PWRAP_SPI0_CK 0 GPIO3 IO CU,CD 2/4/6/8mA -
1 PWRAP_SPICK_I O CU,CD 2/4/6/8mA -
2 - - CU,CD 2/4/6/8mA -
3 - - CU,CD 2/4/6/8mA -
4
5
f o r -
-
-
-
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
6
7
e a s e-
I -
-
R 2
-
-
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
l
PWRAP_SPI0_CSN 0 GPIO4 IO CU,CD 2/4/6/8mA -
1
2
3
Re Pi B P
PWRAP_SPICS_B_I
-
-
O
-
-
CU,CD
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
-
-
-
a
4 - - CU,CD 2/4/6/8mA -
5
6
n a n -
-
-
-
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
PWRAP_SPI0_CK2
B
7
0
1
2
3
a -
GPIO5
PWRAP_SPICK2_I
-
-
O
-
IO
-
-
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
-
-
-
-
-
4 - - CU,CD 2/4/6/8mA -
5 ANT_SEL1 O CU,CD 2/4/6/8mA -
6 - - CU,CD 2/4/6/8mA -
7 - - CU,CD 2/4/6/8mA -
PWRAP_SPI0_CSN2 0 GPIO6 IO CU,CD 2/4/6/8mA -
1 PWRAP_SPICS2_B_I O CU,CD 2/4/6/8mA -
2 - - CU,CD 2/4/6/8mA -
r
3 - - CU,CD 2/4/6/8mA -
4
5
e f o -
ANT_SEL0
2
-
O
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
s
6 - - CU,CD 2/4/6/8mA -
SPI1_CSN
7
0
l e a P I - R
DBG_MON_A[0]
GPIO7
IO
IO
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
Re Pi B
1 SPI1_CS O CU,CD 2/4/6/8mA -
2 - - CU,CD 2/4/6/8mA -
3 - - CU,CD 2/4/6/8mA -
a n a
n
Ba
MT7623N
f o r
Name
Aux.
function
e a s e I - R 2
Aux.name
Aux.
type
PU/PD/
CU/CD
Driving SMT
l P
4 KCOL0 IO CU,CD 2/4/6/8mA -
Re Pi B
5 - - CU,CD 2/4/6/8mA -
6 - - CU,CD 2/4/6/8mA -
7 DBG_MON_B[12] IO CU,CD 2/4/6/8mA -
SPI1_MI 0
1
a n a GPIO8
SPI1_MI
IO
I
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
Ba n2
3
4
5
6
SPI1_MO
-
KCOL1
-
-
O
-
IO
-
-
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
-
-
-
-
-
SPI1_MO 0 GPIO9 IO CU,CD 2/4/6/8mA -
1 SPI1_MO O CU,CD 2/4/6/8mA -
2 SPI1_MI I CU,CD 2/4/6/8mA -
3 EXT_FRAME_SYNC I CU,CD 2/4/6/8mA -
5 - - CU,CD 2/4/6/8mA -
6 - - CU,CD 2/4/6/8mA -
RTC32K_CK
7
0
f o r
DBG_MON_B[14]
GPIO10
IO
IO
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
e
1 RTC32K_CK I CU,CD 2/4/6/8mA -
2
3
l e a s I - R 2 -
-
-
-
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
Re Pi B
4
5
6 P -
-
-
-
-
-
CU,CD
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
-
-
-
a
7 - - CU,CD 2/4/6/8mA -
WATCHDOG
n
0
1
a n GPIO11
WATCHDOG
IO
O
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
Ba
2 - - CU,CD 2/4/6/8mA -
3 - - CU,CD 2/4/6/8mA -
4 - - CU,CD 2/4/6/8mA -
5 - - CU,CD 2/4/6/8mA -
6 - - CU,CD 2/4/6/8mA -
7 - - CU,CD 2/4/6/8mA -
SRCLKENA 0 GPIO12 IO CU,CD 2/4/6/8mA -
1 SRCLKENA O CU,CD 2/4/6/8mA -
2 - - CU,CD 2/4/6/8mA -
3 - - CU,CD 2/4/6/8mA -
4 - - CU,CD 2/4/6/8mA -
5 - - CU,CD 2/4/6/8mA -
r
6 - - CU,CD 2/4/6/8mA -
SRCLKENAI
7
0
e f o -
GPIO13
2
-
IO
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
s
1 SRCLKENAI I CU,CD 2/4/6/8mA -
2
3
l e a P I - R -
-
-
-
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
Re Pi B
4 - - CU,CD 2/4/6/8mA -
5 - - CU,CD 2/4/6/8mA -
6 - - CU,CD 2/4/6/8mA -
a n a
n
Ba
MT7623N
f o r
Name
Aux.
function
e a s e I - R 2
Aux.name
Aux.
type
PU/PD/
CU/CD
Driving SMT
l P
7 - - CU,CD 2/4/6/8mA -
Re Pi B
URXD2 0 GPIO14 IO CU,CD 4/8/12/16mA -
1 URXD2 I CU,CD 4/8/12/16mA -
2 UTXD2 O CU,CD 4/8/12/16mA -
3
4
a n a -
-
-
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
UTXD2
Ba n5
6
7
0
1
SRCCLKENAI2
GPIO15
UTXD2
-
DBG_MON_B[30]
I
-
IO
IO
O
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
-
-
2 URXD2 I CU,CD 4/8/12/16mA -
3 - - CU,CD 4/8/12/16mA -
4 - - CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
6 - - CU,CD 4/8/12/16mA -
PCM_CLK 0 GPIO18 IO CU,CD 4/8/12/16mA -
1 PCM_CLK0 IO CU,CD 4/8/12/16mA -
2
3
f o r
MRG_CLK
-
O
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
e
4 MM_TEST_CK I CU,CD 4/8/12/16mA -
5
6
l e a s
CONN_DSP_JCK
I -
WCN_PCM_CLKO
R 2 I
IO
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
PCM_SYNC
7
0
1
Re Pi B P
DBG_MON_A[3]
GPIO19
PCM_SYNC
IO
IO
IO
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
a
2 MRG_SYNC IO CU,CD 4/8/12/16mA -
n
3 - - CU,CD 4/8/12/16mA -
4
5
a n a -
CONN_DSP_JINTP
-
O
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
PCM_RX B 6
7
0
1
2
WCN_PCM_SYNC
DBG_MON_A[5]
GPIO20
PCM_RX
MRG_RX
IO
IO
IO
I
I
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
-
-
3 MRG_TX O CU,CD 4/8/12/16mA -
4 PCM_TX O CU,CD 4/8/12/16mA -
5 CONN_DSP_JDI I CU,CD 4/8/12/16mA -
6 WCN_PCM_RX I CU,CD 4/8/12/16mA -
7 DBG_MON_A[4] IO CU,CD 4/8/12/16mA -
PCM_TX 0 GPIO21 IO CU,CD 4/8/12/16mA -
2
3
f o r
MRG_TX
MRG_RX
O
I
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
4
5
e a s e PCM_RX
I -
CONN_DSP_JMS
R 2
I
I
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
EINT0
6
7
0
1
l
Re Pi B P
WCN_PCM_TX
DBG_MON_A[2]
GPIO22
UCTS0
O
IO
IO
I
CU,CD
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
-
a n a
n
B a
MT7623N
f o r
Name
Aux.
function
e a s e I - R 2
Aux.name
Aux.
type
PU/PD/
CU/CD
Driving SMT
l P
2 - - CU,CD 4/8/12/16mA -
Re Pi B
4 CONN_DSP_JDO O CU,CD 4/8/12/16mA -
6
7
a n a -
DBG_MON_A[30]
-
IO
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
EINT1
Ba n0
1
2
3
4
GPIO23
URTS0
-
KCOL2
CONN_MCU_TDO
IO
O
-
IO
O
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
-
-
6 - - CU,CD 4/8/12/16mA -
EINT2 0 GPIO24 IO CU,CD 4/8/12/16mA -
1 UCTS1 I CU,CD 4/8/12/16mA -
2 - - CU,CD 4/8/12/16mA -
4 CONN_MCU_DBGACK_N O CU,CD 4/8/12/16mA -
5
6
f o r -
-
-
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
EINT3
7
0
1
e a s e
DBG_MON_A[28]
GPIO25
URTS1
I - R 2
IO
IO
O
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
2
3
4
l
Re Pi B P -
KCOL0
CONN_MCU_DBGI_N
-
IO
I
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
a
5 - - CU,CD 4/8/12/16mA -
6
7
n a n -
DBG_MON_A[27]
-
IO
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
a
B 1
2
3
4
5
UCTS3
DRV_VBUS_P1
KROW3
CONN_MCU_TCK0
CONN_MCU_AICE_JCKC
I
O
IO
I
I
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
-
-
6 - - CU,CD 4/8/12/16mA -
1 URTS3 O CU,CD 4/8/12/16mA -
2 IDDIG_P1 I CU,CD 4/8/12/16mA -
3 KROW2 IO CU,CD 4/8/12/16mA -
r
4 CONN_MCU_TDI I CU,CD 4/8/12/16mA -
5
6
e f o 2
-
-
-
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
s
EINT6 0
1
l e a P I - R
GPIO28
DRV_VBUS
IO
O
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
Re Pi B
2 - - CU,CD 4/8/12/16mA -
3 KROW1 IO CU,CD 4/8/12/16mA -
4 CONN_MCU_TRST_B I CU,CD 4/8/12/16mA -
a n a
n
Ba
MT7623N
f o r
Name
Aux.
function
e a s e I - R 2
Aux.name
Aux.
type
PU/PD/
CU/CD
Driving SMT
l P
5 - - CU,CD 4/8/12/16mA -
Re Pi B
6 - - CU,CD 4/8/12/16mA -
1
2
a n a IDDIG
MSDC1_WP
I
I
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
Ba n3
4
5
6
7
KROW0
CONN_MCU_TMS
CONN_MCU_AICE_JMSC
-
DBG_MON_A[23]
IO
I
IO
-
IO
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
-
-
I2S1_DATA 0 GPIO33 IO CU,CD 4/8/12/16mA -
1 I2S1_DATA IO CU,CD 4/8/12/16mA -
2 I2S1_DATA_BYPS O CU,CD 4/8/12/16mA -
4 IMG_TEST_CK I CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
6 WCN_PCM_TX O CU,CD 4/8/12/16mA -
I2S1_DATA_IN 0
1
f o r GPIO34
I2S1_DATA_IN
IO
IO
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
e
2 - - CU,CD 4/8/12/16mA -
3
4
l e a s I - R 2
PCM_RX
VDEC_TEST_CK
I
I
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
Re Pi B
5
6
7 P WCN_PCM_RX
-
DBG_MON_B[7]
-
I
IO
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
a
I2S1_BCK 0 GPIO35 IO CU,CD 4/8/12/16mA -
n
1 I2S1_BCK IO CU,CD 4/8/12/16mA -
n
2
a - - CU,CD 4/8/12/16mA -
Ba
3 PCM_CLK0 IO CU,CD 4/8/12/16mA -
4 - - CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
6 WCN_PCM_CLKO IO CU,CD 4/8/12/16mA -
I2S1_LRCK 0 GPIO36 IO CU,CD 4/8/12/16mA -
1 I2S1_LRCK IO CU,CD 4/8/12/16mA -
2 - - CU,CD 4/8/12/16mA -
3 PCM_SYNC IO CU,CD 4/8/12/16mA -
4 - - CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
6 WCN_PCM_SYNC IO CU,CD 4/8/12/16mA -
r
o
I2S1_MCLK 0 GPIO37 IO CU,CD 4/8/12/16mA -
1
2
s e f I2S1_MCLK
2
-
IO
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
3
4
l e a P I - R -
-
-
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
Re Pi B
5 - - CU,CD 4/8/12/16mA -
6 - - CU,CD 4/8/12/16mA -
a n a
n
Ba
MT7623N
f o r
Name
Aux.
function
e a s e I - R 2
Aux.name
Aux.
type
PU/PD/
CU/CD
Driving SMT
l
JTMS 0 GPIO39 IO CU,CD 2/4/6/8mA -
Re Pi B
1
2
3
P JTMS
CONN_MCU_TMS
CONN_MCU_AICE_JMSC
IO
I
IO
CU,CD
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
-
-
-
4
5
a n a DFD_TMS_XI
-
I
-
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
JTCK
Ba n6
7
0
1
2
-
-
GPIO40
JTCK
CONN_MCU_TCK1
-
-
IO
I
I
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
-
-
-
-
-
3 CONN_MCU_AICE_JCKC I CU,CD 2/4/6/8mA -
4 DFD_TCK_XI I CU,CD 2/4/6/8mA -
5 - - CU,CD 2/4/6/8mA -
6 - - CU,CD 2/4/6/8mA -
7 - - CU,CD 2/4/6/8mA -
JTDI 0 GPIO41 IO CU,CD 2/4/6/8mA -
1 JTDI I CU,CD 2/4/6/8mA -
2 CONN_MCU_TDI I CU,CD 2/4/6/8mA -
3
4
f o r -
DFD_TDI_XI
-
I
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
e
5 - - CU,CD 2/4/6/8mA -
6
7
l e a s I
-
-
-
R 2 -
-
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
JTDO 0
1
2
Re Pi B P
GPIO42
JTDO
CONN_MCU_TDO
IO
O
O
CU,CD
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
-
-
-
a
3 - - CU,CD 2/4/6/8mA -
n
4 DFD_TDO O CU,CD 2/4/6/8mA -
5
6
a n a -
-
-
-
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
NCLE
B 7
0
1
2
3
-
GPIO43
NCLE
EXT_XCS2
-
O
-
IO
O
-
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
2/4/6/8mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
-
-
4 - - CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
6 - - CU,CD 4/8/12/16mA -
7 - - CU,CD 4/8/12/16mA -
NCEB1 0 GPIO44 IO CU,CD 4/8/12/16mA -
1 NCEB1 O CU,CD 4/8/12/16mA -
2 IDDIG I CU,CD 4/8/12/16mA -
3
4
f o r -
-
-
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
5
6
e a s e I -
-
-
R 2
-
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
NCEB0
7
0
1
2
l
Re Pi B P
-
GPIO45
NCEB0
DRV_VBUS
O
-
IO
O
CU,CD
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
-
a n a
n
B a
MT7623N
f o r
Name
Aux.
function
e a s e I - R 2
Aux.name
Aux.
type
PU/PD/
CU/CD
Driving SMT
l P
3 - - CU,CD 4/8/12/16mA -
Re Pi B
4 - - CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
6 - - CU,CD 4/8/12/16mA -
IR
7
0
a n a -
GPIO46
-
IO
CU,CD
CU,CD
4/8/12/16mA
-
-
-
Ba n1
2
3
4
5
IR
-
-
-
-
I
-
-
-
-
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
-
-
-
-
-
-
-
-
-
-
6 - - CU,CD - -
7 - - CU,CD - -
NREB 0 GPIO47 IO CU,CD 4/8/12/16mA -
1 NREB O CU,CD 4/8/12/16mA -
2 IDDIG_P1 I CU,CD 4/8/12/16mA -
3 - - CU,CD 4/8/12/16mA -
4 - - CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
6
7
f o r
-
- -
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
e
NRNB 0 GPIO48 IO CU,CD 4/8/12/16mA -
1
2
l e a s NRNB
I -
DRV_VBUS_P1
R 2 I
O
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
3
4
5
Re Pi B P -
-
-
-
-
-
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
a
6 - - CU,CD 4/8/12/16mA -
I2S0_DATA
7
0
n a n -
GPIO49
-
IO
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
a
1 I2S0_DATA IO CU,CD 4/8/12/16mA -
B 2
3
4
5
6
I2S0_DATA_BYPS
PCM_TX
-
-
WCN_I2S_DO
O
O
-
-
O
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
-
-
SPI0_CSN 0 GPIO53 IO CU,CD 4/8/12/16mA -
1 SPI0_CS O CU,CD 4/8/12/16mA -
2 - - CU,CD 4/8/12/16mA -
3 SPDIF O CU,CD 4/8/12/16mA -
4 ADC_CK O CU,CD 4/8/12/16mA -
r
5 PWM1 O CU,CD 4/8/12/16mA -
6
7
e f o -
DBG_MON_A[7]
2
-
IO
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
s
SPI0_CK 0 GPIO54 IO CU,CD 4/8/12/16mA -
1
2
l e a P I - R
SPI0_CK
-
O
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
Re Pi B
3 SPDIF_IN1 I CU,CD 4/8/12/16mA -
4 ADC_DAT_IN I CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
a n a
n
Ba
MT7623N
f o r
Name
Aux.
function
e a s e I - R 2
Aux.name
Aux.
type
PU/PD/
CU/CD
Driving SMT
l P
6 - - CU,CD 4/8/12/16mA -
Re Pi B
SPI0_MI 0 GPIO55 IO CU,CD 4/8/12/16mA -
1 SPI0_MI I CU,CD 4/8/12/16mA -
2
3
a n a SPI0_MO
MSDC1_WP
O
I
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
SPI0_MO
Ba n4
5
6
7
0
ADC_WS
PWM2
-
DBG_MON_A[8]
GPIO56
O
O
-
IO
IO
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
-
-
1 SPI0_MO O CU,CD 4/8/12/16mA -
2 SPI0_MI I CU,CD 4/8/12/16mA -
4 - - CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
6 - - CU,CD 4/8/12/16mA -
SDA1 0 GPIO57 IO CD - -
1
2
SDA1
f o r -
IO
-
CD
CD
-
-
-
-
e
3 - - CD - -
4
5
l e a s I -
-
-
R 2 -
-
CD
CD
-
-
-
-
SCL1
6
7
0
Re Pi B P -
-
GPIO58
-
-
IO
CD
CD
CD
-
-
-
-
-
-
a
1 SCL1 IO CD - -
n
2 - - CD - -
3
4
a n a -
-
-
-
CD
CD
-
-
-
-
WB_RSTB
B 5
6
7
0
1
-
-
-
GPIO60
WB_RSTB
-
-
-
IO
O
CD
CD
CD
CU,CD
CU,CD
-
-
-
2/4/6/8mA
2/4/6/8mA
-
-
-
-
-
2 - - CU,CD 2/4/6/8mA -
3 - - CU,CD 2/4/6/8mA -
4 - - CU,CD 2/4/6/8mA -
5 - - CU,CD 2/4/6/8mA -
6 - - CU,CD 2/4/6/8mA -
r
GPIO61 0 GPIO61 IO CU,CD 2/4/6/8mA -
o
1 - I CU,CD 2/4/6/8mA -
2
3
s e f -
-
2
-
-
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
4
5
l e a P I -
-
-
R -
-
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
Re Pi B
6 - - CU,CD 2/4/6/8mA -
GPIO62 0 GPIO62 IO CU,CD 2/4/6/8mA -
a n a
n
B a
MT7623N
f o r
Name
Aux.
function
e a s e I - R 2
Aux.name
Aux.
type
PU/PD/
CU/CD
Driving SMT
l P
1 - I CU,CD 2/4/6/8mA -
Re Pi B
2 - - CU,CD 2/4/6/8mA -
3 - - CU,CD 2/4/6/8mA -
4 - - CU,CD 2/4/6/8mA -
5
6
a n a -
-
-
-
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
WB_SCLK
Ba n7
0
1
2
3
DBG_MON_A[15]
GPIO63
WB_SCLK
-
-
IO
IO
O
-
-
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
-
-
-
-
-
4 - - CU,CD 2/4/6/8mA -
5 - - CU,CD 2/4/6/8mA -
6 - - CU,CD 2/4/6/8mA -
WB_SDATA 0 GPIO64 IO CU,CD 2/4/6/8mA -
1 WB_SDATA IO CU,CD 2/4/6/8mA -
2 - - CU,CD 2/4/6/8mA -
3 - - CU,CD 2/4/6/8mA -
4
5
f o r -
-
-
-
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
6
7
e a s e -
R
DBG_MON_A[12]
I - 2
-
IO
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
l
WB_SEN 0 GPIO65 IO CU,CD 2/4/6/8mA -
1
2
3
Re Pi B P
WB_SEN
-
-
O
-
-
CU,CD
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
-
-
-
a
4 - - CU,CD 2/4/6/8mA -
5
6
n a n -
-
-
-
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
WB_CTRL0
B
7
0
1
2
3
a DBG_MON_A[14]
GPIO66
WB_CTRL0
-
-
IO
IO
IO
-
-
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
-
-
-
-
-
4 - - CU,CD 2/4/6/8mA -
5 DFD_NTRST_XI I CU,CD 2/4/6/8mA -
6 - - CU,CD 2/4/6/8mA -
WB_CTRL1 0 GPIO67 IO CU,CD 2/4/6/8mA -
1 WB_CTRL1 IO CU,CD 2/4/6/8mA -
2 - - CU,CD 2/4/6/8mA -
r
3 - - CU,CD 2/4/6/8mA -
4
5
e f o -
DFD_TMS_XI
2
-
I
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
s
6 - - CU,CD 2/4/6/8mA -
WB_CTRL2
7
0
l e a P I - R
DBG_MON_A[18]
GPIO68
IO
IO
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
Re Pi B
2 - - CU,CD 2/4/6/8mA -
3 - - CU,CD 2/4/6/8mA -
a n a
n
Ba
MT7623N
f o r
Name
Aux.
function
e a s e I - R 2
Aux.name
Aux.
type
PU/PD/
CU/CD
Driving SMT
l P
4 - - CU,CD 2/4/6/8mA -
Re Pi B
5 DFD_TCK_XI I CU,CD 2/4/6/8mA -
6 - - CU,CD 2/4/6/8mA -
WB_CTRL3 0
1
a n a GPIO69
WB_CTRL3
IO
IO
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
Ba n2
3
4
5
6
-
-
-
DFD_TDI_XI
-
-
-
-
I
-
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
-
-
-
-
-
WB_CTRL4 0 GPIO70 IO CU,CD 2/4/6/8mA -
2 - - CU,CD 2/4/6/8mA -
3 - - CU,CD 2/4/6/8mA -
4 - - CU,CD 2/4/6/8mA -
5 DFD_TDO O CU,CD 2/4/6/8mA -
6 - - CU,CD 2/4/6/8mA -
WB_CTRL5
7
0
f o r
DBG_MON_A[21]
GPIO71
IO
IO
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
e
2
3
l e a s I - R 2 -
-
-
-
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
Re Pi B
4
5
6 P -
-
-
-
-
-
CU,CD
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
-
-
-
a
I2S0_DATA_IN
n
0
1
a n GPIO72
I2S0_DATA_IN
IO
IO
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
Ba
2 - - CU,CD 4/8/12/16mA -
3 PCM_RX I CU,CD 4/8/12/16mA -
4 PWM0 O CU,CD 4/8/12/16mA -
5 DISP_PWM O CU,CD 4/8/12/16mA -
6 WCN_I2S_DI I CU,CD 4/8/12/16mA -
I2S0_LRCK 0 GPIO73 IO CU,CD 4/8/12/16mA -
1 I2S0_LRCK IO CU,CD 4/8/12/16mA -
2 - - CU,CD 4/8/12/16mA -
3 PCM_SYNC IO CU,CD 4/8/12/16mA -
4 - - CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
r
6 WCN_I2S_LRCK IO CU,CD 4/8/12/16mA -
I2S0_BCK
7
0
e f oDBG_MON_B[5]
GPIO74
2
IO
IO
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
s
1 I2S0_BCK IO CU,CD 4/8/12/16mA -
2
3
l e a P I - R -
PCM_CLK0
-
IO
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
Re Pi B
4 - - CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
6 WCN_I2S_BCK IO CU,CD 4/8/12/16mA -
a n a
n
Ba
MT7623N
f o r
Name
Aux.
function
e a s e I - R 2
Aux.name
Aux.
type
PU/PD/
CU/CD
Driving SMT
l P
Re Pi B
1 SDA0 IO CD - -
2 - - CD - -
3
4
a n a -
-
-
-
CD
CD
-
-
-
-
SCL0
Ba n5
6
7
0
1
-
-
-
GPIO76
SCL0
-
-
-
IO
IO
CD
CD
CD
CD
CD
-
-
-
-
-
-
-
-
-
-
2 - - CD - -
3 - - CD - -
4 - - CD - -
5 - - CD - -
6 - - CD - -
7 - - CD - -
1 SDA2 IO CD - -
2
3
f o r -
-
-
-
CD
CD
-
-
-
-
e
4 - - CD - -
5
6
l e a s I -
-
-
R 2 -
-
CD
CD
-
-
-
-
SCL2
7
0
1
Re Pi B P -
GPIO78
SCL2
-
IO
IO
CD
CD
CD
-
-
-
-
-
-
a
2 - - CD - -
n
3 - - CD - -
4
5
a n a -
-
-
-
CD
CD
-
-
-
-
URXD0 B 6
7
0
1
2
-
URXD0
-
GPIO79
UTXD0
-
-
IO
I
O
CD
CD
CD
CD
CD
-
-
-
-
-
-
-
-
-
-
3 - - CD - -
4 - - CD - -
5 IO CD - -
6 - - CD - -
7 - - CD - -
UTXD0 0 GPIO80 IO CD - -
1 UTXD0 O CD - -
2
3
f o r
URXD0
-
I
-
CD
CD
-
-
-
-
4
5
e a s e I -
-
-
R 2
-
-
CD
CD
-
-
-
-
URXD1
6
7
0
1
l
Re Pi B P -
-
GPIO81
URXD1
-
-
IO
I
CD
CD
CD
CD
-
-
-
-
-
-
-
-
a n a
n
B a
MT7623N
f o r
Name
Aux.
function
e a s e I - R 2
Aux.name
Aux.
type
PU/PD/
CU/CD
Driving SMT
l P
2 UTXD1 O CD - -
Re Pi B
3 - - CD - -
4 - - CD - -
5 - - CD - -
6
7
a n a -
- -
-
CD
CD
-
-
-
-
UTXD1
Ba n0
1
2
3
4
GPIO82
UTXD1
URXD1
-
-
IO
O
I
-
-
CD
CD
CD
CD
CD
-
-
-
-
-
-
-
-
-
-
5 - - CD - -
6 - - CD - -
7 - - CD - -
LCM_RST 0 GPIO83 IO CU,CD 2/4/6/8mA -
1 LCM_RST O CU,CD 2/4/6/8mA -
2 VDAC_CK_XI I CU,CD 2/4/6/8mA -
3 - - CU,CD 2/4/6/8mA -
4 - - CU,CD 2/4/6/8mA -
5
6
f o r -
-
-
-
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
DSI_TE
7
0
1
e a s e
DBG_MON_B[1]
GPIO84
I
DSI_TE
- R 2
IO
IO
I
CU,CD
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
-
-
-
2
3
4
l
Re Pi B P -
-
-
-
-
-
CU,CD
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
-
-
-
a
5 - - CU,CD 2/4/6/8mA -
6
7
n a n -
DBG_MON_B[0]
-
IO
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
a
1.8V: 2/4/6/8/10/12/14/16mA
6 I2SOUT_LRCK O CU,CD -
B
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
7 - - CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
4 - - CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
5 UTXD0 O CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
6 I2SOUT_DATA_OUT O CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
7 - - CU,CD -
3.3V: 4/8/12/16mA
MIPI_TCN 0 GPIO95 IO - - -
1 MIPI_TCN O - - -
2 - - - - -
3
4
f o r -
-
-
-
-
-
-
-
-
-
5
6
e a s e I -
-
-
R 2
-
-
-
-
-
-
-
-
l
7 - - - - -
MIPI_TCP 0
1
2
Re Pi B P
GPIO96
MIPI_TCP
-
IO
O
-
-
-
-
-
-
-
-
-
-
a
3 - - - - -
B a
MT7623N
f o r
Name
Aux.
function
e a s e I - R 2
Aux.name
Aux.
type
PU/PD/
CU/CD
Driving SMT
l P
4 - - - - -
Re Pi B
5 - - - - -
6 - - - - -
7 - - - - -
MIPI_TDN1 0
1
a n a GPIO97
MIPI_TDN1
IO
O
-
-
-
-
-
-
Ba n2
3
4
5
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
7 - - - - -
MIPI_TDP1 0 GPIO98 IO - - -
1 MIPI_TDP1 O - - -
2 - - - - -
3 - - - - -
4 - - - - -
5 - - - - -
6 - - - - -
MIPI_TDN0
7
0
f o r -
GPIO99
-
IO
-
-
-
-
-
-
e
1 MIPI_TDN0 O - - -
2
3
l e a s I - R 2 -
-
-
-
-
-
-
-
-
-
Re Pi B
4
5
6 P -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
a
7 - - - - -
MIPI_TDP0
n
0
1
a n GPIO100
MIPI_TDP0
IO
O
-
-
-
-
-
-
Ba
2 - - - - -
3 - - - - -
4 - - - - -
5 - - - - -
6 - - - - -
7 - - - - -
SPI2_CSN 0 GPIO101 IO CD - -
1 SPI2_CS O CD - -
2 - - CD - -
3 - IO CD - -
4 KROW0 IO CD - -
5 - - CD - -
r
6 - - CD - -
SPI2_MI
7
0
e f o -
GPIO102
2
-
IO
CD
CD
-
-
-
-
s
1 SPI2_MI I CD - -
2
3
l e a P I - R
SPI2_MO
-
O
IO
CD
CD
-
-
-
-
Re Pi B
4 KROW1 IO CD - -
5 - - CD - -
6 - - CD - -
a n a
n
Ba
MT7623N
f o r
Name
Aux.
function
e a s e I - R 2
Aux.name
Aux.
type
PU/PD/
CU/CD
Driving SMT
l P
7 - - CD - -
Re Pi B
SPI2_MO 0 GPIO103 IO CD - -
1 SPI2_MO O CD - -
2 SPI2_MI I CD - -
3
4
a n a KROW2
- IO
IO
CD
CD
-
-
-
-
SPI2_CK
Ba n5
6
7
0
1
-
-
-
GPIO104
SPI2_CK O
-
-
-
IO
CD
CD
CD
CD
CD
-
-
-
-
-
-
-
-
-
-
2 - - CD - -
3 - IO CD - -
4 KROW3 IO CD - -
5 - - CD - -
6 - - CD - -
7 - - CD - -
1.8V: 2/4/6/8/10/12/14/16mA
MSDC1_CMD 0 GPIO105 IO CU,CD -
3.3V: 4/8/12/16mA
r
1.8V: 2/4/6/8/10/12/14/16mA
1 MSDC1_CMD IO CU,CD -
o
3.3V: 4/8/12/16mA
2
s e f ANT_SEL0
2
O CU,CD
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
-
a R
3 SDA1 IO CU,CD -
-
3.3V: 4/8/12/16mA
4
l e
Re Pi B
5
P I -
-
-
-
CU,CD
CU,CD
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
-
a
6 I2SOUT_BCK O CU,CD -
3.3V: 4/8/12/16mA
n
7
a n DBG_MON_B[27] IO CU,CD
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
-
Ba
1.8V: 2/4/6/8/10/12/14/16mA
MSDC1_CLK 0 GPIO106 IO CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
1 MSDC1_CLK O CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
2 ANT_SEL1 O CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3 SCL1 IO CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
4 - - CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
5 - - CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
6 I2SOUT_LRCK O CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
7 DBG_MON_B[28] IO CU,CD -
3.3V: 4/8/12/16mA
MSDC1_DAT0 0
f o r GPIO107 IO CU,CD
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
-
e
1.8V: 2/4/6/8/10/12/14/16mA
1 MSDC1_DAT0 IO CU,CD -
s 2
3.3V: 4/8/12/16mA
a - R
1.8V: 2/4/6/8/10/12/14/16mA
l e I
3.3V: 4/8/12/16mA
Re Pi B
3
4 P -
-
-
-
CU,CD
CU,CD
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
-
a
5 UTXD0 O CU,CD 1.8V: 2/4/6/8/10/12/14/16mA -
Ba
MT7623N
f o r
Name
Aux.
function
e a s e I - R 2
Aux.name
Aux.
type
PU/PD/
CU/CD
Driving SMT
l
3.3V: 4/8/12/16mA
Re Pi B
6
7 P
I2SOUT_DATA_OUT
DBG_MON_B[26]
O
IO
CU,CD
CU,CD
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
-
MSDC1_DAT1 0
a n a GPIO108 IO CU,CD
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
-
n
1.8V: 2/4/6/8/10/12/14/16mA
Ba
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3 PWM0 O CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
4 - - CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
5 URXD0 I CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
6 PWM1 O CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
MSDC1_DAT2 0 GPIO109 IO CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
r
3.3V: 4/8/12/16mA
2
e f o
ANT_SEL4
2
O CU,CD
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
-
s
1.8V: 2/4/6/8/10/12/14/16mA
R
3 SDA2 IO CU,CD -
a -
3.3V: 4/8/12/16mA
4
6
l e
Re Pi B P I -
UTXD1
PWM2
-
O
CU,CD
CU,CD
CU,CD
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
-
a
3.3V: 4/8/12/16mA
n
1.8V: 2/4/6/8/10/12/14/16mA
a
3.3V: 4/8/12/16mA
MSDC1_DAT3
B
0
2
a n GPIO110
MSDC1_DAT3
ANT_SEL5
IO
IO
O
CU,CD
CU,CD
CU,CD
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
-
-
1.8V: 2/4/6/8/10/12/14/16mA
3 SCL2 IO CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
4 EXT_FRAME_SYNC I CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
5 URXD1 I CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
6 PWM3 O CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
MSDC0_DAT7 0
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
-
e
s 2
3.3V: 4/8/12/16mA
a R
1.8V: 2/4/6/8/10/12/14/16mA
-
2 - - CU,CD -
e I
3.3V: 4/8/12/16mA
3
4 l
Re Pi B P -
NLD7
-
IO
CU,CD
CU,CD
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
-
a
5 - - CU,CD 1.8V: 2/4/6/8/10/12/14/16mA -
Ba
MT7623N
f o r
Name
Aux.
function
e a s e I - R 2
Aux.name
Aux.
type
PU/PD/
CU/CD
Driving SMT
l
3.3V: 4/8/12/16mA
Re Pi B
6
7 P -
-
-
-
CU,CD
CU,CD
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
-
MSDC0_DAT6 0
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
-
n
1.8V: 2/4/6/8/10/12/14/16mA
Ba
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
2 - - CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3 - - CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
4 NLD6 IO CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
5 - - CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
6 - - CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
7 - - CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
r
3.3V: 4/8/12/16mA
2
e f o -
2
- CU,CD
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
-
s
1.8V: 2/4/6/8/10/12/14/16mA
R
3 - - CU,CD -
a -
3.3V: 4/8/12/16mA
4
6
l e
Re Pi B P I
NLD5
-
IO
-
CU,CD
CU,CD
CU,CD
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
-
a
3.3V: 4/8/12/16mA
n
1.8V: 2/4/6/8/10/12/14/16mA
a
7 - - CU,CD -
3.3V: 4/8/12/16mA
MSDC0_DAT4
B
0
2
a n GPIO114
MSDC0_DAT4
-
IO
IO
-
CU,CD
CU,CD
CU,CD
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
-
-
1.8V: 2/4/6/8/10/12/14/16mA
3 - - CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
4 NLD4 IO CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
5 - - CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
6 - - CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
7 - - CU,CD -
3.3V: 4/8/12/16mA
MSDC0_RSTB 0
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
-
e
1 MSDC0_RSTB O CU,CD -
s 2
3.3V: 4/8/12/16mA
a R
1.8V: 2/4/6/8/10/12/14/16mA
-
2 - - CU,CD -
e I
3.3V: 4/8/12/16mA
3
4 l
Re Pi B P -
NLD8
-
IO
CU,CD
CU,CD
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
-
a
5 - - CU,CD 1.8V: 2/4/6/8/10/12/14/16mA -
Ba
MT7623N
f o r
Name
Aux.
function
e a s e I - R 2
Aux.name
Aux.
type
PU/PD/
CU/CD
Driving SMT
l
3.3V: 4/8/12/16mA
Re Pi B
6
7 P -
-
-
-
CU,CD
CU,CD
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
-
MSDC0_CMD 0
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
-
n
1.8V: 2/4/6/8/10/12/14/16mA
1 MSDC0_CMD IO CU,CD -
Ba
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
2 - - CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3 - - CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
4 NALE O CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
5 - - CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
6 - - CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
7 - - CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
MSDC0_CLK 0 GPIO117 IO CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
r
1 MSDC0_CLK O CU,CD -
3.3V: 4/8/12/16mA
2
e f o -
2
- CU,CD
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
-
s
1.8V: 2/4/6/8/10/12/14/16mA
R
3 - - CU,CD -
a -
3.3V: 4/8/12/16mA
4
6
l e
Re Pi B P I
NWEB
-
O
-
CU,CD
CU,CD
CU,CD
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
-
a
3.3V: 4/8/12/16mA
n
1.8V: 2/4/6/8/10/12/14/16mA
a
7 - - CU,CD -
3.3V: 4/8/12/16mA
MSDC0_DAT3
B
0
2
a n GPIO118
MSDC0_DAT3
-
IO
IO
-
CU,CD
CU,CD
CU,CD
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
-
-
1.8V: 2/4/6/8/10/12/14/16mA
3 - - CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
4 NLD3 IO CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
5 - - CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
6 - - CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
7 - - CU,CD -
3.3V: 4/8/12/16mA
MSDC0_DAT2 0
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
-
e
s 2
3.3V: 4/8/12/16mA
a R
1.8V: 2/4/6/8/10/12/14/16mA
-
2 - - CU,CD -
e I
3.3V: 4/8/12/16mA
3
4 l
Re Pi B P -
NLD2
-
IO
CU,CD
CU,CD
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
-
a
5 - - CU,CD 1.8V: 2/4/6/8/10/12/14/16mA -
Ba
MT7623N
f o r
Name
Aux.
function
e a s e I - R 2
Aux.name
Aux.
type
PU/PD/
CU/CD
Driving SMT
l
3.3V: 4/8/12/16mA
Re Pi B
6
7 P -
-
-
-
CU,CD
CU,CD
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
-
MSDC0_DAT1 0
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
-
n
1.8V: 2/4/6/8/10/12/14/16mA
Ba
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
2 - - CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3 - - CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
4 NLD1 IO CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
5 - - CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
6 - - CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
7 - - CU,CD -
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
r
3.3V: 4/8/12/16mA
2
e f o -
2
- CU,CD
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
-
s
1.8V: 2/4/6/8/10/12/14/16mA
R
3 - - CU,CD -
a -
3.3V: 4/8/12/16mA
4
6
l e
Re Pi B P I
NLD0
WATCHDOG
-
IO
-
CU,CD
CU,CD
CU,CD
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
-
a
3.3V: 4/8/12/16mA
n
1.8V: 2/4/6/8/10/12/14/16mA
a
7 - - CU,CD -
3.3V: 4/8/12/16mA
CEC
B
0
1
2
3
4
a n GPIO122
CEC
-
-
SDA2
IO
IO
-
-
IO
CD
CD
CD
CD
CD
-
-
-
-
-
-
-
-
-
-
5 URXD0 I CD - -
6 - - CD - -
7 - - CD - -
HTPLG 0 GPIO123 IO CD - -
1 HTPLG I CD - -
2 - - CD - -
3 - - CD - -
4 SCL2 IO CD - -
5
6
f o r
UTXD0
-
O
-
CD
CD
-
-
-
-
HDMISCK
7
0
1
e a s e -
GPIO124
I -
HDMISCK
R 2
-
IO
IO
CD
CD
CD
-
-
-
-
-
-
2
3
4
l
Re Pi B P -
-
SDA1
-
-
IO
CD
CD
CD
-
-
-
-
-
-
a
5 PWM3 O CD - -
B a
MT7623N
f o r
Name
Aux.
function
e a s e I - R 2
Aux.name
Aux.
type
PU/PD/
CU/CD
Driving SMT
l P
6 - - CD - -
Re Pi B
7 - - CD - -
HDMISD 0 GPIO125 IO CD - -
1 HDMISD IO CD - -
2
3
a n a -
-
-
-
CD
CD
-
-
-
-
I2S0_MCLK
Ba n4
5
6
7
0
SCL1
PWM4
-
-
GPIO126
IO
O
-
-
IO
CD
CD
CD
CD
CU,CD
-
-
-
-
4/8/12/16mA
-
-
-
-
-
1 I2S0_MCLK IO CU,CD 4/8/12/16mA -
2 - - CU,CD 4/8/12/16mA -
3 - - CU,CD 4/8/12/16mA -
4 - - CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
6 WCN_I2S_MCLK O CU,CD 4/8/12/16mA -
SPI1_CK 0 GPIO199 IO CU,CD 2/4/6/8mA -
1
2
f o r
SPI1_CK
-
O
-
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
e
4
5
l e a s KCOL3
I --
R 2 IO
-
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
-
-
SPDIF_OUT
6
7
0
Re Pi B P
GPIO200
-
DBG_MON_B[15]
-
IO
IO
CU,CD
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
4/8/12/16mA
-
-
-
a
1 SPDIF_OUT O CU,CD 4/8/12/16mA -
n
2 - - CU,CD 4/8/12/16mA -
3
4
a n a -
-
-
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
SPDIF_IN0
B 5
6
7
0
1
URXD2
GPIO201
SPDIF_IN0
-
DBG_MON_B[16]
-
I
IO
IO
I
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
-
-
2 - - CU,CD 4/8/12/16mA -
3 - - CU,CD 4/8/12/16mA -
4 - - CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
6 UTXD2 O CU,CD 4/8/12/16mA -
r
SPDIF_IN1 0 GPIO202 IO CU,CD 4/8/12/16mA -
o
2
3
s e f -
-
2
-
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
4
5
l e a P I -
-
-
R -
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
Re Pi B
6 - - CU,CD 4/8/12/16mA -
7 - - CU,CD 4/8/12/16mA -
PWM0 0 GPIO203 IO CU,CD 4/8/12/16mA -
a n a
n
B a
MT7623N
f o r
Name
Aux.
function
e a s e I - R 2
Aux.name
Aux.
type
PU/PD/
CU/CD
Driving SMT
l P
1 PWM0 O CU,CD 4/8/12/16mA -
Re Pi B
2 DISP_PWM O CU,CD 4/8/12/16mA -
3 - - CU,CD 4/8/12/16mA -
4 - - CU,CD 4/8/12/16mA -
5
6
a n a -
-
-
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
PWM1
Ba n7
0
1
2
3
DBG_MON_B[18]
GPIO204
PWM1
CLKM3
-
IO
IO
O
O
-
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
-
-
4 - - CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
6 - - CU,CD 4/8/12/16mA -
1 PWM2 O CU,CD 4/8/12/16mA -
2 CLKM2 O CU,CD 4/8/12/16mA -
3 - - CU,CD 4/8/12/16mA -
4
5
f o r -
-
-
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
6
7
e a s e -
R
DBG_MON_B[20]
I - 2
-
IO
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
l
1
2
3
Re Pi B P
PWM3
CLKM1
EXT_FRAME_SYNC
O
O
I
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
a
4 - - CU,CD 4/8/12/16mA -
5
6
n a n -
-
-
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
PWM4
B
7
0
1
2
3
a DBG_MON_B[21]
GPIO207
PWM4
CLKM0
EXT_FRAME_SYNC
IO
IO
O
O
I
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
-
-
4 - - CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
6 - - CU,CD 4/8/12/16mA -
AUD_EXT_CK1 0 GPIO208 IO CU,CD 4/8/12/16mA -
1 AUD_EXT_CK1 I CU,CD 4/8/12/16mA -
2 PWM0 O CU,CD 4/8/12/16mA -
r
3 - - CU,CD 4/8/12/16mA -
4
5
e f o ANT_SEL5
DISP_PWM
2
O
O
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
s
6 - - CU,CD 4/8/12/16mA -
AUD_EXT_CK2
7
0
l e a P I - R
DBG_MON_A[31]
GPIO209
IO
IO
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
Re Pi B
1 AUD_EXT_CK2 I CU,CD 4/8/12/16mA -
2 MSDC1_WP I CU,CD 4/8/12/16mA -
3 - - CU,CD 4/8/12/16mA -
a n a
n
Ba
MT7623N
f o r
Name
Aux.
function
e a s e I - R 2
Aux.name
Aux.
type
PU/PD/
CU/CD
Driving SMT
l P
4 - - CU,CD 4/8/12/16mA -
Re Pi B
5 PWM1 O CU,CD 4/8/12/16mA -
6 - - CU,CD 4/8/12/16mA -
SFLASH_IO_3 0
1
a n a GPIO236
SFLASH_IO_3
IO
IO
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
Ba n2
3
4
5
6
IDDIG
-
-
-
-
I
-
-
-
-
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
-
-
SFLASH_IO_2 0 GPIO237 IO CU,CD 4/8/12/16mA -
1 SFLASH_IO_2 IO CU,CD 4/8/12/16mA -
2 DRV_VBUS O CU,CD 4/8/12/16mA -
3 - - CU,CD 4/8/12/16mA -
4 - - CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
6 - - CU,CD 4/8/12/16mA -
SFLASH_IO_1
7
0
f o r -
GPIO238
-
IO
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
e
1 SFLASH_IO_1 IO CU,CD 4/8/12/16mA -
2
3
l e a s I - R 2
IDDIG_P1
-
I
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
Re Pi B
4
5
6 P -
-
-
-
-
-
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
a
7 - - CU,CD 4/8/12/16mA -
SFLASH_IO_0
n
0
1
a n GPIO239
SFLASH_IO_0
IO
IO
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
Ba
2 DRV_VBUS_P1 O CU,CD 4/8/12/16mA -
3 - - CU,CD 4/8/12/16mA -
4 - - CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
6 - - CU,CD 4/8/12/16mA -
7 - - CU,CD 4/8/12/16mA -
SFLASH_CS_L 0 GPIO240 IO CU,CD 4/8/12/16mA -
1 SFLASH_CS_L O CU,CD 4/8/12/16mA -
2 - - CU,CD 4/8/12/16mA -
3 - - CU,CD 4/8/12/16mA -
4 - - CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
r
6 - - CU,CD 4/8/12/16mA -
SFLASH_CLK
7
0
e f o -
GPIO241
2
-
IO
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
s
1 SFLASH_CLK O CU,CD 4/8/12/16mA -
2
3
l e a P I - R -
-
-
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
Re Pi B
4 - - CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
6 - - CU,CD 4/8/12/16mA -
a n a
n
Ba
MT7623N
f o r
Name
Aux.
function
e a s e I - R 2
Aux.name
Aux.
type
PU/PD/
CU/CD
Driving SMT
l P
7 - - CU,CD 4/8/12/16mA -
Re Pi B
URTS2 0 GPIO242 IO CU,CD 4/8/12/16mA -
1 URTS2 O CU,CD 4/8/12/16mA -
2 UTXD3 O CU,CD 4/8/12/16mA -
3
4
a n a URXD3
SCL1
I
IO
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
UCTS2
Ba n5
6
7
0
1
GPIO243
UCTS2
-
-
DBG_MON_B[32]
-
-
IO
IO
I
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
-
-
2 URXD3 I CU,CD 4/8/12/16mA -
3 UTXD3 O CU,CD 4/8/12/16mA -
4 SDA1 IO CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
6 - - CU,CD 4/8/12/16mA -
GPIO244 0 GPIO244 IO CD - -
1 - - CD - -
2
3
f o r -
-
-
-
CD
CD
-
-
-
-
e
4 - - CD - -
5
6
l e a s I -
-
-
R 2 -
-
CD
CD
-
-
-
-
GPIO245
7
0
1
Re Pi B P -
GPIO245
-
-
IO
-
CD
CD
CD
-
-
-
-
-
-
a
2 - - CD - -
n
3 - - CD - -
4
5
a n a -
-
-
-
CD
CD
-
-
-
-
MHL_SENCE B 6
7
0
1
2
-
-
-
GPIO246
-
-
-
IO
-
-
CD
CD
CD
CD
CD
-
-
-
-
-
-
-
-
-
-
3 - - CD - -
4 - - CD - -
5 - - CD - -
6 - - CD - -
7 - - CD - -
GPIO247 0 GPIO247 IO CD - -
1 - - CD - -
2
3
f o r -
-
-
-
CD
CD
-
-
-
-
4
5
e a s e I -
-
-
R 2
-
-
CD
CD
-
-
-
-
GPIO248
6
7
0
1
l
Re Pi B
-
P
GPIO248
-
HDMI_TESTOUTP_RX
-
-
IO
O
CD
CD
CU,CD
CU,CD
-
-
4/8/12/16mA
4/8/12/16mA
-
-
-
-
a n a
n
B a
MT7623N
f o r
Name
Aux.
function
e a s e I - R 2
Aux.name
Aux.
type
PU/PD/
CU/CD
Driving SMT
l P
2 - - CU,CD 4/8/12/16mA -
Re Pi B
3 - - CU,CD 4/8/12/16mA -
4 - - CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
6
7
a n a -
- -
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
GPIO250
Ba n0
1
2
3
4
GPIO250
-
-
-
-
IO
IO
-
-
-
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
2/4/6/8/10/12/14/16mA
2/4/6/8/10/12/14/16mA
2/4/6/8/10/12/14/16mA
2/4/6/8/10/12/14/16mA
2/4/6/8/10/12/14/16mA
-
-
-
-
-
5 - - CU,CD 2/4/6/8/10/12/14/16mA -
6 - - CU,CD 2/4/6/8/10/12/14/16mA -
7 - - CU,CD 2/4/6/8/10/12/14/16mA -
GPIO251 0 GPIO251 IO CU,CD 2/4/6/8/10/12/14/16mA -
1 - IO CU,CD 2/4/6/8/10/12/14/16mA -
2 - - CU,CD 2/4/6/8/10/12/14/16mA -
3 - - CU,CD 2/4/6/8/10/12/14/16mA -
4 - - CU,CD 2/4/6/8/10/12/14/16mA -
5
6
f o r -
-
-
-
CU,CD
CU,CD
2/4/6/8/10/12/14/16mA
2/4/6/8/10/12/14/16mA
-
-
GPIO252
7
0
1
e a s e -
GPIO252
I
-
- R 2
-
IO
IO
CU,CD
CU,CD
CU,CD
2/4/6/8/10/12/14/16mA
2/4/6/8/10/12/14/16mA
2/4/6/8/10/12/14/16mA
-
-
-
2
3
4
l
Re Pi B P -
-
-
-
-
-
CU,CD
CU,CD
CU,CD
2/4/6/8/10/12/14/16mA
2/4/6/8/10/12/14/16mA
2/4/6/8/10/12/14/16mA
-
-
-
a
5 - - CU,CD 2/4/6/8/10/12/14/16mA -
6
7
n a n -
- -
-
CU,CD
CU,CD
2/4/6/8/10/12/14/16mA
2/4/6/8/10/12/14/16mA
-
-
a
B 1
2
3
4
5
-
-
-
-
-
IO
-
-
-
-
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
2/4/6/8/10/12/14/16mA
2/4/6/8/10/12/14/16mA
2/4/6/8/10/12/14/16mA
2/4/6/8/10/12/14/16mA
2/4/6/8/10/12/14/16mA
-
-
-
-
-
6 - - CU,CD 2/4/6/8/10/12/14/16mA -
7 - - CU,CD 2/4/6/8/10/12/14/16mA -
1 - IO CU,CD 2/4/6/8/10/12/14/16mA -
2 - - CU,CD 2/4/6/8/10/12/14/16mA -
3 - - CU,CD 2/4/6/8/10/12/14/16mA -
r
4 - - CU,CD 2/4/6/8/10/12/14/16mA -
5
6
e f o 2
-
-
-
-
CU,CD
CU,CD
2/4/6/8/10/12/14/16mA
2/4/6/8/10/12/14/16mA
-
-
s
7 - - CU,CD 2/4/6/8/10/12/14/16mA -
GPIO255 0
1
l e a P I - R
GPIO255
-
IO
IO
CU,CD
CU,CD
2/4/6/8/10/12/14/16mA
2/4/6/8/10/12/14/16mA
-
-
Re Pi B
2 - - CU,CD 2/4/6/8/10/12/14/16mA -
3 - - CU,CD 2/4/6/8/10/12/14/16mA -
4 - - CU,CD 2/4/6/8/10/12/14/16mA -
a n a
n
Ba
MT7623N
f o r
Name
Aux.
function
e a s e I - R 2
Aux.name
Aux.
type
PU/PD/
CU/CD
Driving SMT
l P
5 - - CU,CD 2/4/6/8/10/12/14/16mA -
Re Pi B
6 - - CU,CD 2/4/6/8/10/12/14/16mA -
7 - - CU,CD 2/4/6/8/10/12/14/16mA -
1
2
a n a -
-
IO
-
CU,CD
CU,CD
2/4/6/8/10/12/14/16mA
2/4/6/8/10/12/14/16mA
-
-
Ba n3
4
5
6
7 -
-
-
-
-
-
-
-
-
-
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
2/4/6/8/10/12/14/16mA
2/4/6/8/10/12/14/16mA
2/4/6/8/10/12/14/16mA
2/4/6/8/10/12/14/16mA
2/4/6/8/10/12/14/16mA
-
-
-
-
-
1 - IO CU,CD 2/4/6/8/10/12/14/16mA -
2 - - CU,CD 2/4/6/8/10/12/14/16mA -
3 - - CU,CD 2/4/6/8/10/12/14/16mA -
4 - - CU,CD 2/4/6/8/10/12/14/16mA -
5 - - CU,CD 2/4/6/8/10/12/14/16mA -
6 - - CU,CD 2/4/6/8/10/12/14/16mA -
7 - - CU,CD 2/4/6/8/10/12/14/16mA -
GE2_TXEN 0
1
f o r GPIO262
GE2_TXEN
IO
IO
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
e
2 - - CU,CD 4/8/12/16mA -
3
4
l e a s I - R 2 -
-
-
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
Re Pi B
5
6
7 P -
-
-
-
-
-
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
a
GE2_TXD3 0 GPIO263 IO CU,CD 4/8/12/16mA -
n
1 GE2_TXD3 IO CU,CD 4/8/12/16mA -
n
2
a - - CU,CD 4/8/12/16mA -
Ba
3 - - CU,CD 4/8/12/16mA -
4 - - CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
7 - - CU,CD 4/8/12/16mA -
1 GE2_TXD2 IO CU,CD 4/8/12/16mA -
2 - - CU,CD 4/8/12/16mA -
3 - - CU,CD 4/8/12/16mA -
4 - - CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
r
7 - - CU,CD 4/8/12/16mA -
o
1
2
s e f GE2_TXD1
2
-
IO
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
3
4
l e a P I - R -
-
-
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
Re Pi B
5 - - CU,CD 4/8/12/16mA -
7 - - CU,CD 4/8/12/16mA -
a n a
n
Ba
MT7623N
f o r
Name
Aux.
function
e a s e I - R 2
Aux.name
Aux.
type
PU/PD/
CU/CD
Driving SMT
l
Re Pi B
1
2
3
P GE2_TXD0
-
-
IO
-
-
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
4
5
a n a -
-
-
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
GE2_TXCLK
Ba n6
7
0
1
2
ANT_SEL2
-
GPIO267
GE2_TXCLK
-
O
-
IO
IO
-
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
-
-
3 - - CU,CD 4/8/12/16mA -
4 - - CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
6 - - CU,CD 4/8/12/16mA -
7 - - CU,CD 4/8/12/16mA -
GE2_RXCLK 0 GPIO268 IO CU,CD 4/8/12/16mA -
1 GE2_RXCLK IO CU,CD 4/8/12/16mA -
2 - - CU,CD 4/8/12/16mA -
3
4
f o r -
-
-
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
e
5 - - CU,CD 4/8/12/16mA -
6
7
l e a s I
-
-
-
R 2 -
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
GE2_RXD0 0
1
2
Re Pi B P
GPIO269
GE2_RXD0
-
IO
IO
-
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
a
3 - - CU,CD 4/8/12/16mA -
n
4 - - CU,CD 4/8/12/16mA -
5
6
a n a -
-
-
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
GE2_RXD1
B 7
0
1
2
3
-
GPIO270
GE2_RXD1
-
-
-
IO
IO
-
-
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
-
-
4 - - CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
6 - - CU,CD 4/8/12/16mA -
7 - - CU,CD 4/8/12/16mA -
GE2_RXD2 0 GPIO271 IO CU,CD 4/8/12/16mA -
1 GE2_RXD2 IO CU,CD 4/8/12/16mA -
2 - - CU,CD 4/8/12/16mA -
3
4
f o r -
-
-
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
5
6
e a s e I -
-
-
R 2
-
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
GE2_RXD3
7
0
1
2
l
Re Pi B P
-
GPIO272
GE2_RXD3
-
-
IO
IO
-
CU,CD
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
-
a n a
n
B a
MT7623N
f o r
Name
Aux.
function
e a s e I - R 2
Aux.name
Aux.
type
PU/PD/
CU/CD
Driving SMT
l P
3 - - CU,CD 4/8/12/16mA -
Re Pi B
4 - - CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
6 - - CU,CD 4/8/12/16mA -
GE2_RXDV
7
0
a n a -
GPIO274
-
IO
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
Ba n1
2
3
4
5
GE2_RXDV
-
-
-
-
IO
-
-
-
-
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
-
-
6 - - CU,CD 4/8/12/16mA -
7 - - CU,CD 4/8/12/16mA -
MDC 0 GPIO275 IO CU,CD 4/8/12/16mA -
1 MDC O CU,CD 4/8/12/16mA -
2 - - CU,CD 4/8/12/16mA -
3 - - CU,CD 4/8/12/16mA -
4 - - CU,CD 4/8/12/16mA -
5 - - CU,CD 4/8/12/16mA -
6
7
f o-
r
ANT_SEL0 O
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
e
MDIO 0 GPIO276 IO CU,CD 4/8/12/16mA -
1
2
l e a s MDIO
I - R 2
-
IO
-
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
-
-
3
4
5
Re Pi B P -
-
-
-
-
-
CU,CD
CU,CD
CU,CD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
-
-
-
a
JTAG_RESET
7
0
n a n -
GPIO278
-
IO
CU,CD
CU,CD
4/8/12/16mA
2/4/6/8mA
-
-
a
1 JTAG_RESET I CU,CD 2/4/6/8mA -
B 2
3
4
5
6
-
-
-
-
-
-
-
-
-
-
CU,CD
CU,CD
CU,CD
CU,CD
CU,CD
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
2/4/6/8mA
-
-
-
-
-
7 - - CU,CD 2/4/6/8mA -
Below table shows the reset status of GPIOs.
Table 1-2. Reset Status of GPIOs
Name
f o r
Reset
Output drivability
Termination
when not IO type
e
State Aux PU/PD used
SYSRSTB I
l e a s I
-
- R 2 PU - No need IO type 1
P
WATCHDOG OH 1 PD 2/4/6/8mA No need IO type 2
Re Pi B
TESTMODE I - PD - No need IO type 1
RTC32K_CK I 1 PD 2/4/6/8mA No need IO type 2
a n a
n
B a
MT7623N
f o r
SRCLKENAI
e a
I
s e I - R 2 1 PD 2/4/6/8mA No need IO type 2
l
SRCLKENA OH 1 PU 2/4/6/8mA No need IO type 2
PWRAP_SPI0_MO
PWRAP_SPI0_MI
Re Pi B
OL
OL P 1
1
PD
PD
2/4/6/8mA
2/4/6/8mA
No need
No need
IO type 2
IO type 2
a
PWRAP_SPI0_CSN OH 1 PU 2/4/6/8mA No need IO type 2
PWRAP_SPI0_CK
n a n OL 1 PD 2/4/6/8mA No need IO type 2
Ba
PWRAP_SPI0_CK2 OL 1 PD 2/4/6/8mA No need IO type 2
PWRAP_SPI0_CSN2 OH 1 PU 2/4/6/8mA No need IO type 2

PWRAP_INT I 0 PD 2/4/6/8mA No need IO type 2
JTMS I 1 PU 2/4/6/8mA No need IO type 2
JTCK I 1 PU 2/4/6/8mA No need IO type 2

JTDI I 1 PU 2/4/6/8mA No need IO type 2
JTDO OL 1 PU 2/4/6/8mA No need IO type 2
JTAG_RESET I 0 PU 2/4/6/8mA No need IO type 2

DSI_TE I 0 PD 2/4/6/8mA No need IO type 2
r
LCM_RST I 0 PD 2/4/6/8mA No need IO type 2
I2S0_DATA
I2S0_DATA_IN
OL
I
e f o 1
1
2
PD
PD
4/8/12/16mA
4/8/12/16mA
No need
No need
IO type 2
IO type 2
I2S0_LRCK OH
l e a s I -
1
R PD 4/8/12/16mA No need IO type 2
Re Pi B P
I2S0_MCLK OL 1 PD 4/8/12/16mA No need IO type 2
I2S0_BCK OH 1 PD 4/8/12/16mA No need IO type 2
I2S1_DATA OL 1 PD 4/8/12/16mA No need IO type 2
I2S1_DATA_IN
a
I
n a 1 PD 4/8/12/16mA No need IO type 2
n
I2S1_LRCK OH 1 PD 4/8/12/16mA No need IO type 2
I2S1_MCLK
I2S1_BCK
PCM_CLK B a OL
OH
I
1
1
0
PD
PD
PD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
No need
No need
No need
IO type 2
IO type 2
IO type 2
PCM_SYNC I 0 PD 4/8/12/16mA No need IO type 2
PCM_RX I 0 PD 4/8/12/16mA No need IO type 2
PCM_TX I 0 PD 4/8/12/16mA No need IO type 2
EINT0 I 0 PD 4/8/12/16mA No need IO type 2

EINT3
EINT4
I
I
f o r0
0
PD
PD
4/8/12/16mA
4/8/12/16mA
No need
No need
IO type 2
IO type 2
EINT5 I
e a s e I
0
- R 2 PD 4/8/12/16mA No need IO type 2
l
EINT7
URXD0
Re Pi B
I
I P 1
1
PD
-
4/8/12/16mA
-
No need
No need
IO type 2
IO type 2
a
UTXD0 OH 1 - - No need IO type 2
B a
MT7623N
f o r
URXD1
e a
I
s e I - R 2 0 PD - No need IO type 2
l
UTXD1 I 0 PD - No need IO type 2
URXD2
UTXD2
Re Pi B
I
I P 0
0
PD
PD
-
-
No need
No need
IO type 2
IO type 2
a
URTS2 I 0 PD 4/8/12/16mA No need IO type 2
UCTS2
n a n I 0 PD 4/8/12/16mA No need IO type 2
Ba
SPI0_CSN I 0 PD 4/8/12/16mA No need IO type 2
SPI0_CK I 0 PD 4/8/12/16mA No need IO type 2

SPI0_MI I 0 PD 4/8/12/16mA No need IO type 2
SPI0_MO I 0 PD 4/8/12/16mA No need IO type 2
SPI1_CSN I 0 PD 2/4/6/8mA No need IO type 2

SPI1_CK I 0 PD 2/4/6/8mA No need IO type 2
SPI1_MI I 0 PD 2/4/6/8mA No need IO type 2
SPI1_MO I 0 PD 2/4/6/8mA No need IO type 2

SPI2_CSN I 0 PD - No need IO type 2
r
SPI2_CK I 0 PD - No need IO type 2
SPI2_MI
SPI2_MO
I
I
e f o 0
0
2
PD
PD
-
-
No need
No need
IO type 2
IO type 2
MSDC0_DAT7 I
l e a s I -
1
R PU
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
GND IO type 2
Re Pi B P
1.8V: 2/4/6/8/10/12/14/16mA
MSDC0_DAT6 I 1 PU GND IO type 2
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
a
1.8V: 2/4/6/8/10/12/14/16mA
n
3.3V: 4/8/12/16mA
MSDC0_RSTB
a n a
OH 1 PU
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
No need IO type 2
B
MSDC0_CMD I 1 PU GND IO type 2
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
MSDC0_CLK OL 1 PD GND IO type 2
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
MSDC1_CMD I 1 PU No need IO type 2
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
r
MSDC1_CLK OL 1 PD No need IO type 2
3.3V: 4/8/12/16mA
MSDC1_DAT0 I
e f o 1
2
PU
1.8V: 2/4/6/8/10/12/14/16mA
3.3V: 4/8/12/16mA
No need IO type 2
s
1.8V: 2/4/6/8/10/12/14/16mA
MSDC1_DAT1 I 1 PU No need IO type 2
a R
3.3V: 4/8/12/16mA
MSDC1_DAT2 I
l e P I -
1 PU
1.8V: 2/4/6/8/10/12/14/16mA
No need IO type 2
Re Pi B
3.3V: 4/8/12/16mA
1.8V: 2/4/6/8/10/12/14/16mA
MSDC1_DAT3 I 1 PU No need IO type 2
3.3V: 4/8/12/16mA
GPIO250 I 1 PU 2/4/6/8/10/12/14/16mA GND IO type 2
a n a
n
B a
MT7623N
f o r
GPIO251
e a
I
s e I - R 2 1 PU 2/4/6/8/10/12/14/16mA GND IO type 2
l
GPIO253
GPIO254
Re Pi B
I
I P 1
1
PU
PU
2/4/6/8/10/12/14/16mA
2/4/6/8/10/12/14/16mA
GND
GND
IO type 2
IO type 2
a
GPIO256
n a n I 1 PU 2/4/6/8/10/12/14/16mA GND IO type 2
Ba
GPIO61 I - PD 2/4/6/8mA No need IO type 2

GPIO62 I - PD 2/4/6/8mA No need IO type 2
WB_SCLK I - PD 2/4/6/8mA No need IO type 2
WB_SDATA I - PD 2/4/6/8mA No need IO type 2

WB_SEN I - PD 2/4/6/8mA No need IO type 2
WB_CTRL0 I - PD 2/4/6/8mA No need IO type 2

r
WB_CTRL4
WB_CTRL5
I
I
e f o -
-
2
PD
PD
2/4/6/8mA
2/4/6/8mA
No need
No need
IO type 2
IO type 2
WB_RSTB I
l e a s I -
-
P
Floating
Re Pi B
SDA0 I 1 - - No need
Well
Floating
SCL0 I 1 - - No need
Well
Floating
a
Well
SCL1
n aI
n 1 - - No need
Floating
Well
a
Floating
B
Well
Floating
SCL2 I 1 - - No need
Well
Floating
CEC I 1 - - No need
Well
Floating
HTPLG I 1 - - No need
Well
Floating
HDMISCK I 1 - - No need
Well
Floating
HDMISD I 1 - - No need
Well
Floating
GPIO244 I 1 - - No need
Well
Floating
GPIO245 I 1 - - No need
r
Well
o
Floating
f
MHL_SENCE I 0 - - No need
Well
GPIO247
GPIO248
I
OL
e a s e I
1
-
1
R 2 -
-
-
-
No need
No need
Floating
Well
IO type 2
MIPI_TDP0
MIPI_TDN0
I
Il
Re Pi B P 1
1
-
-
-
-
No need
No need
MIPI
MIPI
a
MIPI_TDP1 I 1 - - No need MIPI
B a
MT7623N
f o r
MIPI_TDN1
e a
I
s e I - R 2 1 - - No need MIPI
l
MIPI_TCP I 1 - - No need MIPI
MIPI_TCN
NCLE
Re Pi B
I
I P 1
0 PD
- -
4/8/12/16mA
No need
No need
MIPI
IO type 2
a
NCEB1 I 0 PU 4/8/12/16mA No need IO type 2
NCEB0
n a n I 0 PU 4/8/12/16mA No need IO type 2
Ba
NREB I 0 PD 4/8/12/16mA No need IO type 2
NRNB I 0 PU 4/8/12/16mA No need IO type 2

PWM0 I 0 PD 4/8/12/16mA No need IO type 2

IR I 0 PD - No need IO type 1
SPDIF_OUT I 0 PD 4/8/12/16mA No need IO type 2
r
SPDIF_IN0 I 0 PD 4/8/12/16mA No need IO type 2
SPDIF_IN1
SFLASH_IO_3
I
I
e f o 0
0
2
PD
PD
4/8/12/16mA
4/8/12/16mA
No need
No need
IO type 2
IO type 2
SFLASH_IO_2 I
l e a s I -
0
Re Pi B P
SFLASH_IO_1 I 0 PD 4/8/12/16mA No need IO type 2
SFLASH_IO_0 I 0 PD 4/8/12/16mA No need IO type 2
SFLASH_CS_L I 0 PD 4/8/12/16mA No need IO type 2
SFLASH_CLK
a
I
n a 0 PD 4/8/12/16mA No need IO type 2
n
GE2_TXD3 I 0 PD 4/8/12/16mA No need IO type 2
GE2_TXD2
GE2_TXD1
GE2_TXD0 B a I
I
I
0
0
0
PD
PD
PD
4/8/12/16mA
4/8/12/16mA
4/8/12/16mA
No need
No need
No need
IO type 2
IO type 2
IO type 2
GE2_RXD3 I 0 PD 4/8/12/16mA No need IO type 2
GE2_TXCLK I 0 PD 4/8/12/16mA No need IO type 2

GE2_RXCLK I 0 PD 4/8/12/16mA No need IO type 2
GE2_RXDV
GE2_TXEN
I
I
f o r0
0
PD
PD
4/8/12/16mA
4/8/12/16mA
No need
No need
IO type 2
IO type 2
MDC I
e a s e I
0
- R 2 PD 4/8/12/16mA No need IO type 2
l
MDIO I 0 PD 4/8/12/16mA No need IO type 2
AUD_EXT_CK1
AUD_EXT_CK2
Re Pi B
I
I P 1
1
PD
PD
4/8/12/16mA
4/8/12/16mA
No need
No need
IO type 2
IO type 2
a n a
n
B a
MT7623N
f o r
e a s e I - R 2
Below table shows the driving control register name and steps.
l
Re Pi B P
Table 1-3: Driving and pull control of GPIOs
a
Mode IES/ Pull Pull Pu PuPd/ Driving
n
Name OCTL Pull_en Pull_sel Driving step
0 type init Pd R1/R0 register
a
SMT
PWRAP_S
PI0_MI
PWRAP_S
PI0_MO
GPIO0
GPIO1
IES0
SMT0
IES0
Ba
pwrap_c
onf[3:0]
pwrap_c
onf[3:0]
n PU/P
D
PU/P
D
PD
PD
0x10005
150[0]
0x10005
150[1]
0x10005
280[0]
0x10005
280[1]
-
-
-
-
0x10005F5
0[3:0]
0x10005F5
0[3:0]
0x00000000,0x00000002,0x000000
04,0x00000006
0x00000000,0x00000002,0x000000
04,0x00000006
SMT0
PWRAP_I IES0 pwrap_c PU/P 0x10005 0x10005 0x10005F5 0x00000000,0x00000002,0x000000

GPIO2 PD - -
NT onf[3:0] D 150[2] 280[2] 0[3:0] 04,0x00000006
SMT0
IES0
PWRAP_S pwrap_c PU/P 0x10005 0x10005 0x10005F5 0x00000000,0x00000002,0x000000
GPIO3 PD - -
PI0_CK onf[3:0] D 150[3] 280[3] 0[3:0] 04,0x00000006
SMT0
IES0
PWRAP_S pwrap_c PU/P 0x10005 0x10005 0x10005F5 0x00000000,0x00000002,0x000000
GPIO4 PU - -
PI0_CSN onf[3:0] D 150[4] 280[4] 0[3:0] 04,0x00000006
r
SMT0
PWRAP_S
PI0_CK2
GPIO5
IES0
pwrap_c
onf[3:0]
PU/P
D
e f o
PD
2
0x10005
150[5]
0x10005
280[5]
- -
0x10005F5
0[3:0]
0x00000000,0x00000002,0x000000
04,0x00000006
s
SMT0
PWRAP_S
GPIO6
IES0
pwrap_c
l e a
PU/P
P I
PU
- R 0x10005 0x10005
- -
0x10005F5 0x00000000,0x00000002,0x000000
Re Pi B
PI0_CSN2 SMT0 onf[3:0] D 150[6] 280[6] 0[3:0] 04,0x00000006
IES1
spi1_con PU/P 0x10005 0x10005 0x10005F5 0x00000000,0x00000020,0x000000
SPI1_CSN GPIO7 PD - -
f[3:0] D 150[7] 280[7] 0[7:4] 40,0x00000060
a
SMT1
SPI1_MI GPIO8
IES1
spi1_con
f[3:0]
n a nPU/P
D
PD
0x10005
150[8]
0x10005
280[8]
- -
0x10005F5
0[7:4]
0x00000000,0x00000020,0x000000
40,0x00000060
Ba
SMT1
IES1
spi1_con PU/P 0x10005 0x10005 0x10005F5 0x00000000,0x00000020,0x000000
SPI1_MO GPIO9 PD - -
f[3:0] D 150[9] 280[9] 0[7:4] 40,0x00000060
SMT1
IES2
RTC32K_C GPIO1 pm_conf[ PU/P 0x10005 0x10005 0x10005F5 0x00000000,0x00000200,0x000004
PD - -
K 0 3:0] D 150[10] 280[10] 0[11:8] 00,0x00000600
SMT2
IES2
WATCHDO GPIO1 pm_conf[ PU/P 0x10005 0x10005 0x10005F5 0x00000000,0x00000200,0x000004
PU - -
G 1 3:0] D 150[11] 280[11] 0[11:8] 00,0x00000600
SMT2
IES2
SRCLKEN GPIO1 pm_conf[ PU/P 0x10005 0x10005 0x10005F5 0x00000000,0x00000200,0x000004
PU - -
A 2 3:0] D 150[12] 280[12] 0[11:8] 00,0x00000600
SMT2
SRCLKEN
AI
GPIO1
3
IES2
SMT2
pm_conf[
3:0]
PU/P
D
f o
PD
r 0x10005
150[13]
0x10005
280[13]
- -
0x10005F5
0[11:8]
0x00000000,0x00000200,0x000004
00,0x00000600
URXD2
GPIO1
4
IES3
uart2_co
nf[3:0]
e
D
a
PU/P
s e PD
I - R 20x10005
150[14]
0x10005
280[14]
- -
0x10005F5
0[15:12]
0x00000000,0x00002000,0x000040
00,0x00006000
l
SMT3
UTXD2
GPIO1
5
IES3
SMT3
uart2_co
nf[3:0]
Re Pi B
PU/P
D
PPD
0x10005
150[15]
0x10005
280[15]
- -
0x10005F5
0[15:12]
0x00000000,0x00002000,0x000040
00,0x00006000
a n a
n
Ba
MT7623N
f o r
SMT4
e a s e I - R 2
l
IES5
P
GPIO1 pcm_con PU/P 0x10005 0x10005 0x10005F6 0x00000000,0x00000020,0x000000
Re Pi B
PCM_CLK PD - -
8 f[3:0] D 160[2] 290[2] 0[7:4] 40,0x00000060
SMT5
IES5
PCM_SYN GPIO1 pcm_con PU/P 0x10005 0x10005 0x10005F6 0x00000000,0x00000020,0x000000
PD - -
a
C 9 f[3:0] D 160[3] 290[3] 0[7:4] 40,0x00000060
SMT5
PCM_RX
GPIO2
IES5
pcm_con
n a nPU/P
PD
0x10005 0x10005
- -
0x10005F6 0x00000000,0x00000020,0x000000
Ba
0 f[3:0] D 160[4] 290[4] 0[7:4] 40,0x00000060
SMT5
IES5
GPIO2 pcm_con PU/P 0x10005 0x10005 0x10005F6 0x00000000,0x00000020,0x000000
PCM_TX PD - -
1 f[3:0] D 160[5] 290[5] 0[7:4] 40,0x00000060
SMT5
IES6
GPIO2 eint0_co PU/P 0x10005 0x10005 0x10005F6 0x00000000,0x00000200,0x000004
EINT0 PD - -
2 nf[3:0] D 160[6] 290[6] 0[11:8] 00,0x00000600
SMT6
IES6
EINT1 PD - -
3 SMT6 nf[3:0] D 160[7] 290[7] 0[11:8] 00,0x00000600
IES6
EINT2 PD - -
4 SMT6 nf[3:0] D 160[8] 290[8] 0[11:8] 00,0x00000600
EINT3
GPIO2
5
IES6
eint0_co
nf[3:0]
PU/P
D
f o
PD
r 0x10005
160[9]
0x10005
290[9]
- -
0x10005F6
0[11:8]
0x00000000,0x00000200,0x000004
00,0x00000600
e
SMT6
EINT4
GPIO2
6
IES6
SMT6
eint0_co
nf[3:0]
l e
D
a
PU/P
s I
PD
- R 20x10005
160[10]
0x10005
290[10]
- -
0x10005F6
0[11:8]
0x00000000,0x00000200,0x000004
00,0x00000600
EINT5
GPIO2
7
IES7
SMT7
eint5_co
nf[3:0]
Re Pi B
PU/P
D PPD
0x10005
160[11]
0x10005
290[11]
- -
0x10005F6
0[15:12]
0x00000000,0x00002000,0x000040
00,0x00006000
EINT6
GPIO2
8
IES7
SMT7
eint5_co
nf[3:0]
a n a
PU/P
D
PD
0x10005
160[12]
0x10005
290[12]
- -
0x10005F6
0[15:12]
0x00000000,0x00002000,0x000040
00,0x00006000
EINT7
I2S1_DAT
GPIO2
9
GPIO3
IES7
SMT7
IES8 Ba
eint5_co
nf[3:0]
i2s1_con
n PU/P
D
PU/P
PD
0x10005
160[13]
0x10005
0x10005
290[13]
0x10005
- -
0x10005F6
0[15:12]
0x10005F7
0x00000000,0x00002000,0x000040
00,0x00006000
0x00000000,0x00000002,0x000000
PD - -
A 3 f[3:0] D 170[1] 2A0[1] 0[3:0] 04,0x00000006
SMT8
IES8
I2S1_DAT GPIO3 i2s1_con PU/P 0x10005 0x10005 0x10005F7 0x00000000,0x00000002,0x000000
PD - -
A_IN 4 f[3:0] D 170[2] 2A0[2] 0[3:0] 04,0x00000006
SMT8
IES8
GPIO3 i2s1_con PU/P 0x10005 0x10005 0x10005F7 0x00000000,0x00000002,0x000000
I2S1_BCK PD - -
5 f[3:0] D 170[3] 2A0[3] 0[3:0] 04,0x00000006
SMT8
IES8
I2S1_LRC GPIO3 i2s1_con PU/P 0x10005 0x10005 0x10005F7 0x00000000,0x00000002,0x000000
r
PD - -
K 6 f[3:0] D 170[4] 2A0[4] 0[3:0] 04,0x00000006
o
SMT8
I2S1_MCL
K
GPIO3
7
IES8
i2s1_con
f[3:0]
PU/P
D
s e f PD
2
0x10005
170[5]
0x10005
2A0[5]
- -
0x10005F7
0[3:0]
0x00000000,0x00000002,0x000000
04,0x00000006
a R
SMT8
IES9
l e P I -
Re Pi B
GPIO3 jtag_conf PU/P 0x10005 0x10005 0x10005F7 0x00000000,0x00000200,0x000004
JTMS PU - -
9 [3:0] D 170[7] 2A0[7] 0[11:8] 00,0x00000600
SMT9
JTCK GPIO4 IES9 jtag_conf PU/P PU 0x10005 0x10005 - - 0x10005F7 0x00000000,0x00000200,0x000004
a n a
n
Ba
MT7623N
f o r
0 SMT9 [3:0] D
e a s e I - R 2
170[8] 2A0[8] 0[11:8] 00,0x00000600
l
IES9
P
Re Pi B
JTDI PU - -
1 SMT9 [3:0] D 170[9] 2A0[9] 0[11:8] 00,0x00000600
IES9
JTDO PU - -
a
2 SMT9 [3:0] D 170[10] 2A0[10] 0[11:8] 00,0x00000600
NCLE
GPIO4
IES10
eint12_c
n a n
PU/P
PD
0x10005 0x10005
- -
0x10005F7 0x00000000,0x00002000,0x000040
Ba
3 onf[3:0] D 170[11] 2A0[11] 0[15:12] 00,0x00006000
SMT10
IES10
GPIO4 eint12_c PU/P 0x10005 0x10005 0x10005F7 0x00000000,0x00002000,0x000040
NCEB1 PU - -
4 SMT10 onf[3:0] D 170[12] 2A0[12] 0[15:12] 00,0x00006000
IES10
NCEB0 PU - -
5 SMT10 onf[3:0] D 170[13] 2A0[13] 0[15:12] 00,0x00006000
1'b1
GPIO4 PU/P 0x10005 0x10005
IR - PD - - - -
6 D 170[14] 2A0[14]
1'b0
IES11
NREB PD - -
7 onf[3:0] D 170[15] 2A0[15] 0[3:0] 04,0x00000006
SMT11
NRNB
GPIO4
8
IES11
eint17_c
onf[3:0]
PU/P
D
f
PU
o r 0x10005
180[0]
0x10005
2B0[0]
- -
0x10005F8
0[3:0]
0x00000000,0x00000002,0x000000
04,0x00000006
e
SMT11
I2S0_DAT
A
GPIO4
9
IES12
SMT12
i2s0_con
f[3:0]
PU/P
D
l e a s PD
I - R 2
0x10005
180[1]
0x10005
2B0[1]
- -
0x10005F8
0[7:4]
0x00000000,0x00000020,0x000000
40,0x00000060
SPI0_CSN
GPIO5
3
IES14
SMT14
spi0_con
f[3:0]
Re Pi B
PU/P
D
PD
P 0x10005
180[5]
0x10005
2B0[5]
- -
0x10005F8
0[15:12]
0x00000000,0x00002000,0x000040
00,0x00006000
SPI0_CK
GPIO5
4
IES14
SMT14
spi0_con
f[3:0] D
n
PU/P
a a PD
0x10005
180[6]
0x10005
2B0[6]
- -
0x10005F8
0[15:12]
0x00000000,0x00002000,0x000040
00,0x00006000
SPI0_MI
GPIO5
5
GPIO5
IES14
SMT14
IES14
spi0_con
f[3:0]
spi0_con
Ba n PU/P
D
PU/P
PD
0x10005
180[7]
0x10005
0x10005
2B0[7]
0x10005
- -
0x10005F8
0[15:12]
0x10005F8
0x00000000,0x00002000,0x000040
00,0x00006000
0x00000000,0x00002000,0x000040
SPI0_MO PD - -
6 SMT14 f[3:0] D 180[8] 2B0[8] 0[15:12] 00,0x00006000
IES15
GPIO5 0x10005 0x10005
SDA1 - PD - - - - -
7 180[9] 2B0[9]
SMT15
IES15
GPIO5 0x10005 0x10005
SCL1 - PD - - - - -
8 180[10] 2B0[10]
SMT15
IES16
GPIO6 fm_conf[ PU/P 0x10005 0x10005 0x10005F9 0x00000000,0x00000200,0x000004
r
WB_RSTB PD - -
0 3:0] D 180[12] 2B0[12] 0[11:8] 00,0x00000600
o
SMT16
GPIO61
GPIO6
1
IES16
fm_conf[
3:0]
PU/P
D
s e f
PD
2
0x10005
180[13]
0x10005
2B0[13]
- -
0x10005F9
0[11:8]
0x00000000,0x00000200,0x000004
00,0x00000600
a R
SMT16
IES16
l e P I -
Re Pi B
GPIO6 fm_conf[ PU/P 0x10005 0x10005 0x10005F9 0x00000000,0x00000200,0x000004
GPIO62 PD - -
2 SMT16 3:0] D 180[14] 2B0[14] 0[11:8] 00,0x00000600
WB_SCLK GPIO6 IES17 wbspi_co PU/P PD 0x10005 0x10005 - - 0x10005F9 0x00000000,0x00002000,0x000040
a n a
n
Ba
MT7623N
f o r
3 SMT17 nf[3:0] D
e a s e I - R 2
180[15] 2B0[15] 0[15:12] 00,0x00006000
l
IES17
P
WB_SDAT GPIO6 wbspi_co PU/P 0x10005 0x10005 0x10005F9 0x00000000,0x00002000,0x000040
Re Pi B
PD - -
A 4 nf[3:0] D 190[0] 2C0[0] 0[15:12] 00,0x00006000
SMT17
IES17
GPIO6 wbspi_co PU/P 0x10005 0x10005 0x10005F9 0x00000000,0x00002000,0x000040
WB_SEN PD - -
a
5 nf[3:0] D 190[1] 2C0[1] 0[15:12] 00,0x00006000
SMT17
WB_CTRL GPIO6
IES18
wb_conf[
n a n
PU/P
PD
0x10005 0x10005
- -
0x10005FA 0x00000000,0x00000002,0x000000
Ba
0 6 3:0] D 190[2] 2C0[2] 0[3:0] 04,0x00000006
SMT18
IES18
WB_CTRL GPIO6 wb_conf[ PU/P 0x10005 0x10005 0x10005FA 0x00000000,0x00000002,0x000000
PD - -
1 7 SMT18 3:0] D 190[3] 2C0[3] 0[3:0] 04,0x00000006
IES18
PD - -
2 8 SMT18 3:0] D 190[4] 2C0[4] 0[3:0] 04,0x00000006
IES18
PD - -
3 9 SMT18 3:0] D 190[5] 2C0[5] 0[3:0] 04,0x00000006
IES18
PD - -
4 0 SMT18 3:0] D 190[6] 2C0[6] 0[3:0] 04,0x00000006
WB_CTRL
5
GPIO7
1
IES18
SMT18
wb_conf[
3:0]
PU/P
D
f
PD
o r 0x10005
190[7]
0x10005
2C0[7]
- -
0x10005FA
0[3:0]
0x00000000,0x00000002,0x000000
04,0x00000006
I2S0_DAT
A_IN
GPIO7
2
IES12
i2s0_con
f[3:0]
PU/P
D
e a s ePD
I - R 2
0x10005
190[8]
0x10005
2C0[8]
- -
0x10005F8
0[7:4]
0x00000000,0x00000020,0x000000
40,0x00000060
l
SMT12
I2S0_LRC
K
GPIO7
3
IES12
SMT12
i2s0_con
f[3:0]
Re Pi B
PU/P
D
PD
P 0x10005
190[9]
0x10005
2C0[9]
- -
0x10005F8
0[7:4]
0x00000000,0x00000020,0x000000
40,0x00000060
I2S0_BCK
GPIO7
4
IES12
SMT12
i2s0_con
f[3:0]
a
D
n
PU/P
a PD
0x10005
190[10]
0x10005
2C0[10]
- -
0x10005F8
0[7:4]
0x00000000,0x00000020,0x000000
40,0x00000060
SDA0
GPIO7
5
GPIO7
IES19
SMT19
IES19
-
Ba n PD -
0x10005
190[11]
0x10005
0x10005
2C0[11]
0x10005
- - - -
SCL0 - PD - - - - -
6 SMT19 190[12] 2C0[12]
IES20
GPIO7 0x10005 0x10005
SDA2 - PD - - - - -
7 190[13] 2C0[13]
SMT20
IES20
GPIO7 0x10005 0x10005
SCL2 - PD - - - - -
8 190[14] 2C0[14]
SMT20
IES21
GPIO7 0x10005 0x10005
r
URXD0 - PD - - - - -
9 190[15] 2C0[15]
o
SMT21
UTXD0
GPIO8
0
IES21
- PD
s e f
-
0x10005
2
1A0[0]
0x10005
2D0[0]
- - - -
a R
SMT21
GPIO8
IES21
l e P I - 0x10005 0x10005
Re Pi B
URXD1 - PD - - - - -
1 SMT21 1A0[1] 2D0[1]
UTXD1 GPIO8 IES21 - PD - 0x10005 0x10005 - - - -
a n a
n
Ba
MT7623N
f o r
2 SMT21
e a s e I - R 2
1A0[2] 2D0[2]
l
IES18
P
GPIO8 wb_conf[ PU/P 0x10005 0x10005 0x10005FA 0x00000000,0x00000002,0x000000
Re Pi B
LCM_RST PD - -
3 3:0] D 1A0[3] 2D0[3] 0[3:0] 04,0x00000006
SMT18
IES18
GPIO8 wb_conf[ PU/P 0x10005 0x10005 0x10005FA 0x00000000,0x00000002,0x000000
DSI_TE PD - -
a
4 3:0] D 1A0[4] 2D0[4] 0[3:0] 04,0x00000006
SMT18
MIPI_TCN GPI95
-
-
n a n
NP NP - - - - - -
Ba
/-
-
MIPI_TCP GPI96 - NP NP - - - - - -
/-
MIPI_TDN -
GPI97 - NP NP - - - - - -
1 /-
-
MIPI_TDP1 GPI98 - NP NP - - - - - -
/-
MIPI_TDN -
GPI99 - NP NP - - - - - -
0 /-
GPI10 -
MIPI_TDP0 - NP NP - - - - - -
0
r
/-
SPI2_CSN
GPIO1
01
IES22
- PD
e f
-
o 0x10005
1B0[5]
2
0x10005
2E0[5]
- - - -
s
SMT22
SPI2_MI
GPIO1
IES22
-
l
PD
e a -
P I - R
0x10005 0x10005
- - - -
Re Pi B
02 SMT22 1B0[6] 2E0[6]
IES22
GPIO1 0x10005 0x10005
SPI2_MO - PD - - - - -
03 SMT22 1B0[7] 2E0[7]
SPI2_CK
GPIO1
IES22
-
a n
PD
a -
0x10005 0x10005
- - - -
n
04 SMT22 1B0[8] 2E0[8]
Ba
1.8V:
0x1000
{r0,r1,p 0x00000000,0x00000001,0x000000
5D40[4
upd}=0 02,0x00000003,0x00000004,0x000
MSDC1_C GPIO1 ] PU/P 0x10005D4
- PU - - - x10005 00005,0x00000006,0x00000007-
MD 05 D 0[3:0]
/0x100 D40[10 3.3V:
05D40[ :8] 0x00000000,0x00000001,0x000000
11] 02,0x00000003,
1.8V:
0x1000
{r0,r1,p 0x00000000,0x00000001,0x000000
5D30[4
upd}=0 02,0x00000003,0x00000004,0x000
MSDC1_C GPIO1 ] PU/P 0x10005D3
- PD - - - x10005 00005,0x00000006,0x00000007-
LK 06 D 0[3:0]
/0x100 D30[10 3.3V:
05D30[ :8] 0x00000000,0x00000001,0x000000
11] 02,0x00000003,
1.8V:
0x1000
{r0,r1,p 0x00000000,0x00000001,0x000000
r
5D50[4
upd}=0 02,0x00000003,0x00000004,0x000
o
MSDC1_D GPIO1 ] PU/P 0x10005D5
f
- PU - - - x10005 00005,0x00000006,0x00000007-
AT0 07 D 0[3:0]
/0x100 D60[2: 3.3V:
05D60[
3]
e a s e I - R 2
0] 0x00000000,0x00000001,0x000000
02,0x00000003,
1.8V:
l
0x1000
P
{r0,r1,p 0x00000000,0x00000001,0x000000
Re Pi B
5D50[4
upd}=0 02,0x00000003,0x00000004,0x000
- PU - - - x10005 00005,0x00000006,0x00000007-
AT1 08 D 0[3:0]
/0x100 D60[6: 3.3V:
05D60[ 4] 0x00000000,0x00000001,0x000000
a
7] 02,0x00000003,
Ba
MT7623N
f o r
0x1000
5D50[4
e a s e I - R 2 {r0,r1,p
1.8V:
0x00000000,0x00000001,0x000000
02,0x00000003,0x00000004,0x000
l
upd}=0
P
00005,0x00000006,0x00000007-
Re Pi B
- PU - - - x10005
AT2 09 D 0[3:0]
/0x100 D60[10 3.3V:
05D60[ :8] 0x00000000,0x00000001,0x000000
11] 02,0x00000003,
1.8V:
a
0x1000
{r0,r1,p 0x00000000,0x00000001,0x000000
n
5D50[4
upd}=0 02,0x00000003,0x00000004,0x000
a
00005,0x00000006,0x00000007-
n
- PU - - - x10005
AT3 10 D 0[3:0]
Ba
/0x100 D60[14 3.3V:
05D60[ :12] 0x00000000,0x00000001,0x000000
15] 02,0x00000003,
1.8V:
0x1000
{r0,r1,p 0x00000000,0x00000001,0x000000
5CE0[
upd}=0 02,0x00000003,0x00000004,0x000
MSDC0_D GPIO1 4] PU/P 0x10005CE
- PU - - - x10005 00005,0x00000006,0x00000007-
AT7 11 D 0[3:0]
/0x100 D00[14 3.3V:
05D00[ :12] 0x00000000,0x00000001,0x000000
15] 02,0x00000003,
1.8V:
0x1000
{r0,r1,p 0x00000000,0x00000001,0x000000
5CE0[
upd}=0 02,0x00000003,0x00000004,0x000
- PU - - - x10005 00005,0x00000006,0x00000007-
AT6 12 D 0[3:0]
/0x100 D00[10 3.3V:
05D00[ :8] 0x00000000,0x00000001,0x000000
11] 02,0x00000003,
0x1000
5CE0[
f o r {r0,r1,p
upd}=0
1.8V:
0x00000000,0x00000001,0x000000
02,0x00000003,0x00000004,0x000
e
2
- PU - - - x10005 00005,0x00000006,0x00000007-
s
AT5 13 D 0[3:0]
D00[6:
R
/0x100 3.3V:
05D00[
7]
l e a P I -
4] 0x00000000,0x00000001,0x000000
02,0x00000003,
Re Pi B
1.8V:
0x1000
{r0,r1,p 0x00000000,0x00000001,0x000000
5CE0[
upd}=0 02,0x00000003,0x00000004,0x000
- PU - - - x10005 00005,0x00000006,0x00000007-
AT4 14 D 0[3:0]
a
/0x100 D00[2: 3.3V:
n
05D00[ 0] 0x00000000,0x00000001,0x000000
a
3] 02,0x00000003,
n
1.8V:
Ba
0x1000
{r0,r1,p 0x00000000,0x00000001,0x000000
5CE0[
upd}=0 02,0x00000003,0x00000004,0x000
MSDC0_R GPIO1 4] PU/P 0x10005CE
- PU - - - x10005 00005,0x00000006,0x00000007-
STB 15 D 0[3:0]
/0x100 D10[2: 3.3V:
05D10[ 0] 0x00000000,0x00000001,0x000000
3] 02,0x00000003,
1.8V:
0x1000
{r0,r1,p 0x00000000,0x00000001,0x000000
5CD0[
upd}=0 02,0x00000003,0x00000004,0x000
MSDC0_C GPIO1 4] PU/P 0x10005C
- PU - - - x10005 00005,0x00000006,0x00000007-
MD 16 D D0[3:0]
/0x100 CD0[1 3.3V:
05CD0 0:8] 0x00000000,0x00000001,0x000000
[11] 02,0x00000003,
1.8V:
0x1000
{r0,r1,p 0x00000000,0x00000001,0x000000
5CC0[
upd}=0 02,0x00000003,0x00000004,0x000
MSDC0_C GPIO1 4] PU/P 0x10005C
r
- PD - - - x10005 00005,0x00000006,0x00000007-
LK 17 D C0[3:0]
o
/0x100 CC0[1 3.3V:
05CC0
[11]
s e f 2
0:8] 0x00000000,0x00000001,0x000000
02,0x00000003,
1.8V:
a R
0x1000
-
{r0,r1,p 0x00000000,0x00000001,0x000000
e I
5CE0[
l
upd}=0 02,0x00000003,0x00000004,0x000
P
Re Pi B
- PU - - - x10005 00005,0x00000006,0x00000007-
AT3 18 D 0[3:0]
/0x100 CF0[14 3.3V:
05CF0[ :12] 0x00000000,0x00000001,0x000000
15] 02,0x00000003,
a n a
n
Ba
MT7623N
f o r
0x1000
5CE0[
e a s e I - R 2 {r0,r1,p
1.8V:
0x00000000,0x00000001,0x000000
02,0x00000003,0x00000004,0x000
l
upd}=0
P
00005,0x00000006,0x00000007-
Re Pi B
- PU - - - x10005
AT2 19 D 0[3:0]
/0x100 CF0[10 3.3V:
05CF0[ :8] 0x00000000,0x00000001,0x000000
11] 02,0x00000003,
1.8V:
a
0x1000
{r0,r1,p 0x00000000,0x00000001,0x000000
n
5CE0[
upd}=0 02,0x00000003,0x00000004,0x000
a
00005,0x00000006,0x00000007-
n
- PU - - - x10005
AT1 20 D 0[3:0]
Ba
/0x100 CF0[6: 3.3V:
05CF0[ 4] 0x00000000,0x00000001,0x000000
7] 02,0x00000003,
1.8V:
0x1000
{r0,r1,p 0x00000000,0x00000001,0x000000
5CE0[
upd}=0 02,0x00000003,0x00000004,0x000
- PU - - - x10005 00005,0x00000006,0x00000007-
AT0 21 D 0[3:0]
/0x100 CF0[2: 3.3V:
05CF0[ 0] 0x00000000,0x00000001,0x000000
3] 02,0x00000003,
IES23
GPIO1 0x10005 0x10005
CEC - PD - - - - -
22 1C0[10] 2F0[10]
SMT23
IES23
GPIO1 0x10005 0x10005
HTPLG - PD - - - - -
23 SMT23 1C0[11] 2F0[11]
HDMISCK
GPIO1
IES23
- PD -
f o r
0x10005 0x10005
- - - -
e
24 SMT23 1C0[12] 2F0[12]
HDMISD
GPIO1
25
IES23
- PD
l e a s-
I - R 2
0x10005
1C0[13]
0x10005
2F0[13]
- - - -
P
SMT23
I2S0_MCL
K
GPIO1
26
IES12
SMT12
i2s0_con
f[3:0]
Re Pi B
PU/P
D
PD
0x10005
1C0[14]
0x10005
2F0[14]
- -
0x10005F8
0[7:4]
0x00000000,0x00000020,0x000000
40,0x00000060
SPI1_CK
GPIO1
99
IES1
spi1_con
f[3:0]
PU/P
D
a n a PD
0x10005
210[7]
0x10005
340[7]
- -
0x10005F5
0[7:4]
0x00000000,0x00000020,0x000000
40,0x00000060
n
SMT1
SPDIF_OU
T
SPDIF_IN0
GPIO2
00
GPIO2
IES33
SMT33
IES33
spdif_co
nf[3:0]
spdif_co
B aPU/P
D
PU/P
PD
PD
0x10005
210[8]
0x10005
0x10005
340[8]
0x10005
-
-
-
-
0x10005FD
0[3:0]
0x10005FD
0x00000000,0x00000002,0x000000
04,0x00000006
0x00000000,0x00000002,0x000000
01 SMT33 nf[3:0] D 210[9] 340[9] 0[3:0] 04,0x00000006
IES33
GPIO2 spdif_co PU/P 0x10005 0x10005 0x10005FD 0x00000000,0x00000002,0x000000
SPDIF_IN1 PD - -
02 SMT33 nf[3:0] D 210[10] 340[10] 0[3:0] 04,0x00000006
IES34
GPIO2 pwm_co PU/P 0x10005 0x10005 0x10005FD 0x00000000,0x00000020,0x000000
PWM0 PD - -
03 nf[3:0] D 210[11] 340[11] 0[7:4] 40,0x00000060
SMT34
IES34
r
PWM1 PD - -
o
04 nf[3:0] D 210[12] 340[12] 0[7:4] 40,0x00000060
f
SMT34
e
IES34
s 2
PWM2 PD - -
a R
05 nf[3:0] D 210[13] 340[13] 0[7:4] 40,0x00000060
-
SMT34
PWM3
PWM4
GPIO2
06
GPIO2
IES34
SMT34
IES34
pwm_co
nf[3:0]
pwm_co
D
l
PU/P
e
Re Pi B
PU/P
PD
PD
P I 0x10005
210[14]
0x10005
0x10005
340[14]
0x10005
-
-
-
-
0x10005FD
0[7:4]
0x10005FD
0x00000000,0x00000020,0x000000
40,0x00000060
0x00000000,0x00000020,0x000000
a n a
n
Ba
MT7623N
f o r
07 SMT34 nf[3:0] D
e a s e I - R 2
210[15] 340[15] 0[7:4] 40,0x00000060
l
IES35
P
AUD_EXT_ GPIO2 audck_c PU/P 0x10005 0x10005 0x10005FD 0x00000000,0x00000200,0x000004
Re Pi B
PD - -
CK1 08 onf[3:0] D 220[0] 350[0] 0[11:8] 00,0x00000600
SMT35
IES35
AUD_EXT_ GPIO2 audck_c PU/P 0x10005 0x10005 0x10005FD 0x00000000,0x00000200,0x000004
PD - -
a
CK2 09 onf[3:0] D 220[1] 350[1] 0[11:8] 00,0x00000600
SMT35
SFLASH_I GPIO2
IES38
ext_conf[
n a n
PU/P
PD
0x10005 0x10005
- -
0x10005FF 0x00000000,0x00000020,0x000000
Ba
O_3 36 3:0] D 230[12] 360[12] 0[7:4] 40,0x00000060
SMT38
IES38
SFLASH_I GPIO2 ext_conf[ PU/P 0x10005 0x10005 0x10005FF 0x00000000,0x00000020,0x000000
PD - -
O_2 37 SMT38 3:0] D 230[13] 360[13] 0[7:4] 40,0x00000060
IES38
PD - -
O_1 38 SMT38 3:0] D 230[14] 360[14] 0[7:4] 40,0x00000060
IES38
PD - -
O_0 39 SMT38 3:0] D 230[15] 360[15] 0[7:4] 40,0x00000060
IES38
SFLASH_C GPIO2 ext_conf[ PU/P 0x10005 0x10005 0x10005FF 0x00000000,0x00000020,0x000000
PD - -
S_L 40 SMT38 3:0] D 240[0] 370[0] 0[7:4] 40,0x00000060
SFLASH_C
LK
GPIO2
41
IES38
SMT38
ext_conf[
3:0]
PU/P
D
f
PD
o r 0x10005
240[1]
0x10005
370[1]
- -
0x10005FF
0[7:4]
0x00000000,0x00000020,0x000000
40,0x00000060
URTS2
GPIO2
42
IES39
ud_conf[
3:0]
PU/P
D
e a s ePD
I - R 2
0x10005
240[2]
0x10005
370[2]
- -
0x10005FF
0[11:8]
0x00000000,0x00000200,0x000004
00,0x00000600
l
SMT39
UCTS2
GPIO2
43
IES39
SMT39
ud_conf[
3:0]
Re Pi B
PU/P
D
PD
P 0x10005
240[3]
0x10005
370[3]
- -
0x10005FF
0[11:8]
0x00000000,0x00000200,0x000004
00,0x00000600
GPIO244
GPIO2
44
IES40
SMT40
mhl_conf
[3:0]
a n
PD
a -
0x10005
240[4]
0x10005
370[4]
- -
0x10005FF
0[15:12]
0x00000000,0x00002000,0x000040
00,0x00006000
GPIO245
MHL_SEN
GPIO2
45
GPIO2
IES40
SMT40
IES40
mhl_conf
[3:0]
mhl_conf Ba n PD -
0x10005
240[5]
0x10005
0x10005
370[5]
0x10005
- -
0x10005FF
0[15:12]
0x10005FF
0x00000000,0x00002000,0x000040
00,0x00006000
0x00000000,0x00002000,0x000040
PD PD - -
CE 46 SMT40 [3:0] 240[6] 370[6] 0[15:12] 00,0x00006000
IES40
GPIO2 mhl_conf 0x10005 0x10005 0x10005FF 0x00000000,0x00002000,0x000040
GPIO247 PD PD - -
47 SMT40 [3:0] 240[7] 370[7] 0[15:12] 00,0x00006000
IES41
GPIO2 hdmiout_ 0x10005 0x10005 0x10005F0 0x00000000,0x00000002,0x000000
GPIO248 PD - - -
48 conf[3:0] 240[8] 370[8] 0[3:0] 04,0x00000006
SMT41
0x1000
{r0,r1,p
5FC0[4
r
upd}=0 0x00000000,0x00000001,0x000000
GPIO2 ] PU/P 0x10005FC
o
GPIO250 - PU - - - x10005 02,0x00000003,0x00000004,0x000
f
50 /0x100 D 0[3:0]
130[14 00005,0x00000006,0x00000007-
05130[
e
:12]
2
15]
0x1000
5FC0[4
l e a s I - R {r0,r1,p
upd}=0 0x00000000,0x00000001,0x000000
P
Re Pi B
GPIO251 - PU - - - x10005 02,0x00000003,0x00000004,0x000
51 /0x100 D 0[3:0]
130[10 00005,0x00000006,0x00000007-
05130[
:8]
11]
a n a
n
Ba
MT7623N
f o r
0x1000
5FC0[4
]
e a s e I - R 2 {r0,r1,p
upd}=0 0x00000000,0x00000001,0x000000
l
GPIO2 PU/P 0x10005FC
GPIO252 - PU - - - x10005 02,0x00000003,0x00000004,0x000
Re Pi B P
52 /0x100 D 0[3:0]
130[6: 00005,0x00000006,0x00000007-
05130[
4]
7]
0x1000
{r0,r1,p
5FC0[4
a
upd}=0 0x00000000,0x00000001,0x000000
n
GPIO253 - PU - - - x10005 02,0x00000003,0x00000004,0x000
53 D 0[3:0]
a
/0x100
130[2: 00005,0x00000006,0x00000007-
n
05130[
0]
Ba
3]
0x1000
{r0,r1,p
5FC0[4
upd}=0 0x00000000,0x00000001,0x000000
GPIO254 - PU - - - x10005 02,0x00000003,0x00000004,0x000
54 /0x100 D 0[3:0]
F40[14 00005,0x00000006,0x00000007-
05F40[ :12]
15]
0x1000
5FC0[4 {r0,r1,p
] upd}=0 0x00000000,0x00000001,0x000000
GPIO2 PU/P 0x10005FC
GPIO255 - PU - - - x10005 02,0x00000003,0x00000004,0x000
55 /0x100 D 0[3:0]
F40[10 00005,0x00000006,0x00000007-
05F40[
:8]
11]
0x1000
{r0,r1,p
5FC0[4
upd}=0 0x00000000,0x00000001,0x000000
GPIO256 - PU - - - x10005 02,0x00000003,0x00000004,0x000
r
56 /0x100 D 0[3:0]
F40[6: 00005,0x00000006,0x00000007-
o
05F40[
4]
f
7]
e
0x1000
2
{r0,r1,p
s
5FC0[4
upd}=0 0x00000000,0x00000001,0x000000
a R
GPIO2 ] PU/P 0x10005CE
-
GPIO257 - PU - - - x10005 02,0x00000003,0x00000004,0x000
e I
57 /0x100 D 0[3:0]
l
F40[2: 00005,0x00000006,0x00000007-
P
05F40[
Re Pi B
0]
3]
IES44
GE2_TXE GPIO2 rgmii_co PU/P 0x10005 0x10005 0x10005F0 0x00000000,0x00000200,0x000004
PD - -
N 62 nf[3:0] D 250[6] 380[6] 0[11:8] 00,0x00000600
a
SMT44
GE2_TXD3
GPIO2
63
IES44
SMT44
rgmii_co
nf[3:0]
n aD
n
PU/P
PD
0x10005
250[7]
0x10005
380[7]
- -
0x10005F0
0[11:8]
0x00000000,0x00000200,0x000004
00,0x00000600
GE2_TXD2
GE2_TXD1
GPIO2
64
GPIO2
65
IES44
SMT44
IES44
SMT44
rgmii_co
nf[3:0]
rgmii_co
nf[3:0]
Ba PU/P
D
PU/P
D
PD
PD
0x10005
250[8]
0x10005
250[9]
0x10005
380[8]
0x10005
380[9]
-
-
-
-
0x10005F0
0[11:8]
0x10005F0
0[11:8]
0x00000000,0x00000200,0x000004
00,0x00000600
0x00000000,0x00000200,0x000004
00,0x00000600
IES44
GPIO2 rgmii_co PU/P 0x10005 0x10005 0x10005F0 0x00000000,0x00000200,0x000004
GE2_TXD0 PD - -
66 SMT44 nf[3:0] D 250[10] 380[10] 0[11:8] 00,0x00000600
IES44
GE2_TXCL GPIO2 rgmii_co PU/P 0x10005 0x10005 0x10005F0 0x00000000,0x00000200,0x000004
PD - -
K 67 SMT44 nf[3:0] D 250[11] 380[11] 0[11:8] 00,0x00000600
r
IES44
GE2_RXC GPIO2 rgmii_co PU/P 0x10005 0x10005 0x10005F0 0x00000000,0x00000200,0x000004
o
PD - -
f
LK 68 SMT44 nf[3:0] D 250[12] 380[12] 0[11:8] 00,0x00000600
GE2_RXD
0
GPIO2
69
IES44
SMT44
rgmii_co
nf[3:0]
PU/P
D
e a s ePD
I - 2
0x10005
R
250[13]
0x10005
380[13]
- -
0x10005F0
0[11:8]
0x00000000,0x00000200,0x000004
00,0x00000600
GE2_RXD
1
GE2_RXD
GPIO2
70
GPIO2
IES44
SMT44
IES44
rgmii_co
nf[3:0]
rgmii_co
D
l
Re Pi B
PU/P
PU/P
PD
PD
P 0x10005
250[14]
0x10005
0x10005
380[14]
0x10005
-
-
-
-
0x10005F0
0[11:8]
0x10005F0
0x00000000,0x00000200,0x000004
00,0x00000600
0x00000000,0x00000200,0x000004
a n a
n
Ba
MT7623N
f o r
2 71 SMT44 nf[3:0]
e
D
a s e I - R 2 250[15] 380[15] 0[11:8] 00,0x00000600
GE2_RXD
3
GPIO2
72
IES44
SMT44 rgmii_co
nf[3:0]
l
Re Pi B
PU/P
D
PPD
0x10005
260[0]
0x10005
390[0]
- -
0x10005F0
0[11:8]
0x00000000,0x00000200,0x000004
00,0x00000600
GE2_RXD
V
GPIO2
74
IES44
SMT44
rgmii_co
nf[3:0]
a n a
PU/P
D
PD
0x10005
260[2]
0x10005
390[2]
- -
0x10005F0
0[11:8]
0x00000000,0x00000200,0x000004
00,0x00000600
MDC
MDIO
GPIO2
75
GPIO2
IES44
SMT44
IES44 Ba
rgmii_co
nf[3:0]
rgmii_co
n PU/P
D
PU/P
PD
PD
0x10005
260[3]
0x10005
0x10005
390[3]
0x10005
-
-
-
-
0x10005F0
0[11:8]
0x10005F0
0x00000000,0x00000200,0x000004
00,0x00000600
0x00000000,0x00000200,0x000004
76 SMT44 nf[3:0] D 260[4] 390[4] 0[11:8] 00,0x00000600
IES45
JTAG_RES GPIO2 jtag_conf PU/P 0x10005 0x10005 0x10005F7 0x00000000,0x00000200,0x000004
PU - -
ET 78 [3:0] D 260[6] 390[6] 0[11:8] 00,0x00000600
SMT45
Below Tables shows the drving control and SMT control registers. Refer to the datasheet of infrasys
configuration for detail command registers.
f o r
Table 1-4: IES control register mapping
IES control bit
IES0
e a s e I - R 2 Register bit
IES0_EN[0]
Register bit
0x10005B20[0]
IES1
IES2
IES3
l
Re Pi B P IES0_EN[1]
IES0_EN[2]
IES0_EN[3]
0x10005B20[1]
0x10005B20[2]
0x10005B20[3]
IES4
a n a IES0_EN[4] 0x10005B20[4]
n
IES5 IES0_EN[5] 0x10005B20[5]
Ba
IES6 IES0_EN[6] 0x10005B20[6]
IES7 IES0_EN[7] 0x10005B20[7]
IES8 IES0_EN[8] 0x10005B20[8]
IES9 IES0_EN[9] 0x10005B20[9]
IES10 IES0_EN[10] 0x10005B20[10]
IES11 IES0_EN[11] 0x10005B20[11]
IES12 IES0_EN[12] 0x10005B20[12]
IES13 IES0_EN[13] 0x10005B20[13]
IES14 IES0_EN[14] 0x10005B20[14]
IES15 IES0_EN[15] 0x10005B20[15]
IES16
f o r IES1_EN[0] 0x10005B30[0]
e
IES17 IES1_EN[1] 0x10005B30[1]
IES18
IES19
l e a s I - R 2 IES1_EN[2]
IES1_EN[3]
0x10005B30[2]
0x10005B30[3]
IES20
IES21
Re Pi B P IES1_EN[4]
IES1_EN[5]
0x10005B30[4]
0x10005B30[5]
a
IES22 IES1_EN[6] 0x10005B30[6]
Ba
MT7623N
f o r
IES control bit
e a s e I - R 2 Register bit Register bit
l
IES23 IES1_EN[7] 0x10005B30[7]
IES24
IES25
Re Pi B P MSDC0_CTRL2[4]
IES1_EN[9]
0x10005CE0[4]
0x10005B30[9]
a
IES26 IES1_EN[10] 0x10005B30[10]
IES27
IES28
n a n IES1_EN[11]
IES1_EN[12]
0x10005B30[11]
0x10005B30[12]
Ba
IES29 IES1_EN[13] 0x10005B30[13]
IES30 IES1_EN[14] 0x10005B30[14]
IES31 IES1_EN[15] 0x10005B30[15]
IES32 IES2_EN[0] 0x10005B40[0]
IES33 IES2_EN[1] 0x10005B40[1]
IES34 IES2_EN[2] 0x10005B40[2]
IES35 IES2_EN[3] 0x10005B40[3]
IES36 IES2_EN[4] 0x10005B40[4]
IES37 IES2_EN[5] 0x10005B40[5]
r
IES38 IES2_EN[6] 0x10005B40[6]
IES39
IES40
e f o 2
IES2_EN[7]
IES2_EN[8]
0x10005B40[7]
0x10005B40[8]
IES41
l e a s I - R IES2_EN[9] 0x10005B40[9]
P
IES42 MSDC3_CTRL2[4] 0x10005FC0[4]
Re Pi B
IES43 MSDC1_CTRL2[4] 0x10005D50[4]
IES44 IES2_EN[12] 0x10005B40[12]
IES45
a n a IES2_EN[13] 0x10005B40[13]
n
Table 1-5: SMTcontrol register mapping
SMT control bit
SMT0
SMT1 B a Register bit
SMT0_EN[0]
SMT0_EN[1]
Register bit
0x10005B50[0]
0x10005B50[1]
SMT2 SMT0_EN[2] 0x10005B50[2]
SMT3 SMT0_EN[3] 0x10005B50[3]
SMT4 SMT0_EN[4] 0x10005B50[4]
SMT5 SMT0_EN[5] 0x10005B50[5]
SMT6 SMT0_EN[6] 0x10005B50[6]
SMT7 SMT0_EN[7] 0x10005B50[7]
SMT8 SMT0_EN[8] 0x10005B50[8]
SMT9
f o r SMT0_EN[9] 0x10005B50[9]
e
SMT10 SMT0_EN[10] 0x10005B50[10]
SMT11
SMT12
l e a s I - R 2SMT0_EN[11]
SMT0_EN[12]
0x10005B50[11]
0x10005B50[12]
SMT13
SMT14
Re Pi B P SMT0_EN[13]
SMT0_EN[14]
0x10005B50[13]
0x10005B50[14]
a n a
n
B a
MT7623N
f o r
SMT control bit
e a s e I - R 2 Register bit Register bit
l
SMT15 SMT0_EN[15] 0x10005B50[15]
SMT16
SMT17
Re Pi B P SMT1_EN[0]
SMT1_EN[1]
0x10005B60[0]
0x10005B60[1]
a
SMT18 SMT1_EN[2] 0x10005B60[2]
SMT19
SMT20
n a n SMT1_EN[3]
SMT1_EN[4]
0x10005B60[3]
0x10005B60[4]
Ba
SMT21 SMT1_EN[5] 0x10005B60[5]
SMT22 SMT1_EN[6] 0x10005B60[6]
SMT23 SMT1_EN[7] 0x10005B60[7]
SMT24 MSDC0_CTRL5[3] 0x10005D10[3]
SMT25 SMT1_EN[9] 0x10005B60[9]
SMT26 SMT1_EN[10] 0x10005B60[10]
SMT27 SMT1_EN[11] 0x10005B60[11]
SMT28 SMT1_EN[12] 0x10005B60[12]
SMT29 SMT1_EN[13] 0x10005B60[13]
r
SMT30 SMT1_EN[14] 0x10005B60[14]
SMT31
SMT32
e f o 2
SMT1_EN[15]
SMT2_EN[0]
0x10005B60[15]
0x10005B70[0]
SMT33
l e a s I - R SMT2_EN[1] 0x10005B70[1]
P
SMT34 SMT2_EN[2] 0x10005B70[2]
Re Pi B
SMT35 SMT2_EN[3] 0x10005B70[3]
SMT36 SMT2_EN[4] 0x10005B70[4]
SMT37
SMT38
a n a SMT2_EN[5]
SMT2_EN[6]
0x10005B70[5]
0x10005B70[6]
SMT39
SMT40
SMT41
B a n SMT2_EN[7]
SMT2_EN[8]
SMT2_EN[9]
0x10005B70[7]
0x10005B70[8]
0x10005B70[9]
SMT42 MSDC3_CTRL5[3] 0x10005140[3]
SMT43 MSDC1_CTRL6[3] 0x100050B0[3]
SMT44 SMT2_EN[12] 0x10005B70[12]
SMT45 SMT2_EN[13] 0x10005B70[13]
Table 1-6: Driving control register mapping

Name Driving control Register name MSB LSB
PWRAP_SPI0_MI pwrap_conf[3:0]
f o r DRV_SEL0 3 0
e
PWRAP_SPI0_MO pwrap_conf[3:0] DRV_SEL0 3 0
PWRAP_INT
PWRAP_SPI0_CK
l e a s
pwrap_conf[3:0]
pwrap_conf[3:0]
I - R 2 DRV_SEL0
DRV_SEL0
3
3
0
0
PWRAP_SPI0_CSN
PWRAP_SPI0_CK2
Re Pi B
pwrap_conf[3:0]
pwrap_conf[3:0] P DRV_SEL0
DRV_SEL0
3
3
0
0
a
PWRAP_SPI0_CSN2 pwrap_conf[3:0] DRV_SEL0 3 0
B a
MT7623N
f o r
Name
e a s e
Driving control
I - R 2 Register name MSB LSB
l
SPI1_CSN spi1_conf[3:0] DRV_SEL0 7 4
SPI1_MI
SPI1_MO
Re Pi B P
spi1_conf[3:0]
spi1_conf[3:0]
DRV_SEL0
DRV_SEL0
7
7
4
4
a
RTC32K_CK pm_conf[3:0] DRV_SEL0 11 8
WATCHDOG
SRCLKENA
n a n pm_conf[3:0]
pm_conf[3:0]
DRV_SEL0
DRV_SEL0
11
11
8
8
Ba
SRCLKENAI pm_conf[3:0] DRV_SEL0 11 8
URXD2 uart2_conf[3:0] DRV_SEL0 15 12
UTXD2 uart2_conf[3:0] DRV_SEL0 15 12
PCM_CLK pcm_conf[3:0] DRV_SEL1 7 4
PCM_SYNC pcm_conf[3:0] DRV_SEL1 7 4
PCM_RX pcm_conf[3:0] DRV_SEL1 7 4
PCM_TX pcm_conf[3:0] DRV_SEL1 7 4
EINT0 eint0_conf[3:0] DRV_SEL1 11 8
r
EINT3
EINT4
e f
eint0_conf[3:0]
eint0_conf[3:0]
o 2
DRV_SEL1
DRV_SEL1
11
11
8
8
EINT5
l e a s
eint5_conf[3:0]
I - R DRV_SEL1 15 12
P
Re Pi B
I2S1_DATA i2s1_conf[3:0] DRV_SEL2 3 0
I2S1_DATA_IN
I2S1_BCK
a n a
i2s1_conf[3:0]
i2s1_conf[3:0]
DRV_SEL2
DRV_SEL2
3
3
0
0
I2S1_LRCK
I2S1_MCLK
JTMS
B a ni2s1_conf[3:0]
i2s1_conf[3:0]
jtag_conf[3:0]
DRV_SEL2
DRV_SEL2
DRV_SEL2
3
3
11
0
0
8
JTCK jtag_conf[3:0] DRV_SEL2 11 8
JTDI jtag_conf[3:0] DRV_SEL2 11 8
JTDO jtag_conf[3:0] DRV_SEL2 11 8
NCLE eint12_conf[3:0] DRV_SEL2 15 12
NCEB1 eint12_conf[3:0] DRV_SEL2 15 12
NCEB0 eint12_conf[3:0] DRV_SEL2 15 12
NREB eint17_conf[3:0] DRV_SEL3 3 0
NRNB
I2S0_DATA
eint17_conf[3:0]
f
i2s0_conf[3:0]
o r DRV_SEL3
DRV_SEL3
3
7
0
4
SPI0_CSN
SPI0_CK
e a s e
spi0_conf[3:0]
spi0_conf[3:0]
I - R 2 DRV_SEL3
DRV_SEL3
15
15
12
12
SPI0_MI
SPI0_MO
SDA1
l
Re Pi B
spi0_conf[3:0]
spi0_conf[3:0]
i2c1_conf[3:0]
P DRV_SEL3
DRV_SEL3
DRV_SEL4
15
15
3
12
12
0
a n a
n
B a
MT7623N
f o r
Name
e a s e
Driving control
l
SCL1 i2c1_conf[3:0] DRV_SEL4 3 0
WB_RSTB
GPIO61
Re Pi B P
fm_conf[3:0]
fm_conf[3:0]
DRV_SEL4
DRV_SEL4
11
11
8
8
a
GPIO62 fm_conf[3:0] DRV_SEL4 11 8
WB_SCLK
WB_SDATA
n a n wbspi_conf[3:0]
wbspi_conf[3:0]
DRV_SEL4
DRV_SEL4
15
15
12
12
Ba
WB_SEN wbspi_conf[3:0] DRV_SEL4 15 12
WB_CTRL0 wb_conf[3:0] DRV_SEL5 3 0
I2S0_DATA_IN i2s0_conf[3:0] DRV_SEL3 7 4
I2S0_LRCK i2s0_conf[3:0] DRV_SEL3 7 4
r
I2S0_BCK i2s0_conf[3:0] DRV_SEL3 7 4
SDA0
SCL0
e f
i2c0_conf[3:0]
i2c0_conf[3:0]
o 2
DRV_SEL5
DRV_SEL5
7
7
4
4
SDA2
l e a s
i2c2_conf[3:0]
I - R DRV_SEL5 11 8
P
SCL2 i2c2_conf[3:0] DRV_SEL5 11 8
Re Pi B
URXD0 uart0_conf[3:0] DRV_SEL5 15 12
UTXD0 uart0_conf[3:0] DRV_SEL5 15 12
URXD1
UTXD1
a n a
uart0_conf[3:0]
uart0_conf[3:0]
DRV_SEL5
DRV_SEL5
15
15
12
12
LCM_RST
DSI_TE
SPI2_CSN
B a n wb_conf[3:0]
wb_conf[3:0]
spi2_conf[3:0]
DRV_SEL5
DRV_SEL5
DRV_SEL6
3
3
3
0
0
0
SPI2_MI spi2_conf[3:0] DRV_SEL6 3 0
SPI2_MO spi2_conf[3:0] DRV_SEL6 3 0
SPI2_CK spi2_conf[3:0] DRV_SEL6 3 0
CEC hdmi_conf[3:0] DRV_SEL6 7 4
HTPLG hdmi_conf[3:0] DRV_SEL6 7 4
HDMISCK hdmi_conf[3:0] DRV_SEL6 7 4
HDMISD hdmi_conf[3:0] DRV_SEL6 7 4
I2S0_MCLK
SPI1_CK
i2s0_conf[3:0]
f
spi1_conf[3:0]
o r DRV_SEL3
DRV_SEL0
7
7
4
4
SPDIF_OUT
SPDIF_IN0
e a s e
spdif_conf[3:0]
spdif_conf[3:1]
I - R 2 DRV_SEL8
DRV_SEL8
3
3
0
0
SPDIF_IN1
PWM0
PWM1
l
Re Pi B
spdif_conf[3:2]
pwm_conf[3:0]
pwm_conf[3:0]
P DRV_SEL8
DRV_SEL8
DRV_SEL8
3
7
7
0
4
4
a n a
n
B a
MT7623N
f o r
Name
e a s e
Driving control
l
PWM2 pwm_conf[3:0] DRV_SEL8 7 4
PWM3
PWM4
Re Pi B P
pwm_conf[3:0]
pwm_conf[3:0]
DRV_SEL8
DRV_SEL8
7
7
4
4
a
AUD_EXT_CK1 audck_conf[3:0] DRV_SEL8 11 8
AUD_EXT_CK2
SFLASH_IO_3
n a naudck_conf[3:0]
ext_conf[3:0]
DRV_SEL8
DRV_SEL9
11
7
8
4
Ba
SFLASH_IO_2 ext_conf[3:0] DRV_SEL9 7 4
SFLASH_CS_L ext_conf[3:0] DRV_SEL9 7 4
SFLASH_CLK ext_conf[3:0] DRV_SEL9 7 4
URTS2 ud_conf[3:0] DRV_SEL9 11 8
UCTS2 ud_conf[3:0] DRV_SEL9 11 8
GPIO244 mhl_conf[3:0] DRV_SEL9 15 12
GPIO245 mhl_conf[3:0] DRV_SEL9 15 12
r
MHL_SENCE mhl_conf[3:0] DRV_SEL9 15 12
GPIO247
GPIO248
mhl_conf[3:0]
e f
hdmiout_conf[3:0]
o 2
DRV_SEL9
DRV_SELA
15
3
12
0
GE2_TXEN
l e a s
rgmii_conf[3:0]
I - R DRV_SELA 11 8
P
GE2_TXD3 rgmii_conf[3:0] DRV_SELA 11 8
Re Pi B
GE2_TXD0
GE2_TXCLK
a n a
rgmii_conf[3:0]
rgmii_conf[3:0]
DRV_SELA
DRV_SELA
11
11
8
8
GE2_RXCLK
GE2_RXD0
GE2_RXD1
B a n
rgmii_conf[3:0]
rgmii_conf[3:0]
rgmii_conf[3:0]
DRV_SELA
DRV_SELA
DRV_SELA
11
11
11
8
8
8
GE2_RXD2 rgmii_conf[3:0] DRV_SELA 11 8
GE2_RXD3 rgmii_conf[3:0] DRV_SELA 11 8
GE2_RXDV rgmii_conf[3:0] DRV_SELA 11 8
MDC rgmii_conf[3:0] DRV_SELA 11 8
MDIO rgmii_conf[3:0] DRV_SELA 11 8
JTAG_RESET jtag_conf[3:0] DRV_SEL2 11 8
MSDC1_CMD 0x10005D40 MSDC1_CTRL1 3 0
MSDC1_CLK
MSDC1_DAT0
0x10005D30
0x10005D50
f o r MSDC1_CTRL0
MSDC1_CTRL2
3
3
0
0
MSDC1_DAT1
MSDC1_DAT2
e a s
0x10005D50
0x10005D50e I - R 2 MSDC1_CTRL2
MSDC1_CTRL2
3
3
0
0
MSDC1_DAT3
MSDC0_DAT7
MSDC0_DAT6
l
Re Pi B
0x10005D50
0x10005CE0
0x10005CE0
P MSDC1_CTRL2
MSDC0_CTRL2
MSDC0_CTRL2
3
3
3
0
0
0
a n a
n
B a
MT7623N
f o r
Name
e a s e
Driving control
l
MSDC0_DAT5 0x10005CE0 MSDC0_CTRL2 3 0
MSDC0_DAT4
MSDC0_RSTB
Re Pi B P
0x10005CE0
0x10005CE0
MSDC0_CTRL2
MSDC0_CTRL2
3
3
0
0
a
MSDC0_CMD 0x10005CD0 MSDC0_CTRL1 3 0
MSDC0_CLK
MSDC0_DAT3
n a n 0x10005CC0
0x10005CE0
MSDC0_CTRL0
MSDC0_CTRL2
3
3
0
0
Ba
GPIO250 0x10005FC0 MSDC3_CTRL2 3 0
r
GPIO257 0x10005FC0
e f o 2
MSDC3_CTRL2 3 0
1.4 External Interrupt List

l e a s I - R
Re Pi B P
GPIO module provides the external interrupt path for external interrupt controller. When using GPIO
as external interrupt source, the GPIO need to be programmed to be GPIO mode (aux. function 0)
and input direction.
a n a
n
Most of GPIOs can be used external source. The detail GPIO and EINT source mapping is listed in
below table.
B a Table 1-7: External Interrupt List

Pin NamePAD GPIO Name EINT Controller Source
PWRAP_SPI0_MI GPIO0 148
PWRAP_SPI0_MO GPIO1 149
PWRAP_INT GPIO2 150
PWRAP_SPI0_CK GPIO3 151
PWRAP_SPI0_CSN GPIO4 152
r
PWRAP_SPI0_CK2 GPIO5 153
PWRAP_SPI0_CSN2
SPI1_CSN
e f o 2
GPIO6
GPIO7
154
155
SPI1_MI
l e a s I - R GPIO8 156
P
SPI1_MO GPIO9 157
RTC32K_CK
WATCHDOG
Re Pi B GPIO10
GPIO11
158
159
a n a
n
B a
MT7623N
f o r
Pin NamePAD
e a s e I - R 2 GPIO Name EINT Controller Source
l
SRCLKENA GPIO12 160
SRCLKENAI
URXD2
Re Pi B P GPIO13
GPIO14
161
162
a
UTXD2 GPIO15 163
PCM_CLK
PCM_SYNC
n a n GPIO18
GPIO19
166
167
Ba
EINT0 GPIO22 0
EINT1 GPIO23 1
EINT2 GPIO24 2
EINT3 GPIO25 3
EINT4 GPIO26 4
EINT5 GPIO27 5
EINT6 GPIO28 6
EINT7 GPIO29 7
Iddig Internal signal 10
r
USB20_VBUSVALID Internal signal 11
I2S1_DATA
I2S1_DATA_IN
e f o 2
GPIO33
GPIO34
15
16
I2S1_BCK
P
I2S1_LRCK GPIO36 18
Re Pi B
I2S1_MCLK GPIO37 19
JTMS GPIO39 21
JTCK
JTDI
a n a GPIO40
GPIO41
22
23
JTDO
NCLE
NCEB1
B a n GPIO42
GPIO43
GPIO44
24
25
26
NCEB0 GPIO45 27
IR GPIO46 28
NREB GPIO47 29
NRNB GPIO48 30
I2S0_DATA GPIO49 31
SPI0_CSN GPIO53 35
SPI0_CK GPIO54 36
SPI0_MI
SPI0_MO
f o r GPIO55
GPIO56
37
38
SDA1
SCL1
e a s e I - R 2 GPIO57
GPIO58
39
40
WB_RSTB
GPIO61
GPIO62
l
Re Pi B P GPIO60
GPIO61
GPIO62
41
42
43
a n a
n
B a
MT7623N
f o r
Pin NamePAD
l
WB_SCLK GPIO63 44
WB_SDATA
WB_SEN
Re Pi B P GPIO64
GPIO65
45
46
a
WB_CTRL0 GPIO66 47
WB_CTRL1
WB_CTRL2
n a n GPIO67
GPIO68
48
49
Ba
WB_CTRL3 GPIO69 50
WB_CTRL4 GPIO70 51
WB_CTRL5 GPIO71 52
I2S0_DATA_IN GPIO72 53
I2S0_LRCK GPIO73 54
I2S0_BCK GPIO74 55
SDA0 GPIO75 56
SCL0 GPIO76 57
SDA2 GPIO77 58
r
SCL2 GPIO78 59
URXD0
UTXD0
e f o 2
GPIO79
GPIO80
60
61
URXD1
P
UTXD1 GPIO82 63
Re Pi B
LCM_RST GPIO83 64
DSI_TE GPIO84 65
GPIO247
SPI2_CSN
a n a GPIO247
GPIO101
69/70
74
SPI2_MI
SPI2_MO
SPI2_CK
B a n GPIO102
GPIO103
GPIO104
75
76
77
MSDC1_CMD GPIO105 78
MSDC1_CLK GPIO106 79
MSDC1_DAT0 GPIO107 80
MSDC0_DAT6
MSDC0_DAT5
f o r GPIO112
GPIO113
85
86
MSDC0_DAT4
MSDC0_RSTB
GPIO115
87
88
MSDC0_CMD
MSDC0_CLK
MSDC0_DAT3
l
Re Pi B P GPIO116
GPIO117
GPIO118
89
90
91
a n a
n
B a
MT7623N
f o r
Pin NamePAD
l
MSDC0_DAT1
MSDC0_DAT0
Re Pi B P GPIO120
GPIO121
93
94
a
CEC GPIO122 95
HTPLG
HDMISCK
n a n GPIO123
GPIO124
96
97
Ba
HDMISD GPIO125 98
I2S0_MCLK GPIO126 99
SPI1_CK GPIO199 111
SPDIF_OUT GPIO200 112
SPDIF_IN0 GPIO201 113
SPDIF_IN1 GPIO202 114
PWM0 GPIO203 115
PWM1 GPIO204 116
PWM2 GPIO205 117
r
PWM3 GPIO206 118
PWM4
AUD_EXT_CK1
e f o 2
GPIO207
GPIO208
119
120
AUD_EXT_CK2
P
SFLASH_IO_3 GPIO236 122
Re Pi B
SFLASH_IO_0
SFLASH_CS_L
a n a GPIO239
GPIO240
125
126
SFLASH_CLK
URTS2
UCTS2
B a n GPIO241
GPIO242
GPIO243
127
128
129
GPIO244 GPIO244 130
GPIO245 GPIO245 131
MHL_SENCE GPIO246 132
GPIO248 GPIO248 133
GPIO250 GPIO250 135
GPIO251 GPIO251 136
GPIO252 GPIO252 137
GPIO253
GPIO254
f o r GPIO253
GPIO254
138
139
GPIO255
GPIO256
GPIO256
140
141
GPIO257
JTAG_RESET l
Re Pi B P GPIO257
GPIO278
142
147
a n a
n
B a
MT7623N
f o r
e a s e I - R 2
The debounce feature should be enable when below GPIOs is used as external interrupt source,
l
Re Pi B P
Table 1-8: EINT source usage notes
EINT Controller Source
a
Pin NamePAD Notes
(eirq_bus[168:0])
EINT0
n a n 0 Need Enable Debounce Feature
Ba
EINT1 1 Need Enable Debounce Feature
f o r
1.5 GPIO Usage Tips
e a s e I - R 2
l
MIPI Tx pins in below table are analog and digital shared pins. In GPIO mode, these pins can only be
Re Pi B P
used as GPI. These pins must be set to MIPI mode or GPI mode at the same time to get good
performance.
MIPI_TCN
a n a Table 1-9: GPIO use MIPI-DSI Tx pin

GPI95
Ba n
MIPI_TCP
MIPI_TDN1
MIPI_TDP1
GPI96
GPI97
GPI98
MIPI_TDN0 GPI99
MIPI_TDP0 GPI100
There are two special pins (I2S0_MCLK and I2S1_MCLK) cannot be used as normal GPIO. These
pins will output MCLK after boot-up until software modify their mode selection setting. Because these
pins’ aux function default are MCLK output
f o r
e
Table 1-10: GPIO use I2S MCLK
I2S0_MCLK
l e a s I - R 2 GPIO126
Re Pi B
I2S1_MCLK
P GPIO37
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
l
Re Pi B P
1.6 Register Definition
a n a
Address
10005000
Name
Ba
GPIO_DIR1
n
Module name: GPIO Base address: (+10005000h)
Width
16
Register Function
GPIO Direction Control Register 1
10005010 GPIO_DIR2 16 GPIO Direction Control Register 2
r
10005090
100050A0
GPIO_DIR10
GPIO_DIR11
e f o 16
16
2
100050B0
100050C0
MSDC1_CTRL6
GPIO_DIR12
l e a s I
16
-
16
R
MSDC 1 INS Pad Control Register 3
100050D0
100050E0
100050F0
GPIO_DIR13
GPIO_DIR14
GPIO_DIR15
Re Pi B P 16
16
16
10005100 GPIO_DIR16
a n a 16 GPIO Direction Control Register 16
n
Ba
10005130 SDIO_CTRL4 16 SDIO DATA Pad Control Register 2
10005140 SDIO_CTRL5 16 SDIO DATA Pad Control Register 3
10005150 GPIO_PULLEN1 16 GPIO Pull-up/Pull-down Enable Register 1
100051A0 GPIO_PULLEN6 16 GPIO Pull-up/Pull-down Enable Register 6
100051B0 GPIO_PULLEN7 16 GPIO Pull-up/Pull-down Enable Register 7
100051C0 GPIO_PULLEN8 16 GPIO Pull-up/Pull-down Enable Register 8
100051D0
100051E0
GPIO_PULLEN9
GPIO_PULLEN10
f o r16
16
GPIO Pull-up/Pull-down Enable Register 9
100051F0
10005200
GPIO_PULLEN11
GPIO_PULLEN12
e a s e I
16
-
16
R 2 GPIO Pull-up/Pull-down Enable Register 11

10005210
10005220
10005230
GPIO_PULLEN13
GPIO_PULLEN14
GPIO_PULLEN15
l
Re Pi B P 16
16
16
a n a
n
Ba
MT7623N
f o r
e a s e
I - R 2
10005240
10005250
10005260
GPIO_PULLEN16
GPIO_PULLEN17
GPIO_PULLEN18
l
Re Pi B P
16
16
16
a
10005280 GPIO_PULLSEL1 16 GPIO Pull-up/Pull-down Selection Register 1
10005290
100052A0
GPIO_PULLSEL2
GPIO_PULLSEL3
n a n 16
16
GPIO Pull-up/Pull-down Selection Register 2
Ba
100052B0 GPIO_PULLSEL4 16 GPIO Pull-up/Pull-down Selection Register 4
100052C0 GPIO_PULLSEL5 16 GPIO Pull-up/Pull-down Selection Register 5
100052D0 GPIO_PULLSEL6 16 GPIO Pull-up/Pull-down Selection Register 6
100052E0 GPIO_PULLSEL7 16 GPIO Pull-up/Pull-down Selection Register 7
100052F0 GPIO_PULLSEL8 16 GPIO Pull-up/Pull-down Selection Register 8
r
10005360
10005370
GPIO_PULLSEL15
GPIO_PULLSEL16
e f o 16
16
2
10005380
10005390
GPIO_PULLSEL17
GPIO_PULLSEL18
l e a s I
16
-
16
R
100053A0
10005410
10005420
SDIO_CTRL7
BIAS_CTRL3
BIAS_CTRL4 Re Pi B P 16
16
16
SDIO RCLK Pad Control Register 3
18OD33 IO Group BIAS Control Register 3
10005430 SDIO_CTRL8
a n a 16 SDIO RCLK SEL Control Register
n
10005440 OD33_CTRL11 16 18OD33 IO Group TDSEL/RDSEL Control Register 11
Ba
100054C0 OD33_CTRL8 16 18OD33 IO Group TDSEL/RDSEL Control Register 8
100054D0 OD33_CTRL9 16 18OD33 IO Group TDSEL/RDSEL Control Register 9
100054E0 OD33_CTRL10 16 18OD33 IO Group TDSEL/RDSEL Control Register 10
10005500 GPIO_DOUT1 16 GPIO Data Output Register 1
10005550
10005560
GPIO_DOUT6
GPIO_DOUT7
f o r16
16
GPIO Data Output Register 6
10005570
10005580
GPIO_DOUT8
GPIO_DOUT9
e a s e I
16
-
16
R 2 GPIO Data Output Register 8

10005590
100055A0
100055B0
GPIO_DOUT10
GPIO_DOUT11
GPIO_DOUT12
l
Re Pi B P 16
16
16
a n a
n
Ba
MT7623N
f o r
e a s e
I - R 2
100055C0
100055D0
100055E0
GPIO_DOUT13
GPIO_DOUT14
GPIO_DOUT15
l
Re Pi B P
16
16
16
a
100055F0 GPIO_DOUT16 16 GPIO Data Output Register 16
10005600
10005610
GPIO_DOUT17
GPIO_DOUT18
n a n 16
16
Ba
10005620 SDIO_CTRL6 16 SDIO Pad Control Register
10005630 GPIO_DIN1 16 GPIO Data Input Register 1
100056A0 GPIO_DIN8 16 GPIO Data Input Register 8
100056B0 GPIO_DIN9 16 GPIO Data Input Register 9
r
100056C0 GPIO_DIN10 16 GPIO Data Input Register 10
100056D0
100056E0
GPIO_DIN11
GPIO_DIN12
e f o 16
16
2
GPIO Data Input Register 11
100056F0
10005700
GPIO_DIN13
GPIO_DIN14
l e a s I
16
-
16
R
10005710
10005720
10005730
GPIO_DIN15
GPIO_DIN16
GPIO_DIN17 Re Pi B P 16
16
16
10005740 GPIO_DIN18
a n a 16 GPIO Data Input Register 18
n
10005760 GPIO_MODE1 16 GPIO Mode Control Register 1
Ba
100057A0 GPIO_MODE5 16 GPIO Mode Control Register 5
100057B0 GPIO_MODE6 16 GPIO Mode Control Register 6
100057C0 GPIO_MODE7 16 GPIO Mode Control Register 7
100057D0 GPIO_MODE8 16 GPIO Mode Control Register 8
100057E0 GPIO_MODE9 16 GPIO Mode Control Register 9
100057F0 GPIO_MODE10 16 GPIO Mode Control Register 10
10005820
10005830
GPIO_MODE13
GPIO_MODE14
f o r16
16
GPIO Mode Control Register 13
10005840
10005850
GPIO_MODE15
GPIO_MODE16
e a s e I
16
-
16
R 2 GPIO Mode Control Register 15

10005860
10005870
10005880
GPIO_MODE17
GPIO_MODE18
GPIO_MODE19
l
Re Pi B P 16
16
16
a n a
n
Ba
MT7623N
f o r
e a s e
I - R 2
10005890
100058A0
100058B0
GPIO_MODE20
GPIO_MODE21
GPIO_MODE22
l
Re Pi B P
16
16
16
a
100058C0 GPIO_MODE23 16 GPIO Mode Control Register 23
100058D0
100058E0
GPIO_MODE24
GPIO_MODE25
n a n 16
16
Ba
100058F0 GPIO_MODE26 16 GPIO Mode Control Register 26
r
100059A0
100059B0
GPIO_MODE37
GPIO_MODE38
e f o 16
16
2
100059C0
100059D0
GPIO_MODE39
GPIO_MODE40
l e a s I
16
-
16
R
100059E0
100059F0
10005A00
GPIO_MODE41
GPIO_MODE42
GPIO_MODE43 Re Pi B P 16
16
16
10005A10 GPIO_MODE44
a n a 16 GPIO Mode Control Register 44
n
Ba
10005AA0 GPIO_MODE53 16 GPIO Mode Control Register 53
10005AB0 GPIO_MODE54 16 GPIO Mode Control Register 54
10005AC0 GPIO_MODE55 16 GPIO Mode Control Register 55
10005AD0 GPIO_MODE56 16 GPIO Mode Control Register 56
10005B10
10005B20
GPIO_BANK
IES_EN0
f o r16
16
GPIO Misc Control Register
GPIO IES Control Register 0
10005B30
10005B40
IES_EN1
IES_EN2
e a s e I
16
-
16
R 2 GPIO IES Control Register 1

10005B50
10005B60
10005B70
SMT_EN0
SMT_EN1
SMT_EN2
l
Re Pi B P 16
16
16
GPIO SMT Control Register 0
a n a
n
Ba
MT7623N
f o r
e a s e
I - R 2
10005B80
10005B90
10005BA0
TDSEL0
TDSEL1
TDSEL2
l
Re Pi B P
16
16
16
GPIO TDSEL Control Register 0
a
10005BB0 TDSEL3 16 GPIO TDSEL Control Register 3
10005BC0
10005BD0
TDSEL4
TDSEL5
n a n 16
16
Ba
10005BE0 OD33_CTRL4 16 18OD33 IO Group TDSEL/RDSEL Control Register 4
10005BF0 OD33_CTRL5 16 18OD33 IO Group TDSEL/RDSEL Control Register 5
10005C20 RDSEL0 16 GPIO RDSEL Control Register 0
10005C70 RDSEL5 16 GPIO RDSEL Control Register5
r
10005C80 DRVN0_EN 16 GPIO Control DDR Register
10005CA0
10005CC0
DRVP0_EN
MSDC0_CTRL0
e f o 16
16
2
GPIO Control DDR Register
MSDC 0 CLK Pad Control Register
10005CD0
10005CE0
MSDC0_CTRL1
MSDC0_CTRL2
l e a s I
16
-
16
R
MSDC 0 CMD Pad Control Register
MSDC 0 DATA Pad Control Register 0
10005CF0
10005D00
10005D10
MSDC0_CTRL3
MSDC0_CTRL4
MSDC0_CTRL5 Re Pi B P 16
16
16
10005D20 MSDC0_CTRL6
a n a 16 MSDC 0 Pad Control Register
n
10005D30 MSDC1_CTRL0 16 MSDC 1 CLK Pad Control Register
Ba
10005D40 MSDC1_CTRL1 16 MSDC 1 CMD Pad Control Register
10005D50 MSDC1_CTRL2 16 MSDC 1 DATA Pad Control Register 0
10005D80 MSDC1_CTRL5 16 MSDC 1 Pad Control Register
10005DF0 GPIO_TM 16 GPIO DIR Status Selection Register
10005E00 GPIO_USB 16 USB IDDIG GPIO PULLUP Control Register
10005E50
10005E60
KPAD_CTRL0
KPAD_CTRL1
f o r16
16
Keypad ROW Pad R0/R1/PUPD Control Register 0
Keypad COL Pad R0/R1/PUPD Control Register 1
10005E70
10005E80
EINT_CTRL0
EINT_CTRL1
e a s e I
16
-
16
R 2 EINT Pad R0/R1/PUPD Control Register 0

EINT Pad R0/R1/PUPD Control Register 1
10005EB0
10005EC0
10005ED0
BIAS_CTRL0
BIAS_CTRL1
BIAS_CTRL2
l
Re Pi B P 16
16
16
a n a
n
Ba
MT7623N
f o r
e a s e
I - R 2
10005F00
10005F10
10005F30
DRV_SEL10
DRV_SEL11
DRV_SEL12
l
Re Pi B P
16
16
16
GPIO Driving Control Register 10
a
10005F40 SDIO_CTRL3 16 SDIO DATA Pad Control Register 1
10005F50
10005F60
DRV_SEL0
DRV_SEL1
n a n 16
16
Ba
10005F70 DRV_SEL2 16 GPIO Driving Control Register 2
10005FA0 DRV_SEL5 16 GPIO Driving Control Register 5
10005FB0 DRV_SEL6 16 GPIO Driving Control Register 6
10005FC0 SDIO_CTRL2 16 SDIO DATA Pad Control Register 0
10005FD0 DRV_SEL8 16 GPIO Driving Control Register 8
10005FE0 DRV_SEL7 16 GPIO Driving Control Register 7
10005FF0 DRV_SEL9 16 GPIO Driving Control Register 9
1000500
f o r
0
Bit 15
GPIO_DIR1
14 13 12
e a s e 11
I - R
210 9 8 7 6 5 4 3 2 1
0000
Mne
Type
GPI
O15
_D
RW
GPI
O14
_D
RW
GPI
O13
_D
RW
l
Re Pi B
GPI
O12
_D
RW
_D
RW
P
GPI
O11
GPI
O1
0_
D
RW
GPI
O9
_D
RW
GPI
O8
_D
RW
GPI
O7
_D
RW
GPI
O6
_D
RW
GPI
O5
_D
RW
GPI
O4
_D
RW
GPI
O3
_D
RW
GPI
O2
_D
RW
GPI
O1
_D
RW
GPI
O0
_D
RW
Reset 0 0 0
a n
0
a 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
15
Mnemon
ic
GPIO15_
D
Ba n Name
GPIO15_DIR
Description
GPIO 15 Direction Control

0: Input
1: Output
GPIO14_
14 GPIO14_DIR 0: Input
D
1: Output
GPIO13_
D
1: Output
GPIO12_
12 GPIO12_DIR
r
D 0: Input
o
1: Output
11
GPIO11_
D
s
GPIO11_DIR
e f 2
0: Input
l e a P I - R 1: Output
Re Pi B
GPIO10_
D
1: Output
9 GPIO9_D GPIO9_DIR GPIO 9 Direction Control
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
e a s e I - R 2 Description
8
GPIO8_
l
Re Pi B
GPIO8_DIR
P 0: Input
1: Output
0: Input
a
D
1: Output
7 GPIO7_D
n a n
GPIO7_DIR
Ba
0: Input
1: Output
6 GPIO6_D GPIO6_DIR 0: Input
1: Output
1: Output
1: Output
f o r 1: Output
2 GPIO2_D GPIO2_DIR
e a s e I - R 2 0: Input
1: Output
1 GPIO1_D
GPIO0_
l
Re Pi B
GPIO1_DIR
P
0: Input
1: Output
0
D
a n a
GPIO0_DIR 0: Input
1: Output
10005010 GPIO_DIR2
Ba n GPIO Direction Control Register 2 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI
GPI GPI GPI GPI GPI
O3 O2 O2 O2 O2 O2 O2 O2 O2 O2 O1
Mne O31
0_ 9_ 8_ 7_ 6_ 5_ 4_ 3_ 2_
O21
0_
O19
8_
O17 O16
_D _D _D _D _D
D D D D D D D D D D D
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
15
GPIO31_
GPIO31_DIR
f o r GPIO 31 Direction Control

0: Input
e
D
2
1: Output
14
GPIO30_
l e
GPIO30_DIR
a s I - R GPIO 30 Direction Control
0: Input
P
D
Re Pi B
1: Output
GPIO29_
D
a n a 1: Output
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
12
GPIO28_
D l
Re Pi B
GPIO28_DIR
P GPIO 28 Direction Control
0: Input
1: Output
a
GPIO27_
11
D
n a n
GPIO27_DIR 0: Input
1: Output
Ba
GPIO26_
D
1: Output
GPIO25_
D
1: Output
GPIO24_
D
1: Output
GPIO23_
D
1: Output
r
GPIO22_
6
D
GPIO22_DIR
e f o 2
0: Input
1: Output
s
R
GPIO21_
5
D
GPIO21_DIR
l e a P I -
0: Input
1: Output
Re Pi B
GPIO20_
D
1: Output
3
GPIO19_
D
a n a
GPIO19_DIR
0: Input
2
GPIO18_
D
Ba n
GPIO18_DIR
1: Output
0: Input
1: Output
GPIO17_
D
1: Output
GPIO16_
D
1: Output
10005020
Bit 15
GPIO_DIR3
14 13 12 11
f r
o10 9 8 7 6 5 4 3 2 1
0000
0
Mne
GPI
O4
7_
GPI
O4
6_
GPI
O4
5_
GPI
O4
4_
e
GPI
O4
a
3_
s e GPI
O4
2_
I - R 2 GPI
O41
_D
GPI
O4
0_
GPI
O3
9_
GPI
O3
8_
GPI
O3
7_
GPI
O3
6_
GPI
O3
5_
GPI
O3
4_
GPI
O3
3_
GPI
O3
2_
Type
Reset
D
RW
0
D
RW
0
D
RW
0
D
RW
0
l
Re Pi B
D
RW
0
P
D
RW
0
RW
0
D
RW
0
D
RW
0
D
RW
0
D
RW
0
D
RW
0
D
RW
0
D
RW
0
D
RW
0
D
RW
0
a n a
n
B a
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
15
GPIO47_
D l
Re Pi B
GPIO47_DIR
0: Input
1: Output
a
GPIO46_
14
D
n a n
GPIO46_DIR 0: Input
1: Output
Ba
GPIO45_
D
1: Output
GPIO44_
D
1: Output
GPIO43_
D
1: Output
GPIO42_
D
1: Output
r
GPIO41_
9
D
GPIO41_DIR
e f o 2
0: Input
1: Output
s
R
GPIO40_
8
D
GPIO40_DIR
l e a P I -
0: Input
1: Output
Re Pi B
GPIO39_
D
1: Output
6
GPIO38_
D
a n a
GPIO38_DIR
0: Input
5
GPIO37_
D
Ba n
GPIO37_DIR
1: Output
0: Input
1: Output
GPIO36_
D
1: Output
GPIO35_
D
1: Output
GPIO34_
D
1: Output
1
GPIO33_
D
GPIO33_DIR

0: Input
0
GPIO32_
e a
GPIO32_DIR
s e I - R 2
1: Output
l
D 0: Input
Re Pi B P 1: Output
a n a
n
Ba
MT7623N
f o r
10005030 GPIO_DIR4
e a s e I - R 2
GPIO Direction Control Register 4 0000
l
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne
GPI
O6
3_
D
GPI
O6
2_
D
GPI
O61
_D
Re Pi B
GPI
O6
0_
D
GPI
O5
9_
D
P GPI
O5
8_
D
GPI
O5
7_
D
GPI
O5
6_
D
GPI
O5
5_
D
GPI
O5
4_
D
GPI
O5
3_
D
GPI
O5
2_
D
GPI
O51
_D
GPI
O5
0_
D
GPI
O4
9_
D
GPI
O4
8_
D
Type
Reset
RW
0
RW
0
RW
0
a
RW
n
0
a RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit(s
)
Mnemon
ic
GPIO63_ Ba n Name Description

D
1: Output
GPIO62_
D
1: Output
GPIO61_
D
1: Output
12
GPIO60_
D
GPIO60_DIR
f o r 0: Input
1: Output
11 Reserved
GPIO58_
Reserved
e a s e I - R 2
Reserved
l
9
D
GPIO57_
D Re Pi B
GPIO57_DIR
P 1: Output
0: Input
GPIO56_
a n a 1: Output
8
7
D
GPIO55_
D Ba n
GPIO56_DIR
GPIO55_DIR
0: Input
1: Output
0: Input
1: Output
GPIO54_
D
1: Output
GPIO53_
D
1: Output
GPIO52_
D
GPIO51_
f o r 1: Output
3
D
GPIO51_DIR
e a s e I - R 2
0: Input
1: Output
2
1
GPIO50_
D
GPIO49_
D
l
Re Pi B
GPIO50_DIR
GPIO49_DIR
P 0: Input
1: Output
a
0: Input
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
0
GPIO48_
D
l
Re Pi B
GPIO48_DIR P 1: Output
0: Input
1: Output
a n a
10005040
Bit 15
GPI
GPIO_DIR5
14
GPI Ba
13
GPI
n 12
GPI
11
GPI
10
GPI
9
GPI
8
GPI
7
GPI
6
GPI
5
GPI
4
GPI
3
GPI
2
GPI
1
GPI
0000
0
GPI
O7 O7 O7 O7 O7 O7 O7 O7 O6 O6 O6 O6 O6 O6
Mne O77 O71
9_ 8_ 6_ 5_ 4_ 3_ 2_ 0_ 9_ 8_ 7_ 6_ 5_ 4_
_D _D
D D D D D D D D D D D D D D
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
GPIO79_
15
D
GPIO79_DIR
f o r 0: Input
1: Output
14
GPIO78_
D
GPIO78_DIR
e a s e I - R 2
0: Input
1: Output
13
GPIO77_
D l
Re Pi B
GPIO77_DIR
0: Input
1: Output
a
GPIO76_
12
D
n a n
GPIO76_DIR 0: Input
1: Output
Ba
GPIO75_
D
1: Output
GPIO74_
D
1: Output
GPIO73_
D
1: Output
GPIO72_
D
1: Output
r
GPIO71_
7
D
GPIO71_DIR
e f o 2
0: Input
1: Output
s
R
GPIO70_
6
D
GPIO70_DIR
l e a P I -
0: Input
1: Output
Re Pi B
GPIO69_
D
1: Output
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
4
GPIO68_
D l
Re Pi B
GPIO68_DIR
0: Input
1: Output
a
GPIO67_
3
D
n a n
GPIO67_DIR 0: Input
1: Output
Ba
GPIO66_
D
1: Output
GPIO65_
D
1: Output
GPIO64_
D
1: Output
10005050 GPIO_DIR6 GPIO Direction Control Register 6 0000

Bit 15
GPI
14
GPI
13
GPI
12
GPI
11
f o r
10
GPI
9
GPI
8
GPI
7
GPI
6
GPI
5
GPI
4
GPI
3
GPI
2
GPI
1
GPI
0
GPI
e
GPI
2
O9 O9 O9 O9 O9 O8 O8 O8 O8 O8 O8 O8 O8 O8 O8
Mne
5_
D
4_
D
3_
D
2_
D
l e
O91
a
_D
s 0_
I
D
- R
9_
D
8_
D
7_
D
6_
D
5_
D
4_
D
3_
D
2_
D
1_
D
0_
D
P
Re Pi B
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
) ic
Name
a n a Description

15
14:11
GPIO95_
D
Reserved
B a n
GPIO95_DIR
Reserved
0: Input
1: Output
Reserved
GPIO90_
D
1: Output
GPIO89_
D
1: Output
GPIO88_
D
1: Output
r
GPIO87_
7
D
GPIO87_DIR
e f o 2
0: Input
1: Output
6
GPIO86_
D
GPIO86_DIR
l e a s I - R
0: Input
P
1: Output
Re Pi B
GPIO85_
D
1: Output
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
4
GPIO84_
D l
Re Pi B
GPIO84_DIR
0: Input
1: Output
a
GPIO83_
3
D
n a n
GPIO83_DIR 0: Input
1: Output
Ba
GPIO82_
D
1: Output
GPIO81_
D
1: Output
GPIO80_
D
1: Output

Bit 15
GPI
14
GPI
13
GPI
12
GPI
11
GPI
f o r
10
GPI
9
GPI
8
GPI
7
GPI
6
GPI
5
GPI
4
GPI
3
GPI
2
GPI
1
GPI
0
GPI
Mne O11
1_
D
O11
0_
D
O1
09
_D
O1
08
_D
e
O1
a
07_
D
s e O1
06
I
_D
- R 2
O1
05
_D
O1
04
_D
O1
03
_D
O1
02
_D
O1
01_
D
O1
00
_D
O9
9_
D
O9
8_
D
O9
7_
D
O9
6_
D
Type
Reset
Bit(s
RW
0
Mnemon
RW
0
RW
0
RW
0
l
Re Pi B
RW
0
P
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
) ic
Name
a n a Description

15
14
GPIO111_
D
GPIO110
_D
B a n
GPIO111_DIR
GPIO110_DIR
0: Input
1: Output
0: Input
1: Output
GPIO109
_D
1: Output
GPIO108
_D
1: Output
GPIO107
11 GPIO107_DIR
r
_D 0: Input
o
1: Output
10
GPIO106
_D
GPIO106_DIR
s e f 2
0: Input
Re Pi B
GPIO105
_D
1: Output
8 GPIO104 GPIO104_DIR GPIO 104 Direction Control
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
7
_D
GPIO103
l
Re Pi B
GPIO103_DIR
P 0: Input
1: Output
0: Input
a
_D
1: Output
6
GPIO102
n a n
GPIO102_DIR
Ba
_D 0: Input
1: Output
GPIO101
_D
1: Output
GPIO100
_D
1: Output
GPIO99_
D
1: Output
GPIO98_
r
D
1: Output
1
GPIO97_
GPIO97_DIR
e f o 2
s
D 0: Input
Re Pi B
GPIO96_
D
1: Output
a n a
10005070
Bit
Mne
15
GPI
O12
7_
GPIO_DIR8
14
GPI
O12
6_ Ba
13
GPI
O12
5_
n 12
GPI
O12
4_
11
GPI
O12
3_
10
GPI
O12
2_
9
GPI
O12
1_
8
GPI
O12
0_
7
GPI
O11
9_
6
GPI
O11
8_
5
GPI
O11
7_
4
GPI
O11
6_
3
GPI
O11
5_
2
GPI
O11
4_
1
GPI
O11
3_
0000
0
GPI
O11
2_
D D D D D D D D D D D D D D D D
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
15 Reserved Reserved Reserved
GPIO126
14 GPIO126_DIR
r
_D 0: Input
o
1: Output
13
GPIO125
_D
GPIO125_DIR
s e f 2
0: Input
Re Pi B
GPIO124
_D
1: Output
11 GPIO123 GPIO123_DIR GPIO 123 Direction Control
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
10
_D
GPIO122
l
Re Pi B
GPIO122_DIR
P 0: Input
1: Output
0: Input
a
_D
1: Output
9
GPIO121
n a n
GPIO121_DIR
Ba
_D 0: Input
1: Output
GPIO120
_D
1: Output
GPIO119
_D
1: Output
GPIO118
_D
1: Output
GPIO117
r
_D
1: Output
4
GPIO116
GPIO116_DIR
e f o 2
s
_D 0: Input
Re Pi B
GPIO115
_D
1: Output
GPIO114
2
_D
a n a
GPIO114_DIR 0: Input
1: Output
0
GPIO113
_D
GPIO112 Ba n
GPIO113_DIR
GPIO112_DIR
0: Input
1: Output
0: Input
_D
1: Output
1000508
GPIO_DIR9 GPIO Direction Control Register 9 0000
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI
r
O14 O14 O14 O14 O13 O13 O13 O13 O13 O13 O13 O13 O13 O13 O12 O12
Mne
Type
3_
D
RW
2_
D
RW
1_
D
RW
0_
D
RW
9_
e
D
RW
f o 8_
D
RW
2
7_
D
RW
6_
D
RW
5_
D
RW
4_
D
RW
3_
D
RW
2_
D
RW
1_
D
RW
0_
D
RW
9_
D
RW
8_
D
RW
Reset 0 0 0 0
l e a s 0
I - R
0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
15:0
Mnemon
ic
Reserved
Re Pi B
Name
Reserved
P Description
Reserved
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
10005090
Bit 15
GPI
GPIO_DIR10
14
GPI
13
GPI
l
Re Pi B
12
GPI
P
11
GPI
10
GPI
9
GPI
8
GPI
7
GPI
6
GPI
5
GPI
4
GPI
3
GPI
2
GPI
1
GPI
0000
0
GPI
Mne O15
9_
D
O15
8_
D
O15
7_
D
a n
6_
D
a
O15 O15
5_
D
O15
4_
D
O15
3_
D
O15
2_
D
O15
1_
D
O15
0_
D
O14
9_
D
O14
8_
D
O14
7_
D
O14
6_
D
O14
5_
D
O14
4_
D
Type
Reset
Bit(s
RW
0
Mnemon
RW
0
RW
0
Ba n RW
0
Name
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Description
RW
0
RW
0
RW
0
RW
0
RW
0
) ic
15:0 Reserved Reserved Reserved
100050A
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne
GPI
O17
5_
GPI
O17
4_
GPI
O17
3_
GPI
O17
2_
GPI
O17
f
1_
o r GPI
O17
0_
GPI
O16
9_
GPI
O16
8_
GPI
O16
7_
GPI
O16
6_
GPI
O16
5_
GPI
O16
4_
GPI
O16
3_
GPI
O16
2_
GPI
O16
1_
GPI
O16
0_
Type
Reset
D
RW
0
D
RW
0
D
RW
0
D
RW
0
e a s e D
RW
0
I - R
D
2
RW
0
D
RW
0
D
RW
0
D
RW
0
D
RW
0
D
RW
0
D
RW
0
D
RW
0
D
RW
0
D
RW
0
D
RW
0
Bit(s
)
Mnemon
ic
l
Re Pi B
Name P Description
15:0 Reserved
a
Reserved
a n
Reserved
100050B
0
MSDC1_CTR
L6
Ba n MSDC 1 INS Pad Control Register 3 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MS
1IN
MS1INS_BACK
Mne MS1INS_BACKUP1 S_
UP0
SM
T
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
)
15:4
ic
MS1INS_BACKU
f o r Reserved
3
P1
e
MS1INS_SMT
a s e I - R 2 Schmitter Trigger
l
0:Disable
2:0
Re Pi B
MS1INS_BACKU
P0 P 1:Enable
Reserved
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
100050C
0
Bit 15
GPI
GPIO_DIR12
14
GPI
13
GPI
l
Re Pi B
12
GPI
11
GPI
P GPIO Direction Control Register 12
10
GPI
9
GPI
8
GPI
7
GPI
6
GPI
5
GPI
4
GPI
3
GPI
2
GPI
1
GPI
0000
0
GPI
Mne O19
1_
D
O19
0_
D
O1
89
_D
a
O1
n
88
_D
a O1
87_
D
O1
86
_D
O1
85
_D
O1
84
_D
O1
83
_D
O1
82
_D
O1
81_
D
O1
80
_D
O17
9_
D
O17
8_
D
O17
7_
D
O17
6_
D
Type
Reset
Bit(s
RW
0
Mnemon
RW
0
RW
Ba
0
n RW
0
Name
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Description
RW
0
RW
0
RW
0
RW
0
RW
0
) ic
GPIO191
_D
1: Output
GPIO190
_D
1: Output
GPIO189
_D
f o r 1: Output
12
GPIO188
_D
GPIO188_DIR
e a s e I - R 2 0: Input
1: Output
11:0 Reserved
l
Reserved
Re Pi B P
Reserved
100050D
0
GPIO_DIR13
a n a GPIO Direction Control Register 13 0000
Bit
Mne
15
GPI
O2
07_
D
14
GPI
O2
06
_D
13
Ba
GPI
O2
05
_D
n 12
GPI
O2
04
_D
11
GPI
O2
03
_D
10
GPI
O2
02
_D
9
GPI
O2
01_
D
O2
00
_D
8
GPI
7
GPI
O19
9_
D
6
GPI
O19
8_
D
5
GPI
O19
7_
D
4
GPI
O19
6_
D
3
GPI
O19
5_
D
2
GPI
O19
4_
D
1
GPI
O19
3_
D
0
GPI
O19
2_
D
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
GPIO207
_D
1: Output
r
GPIO206
14
_D
GPIO206_DIR
e f o 2
0: Input
1: Output
13
GPIO205
_D
GPIO205_DIR
l e a s I - R
0: Input
1: Output
12
GPIO204
_D
Re Pi B
GPIO204_DIR P GPIO 204 Direction Control
0: Input
1: Output
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
11
GPIO203
_D l
Re Pi B
GPIO203_DIR
0: Input
1: Output
a
GPIO202
10
_D
n a n
1: Output
Ba
GPIO201
_D
1: Output
GPIO200
_D
1: Output
GPIO199
_D
1: Output
GPIO198
_D
1: Output
r
GPIO197
5
_D
GPIO197_DIR
e f o 2
0: Input
1: Output
s
R
GPIO196
4
_D
GPIO196_DIR
l e a P I -
0: Input
1: Output
Re Pi B
GPIO195
_D
1: Output
2
GPIO194
_D
a n a
GPIO194_DIR
0: Input
1
GPIO193
_D
Ba n
GPIO193_DIR
1: Output
0: Input
1: Output
GPIO192
_D
1: Output
100050E
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne
GPI
O2
23_
GPI
O2
22_
GPI
O2
21_
GPI
O2
20
GPI
9_
f
O21
o r GPI
O21
8_
GPI
O21
7_
GPI
O21
6_
GPI
O21
5_
GPI
O21
4_
GPI
O21
3_
GPI
O21
2_
GPI
O21
1_
GPI
O21
0_
GPI
O2
09
GPI
O2
08
Type
Reset
D
RW
0
D
RW
0
D
RW
0
_D
RW
0
e a s eD
RW
0
I - R
D
RW
0
2
D
RW
0
D
RW
0
D
RW
0
D
RW
0
D
RW
0
D
RW
0
D
RW
0
D
RW
0
_D
RW
0
_D
RW
0
Bit(s
)
Mnemon
ic
l
Re Pi B
Name P Description
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
15:2
1
Reserved
GPIO209
_D
l
Re Pi B
Reserved
GPIO209_DIR P Reserved
0: Input
a
1: Output
0
GPIO208
_D
a n
GPIO208_DIR
n
0: Input
Ba
1: Output
100050F
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne
39 38 37_ 36 35_ 34 33_ 32_ 31_ 30 29 28 27_ 26 25_ 24_
_D _D D _D D _D D D D _D _D _D D _D D D
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name
f o r Description
e
) ic
15
GPIO239
_D
e
GPIO239_DIR
l a s I - R 2 GPIO 239 Direction Control

0: Input
14
GPIO238
_D
Re Pi B
0: Input
a
1: Output
13
GPIO237
_D
a n
GPIO237_DIR
n
0: Input
Ba
1: Output
GPIO236
_D
1: Output

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne
55_ 54_ 53_ 52_ 51_ 50 49 48 47_ 46 45_ 44 43_ 42 41_ 40
Type
D
RW
D
RW
D
RW
D
RW
D
RW
f o r _D
RW
_D
RW
_D
RW
D
RW
_D
RW
D
RW
_D
RW
D
RW
_D
RW
D
RW
_D
RW
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
l e a s I - R 2
P
Name Description
Re Pi B
) ic
GPIO255
_D
a
1: Output
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
14
GPIO254
_D l
Re Pi B
GPIO254_DIR
0: Input
1: Output
a
GPIO253
13
_D
n a n
1: Output
Ba
GPIO252
_D
1: Output
GPIO251
_D
1: Output
GPIO250
_D
1: Output
GPIO249
_D
1: Output
r
GPIO248
8
_D
GPIO248_DIR
e f o 2
0: Input
1: Output
s
R
GPIO247
7
_D
GPIO247_DIR
l e a P I -
0: Input
1: Output
Re Pi B
GPIO246
_D
1: Output
5
GPIO245
_D
a n a
GPIO245_DIR
0: Input
4
GPIO244
_D
Ba n
GPIO244_DIR
1: Output
0: Input
1: Output
GPIO243
_D
1: Output
GPIO242
_D
1: Output
GPIO241
_D
1: Output
0
GPIO240
_D
GPIO240_DIR

0: Input
e a s e I - R 2
1: Output
10005110
Bit 15
GPIO_DIR17
14 13
l
Re Pi B
12 11
P GPIO Direction Control Register 17
10 9 8 7 6 5 4 3 2 1
0000
0
a
Mne GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI
Ba
MT7623N
f o r
10005110 GPIO_DIR17
e a s e I - R 2
GPIO Direction Control Register 17 0000
l
Type
Reset
71_
D
RW
0
70_
D
RW
0
69
_D
RW
0
Re Pi B
68
_D
RW
0
D
RW
0
P
67_ 66
_D
RW
0
65_
D
RW
0
64
_D
RW
0
63
_D
RW
0
62
_D
RW
0
61_
D
RW
0
60
_D
RW
0
59_
D
RW
0
58
_D
RW
0
57_
D
RW
0
56_
D
RW
0
Bit(s Mnemon
a n a
)
15
ic
GPIO271
_D
Ba n Name
GPIO271_DIR
Description

0: Input
1: Output
GPIO270
_D
1: Output
GPIO269
_D
1: Output
GPIO268
_D
1: Output
11
GPIO267
GPIO267_DIR
0: Input
_D
GPIO266
e a s e I - R 2 1: Output
10
9
_D
GPIO265
l
GPIO266_DIR
Re Pi B
GPIO265_DIR
P
0: Input
1: Output
0: Input
a
_D
1: Output
8
GPIO264
n a n
GPIO264_DIR
0: Input
Ba
_D
1: Output
GPIO263
_D
1: Output
GPIO262
_D
1: Output
GPIO261
_D
1: Output
GPIO260
r
_D
1: Output
3
GPIO259
GPIO259_DIR
e f o 2
0: Input
_D
l e a s I - R
1: Output
P
GPIO258
Re Pi B
_D
1: Output
GPIO257 GPIO 257 Direction Control
1 GPIO257_DIR
a
_D 0: Input
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
0
GPIO256
_D
l
Re Pi B
0: Input
1: Output
a n a
10005120
Bit 15 14
Ba
GPIO_DIR18
13
n 12 11
10 9 8 7
GPI
6
GPI
5
GPI
4
GPI
3
GPI
2
GPI
1
GPI
0000
0
GPI
Nam O2 O2 O2 O2 O27 O2 O2 O2
e 79_ 78_ 77_ 76_ 5_ 74_ 73_ 72_
D D D D D D D D
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
6
GPIO278
_D
GPIO278_DIR

0: Input
5 Reserved
a
Reserved
e s e I - R 2
1: Output
Reserved
l
4
GPIO276
_D
GPIO275 Re Pi B
GPIO276_DIR
P 0: Input
1: Output
3
_D
a n a
1: Output
1
GPIO274
_D
Reserved
Ba n
GPIO274_DIR
Reserved
0: Input
1: Output
Reserved
GPIO272
_D
1: Output
MSDC3_CTR
10005130 MSDC 3DATA Pad Control Register 2 4444
L4
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
MS
3D
MS
3D
MS
3D
MS
3D
AT
MS
f
3D
AT
o r MS
3D
MS
3D
MS
3D
AT
MS
3D
MS
3D
MS
3D
MS
3D
AT
MS
3D
MS
3D
MS
3D
MS
3D
AT
e
AT AT AT AT AT AT AT AT AT AT AT
2
e 7_P 6_ 6_ 5_ 4_
7_S
MT
7_
R0
7_
R1
UP
l
D
e a s SM
T
I - R
6_
R0
6_
R1
PU
PD
5_S
MT
5_
R0
5_
R1
PU
PD
4_S
MT
4_
R0
4_
R1
PU
PD
P
Re Pi B
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
15
l
Re Pi B
MS3DAT7_SMT
P Schmitter Trigger Control
0:Disable
1:Enable
a
14 MS3DAT7_R0 10K resistot control
13
12
n n
MS3DAT7_R1
a
MS3DAT7_PUPD
50K resistor control
pull-up(0)/pull-down(1) control
Ba
Schmitter Trigger Control
11 MS3DAT6_SMT 0:Disable
1:Enable
9 MS3DAT6_R1 50K resistor control
8 MS3DAT6_PUPD pull-up(0)/pull-down(1) control
1:Enable
4 MS3DAT5_PUPD
f o r pull-up(0)/pull-down(1) control
3 MS3DAT4_SMT
e a s e I - R 2 0:Disable
1:Enable
2
1
0
l
MS3DAT4_R0
Re Pi B
MS3DAT4_R1
MS3DAT4_PUPD P
10K resistot control
a n a
10005140
Bit 15
MSDC3_CTR
14
L5
Ba
13
n 12 11
MSDC3 DATA Pad Control Register 3
10 9 8 7 6 5 4 3
MS
2 1
0404
0
MS
MS MS MS
MS MS 3R 3R
1IN 3R 3R
Nam MS0DAT_BACKUP
1IN 1IN
S_ MS3DAT_BACKUP0
ST
ST ST
ST
e S_ S_
PU
B_
B_ B_
B_
R0 R1 SM PU
PD R0 R1
T PD
Type RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0
Bit(s Mnemon
Name Description
) ic
15:11
MS0DAT_BACK
UP
f o r Reserved
10
9
MS1INS_R0
e a
MS1INS_R1
s e I - R 2 10K resistot control
8
7:4 l
Re Pi B
MS1INS_PUPD
MS3DAT_BACK
UP0 P pull-up(0)/pull-down(1) control
Reserved
3
a n a
MS3RSTB_SMT Schmitter Trigger Control
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
2
l
Re Pi B
MS3RSTB_R0 P 0:Disable
1:Enable
a
1 MS3RSTB_R1 50K resistor control
0
n a n
MS3RSTB_PUPD pull-up(0)/pull-down(1) control
10005150
Bit 15
GPIO_PULL
14
EN1
Ba
13 12
11 10 9 8 7 6 5 4 3 2 1
FFFF
0
GPI
GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI
Nam O15 O14 O13 O12 O11
O1
O9 O8 O7 O6 O5 O4 O3 O2 O1 O0
e _P _P _P _P _P
0_
_P _P _P _P _P _P _P _P _P _P
P
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s Mnemon
r
Name Description
) ic
15
GPIO15_ GPIO15_PULLE
e f o 2
GPIO 15 Pull-up/Pull-down Enable
s
P N 0: Disable
l e a P I - R 1: Enable
Re Pi B
14 0: Disable
P N
1: Enable
a
13 0: Disable
n
P N
1: Enable
n a GPIO 12 Pull-up/Pull-down Enable
Ba
12 0: Disable
P N
1: Enable
GPIO11_
11 GPIO11_PULLEN 0: Disable
P
1: Enable
10 0: Disable
P N
1: Enable
9 GPIO9_P GPIO9_PULLEN 0: Disable
1: Enable
8 GPIO8_P GPIO8_PULLEN
f o r 0: Disable
1: Enable
7 GPIO7_P GPIO7_PULLEN
e a s e I - R 2
0: Disable
1: Enable
6 GPIO6_P
l
Re Pi B
GPIO6_PULLEN
P GPIO 6 Pull-up/Pull-down Enable
0: Disable
1: Enable
a
5 GPIO5_P GPIO5_PULLEN GPIO 5 Pull-up/Pull-down Enable
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
4 GPIO4_P
l
Re Pi B
GPIO4_PULLEN
P 0: Disable
1: Enable
0: Disable
a n a 1: Enable
3
2
GPIO3_P
GPIO2_P
n
GPIO3_PULLEN
Ba
GPIO2_PULLEN
0: Disable
1: Enable
0: Disable
1: Enable
1: Enable
1: Enable
GPIO_PULL
f o r
e
10005160 GPIO Pull-up/Pull-down Enable Register 2 FFFF
2
EN2
Bit 15 14
GPI
13
GPI
12
l
GPI
e a s 11
I - R10
GPI
9
GPI
8
GPI
7
GPI
6
GPI
5 4
GPI
3 2
GPI
1 0
P
GPI GPI GPI GPI GPI GPI
Re Pi B
Nam O3 O2 O2 O2 O2 O2 O2 O2 O2 O1
O31 O2 O21 O19 O17 O16
e 0_ 9_ 8_ 6_ 5_ 4_ 3_ 2_ 0_ 8_
_P 7_P _P _P _P _P
P P P P P P P P P P
Reset 1 1 1
a
1
n a 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s
)
15
Mnemon
ic
GPIO31_
P Ba n Name
GPIO31_PULLE
N
Description

0: Disable
1: Enable
14 0: Disable
P N
1: Enable
13 0: Disable
P N
1: Enable
12 0: Disable
r
P N
1: Enable
11
e f o 2
s
P N 0: Disable
Re Pi B
10 0: Disable
P N
1: Enable
GPIO25_ GPIO25_PULLE GPIO 25 Pull-up/Pull-down Enable
9
P N
a n a 0: Disable
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
8
GPIO24_
P
l
Re Pi B
GPIO24_PULLE
N
P 1: Enable
0: Disable
1: Enable
7
GPIO23_
a n a
GPIO23_PULLE
0: Disable
6
P
GPIO22_
P
Ba n N
GPIO22_PULLE
N
1: Enable
0: Disable
1: Enable
5 0: Disable
P N
1: Enable
4 0: Disable
P N
1: Enable
3 0: Disable
P N
1: Enable
2
f o r GPIO 18 Pull-up/Pull-down Enable

0: Disable
e
P N
1
GPIO17_
l e a
GPIO17_PULLEN s I - R 2 1: Enable
P
0: Disable
Re Pi B
P
1: Enable
0 0: Disable
P N
a n a 1: Enable
10005170
GPIO_PULL
EN3
Ba n GPIO Pull-up/Pull-down Enable Register 3 FFFF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI
GPI GPI GPI GPI
Nam O4
O4 O4 O4 O4 O4
O41
O4 O3 O3
O3
O3
O3
O3 O3 O3
e 7_P
6_ 5_ 4_ 3_ 2_
_P
0_ 9_ 8_
7_P
6_
5_P
4_ 3_ 2_
P P P P P P P P P P P P
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s Mnemon
Name Description
) ic
15

0: Disable
e
P N
14
GPIO46_
e
GPIO46_PULLE
l a s I - R 2 1: Enable
P
0: Disable
Re Pi B
P N
1: Enable
GPIO45_ GPIO45_PULLE GPIO 45 Pull-up/Pull-down Enable
13
P N 0: Disable
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
12
GPIO44_
P
l
Re Pi B
GPIO44_PULLE
N
P 1: Enable
0: Disable
1: Enable
11
GPIO43_
a n a
GPIO43_PULLE
0: Disable
10
P
GPIO42_
P
Ba n N
GPIO42_PULLE
N
1: Enable
0: Disable
1: Enable
9 0: Disable
P N
1: Enable
8 0: Disable
P N
1: Enable
7 0: Disable
P N
1: Enable
6

0: Disable
e
P N
5
GPIO37_
e a
GPIO37_PULLE
l s I - R 2 1: Enable
P
0: Disable
Re Pi B
P N
1: Enable
4 0: Disable
P N
a n a 1: Enable
n
3 0: Disable
Ba
P N
1: Enable
2 0: Disable
P N
1: Enable
1 0: Disable
P N
1: Enable
0 0: Disable
P N
1: Enable
10005180
GPIO_PULL
f o r
GPIO Pull-up/Pull-down Enable Register 4 FFFF
Bit 15 14
EN4
13 12
e a s e11
I - R 2
10 9 8 7 6 5 4 3 2 1 0
l
GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI
P
GPI GPI GPI
Re Pi B
Nam O6 O6
O61
O6 O5 O5
O5
O5 O5 O5 O5 O5
O51
O5 O4 O4
e 3_ 2_
_P
0_ 9_ 8_
7_P
6_ 5_ 4_ 3_ 2_
_P
0_ 9_ 8_
P P P P P P P P P P P P P
a
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Ba
MT7623N
f o r
Bit(s Mnemon
e a s e I - R 2
)
15
ic
GPIO63_
P
l
Name
Re Pi B
GPIO63_PULLE
N
P
Description

0: Disable
a
1: Enable
14
GPIO62_
P
n aN
n
GPIO62_PULLE
0: Disable
Ba
1: Enable
13 0: Disable
P N
1: Enable
12 0: Disable
P N
1: Enable
10 0: Disable
P N
1: Enable
9
P N
f o r 0: Disable
1: Enable
e
8
GPIO56_
P
GPIO56_PULLE
N
l e a s I - R 2 0: Disable
1: Enable
7
GPIO55_
P
Re Pi B
GPIO55_PULLE
N
0: Disable
1: Enable
a
n
6 0: Disable
P N
n a 1: Enable
Ba
5 0: Disable
P N
1: Enable
4 0: Disable
P N
1: Enable
3 0: Disable
P N
1: Enable
2 0: Disable
P N
1: Enable
r
1
P N
e f o 2
0: Disable
1: Enable
s
R
0
P N
l e a P I -
0: Disable
1: Enable
Re Pi B
a n a
n
Ba
MT7623N
f o r
10005190
GPIO_PULL
EN5
e a s e I - R 2
Bit
Nam
e
15
GPI
O7
9_
14
GPI
O7
8_
13
GPI
O77
l
Re Pi B
12
GPI
O7
6_
11
GPI
O7
5_
P 10
GPI
O7
4_
O7
3_
9
GPI
O7
2_
8
GPI
7
GPI
O71
O7
0_
6
GPI
O6
9_
5
GPI
O6
8_
4
GPI
3
GPI
O6
2
GPI
O6
6_
1
GPI
O6
5_
0
GPI
O6
4_
a
_P _P 7_P
Type
Reset
RW
1
RW
1
RW
1
n a n
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
Bit(s
)
15
Mnemon
ic
GPIO79_
Ba Name
GPIO79_PULLE
Description

0: Disable
P N
1: Enable
14 0: Disable
P N
1: Enable
13 0: Disable
P N
1: Enable
12
GPIO76_
P
GPIO76_PULLE
N
0: Disable
GPIO75_
a
GPIO75_PULLE
e s e I - R 2
1: Enable
l
11 0: Disable
P
P N
Re Pi B
1: Enable
10 0: Disable
P N
a
1: Enable
9
GPIO73_
P
n aNn
GPIO73_PULLE
0: Disable
Ba
1: Enable
8 0: Disable
P N
1: Enable
GPIO71_
7 GPIO71_PULLEN 0: Disable
P
1: Enable
6 0: Disable
P N
1: Enable
5 0: Disable
P N
r
1: Enable
4
GPIO68_
P
GPIO68_PULLE
N
e f o 2
0: Disable
GPIO67_
l e
GPIO67_PULLE
a s I - R
1: Enable
3
2
P
GPIO66_
P Re Pi B
N
GPIO66_PULLE
N
P 0: Disable
1: Enable
0: Disable
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
1
GPIO65_
P
l
Re Pi B
GPIO65_PULLE
N
P 1: Enable
0: Disable
1: Enable
0
GPIO64_
a n a
GPIO64_PULLE
0: Disable
P
Ba n N
1: Enable
GPIO_PULL
100051A0 GPIO Pull-up/Pull-down Enable Register 6 FFFF
EN6
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPI GPI GPI
Nam O9 O9 O9 O9
O91
O9 O8 O8
O8
O8 O8 O8 O8 O8
O8
O8
e 5_ 4_ 3_ 2_
_P
0_ 9_ 8_
7_P
6_ 5_ 4_ 3_ 2_
1_P
0_
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s
)
Mnemon
ic
Name
f o r Description
15
e a s e I - R 2 GPIO 95 Pull-up/Pull-down Enable

0: Disable
l
P N
14
13
Reserved
Reserved
Re Pi B
Reserved
Reserved P 1: Enable
Reserved
Reserved
12
11
Reserved
Reserved
a n a
Reserved
Reserved
Reserved
Reserved
10
GPIO90_
P
GPIO89_ Ba n
GPIO90_PULLE
N
GPIO89_PULLE
0: Disable
1: Enable
9 0: Disable
P N
1: Enable
8 0: Disable
P N
1: Enable
7 0: Disable
P N
1: Enable
r
6 0: Disable
P N
e f o 2
1: Enable
5
GPIO85_
P
GPIO85_PULLE
N
l e a s I - R 0: Disable
1: Enable
4
GPIO84_
P
Re Pi B
GPIO84_PULLE
N P GPIO 84 Pull-up/Pull-down Enable
0: Disable
1: Enable
3 GPIO83_
a
GPIO83_PULLE
a n
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
2
P
GPIO82_
l N
Re Pi B
GPIO82_PULLE
P 0: Disable
1: Enable
0: Disable
a
P N
1: Enable
1
GPIO81_
n a n
GPIO81_PULLE
Ba
P N 0: Disable
1: Enable
0 0: Disable
P N
1: Enable
GPIO_PULL
100051B0 GPIO Pull-up/Pull-down Enable Register 7 FFFF
EN7
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI
GPI GPI
Nam O11 O1 O1 O1 O1 O1 O1 O1 O1 O1 O1 O9 O9 O9
r
O11 O9
e 0_ 09 08 07_ 06 05 04 03 02 01_ 00 9_ 8_ 6_
o
1_P 7_P
f
P _P _P P _P _P _P _P _P P _P P P P
Reset 1 1 1 1
e a s e1
I - R
1
2
1 1 1 1 1 1 1 1 1 1
Bit(s
)
15
Mnemon
ic
GPIO111_
l
Re Pi B
Name
GPIO111_PULLE
P Description

0: Disable
a
P N
1: Enable
14
GPIO110
n a n
GPIO110_PULLE
Ba
_P N 0: Disable
1: Enable
GPIO109 GPIO109_PULLE
13 0: Disable
_P N
1: Enable
12 0: Disable
_P N
1: Enable
11 0: Disable
_P N
1: Enable
10 0: Disable
r
_P N
1: Enable
9
e f o 2
s
_P N 0: Disable
Re Pi B
8 0: Disable
_P N
1: Enable
GPIO103 GPIO103_PULLE GPIO 103 Pull-up/Pull-down Enable
7
_P N
a n a 0: Disable
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
6
GPIO102
_P
l
Re Pi B
GPIO102_PULLE
N
P 0: Disable
1: Enable
1: Enable
5
GPIO101
a n a
GPIO101_PULLE
0: Disable
4
_P
GPIO100
_P
Ba n N
GPIO100_PULLE
N
1: Enable
0: Disable
1: Enable
3 0: Disable
P N
1: Enable
2 0: Disable
P N
1: Enable
1 0: Disable
P N
1: Enable
0

0: Disable
e
P N
l e a s I - R 2 1: Enable
100051C0
GPIO_PULL
EN8
Re Pi B P
Bit 15
GPI
14
GPI
13
GPI
a
12
n
GPI
a 11
GPI
10
GPI
9
GPI
8
GPI
7
GPI
6
GPI
5
GPI
4
GPI
3
GPI
2
GPI
1
GPI
0
GPI
Nam
e
Type
Reset
O12
7_P
RW
1
O12
6_
P
RW
1
O12
Ba
5_
P
RW
1
n O12
4_
P
RW
1
O12
3_
P
RW
1
O12
2_
P
RW
1
O12
1_P
RW
1
O12
0_
P
RW
1
O11
9_
P
RW
1
O11
8_
P
RW
1
O11
7_P
RW
1
O11
6_
P
RW
1
O11
5_P
RW
1
O11
4_
P
RW
1
O11
3_
P
RW
1
O11
2_
P
RW
1
Bit(s Mnemon
Name Description
) ic
14 0: Disable
_P N
1: Enable
r
13 0: Disable
_P N
e f o 2
1: Enable
12
_P N
l e a s I - R
0: Disable
1: Enable
P
Re Pi B
11 0: Disable
_P N
1: Enable
10 GPIO122 GPIO122_PULLE GPIO 122 Pull-up/Pull-down Enable
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
9
_P
GPIO121
l N
Re Pi B
GPIO121_PULLE
P 0: Disable
1: Enable
0: Disable
a
_P N
1: Enable
8
GPIO120
n a n
GPIO120_PULLE
Ba
_P N 0: Disable
1: Enable
7 0: Disable
_P N
1: Enable
6 0: Disable
_P N
1: Enable
5 0: Disable
_P N
1: Enable
4 0: Disable
r
_P N
1: Enable
3
e f o 2
s
_P N 0: Disable
Re Pi B
2 0: Disable
_P N
1: Enable
1
_P N
a n a 0: Disable
1: Enable
0
GPIO112
_P
Ba n
GPIO112_PULLE
N
0: Disable
1: Enable
GPIO_PULL
100051D0 GPIO Pull-up/Pull-down Enable Register 9 FFFF
EN9
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPI GPI GPI
Nam O14 O14 O14 O13 O13 O13 O13 O13 O13 O13 O13 O12 O12
O14 O13 O13
e 3_ 2_ 0_ 9_ 8_ 6_ 5_ 4_ 3_ 2_ 0_ 9_ 8_
1_P 7_P 1_P
Reset 1 1 1 1 1
f o r 1 1 1 1 1 1 1 1 1 1 1
Bit(s
)
Mnemon
ic
Name
15:0 Reserved
l
Reserved
Re Pi B P
Reserved
a n a
n
Ba
MT7623N
f o r
100051E0
GPIO_PULL
EN10
e a s e I - R 2
Bit
Nam
e
15
GPI
O15
9_
14
GPI
O15
8_
13
GPI
O15
l
Re Pi B
12
GPI
O15
6_
11
GPI
O15
5_
P 10
GPI
O15
4_
9
GPI
O15
3_
8
GPI
O15
2_
7
GPI
O15
6
GPI
O15
0_
5
GPI
O14
9_
4
GPI
O14
8_
3
GPI
O14
2
GPI
O14
6_
1
GPI
O14
5_
0
GPI
O14
4_
a
7_P 1_P 7_P
Type
Reset
RW
1
RW
1
RW
1
n a n
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
Bit(s
)
15:0
Mnemon
ic
Reserved
Ba Name
Reserved
Description
Reserved
GPIO_PULL
100051F0 GPIO Pull-up/Pull-down Enable Register 11 FFFF
EN11
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPI GPI GPI
Nam O17 O17 O17 O17 O17 O16 O16 O16 O16 O16 O16 O16 O16
r
O17 O16 O16
e 5_ 4_ 3_ 2_ 0_ 9_ 8_ 6_ 5_ 4_ 3_ 2_ 0_
o
1_P 7_P 1_P
f
Reset 1 1 1 1
e a s e1
I - R
1
2
1 1 1 1 1 1 1 1 1 1
Bit(s
)
15:0
Mnemon
ic
Reserved l
Re Pi B
Name
Reserved P Description
Reserved
a n a
10005200
Bit 15
GPI
GPIO_PULL
14
GPI
EN12
Ba
13
GPI
n 12
GPI
11
GPI
10
GPI
9
GPI
8
GPI
7
GPI
6
GPI
5
GPI
4
GPI
3
GPI
2
GPI
1
GPI
FFFF
0
GPI
Nam O19
O19 O1 O1 O1 O1 O1 O1 O1 O1 O1 O1 O17 O17
O17
O17
e 1_P
0_ 89 88 87_ 86 85 84 83 82 81_ 80 9_ 8_
7_P
6_
P _P _P P _P _P _P _P _P P _P P P P
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s Mnemon
Name Description
) ic
15
_P N
f o r 0: Disable
1: Enable
14
GPIO190
_P
GPIO190_PULLE
N
e a s e I - R 2
0: Disable
1: Enable
13
GPIO189
_P l
Re Pi B
GPIO189_PULLE
N
0: Disable
1: Enable
a
12 GPIO188 GPIO188_PULLE GPIO 188 Pull-up/Pull-down Enable
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
11:0
_P
Reserved l N
Re Pi B
Reserved P 0: Disable
1: Enable
Reserved
a n a
10005210
Bit 15
GPI
GPIO_PULL
14
GPI
EN13
Ba
13
GPI
n 12
GPI
11
GPI
10
GPI
9
GPI
8
GPI
7
GPI
6
GPI
5
GPI
4
GPI
3
GPI
2
GPI
1
GPI
FFFF
0
GPI
Nam O2 O2 O2 O2 O2 O2 O2 O2 O19 O19
O19
O19
O19
O19 O19 O19
e 07_ 06 05 04 03 02 01_ 00 9_ 8_
7_P
6_
5_P
4_ 3_ 2_
P _P _P _P _P _P P _P P P P P P P
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s Mnemon
Name Description
) ic
15
_P N
f o r 0: Disable
1: Enable
14
GPIO206
_P
GPIO206_PULL
EN
e a s e I - R 2
0: Disable
1: Enable
13
GPIO205
_P l
Re Pi B
GPIO205_PULLE
N
0: Disable
1: Enable
a
GPIO204 GPIO204_PULL
12
_P
n
EN
a n 0: Disable
1: Enable
Ba
11 0: Disable
_P EN
1: Enable
10 0: Disable
_P EN
1: Enable
9 0: Disable
_P N
1: Enable
8 0: Disable
_P EN
1: Enable
r
7
_P N
e f o 2
0: Disable
1: Enable
s
R
6
_P N
l e a P I -
0: Disable
1: Enable
Re Pi B
5 0: Disable
_P N
1: Enable
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
4
GPIO196
_P l
Re Pi B
GPIO196_PULLE
N
0: Disable
1: Enable
a
3
_P
n
N
a n 0: Disable
1: Enable
Ba
2 0: Disable
_P N
1: Enable
1 0: Disable
_P N
1: Enable
0 0: Disable
_P N
1: Enable
GPIO_PULL
10005220
Bit 15 14
EN14
13 12
f
11
o r
10 9 8 7 6 5 4 3 2 1
FFFF
Nam
e
GPI
O2
23_
GPI
O2
22_
GPI
O2
21_
GPI
O2
20
e a s e
GPI
O21
9_
I - R
8_
2
GPI
O21
GPI
O21
GPI
O21
6_
GPI
O21
5_
GPI
O21
4_
GPI
O21
3_
GPI
O21
2_
GPI
O21
GPI
O21
0_
GPI
O2
09
GPI
O2
08
Type
Reset
P
RW
1
P
RW
1
P
RW
1 l
_P
Re Pi B
RW
1
P
RW
1
P P
RW
1
7_P
RW
1
P
RW
1
P
RW
1
P
RW
1
P
RW
1
P
RW
1
1_P
RW
1
P
RW
1
_P
RW
1
_P
RW
1
Bit(s
)
Mnemon
ic
a n a
Name Description
15:2
1
Reserved
GPIO209
_P
Ba n Reserved
GPIO209_PULL
EN 0: Disable
1: Enable
Reserved

0 0: Disable
_P EN
1: Enable
GPIO_PULL
10005230 GPIO Pull-up/Pull-down Enable Register 15 FFFF
EN15
Bit
Nam
15
GPI
O2
14
GPI
O2
13
GPI
O2
12
GPI
O2
11
O2
f
GPI
o r 10
GPI
O2
9
GPI
O2
8
GPI
O2
7
GPI
O2
6
GPI
O2
5
GPI
O2
4
GPI
O2
3
GPI
O2
2
GPI
O2
1
GPI
O2
0
GPI
O2
e
Type
39
_P
RW
38
_P
RW
37_
P
RW
36
_P
RW
e a s e
35_
P
RW
I -
34
_P
R
RW
2
33_
P
RW
32_
P
RW
31_
P
RW
30
_P
RW
29
_P
RW
28
_P
RW
27_
P
RW
26
_P
RW
25_
P
RW
24_
P
RW
Reset
Bit(s
)
1
Mnemon
ic
1 1
l
1
Re Pi B
Name
1
P
1 1 1 1 1 1
Description
1 1 1 1 1
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
15
GPIO239
_P l
Re Pi B
GPIO239_PULLE
N
0: Disable
1: Enable
a
14
_P
n
EN
a n 0: Disable
1: Enable
Ba
13 0: Disable
_P N
1: Enable
12 0: Disable
_P N
1: Enable
GPIO_PULL
10005240 GPIO Pull-up/Pull-down Enable Register 16 FEFF
EN16
Bit
Nam
15
GPI
O2
14
GPI
O2
13
GPI
O2
12
GPI
O2
11
O2
f
GPI
o r 10
GPI
O2
9
GPI
O2
8
GPI
O2
7
GPI
O2
6
GPI
O2
5
GPI
O2
4
GPI
O2
3
GPI
O2
2
GPI
O2
1
GPI
O2
0
GPI
O2
e
Type
55_
P
RW
54_
P
RW
53_
P
RW
52_
P
RW
e a s e
51_
P
RW
I -
50
_P
R
RW
2
49
_P
RW
48
_P
RW
47_
P
RW
46
_P
RW
45_
P
RW
44
_P
RW
43_
P
RW
42
_P
RW
41_
P
RW
40
_P
RW
Reset
Bit(s
)
1
Mnemon
ic
1 1
l
1
Re Pi B
Name
1
P
1 1 0 1 1 1
Description
1 1 1 1 1
15
GPIO255
a n a
GPIO255_PULLE
n
_P N 0: Disable
Ba
1: Enable
14 0: Disable
_P N
1: Enable
13 0: Disable
_P N
1: Enable
12 0: Disable
_P N
1: Enable
11 0: Disable
_P N
r
1: Enable
10
GPIO250
_P
GPIO250_PULLE
N
e f o 2
0: Disable
s
1: Enable
9
GPIO249
l e a
GPIO249_PULLE
P I - R GPIO 249 Pull-up/Pull-down Enable

0: Disable
Re Pi B
_P N
1: Enable
GPIO248 GPIO248_PULL GPIO 248 Pull-up/Pull-down Enable
8
_P EN 0: Disable
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
7
GPIO247
_P
l
Re Pi B
GPIO247_PULLE
N
P 0: Disable
1: Enable
1: Enable
6
GPIO246
a n a
GPIO246_PULLE
0: Disable
5
_P
GPIO245
_P
Ba n N
GPIO245_PULLE
N
1: Enable
0: Disable
1: Enable
4 0: Disable
_P N
1: Enable
3 0: Disable
_P N
1: Enable
2 0: Disable
_P N
1: Enable
1

0: Disable
e
_P N
0
GPIO240
e
GPIO240_PULL
l a s I - R 2 1: Enable
P
0: Disable
Re Pi B
_P EN
1: Enable
10005250
GPIO_PULL
a n a GPIO Pull-up/Pull-down Enable Register 17 FFFF
Bit
Nam
e
15
GPI
O2
71_
14
GPI
O2
70_
EN17
Ba
13
GPI
O2
69
n 12
GPI
O2
68
11
GPI
O2
67_
10
GPI
O2
66
O2
9
GPI
65_
O2
64
8
GPI
O2
63
7
GPI
O2
62
6
GPI
O2
5
GPI
61_
O2
60
4
GPI
O2
3
GPI
59_
2
GPI
O2
58
1
GPI
O2
57_
0
GPI
O2
56_
P P _P _P P _P P _P _P _P P _P P _P P P
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s Mnemon
Name Description
) ic
15 0: Disable
_P N
1: Enable
14

0: Disable
e
_P N
13
GPIO269
e a
GPIO269_PULLE
P
0: Disable
Re Pi B
_P N
1: Enable
GPIO268 GPIO268_PULL GPIO 268 Pull-up/Pull-down Enable
12
_P EN 0: Disable
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
11
GPIO267
_P
l
Re Pi B
GPIO267_PULLE
N
P 0: Disable
1: Enable
1: Enable
10
GPIO266
a n a
GPIO266_PULLE
0: Disable
9
_P
GPIO265
_P
Ba n N
GPIO265_PULLE
N
1: Enable
0: Disable
1: Enable
8 0: Disable
_P N
1: Enable
7 0: Disable
_P N
1: Enable
6 0: Disable
_P N
1: Enable
5

0: Disable
e
_P N
4
GPIO260
e a
GPIO260_PULL
P
0: Disable
Re Pi B
_P EN
1: Enable
3 0: Disable
_P N
a n a 1: Enable
n
2 0: Disable
Ba
_P N
1: Enable
1 0: Disable
_P N
1: Enable
0 0: Disable
_P N
1: Enable
GPIO_PULL
10005260 GPIO Pull-up/Pull-down Enable Register 18 00FF
EN18
Bit 15 14 13 12 11
f o r 10 9 8 7
GPI
6
GPI
5
GPI
4
GPI
3
GPI
2
GPI
1
GPI
0
GPI
e
Nam O2 O2 O2 O2 O2 O2 O2
2
O27
e
Type
l e a s I - R
79_
P
RW
78_
P
RW
77_
P
RW
76_
P
RW
5_P
RW
74_
P
RW
73_
P
RW
72_
P
RW
Reset
Re Pi B P 1 1 1 1 1 1 1 1
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
6
Reserved
GPIO278
_P
l
Re Pi B
Reserved
GPIO278_PULLE
N
P Reserved
0: Disable
a
1: Enable
5 Reserved
n a n
Reserved Reserved
Ba
4 0: Disable
_P N
1: Enable
3 0: Disable
_P N
1: Enable
2 0: Disable
_P N
1: Enable
0 0: Disable
_P N
1: Enable
f o r
10005280
GPIO_PULL
SEL1
e a s e I - 2
GPIO Pull-up/Pull-down Selection Register
R 1
1050
Bit
Nam
e
15
GPI
O15
14
GPI
O14
13
GPI
O13
l
Re Pi B
12
GPI
O12
11
GPI
O11P 10
GPI
O1
0_
O9
9
GPI
8
GPI
O8
7
GPI
O7
6
GPI
O6
5
GPI
O5
4
GPI
O4
3
GPI
O3
2
GPI
O2
1
GPI
O1
0
GPI
O0
a
_U _U _U _U _U _U _U _U _U _U _U _U _U _U _U
U
Type
Reset
RW
0
RW
0
RW
0
n a n
RW
1
RW
0
RW
0
RW
0
RW
0
RW
0
RW
1
RW
0
RW
1
RW
0
RW
0
RW
0
RW
0
Bit(s
)
15
Mnemon
ic
GPIO15_
U
Ba Name
GPIO15_PULLSE
L
Description
GPIO 15 Pull-up/Pull-down Selection

0: Pull-down
1: Pull-up
GPIO14_ GPIO14_PULLSE
14 0: Pull-down
U L
1: Pull-up
13 0: Pull-down
U L
1: Pull-up
12
GPIO12_
U
GPIO12_PULLSE
L
f o r GPIO 12 Pull-up/Pull-down Selection

0: Pull-down
e
1: Pull-up
11
GPIO11_
U
a
GPIO11_PULLSE
L
l e s I - R 2 GPIO 11 Pull-up/Pull-down Selection

0: Pull-down
10
GPIO10_
U
Re Pi B
GPIO10_PULLSE
L
P 1: Pull-up
0: Pull-down
1: Pull-up
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
9 GPIO9_U
L l
Re Pi B
GPIO9_PULLSE
P GPIO 9 Pull-up/Pull-down Selection
0: Pull-down
1: Pull-up
a
GPIO8_ GPIO8_PULLSE
8
U
n
L
a n 0: Pull-down
1: Pull-up
Ba
7 GPIO7_U GPIO7_PULLSEL 0: Pull-down
1: Pull-up
GPIO6_PULLSE
6 GPIO6_U 0: Pull-down
L
1: Pull-up
1: Pull-up
GPIO4_PULLSE
4 GPIO4_U 0: Pull-down
L
1: Pull-up
r
GPIO3_PULLSE
3 GPIO3_U
L
e f o 2
0: Pull-down
1: Pull-up
s
R
GPIO2_PULLSE
2 GPIO2_U
L
l e a P I -
0: Pull-down
1: Pull-up
Re Pi B
1: Pull-up
0
GPIO0_
U
a
L
n a
GPIO0_PULLSE
0: Pull-down
Ba n 1: Pull-up
GPIO_PULL GPIO Pull-up/Pull-down Selection Register

10005290 0000
SEL2 2
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI
GPI GPI GPI GPI GPI
Nam O31
O3 O2 O2 O2 O2 O2 O2 O2 O2
O21
O2
O19
O1
O17 O16
e _U
0_ 9_ 8_ 7_ 6_ 5_ 4_ 3_ 2_
_U
0_
_U
8_
_U _U
U U U U U U U U U U U
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Name
f o r Description
15
GPIO31_
U
GPIO31_PULLSE
L
e a s e I - R 2 GPIO 31 Pull-up/Pull-down Selection

0: Pull-down
14
GPIO30_
U
l
Re Pi B
GPIO30_PULLS
EL P
1: Pull-up
0: Pull-down
1: Pull-up
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
13
GPIO29_
U l
Re Pi B
GPIO29_PULLSE
L
0: Pull-down
1: Pull-up
a
GPIO28_ GPIO28_PULLS
12
U
n
EL
a n 0: Pull-down
1: Pull-up
Ba
11 0: Pull-down
U L
1: Pull-up
10 0: Pull-down
U L
1: Pull-up
9 0: Pull-down
U L
1: Pull-up
8 0: Pull-down
U L
1: Pull-up
r
7
U L
e f o 2
0: Pull-down
1: Pull-up
s
R
6
U L
l e a P I -
0: Pull-down
1: Pull-up
Re Pi B
5 0: Pull-down
U L
1: Pull-up
4
GPIO20_
U
a
EL
n a
GPIO20_PULLS
0: Pull-down
3
GPIO19_
U
Ba n
GPIO19_PULLSE
L
1: Pull-up
0: Pull-down
1: Pull-up
2 0: Pull-down
U L
1: Pull-up
1 0: Pull-down
U L
1: Pull-up
0 0: Pull-down
U L
1: Pull-up
f o r
100052A
0
GPIO_PULL
SEL3
e a s e I - 2
R 3
0780
Bit
Nam
e
15
GPI
O4
7_
14
GPI
O4
6_
13
GPI
O4
5_
l
Re Pi B
12
GPI
O4
4_
11
GPI
O4
3_
P 10
GPI
O4
2_
9
GPI
O41
_U
O4
0_
8
GPI
O3
9_
7
GPI
O3
8_
6
GPI
O3
7_
5
GPI
O3
6_
4
GPI
O3
5_
3
GPI
2
GPI
O3
4_
1
GPI
O3
3_
0
GPI
O3
2_
a n a
n
Ba
MT7623N
f o r
100052A
0
GPIO_PULL
SEL3
e a s e R 2
I - 3
0780
Type
Reset
U
RW
0
U
RW
0
U
RW
0
l
Re Pi B
U
RW
0
U
RW
0P U
RW
1
RW
1
U
RW
1
U
RW
1
U
RW
0
U
RW
0
U
RW
0
U
RW
0
U
RW
0
U
RW
0
U
RW
0
Bit(s Mnemon
a n a
Name Description
n
) ic
Ba
15 0: Pull-down
U L
1: Pull-up
14 0: Pull-down
U L
1: Pull-up
13 0: Pull-down
U L
1: Pull-up
12 0: Pull-down
U L
1: Pull-up
11
GPIO43_
U
GPIO43_PULLSE
L
0: Pull-down
10
GPIO42_
a
GPIO42_PULLSE
e s e I - R 2
1: Pull-up
0: Pull-down
9
U
GPIO41_
U
L
l
Re Pi B
GPIO41_PULLSE
L
P 1: Pull-up
0: Pull-down
a
1: Pull-up
8
GPIO40_
U
n a
EL
n
GPIO40_PULLS
0: Pull-down
Ba
1: Pull-up
7 0: Pull-down
U L
1: Pull-up
6 0: Pull-down
U EL
1: Pull-up
5 0: Pull-down
U L
1: Pull-up
4 0: Pull-down
U L
r
1: Pull-up
3
GPIO35_
U
GPIO35_PULLSE
L
e f o 2
0: Pull-down
GPIO34_
l e a
GPIO34_PULLSE
s I - R
1: Pull-up
P
2 0: Pull-down
Re Pi B
U L
1: Pull-up
GPIO33_ GPIO33_PULLSE GPIO 33 Pull-up/Pull-down Selection
1
U L 0: Pull-down
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
0
GPIO32_
U
l
Re Pi B
GPIO32_PULLSE
L
P 1: Pull-up
0: Pull-down
1: Pull-up
a n a
100052B
0
Bit 15
GPIO_PULL
14
SEL4
Ba
13
n 12
11 10 9
4
8 7 6 5 4 3 2 1
0600
0
GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI
GPI GPI
Nam O6 O6
O61
O6 O5 O5 O5 O5 O5 O5 O5 O5
O51
O5 O4 O4
e 3_ 2_
_U
0_ 9_ 8_ 7_ 6_ 5_ 4_ 3_ 2_
_U
0_ 9_ 8_
U U U U U U U U U U U U U U
Reset 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
15
GPIO63_
U
GPIO63_PULLSE
L

0: Pull-down
e
1: Pull-up
14
GPIO62_
U
a
GPIO62_PULLSE
L
l e s I - R 2 GPIO 62 Pull-up/Pull-down Selection

0: Pull-down
13
GPIO61_
U
Re Pi B
GPIO61_PULLSE
L
P 1: Pull-up
0: Pull-down
1: Pull-up
12
GPIO60_
a n a
GPIO60_PULLS
0: Pull-down
11
10
U
Reserved
GPIO58_ Ba nEL
Reserved
GPIO58_PULLSE
1: Pull-up
Reserved
0: Pull-down
U L
1: Pull-up
9 0: Pull-down
U L
1: Pull-up
8 0: Pull-down
U L
1: Pull-up
r
7 0: Pull-down
U L
e f o 2
1: Pull-up
6
U L
l e a s I - R
0: Pull-down
1: Pull-up
P
Re Pi B
5 0: Pull-down
U L
1: Pull-up
4 GPIO52_ GPIO52_PULLSE GPIO 52 Pull-up/Pull-down Selection
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
3
U
GPIO51_
l L
Re Pi B
GPIO51_PULLSE
P 0: Pull-down
1: Pull-up
0: Pull-down
a
U L
1: Pull-up
2
GPIO50_
n a n
GPIO50_PULLSE
Ba
U L 0: Pull-down
1: Pull-up
1 0: Pull-down
U L
1: Pull-up
0 0: Pull-down
U EL
1: Pull-up

100052C0 F800
SEL5 5
Bit 15
GPI
14
GPI
13 12
GPI
11
f
GPI
o r 10
GPI
9
GPI
8
GPI
7 6
GPI
5
GPI
4
GPI
3
GPI
2
GPI
1
GPI
0
GPI
e
GPI GPI
Nam O7 O7 O7 O7 O7 O7 O7 O7 O6 O6 O6 O6 O6 O6
e
Type
9_
U
RW
8_
U
RW
O77
_U
RW
6_
U
l
RW
e a s 5_
U
RW
I -
4_
RU
RW2 3_
U
RW
2_
U
RW
O71
_U
RW
0_
U
RW
9_
U
RW
8_
U
RW
7_
U
RW
6_
U
RW
5_
U
RW
4_
U
RW
Reset
Bit(s
1
Mnemon
1 1
Re Pi B
1 1
P 0 0 0 0 0 0 0 0 0 0 0
a
Name Description
) ic
15
GPIO79_
n a n
GPIO79_PULLSE
Ba
U L 0: Pull-down
1: Pull-up
14 0: Pull-down
U L
1: Pull-up
13 0: Pull-down
U L
1: Pull-up
12 0: Pull-down
U L
1: Pull-up
11 0: Pull-down
r
U L
1: Pull-up
10
e f o 2
s
U L 0: Pull-down
l e a P I - R 1: Pull-up
Re Pi B
9 0: Pull-down
U L
1: Pull-up
GPIO72_ GPIO72_PULLSE GPIO 72 Pull-up/Pull-down Selection
8
U L
a n a 0: Pull-down
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
7
GPIO71_
U
l
Re Pi B
GPIO71_PULLSE
L
P 1: Pull-up
0: Pull-down
1: Pull-up
6
GPIO70_
a n a
GPIO70_PULLSE
0: Pull-down
5
U
GPIO69_
U
Ba n L
GPIO69_PULLSE
L
1: Pull-up
0: Pull-down
1: Pull-up
4 0: Pull-down
U EL
1: Pull-up
3 0: Pull-down
U L
1: Pull-up
2 0: Pull-down
U L
1: Pull-up
1

0: Pull-down
e
U L
0
GPIO64_
e a
GPIO64_PULLSE
l s I - R 2 1: Pull-up
P
0: Pull-down
Re Pi B
U L
1: Pull-up
100052D GPIO_PULL
a n a GPIO Pull-up/Pull-down Selection Register

0001
0
Bit
Nam
e
15
GPI
O9
5_
14
GPI
O9
4_
SEL6
Ba
13
GPI
O9
3_
n 12
GPI
O9
2_
11
GPI
O91
_U
10
GPI
O9
0_
O8
9_
9
GPI
6
O8
8_
8
GPI
O8
7_
7
GPI
O8
6_
6
GPI
O8
5_
5
GPI
O8
4_
4
GPI
O8
3_
3
GPI
2
GPI
O8
2_
1
GPI
O8
1_
0
GPI
O8
0_
U U U U U U U U U U U U U U U
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit(s Mnemon
Name Description
) ic
15 0: Pull-down
U L
1: Pull-up
14 Reserved Reserved
f o r Reserved
e
12
11
Reserved
Reserved
Reserved
e a
Reserved
l s I - R 2 Reserved
Reserved
10
GPIO90_
U
Re Pi B
GPIO90_PULLS
EL P GPIO 90 Pull-up/Pull-down Selection
0: Pull-down
1: Pull-up
9 GPIO89_
a
GPIO89_PULLS
a n
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
8
U
GPIO88_
lEL
Re Pi B
GPIO88_PULLS
P 0: Pull-down
1: Pull-up
0: Pull-down
a
U EL
1: Pull-up
7
GPIO87_
n a n
GPIO87_PULLSE
Ba
U L 0: Pull-down
1: Pull-up
6 0: Pull-down
U EL
1: Pull-up
5 0: Pull-down
U L
1: Pull-up
4 0: Pull-down
U EL
1: Pull-up
3 0: Pull-down
r
U EL
1: Pull-up
2
e f o 2
s
U EL 0: Pull-down
Re Pi B
1 0: Pull-down
U L
1: Pull-up
0
U EL
a n a 0: Pull-down
1: Pull-up
100052E0
GPIO_PULL
SEL7 Ba n GPIO Pull-up/Pull-down Selection Register
7
FA00
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam O11 O11 O1 O1 O1 O1 O1 O1 O1 O1 O1 O1 O9 O9 O9 O9
e 1_ 0_ 09 08 07_ 06 05 04 03 02 01_ 00 9_ 8_ 7_ 6_
U U _U _U U _U _U _U _U _U U _U U U U U
Reset 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
r
Name Description
) ic
15
e f o 2
s
U EL 0: Pull-down
Re Pi B
GPIO110 GPIO110_PULLS
14 0: Pull-down
_U EL
1: Pull-up
GPIO109 GPIO109_PULLS GPIO 109 Pull-up/Pull-down Selection
13
_U EL
a n a 0: Pull-down
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
12
GPIO108
_U
l
Re Pi B
GPIO108_PULLS
EL
P 1: Pull-up
0: Pull-down
1: Pull-up
11
GPIO107
a n a
GPIO107_PULLS
0: Pull-down
10
_U
GPIO106
_U
Ba n EL
GPIO106_PULLS
EL
1: Pull-up
0: Pull-down
1: Pull-up
9 0: Pull-down
_U EL
1: Pull-up
8 0: Pull-down
_U EL
1: Pull-up
7 0: Pull-down
_U EL
1: Pull-up
6

0: Pull-down
e
_U EL
5
GPIO101
e a
GPIO101_PULLS
P
0: Pull-down
Re Pi B
_U EL
1: Pull-up
4 0: Pull-down
_U EL
a n a 1: Pull-up
n
3 0: Pull-down
Ba
U L
1: Pull-up
2 0: Pull-down
U EL
1: Pull-up
1 0: Pull-down
U L
1: Pull-up
0 0: Pull-down
U L
1: Pull-up
100052F0
GPIO_PULL
f o r
3FDF
Bit 15 14
SEL8
13 12
e a s e11
I - R 2
10 9
8
8 7 6 5 4 3 2 1 0
l
Nam
e
Type
O12
7_
U
RW
O12
6_
U
RW
O12
5_
U
RW
Re Pi B
O12
4_
U
RW
O12
3_
U
RW
P O12
2_
U
RW
O12
1_
U
RW
O12
0_
U
RW
O11
9_
U
RW
O11
8_
U
RW
O11
7_
U
RW
O11
6_
U
RW
O11
5_
U
RW
O11
4_
U
RW
O11
3_
U
RW
O11
2_
U
RW
a
Reset 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1
Ba
MT7623N
f o r
Bit(s Mnemon
e a s e I - R 2
)
15
ic
Reserved
GPIO126
l
Name
Re Pi B
Reserved
GPIO126_PULLS
P
Description
Reserved
14
_U
a n
EL
a 0: Pull-down
1: Pull-up
13
12
GPIO125
_U
GPIO124 Ba n
GPIO125_PULLS
EL
GPIO124_PULLS
0: Pull-down
1: Pull-up
0: Pull-down
_U EL
1: Pull-up
11 0: Pull-down
_U EL
1: Pull-up
10 0: Pull-down
_U EL
1: Pull-up
9
_U EL
f o r 0: Pull-down
1: Pull-up
e
8
GPIO120
_U
GPIO120_PULLS
EL
l e a s I - R 2 0: Pull-down
1: Pull-up
7
GPIO119
_U
Re Pi B
GPIO119_PULLS
EL
0: Pull-down
1: Pull-up
a
n
6 0: Pull-down
_U EL
n a 1: Pull-up
Ba
5 0: Pull-down
_U EL
1: Pull-up
4 0: Pull-down
_U EL
1: Pull-up
3 0: Pull-down
_U EL
1: Pull-up
2 0: Pull-down
_U EL
1: Pull-up
r
1
_U EL
e f o 2
0: Pull-down
1: Pull-up
s
R
0
_U EL
l e a P I -
0: Pull-down
1: Pull-up
Re Pi B
a n a
n
Ba
MT7623N
f o r
10005300
GPIO_PULL
SEL9
e a s e I - R 2
9
0000
Bit
Nam
e
15
GPI
O14
3_
14
GPI
O14
2_
13
GPI
O14
1_
l
Re Pi B
12
GPI
O14
0_
11
GPI
O13
9_
P 10
GPI
O13
8_
9
GPI
O13
7_
8
GPI
O13
6_
7
GPI
O13
5_
6
GPI
O13
4_
5
GPI
O13
3_
4
GPI
O13
2_
3
GPI
O13
1_
2
GPI
O13
0_
1
GPI
O12
9_
0
GPI
O12
8_
Type
U
RW
U
RW
U
RW
a
U
n
RW
a U
RW
U
RW
U
RW
U
RW
U
RW
U
RW
U
RW
U
RW
U
RW
U
RW
U
RW
U
RW
n
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
15:0
Mnemon
ic
Reserved
Ba Name
Reserved
Description
Reserved

10005310 0000
SEL10 10
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
e
Type
9_
U
RW
8_
U
RW
7_
U
RW
6_
U
RW
5_
U
RW
f o r 4_
U
RW
3_
U
RW
2_
U
RW
1_
U
RW
0_
U
RW
9_
U
RW
8_
U
RW
7_
U
RW
6_
U
RW
5_
U
RW
4_
U
RW
Reset 0 0 0 0
e a s e0
I - R
0
2
0 0 0 0 0 0 0 0 0 0
Bit(s
)
15:0
Mnemon
ic
Reserved l
Re Pi B
Name
Reserved
a n a
10005320
Bit 15
GPI
GPIO_PULL
14
SEL11
GPI Ba
13
GPI
n 12
GPI
11
GPI
10
GPI
11
9
GPI
8
GPI
7
GPI
6
GPI
5
GPI
4
GPI
3
GPI
2
GPI
1
GPI
0000
0
GPI
e 5_ 4_ 3_ 2_ 1_ 0_ 9_ 8_ 7_ 6_ 5_ 4_ 3_ 2_ 1_ 0_
U U U U U U U U U U U U U U U U
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
f o r
10005330
GPIO_PULL
SEL12
e a s e I - 2
R 12
0000
Bit
Nam
e
15
GPI
O19
1_
14
GPI
O19
0_
13
GPI
O1
89
l
Re Pi B
12
GPI
O1
88
11
GPI
O1
87_
P 10
GPI
O1
86
O1
85
9
GPI
O1
84
8
GPI
O1
83
7
GPI
O1
82
6
GPI
O1
5
GPI
81_
O1
80
4
GPI
3
GPI
O17
9_
2
GPI
O17
8_
1
GPI
O17
7_
0
GPI
O17
6_
a n a
n
Ba
MT7623N
f o r
10005330
GPIO_PULL
SEL12
e a s e I - R 2
12
0000
Type
Reset
U
RW
0
U
RW
0
_U
RW
0
l
Re Pi B
_U
RW
0
U
RW
0 P _U
RW
0
_U
RW
0
_U
RW
0
_U
RW
0
_U
RW
0
U
RW
0
_U
RW
0
U
RW
0
U
RW
0
U
RW
0
U
RW
0
Bit(s Mnemon
a n a
Name Description
n
) ic
Ba
15 0: Pull-down
_U EL
1: Pull-up
14 0: Pull-down
_U EL
1: Pull-up
13 0: Pull-down
_U EL
1: Pull-up
12 0: Pull-down
_U EL
1: Pull-up
11:0 Reserved Reserved
f o r Reserved
GPIO_PULL
e a s e I - R 2
10005340
Bit 15
GPI
14
SEL13
GPI
13
GPI
l
Re Pi B
12
GPI
11
GPI
P 10
GPI
13
9
GPI
8
GPI
7
GPI
6
GPI
5
GPI
4
GPI
3
GPI
2
GPI
1
GPI
0000
0
GPI
a
n
e 07_ 06 05 04 03 02 01_ 00 9_ 8_ 7_ 6_ 5_ 4_ 3_ 2_
a
U _U _U _U _U _U U _U U U U U U U U U
Type
Reset
Bit(s
)
RW
0
Mnemon
ic
RW
0
RW
Ba
0
n RW
0
Name
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Description
RW
0
RW
0
RW
0
RW
0
RW
0

15 0: Pull-down
_U EL
1: Pull-up
14 0: Pull-down
_U EL
1: Pull-up
13 0: Pull-down
r
_U EL
1: Pull-up
12
e f o 2
0: Pull-down
_U EL
l e a s I - R
1: Pull-up
11
10
GPIO203
_U
GPIO202
GPIO203_PULLS
Re Pi B
EL
GPIO202_PULLS
P 0: Pull-down
1: Pull-up
_U EL
a n a 0: Pull-down
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
9
GPIO201
_U
l
Re Pi B
GPIO201_PULLS
EL
P 1: Pull-up
0: Pull-down
1: Pull-up
8
GPIO200
a n a
GPIO200_PULLS
0: Pull-down
7
_U
GPIO199
_U
Ba n EL
GPIO199_PULLS
EL
1: Pull-up
0: Pull-down
1: Pull-up
6 0: Pull-down
_U EL
1: Pull-up
5 0: Pull-down
_U EL
1: Pull-up
4 0: Pull-down
_U EL
1: Pull-up
3

0: Pull-down
e
_U EL
2
GPIO194
e a
GPIO194_PULLS
P
0: Pull-down
Re Pi B
_U EL
1: Pull-up
1 0: Pull-down
_U EL
a n a 1: Pull-up
n
0 0: Pull-down
Ba
_U EL
1: Pull-up

10005350 0000
SEL14 14
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
e 23_ 22_ 21_ 20 9_ 8_ 7_ 6_ 5_ 4_ 3_ 2_ 1_ 0_ 09 08
U U U _U U U U U U U U U U U _U _U
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
f o r
e
Name Description
2
) ic
15:2 Reserved
a
Reserved
l e s I - R Reserved
P
Re Pi B
1 0: Pull-down
_U EL
1: Pull-up
0 GPIO208 GPIO208_PULLS GPIO 208 Pull-up/Pull-down Selection
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
_U
lEL
Re Pi B P 0: Pull-down
1: Pull-up
GPIO_PULL
n
10005360 0000
SEL15 15
Bit
Nam
e
Type
15
GPI
O2
39
_U
RW
14
GPI
O2
38
_U
RW
Ba
13
GPI
O2
37_
U
RW
12
GPI
O2
36
_U
RW
11
GPI
O2
35_
U
RW
10
GPI
O2
34
_U
RW
O2
9
GPI
33_
U
RW
8
GPI
O2
32_
U
RW
7
GPI
O2
31_
U
RW
30
_U
RW
6
GPI
O2
29
_U
RW
5
GPI
O2
28
_U
RW
4
GPI
O2
3
GPI
O2
27_
U
RW
2
GPI
O2
26
_U
RW
1
GPI
O2
25_
U
RW
0
GPI
O2
24_
U
RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
15 0: Pull-down
_U EL
r
1: Pull-up
14
GPIO238
_U
GPIO238_PULLS
EL
e f o 2
0: Pull-down
GPIO237
l e a
GPIO237_PULLS
s I - R
1: Pull-up
P
13 0: Pull-down
Re Pi B
_U EL
1: Pull-up
12 0: Pull-down
a
_U EL
1: Pull-up
11:0 Reserved
n a n
Reserved Reserved
10005370
GPIO_PULL
SEL16
Ba GPIO Pull-up/Pull-down Selection Register
16
FEB0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
e 55_ 54_ 53_ 52_ 51_ 50 49 48 47_ 46 45_ 44 43_ 42 41_ 40
U U U U U _U _U _U U _U U _U U _U U _U
Reset 1 1 1 1 1 1 1 0 1 0 1 1 0 0 0 0
Bit(s
)
Mnemon
ic
Name
f o r Description
15
GPIO255
_U
GPIO255_PULLS
EL
e a s e I - R 2
0: Pull-down
1: Pull-up
14
GPIO254
_U l
Re Pi B
GPIO254_PULLS
EL
0: Pull-down
1: Pull-up
a
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
12
_U
GPIO252
lEL
Re Pi B
GPIO252_PULLS
P 0: Pull-down
1: Pull-up
0: Pull-down
a
_U EL
1: Pull-up
11
GPIO251
n a n
GPIO251_PULLS
Ba
_U EL 0: Pull-down
1: Pull-up
10 0: Pull-down
_U EL
1: Pull-up
9 0: Pull-down
_U EL
1: Pull-up
8 0: Pull-down
_U EL
1: Pull-up
7 0: Pull-down
r
_U EL
1: Pull-up
6
e f o 2
s
_U EL 0: Pull-down
Re Pi B
5 0: Pull-down
_U EL
1: Pull-up
4
_U EL
a n a 0: Pull-down
1: Pull-up
2
GPIO243
_U
GPIO242 Ba n
GPIO243_PULLS
EL
GPIO242_PULLS
0: Pull-down
1: Pull-up
0: Pull-down
_U EL
1: Pull-up
1 0: Pull-down
_U EL
1: Pull-up
0 0: Pull-down
_U EL
1: Pull-up
f o r
e
10005380
Bit 15 14
SEL17
13 12
l e a s 11
I - R 2
10
17
9 8 7 6 5 4 3 2 1
0017
Nam
e
GPI
O2
71_
U
GPI
O2
70_
U
GPI
O2
69
_U
Re Pi B
GPI
O2
68
_U
GPI
O2
67_
U
P GPI
O2
66
_U
GPI
O2
65_
U
GPI
O2
64
_U
GPI
O2
63
_U
GPI
O2
62
_U
GPI
O2
61_
U
GPI
O2
60
_U
GPI
O2
59_
U
GPI
O2
58
_U
GPI
O2
57_
U
GPI
O2
56_
U
a
Ba
MT7623N
f o r
10005380
GPIO_PULL
SEL17
e a s e I - R 2
17
0017
Reset
Bit(s
0
Mnemon
0 0
l
Re Pi B
0
P
0 0 0 0 0 0 0 1 0 1 1 1
) ic
a n a
Name Description

15
14
GPIO271
_U
GPIO270
_U
n
GPIO271_PULLS
Ba
EL
GPIO270_PULLS
EL
0: Pull-down
1: Pull-up
0: Pull-down
1: Pull-up
13 0: Pull-down
_U EL
1: Pull-up
12 0: Pull-down
_U EL
1: Pull-up
11 0: Pull-down
_U EL
f o r 1: Pull-up
10
GPIO266
_U
GPIO266_PULLS
EL
e a s e I - R 2 0: Pull-down
1: Pull-up
9
GPIO265
_U EL
l
Re Pi B
GPIO265_PULLS
P
0: Pull-down
1: Pull-up
a
8 0: Pull-down
_U
n
EL
a n 1: Pull-up
Ba
7 0: Pull-down
_U EL
1: Pull-up
6 0: Pull-down
_U EL
1: Pull-up
5 0: Pull-down
_U EL
1: Pull-up
4 0: Pull-down
_U EL
1: Pull-up
r
3 0: Pull-down
_U EL
e f o 2
1: Pull-up
2
GPIO258
_U
GPIO258_PULLS
EL
l e a s I - R
0: Pull-down
1: Pull-up
1
GPIO257
_U
Re Pi B
GPIO257_PULLS
EL
0: Pull-down
1: Pull-up
a
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
_U
l EL
Re Pi B P 0: Pull-down
1: Pull-up
GPIO_PULL
n
10005390 0040
SEL18 18
Bit
Nam
e
Type
15 14
Ba
13 12 11 10 9 8 7
GPI
O2
79_
U
RW
6
GPI
O2
78_
U
RW
5
GPI
O2
77_
U
RW
O2
4
GPI
76_
U
RW
3
GPI
O27
5_
U
RW
2
GPI
O2
74_
U
RW
1
GPI
O2
73_
U
RW
0
GPI
O2
72_
U
RW
Reset 0 1 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
6
_U EL
f o r 0: Pull-down
1: Pull-up
5
4
Reserved
GPIO276
Reserved
a
GPIO276_PULLS
e s e I - R 2
Reserved
0: Pull-down
3
_U
GPIO275
_U
EL
l
Re Pi B
GPIO275_PULLS
EL
P 1: Pull-up
0: Pull-down
a
1: Pull-up
2
GPIO274
_U
n a
EL
n
GPIO274_PULLS
0: Pull-down
Ba
1: Pull-up
0 0: Pull-down
_U EL
1: Pull-up
100053A MSDC3_CTR
MSDC 3 RCLK Pad Control Register 3 0414
0 L7
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MS
MS MS MS MS MS MS MS MS
r
3R
3R 3R 3R 3R 3R 3R 3R 3R
o
Nam CK MS3RCK_BACK
f
MS3RCK_BACKUP1 CK CK CK CK CK CK CK CK
e _S _R _R
_P UP0
_IE _S _E _E _E
e
UP
2
MT 0 1 S R 8 4 2
Type
Reset 0 0
RW
0
l e
0
a s RW
0
I - RRW
1
RW
0
D
RW
0 0
RW
0 0
RW
1
RW
0
RW
1
RW
0
RW
0
Bit(s
)
Mnemon
ic
Re Pi B
Name P Description
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
15:12
UP1
l
Re Pi B
MS3RCK_BACK
P Reserved
a
11 MS3RCK_SMT 0:Disable
10
n a n
MS3RCK_R0
1:Enable
Ba
9 MS3RCK_R1 50K resistor control
8 MS3RCK_PUPD pull-up(0)/pull-down(1) control
MS3RCK_BACK
7:5 Reserved
UP0
4 MS3RCK_IES Input enable control
Output Slew Rate Control.
3 MS3RCK_SR 1: slower slew
0: no slew rate controlled
Driving Strength Control
000 : 2mA
001: 4mA
r
010: 6mA
2:0 MS3RCK_DRV
e f o 2
011: 8mA
100: 10mA
s
101: 12mA
l e a P I - R 110: 14mA
111: 16mA
Re Pi B
10005410
Bit 15
BIAS_CTRL3
14 13
a n a
12
11 10 9 8 7 6 5 4 3 2 1
0000
0
Nam
e
Type
Reset
GATE_MC02_CTRL
0 0
RW
Ba
0
n 0
GATE_MC01_CTRL
0 0
RW
0 0
GATE_NORB_CTRL
0 0
RW
0 0 0
GATE_NOR_CTRL
0
RW
0 0
Bit(s Mnemon
Name Description
) ic
GATE_MC02_CT
15:12 BIAS PAD TUNE Control
RL
GATE_MC01_CT
RL
GATE_NORB_C BIAS PAD TUNE Control
7:4
TRL
3:0
GATE_NOR_CT
RL
f o r BIAS PAD TUNE Control
e a s e I - R 2
10005420
Bit
Nam
15
BIAS_CTRL4
14 13 l
Re Pi B
12
BIAS_CTRL4_BACKUP0
P
11 10 9 8 7 6
GATE_MC1_CTRL
5 4 3 2
GATE_MC03_CTRL
1
0000
0
a
e
Ba
MT7623N
f o r
10005420 BIAS_CTRL4
e a s e R 2
I -
0000
l
Type RW RW RW
Reset
Bit(s
0
Mnemon
0 0
Re Pi B
0
P0 0 0 0 0 0 0 0 0 0 0 0
a
Name Description
) ic
15:8
n a n
BIAS_CTRL4_BA
CKUP0
Reserved
Ba
GATE_MC1_CTR BIAS PAD TUNE Control
7:4
L
GATE_MC03_CT BIAS PAD TUNE Control
3:0
RL
MSDC3_CTR
10005430 MSDC3 RCLK SEL Control Register 00AC
L8
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam MS3RCLK_BACKUP MS3RCLK_RDSEL MS3RCLK_TDSEL
e
Type
Reset 0 0 0
RW
0 0
f o r
0 0 0 1
RW
0 1 0 1 1
RW
0 0
Bit(s
)
Mnemon
ic
Name
15:10
9:4
UP
MS3RCLK_RDSE
l
Re Pi B
MS3RCLK_BACK
P Reserved
BIAS PAD TUNE Control
a
L
3:0
MS3RCLK_TDSE
L
n a n BIAS PAD TUNE Control
10005440
OD33_CTRL
11
B a 18OD33 IO Group TDSEL/RDSEL Control
Register 11
0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
OD33_BACKUP11 OD33_RDSEL11 OD33_TDSEL11
e
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
15:10
OD33_BACKUP1
1
f o r OD33 Control Reserve Registers
9:4
3:0
OD33_RDSEL11
e a
OD33_TDSEL11
s e I - R 2 RDSEL control register for eint17_tdsel
TDSEL control register for eint17_tdsel
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
10005450
OD33_CTRL
12
e a s e I - R 2
18OD33 IO Group TDSEL/RDSEL Control
Register 12
0000
Bit
Nam
e
Type
15 14 13
OD33_BACKUP12
RW
l
Re Pi B
12
P
11 10 9 8 7
OD33_RDSEL12
RW
6 5 4 3 2
OD33_TDSEL12
RW
1 0
Reset 0 0 0
a n a
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
15:10
Mnemon
ic
Ba n Name
OD33_BACKUP1
2
Description
OD33 Control Reserve Registers
9:4 OD33_RDSEL12 RDSEL control register for eint17_tdsel

3:0 OD33_TDSEL12 TDSEL control register for eint17_tdsel
OD33_CTRL 18OD33 IO Group TDSEL/RDSEL Control

10005460 0000
13 Register 13
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type
OD33_BACKUP13
RW
f o r OD33_RDSEL13
RW
OD33_TDSEL13
RW
Reset 0 0 0 0
e a s e 0
I - R 20 0 0 0 0 0 0 0 0 0 0
Bit(s
)
15:10
Mnemon
ic
l
Re Pi B
Name
OD33_BACKUP1
3
P Description
9:4
a n a
OD33_RDSEL13
RDSEL control register for uart2_tdsel, pcm_tdsel,
eint0_tdsel and eint5_tdsel
3:0
Ba n
OD33_TDSEL13
TDSEL control register for uart2_tdsel, pcm_tdsel,

10005470 0000
14 Register 14
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam OD33_BACKUP14 OD33_RDSEL14 OD33_TDSEL14
e
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Name
f o r Description
15:10
OD33_BACKUP1
4
e a s e I - R 2 OD33 Control Reserve Registers
9:4
3:0
l
OD33_RDSEL14
Re Pi B
OD33_TDSEL14
P
RDSEL control register for eint12_tdsel
a n a
n
Ba
MT7623N
f o r
100054C0
OD33_CTRL
8
e a s e I - R 2
Register 8
0000
Bit
Nam
e
Type
15 14 13
OD33_BACKUP8
RW
l
Re Pi B
12
P
11 10 9 8 7
OD33_RDSEL8
RW
6 5 4 3 2
OD33_TDSEL8
RW
1 0
Reset 0 0 0
a n a
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
15:10
9:4
Mnemon
ic
Ba n Name
OD33_BACKUP8
OD33_RDSEL8
Description

100054D OD33_CTRL 18OD33 IO Group TDSEL/RDSEL Control

0000
0 9 Register 9
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
r
e
Type
Reset 0 0 0
RW
0 0
e f o 0
2
0 0 0
RW
0 0 0 0 0
RW
0 0
Bit(s Mnemon
Name
l e a s I - R Description
)
15:10
9:4
ic
Re Pi B
OD33_BACKUP9
OD33_RDSEL9
P OD33 Control Reserve Registers
3:0 OD33_TDSEL9
a n a eint0_tdsel and eint5_tdsel

n
100054E0
OD33_CTRL B a 18OD33 IO Group TDSEL/RDSEL Control
0000
10 Register 10
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam OD33_BACKUP10 OD33_RDSEL10 OD33_TDSEL10
e
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
15:10
OD33_BACKUP1
0
f o r OD33 Control Reserve Registers
9:4
3:0
OD33_RDSEL10
e
OD33_TDSEL10
a s e I - R 2 RDSEL control register for eint12_tdsel
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
10005500
GPIO_DOUT
1
e a s e I - R 2 GPIO Data Output Register 1 0000
Bit
Nam
e
15
GP
O15
14
GP
O14
13
GP
O13
l
Re Pi B
12
GP
O12
GPP
11
O11
10
GP
O1
0
9
GP
O9
8
GP
O8
7
GP
O7
6
GP
O6
5
GP
O5
4
GP
O4
3
GP
O3
2
GP
O2
1
GP
O1
0
GP
O0
Type
Reset
RW
0
RW
0
RW
0
a
RW
n0
a RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit(s
)
Mnemon
ic
Ba n Name Description
GPIO 15 Data Output Value

15 GPO15 GPIO15_DOUT 0: Output 0
1: Output 1
1: Output 1
1: Output 1
12 GPO12 GPIO12_DOUT
f o r 0: Output 0
1: Output 1
e a s e I - R 2 GPIO 11 Data Output Value

0: Output 0
l
1: Output 1
10 GPO10
Re Pi B
GPIO10_DOUT
P GPIO 10 Data Output Value
0: Output 0
1: Output 1
9 GPO9
a n a
GPIO9_DOUT
0: Output 0
8 GPO8
Ba n
GPIO8_DOUT
1: Output 1
0: Output 0
1: Output 1
1: Output 1
1: Output 1
1: Output 1
4 GPO4 GPIO4_DOUT
f o r GPIO 4 Data Output Value

0: Output 0
3 GPO3
e
GPIO3_DOUT
a s e I - R 2
1: Output 1
0: Output 0
2 GPO2
l
Re Pi B
GPIO2_DOUT P 1: Output 1
0: Output 0
a
1: Output 1
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
1 GPO1
l
Re Pi B
GPIO1_DOUT
0: Output 0
1: Output 1
a
0 GPO0
n a n
GPIO0_DOUT 0: Output 0
1: Output 1
10005510
GPIO_DOUT
2
Ba GPIO Data Output Register 2 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP GP GP GP GP GP GP GP GP GP GP
Nam GP GP GP GP GP
O3 O2 O2 O2 O2 O2 O2 O2 O2 O2 O1
e O31 O21 O19 O17 O16
0 9 8 7 6 5 4 3 2 0 8
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic

e a s e I - R 2
0: Output 0
1: Output 1
l
14 GPO30
Re Pi B
GPIO30_DOUT
P 0: Output 0
1: Output 1
a
n a n 1: Output 1
Ba
1: Output 1
1: Output 1
1: Output 1
1: Output 1
r
e f o 2
1: Output 1
7 GPO23 GPIO23_DOUT
l e a s I - R
0: Output 0
1: Output 1
5
GPO22
GPO21 Re Pi B
GPIO22_DOUT
GPIO21_DOUT
0: Output 0
1: Output 1
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
4 GPO20
l
Re Pi B
GPIO20_DOUT
P 0: Output 0
1: Output 1
0: Output 0
a n a 1: Output 1
3
2
GPO19
GPO18
n
GPIO19_DOUT
Ba
GPIO18_DOUT
0: Output 0
1: Output 1
0: Output 0
1: Output 1
1: Output 1
1: Output 1
GPIO_DOUT
f o r
e
10005520 GPIO Data Output Register 3 0000
2
3
Bit 15
GP
14
GP
13
GP
l
12
GP
e a s 11
GP
I - R 10
GP
9
GP
8
GP
7 6
GP
5
GP
4
GP
3
GP
2
GP
1
GP
0
GP
P
Nam GP
Re Pi B
O4 O4 O4 O4 O4 O4 O4 O3 O3 O3 O3 O3 O3 O3 O3
e 7 6 5 4 3 2
O41
0 9 8 7 6 5 4 3 2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
a n a
)
15
ic
GPO47
Ba n Name
GPIO47_DOUT
Description

0: Output 0
1: Output 1
1: Output 1
1: Output 1
1: Output 1
0: Output 0
e a s e I - R 2 1: Output 1
10
9
GPO42
GPO41
l
GPIO42_DOUT
Re Pi B
GPIO41_DOUT P
0: Output 0
1: Output 1
0: Output 0
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
8 GPO40
l
Re Pi B
0: Output 0
1: Output 1
7 GPO39
a n a
GPIO39_DOUT
0: Output 0
6 GPO38
Ba n
GPIO38_DOUT
1: Output 1
0: Output 0
1: Output 1
1: Output 1
1: Output 1
1: Output 1
2 GPO34 GPIO34_DOUT
0: Output 0
e a s e I - R 2 1: Output 1
1
0
GPO33
GPO32
l
GPIO33_DOUT
Re Pi B
GPIO32_DOUT
P
0: Output 0
1: Output 1
0: Output 0
a n a 1: Output 1
10005530
GPIO_DOUT
4
Ba n GPIO Data Output Register 4 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP GP GP GP GP GP GP GP GP GP GP GP GP GP
Nam GP GP
O6 O6 O6 O5 O5 O5 O5 O5 O5 O5 O5 O5 O4 O4
e O61 O51
3 2 0 9 8 7 6 5 4 3 2 0 9 8
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic

0: Output 0
1: Output 1
e a s e I - R 2 GPIO 62 Data Output Value

0: Output 0
13 GPO61 l
Re Pi B
GPIO61_DOUT P
1: Output 1
0: Output 0
1: Output 1
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
12 GPO60
l
Re Pi B
GPIO60_DOUT
0: Output 0
1: Output 1
a
10 GPO58
a n
GPIO58_DOUT
n
0: Output 0
Ba
1: Output 1
1: Output 1
1: Output 1
1: Output 1
r
1: Output 1
5 GPO53 GPIO53_DOUT
e f o 2
0: Output 0
s
1: Output 1
4 GPO52
l e
GPIO52_DOUT
a P I - R GPIO 52 Data Output Value
0: Output 0
Re Pi B
1: Output 1
a n a 1: Output 1
2
1
GPO50
GPO49
n
GPIO50_DOUT
Ba
GPIO49_DOUT
0: Output 0
1: Output 1
0: Output 0
1: Output 1
1: Output 1
GPIO_DOUT
5
Bit
Nam
15
GP
14
GP
13 12
GP
11
GP
f o r 10
GP GP
9
GP
8 7 6
GP
5
GP
4
GP
3
GP
2
GP
1
GP
0
GP
e
GP GP
O7 O7 O7 O7 O7 O7 O7 O7 O6 O6 O6 O6 O6 O6
e
Type
Reset
9
RW
0
8
RW
0
O77
RW
0
6
RW
l
0
e a s 5
RW
0
I - R
4
RW
02 3
RW
0
2
RW
0
O71
RW
0
0
RW
0
9
RW
0
8
RW
0
7
RW
0
6
RW
0
5
RW
0
4
RW
0
Bit(s
)
Mnemon
ic Re Pi B
Name
P Description
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
15 GPO79
l
Re Pi B
GPIO79_DOUT
0: Output 0
1: Output 1
a
14 GPO78
n a n
1: Output 1
Ba
1: Output 1
1: Output 1
1: Output 1
1: Output 1
r
9 GPO73 GPIO73_DOUT
e f o 2
0: Output 0
1: Output 1
s
8 GPO72 GPIO72_DOUT
l e a P I - R 0: Output 0
1: Output 1
Re Pi B
1: Output 1
6 GPO70
a n a
GPIO70_DOUT
0: Output 0
5 GPO69
Ba n
GPIO69_DOUT
1: Output 1
0: Output 0
1: Output 1
1: Output 1
1: Output 1
1: Output 1
1 GPO65 GPIO65_DOUT

0: Output 0
0 GPO64
e
GPIO64_DOUT
a s e I - R 2
1: Output 1
l
0: Output 0
Re Pi B P 1: Output 1
a n a
n
Ba
MT7623N
f o r
10005550
GPIO_DOUT
6
Bit
Nam
e
15
GP
O9
5
14
GP
O9
4
13
GP
O9
3
l
Re Pi B
12
GP
O9
2
GPP
11
O91
10
GP
O9
0
GP
O8
9
9
GP
O8
8
8
GP
O8
7
7 6
GP
O8
6
5
GP
O8
5
4
GP
O8
4
3
GP
O8
3
2
GP
O8
2
1
GP
O8
1
0
GP
O8
0
Type
Reset
RW
0
RW
0
RW
0
a
RW
n0
a RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit(s
)
Mnemon
ic

1: Output 1
f o r 1: Output 1
9 GPO89 GPIO89_DOUT
e a s e I - R 2
0: Output 0
1: Output 1
l
8 GPO88
Re Pi B
GPIO88_DOUT
P 0: Output 0
1: Output 1
a
n a n 1: Output 1
Ba
1: Output 1
1: Output 1
1: Output 1
1: Output 1
r
e f o 2
1: Output 1
1 GPO81 GPIO81_DOUT
l e a s I - R
0: Output 0
1: Output 1
0 GPO80
Re Pi B
GPIO80_DOUT
0: Output 0
1: Output 1
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
10005560
Bit
Nam
15
GP
GPIO_DOUT
14
GP
7
13
GP
l
Re Pi B
12
GP GP
P
11 10
GP
GP
9
GP
8
GP
7 6
GP
5
GP
4
GP
3
GP
2
GP
1
GP
0000
0
GP
e
Type
O11
1
RW
O11
0
RW
O1
09
RW
a
O1
n
08
RW
a O1
07
RW
O1
06
RW
O1
05
RW
O1
04
RW
O1
03
RW
O1
02
RW
O1
01
RW
O1
00
RW
O9
9
RW
O9
8
RW
O9
7
RW
O9
6
RW
Reset
Bit(s
)
0
Mnemon
ic
0 0
Ba n 0
Name
0 0 0 0 0 0 0
Description
0 0 0 0 0

1: Output 1
1: Output 1
r
1: Output 1
e f o 2
0: Output 0
s
1: Output 1
11 GPO107
l e a
GPIO107_DOUT
P I - R GPIO 107 Data Output Value

0: Output 0
Re Pi B
1: Output 1
a n a 1: Output 1
9
8
GPO105
GPO104
n
GPIO105_DOUT
Ba
GPIO104_DOUT
0: Output 0
1: Output 1
0: Output 0
1: Output 1
1: Output 1
1: Output 1
f o r 1: Output 1
e a s e I - R 2
0: Output 0
1: Output 1
l
3
2
GPO99
GPO98 Re Pi B
GPIO99_DOUT
GPIO98_DOUT
P 0: Output 0
1: Output 1
a n a 0: Output 0
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
1 GPO97
l
Re Pi B
0: Output 0
1: Output 1
0 GPO96
a n a
GPIO96_DOUT
0: Output 0
Ba n 1: Output 1
GPIO_DOUT
8
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP GP
Nam
e
7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Name
f o r Description
15 Reserved Reserved
e a s e I - R 2
Reserved
l
13 GPO125
Re Pi B
GPIO125_DOUT
P 1: Output 1
0: Output 0
a n a 1: Output 1
12
11
GPO124
GPO123
n
GPIO124_DOUT
Ba
GPIO123_DOUT
0: Output 0
1: Output 1
0: Output 0
1: Output 1
1: Output 1
1: Output 1
f o r 1: Output 1
e
l e a s I - R 2 1: Output 1
6
5
GPO118
GPO117
Re Pi B
GPIO118_DOUT
GPIO117_DOUT
P 0: Output 0
1: Output 1
a
0: Output 0
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
4 GPO116
l
Re Pi B
0: Output 0
1: Output 1
3 GPO115
a n a
GPIO115_DOUT
0: Output 0
2 GPO114
Ba n
GPIO114_DOUT
1: Output 1
0: Output 0
1: Output 1
1: Output 1
1: Output 1
10005580
GPIO_DOUT
9
f o r GPIO Data Output Register 9 0000
Bit
Nam
15
GP
14
GP
13
GP
12
GP
e
11
a
GP
s e 10
GP
I - R 2 GP
9
GP
8
GP
7
GP
6
GP
5
GP
4
GP
3 2
GP
1
GP
0
GP
l
P
e
Re Pi B
3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Name
a n a Description
15:0 Reserved
B a n
Reserved Reserved
GPIO_DOUT
10
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
e 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Name
f o r Description
e a s e I - R 2 Reserved
100055A0
GPIO_DOUT
11
l
Re Pi B P GPIO Data Output Register 11 0000
a n a
n
Ba
MT7623N
f o r
100055A0
GPIO_DOUT
11
Bit
Nam
e
15
GP
O17
5
14
GP
O17
4
13
GP
O17
3
l
Re Pi B
12
GP
O17
2
11
GP
O17
1
P 10
GP
O17
0
GP
9
O16
9
GP
8
O16
8
GP
7
O16
7
GP
6
O16
6
GP
5
O16
5
GP
4
O16
4
GP
3
O16
3
2
GP
O16
2
1
GP
O16
1
0
GP
O16
0
Type
Reset
RW
0
RW
0
RW
0
a
RW
n
0
a RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit(s
)
15:0
Mnemon
ic
Reserved Ba n Name
Reserved
Description
Reserved
GPIO_DOUT
100055B0 GPIO Data Output Register 12 0000
12
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
e 1 0 89 88 87 86 85 84 83 82 81 80 9 8 7 6
Type
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
f o r RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit(s
)
Mnemon
ic
Name
15 GPO191 l
Re Pi B
GPIO191_DOUT
0: Output 0
1: Output 1
14 GPO190
n a
GPIO190_DOUT
a
0: Output 0
n
1: Output 1
Ba
1: Output 1
1: Output 1
GPIO_DOUT
100055C0 GPIO Data Output Register 13 0000
13
Bit
Nam
15
GP
14
GP
13
GP
12
GP
11
GP
f o r 10
GP GP
9
GP
8
GP
7
GP
6
GP
5
GP
4
GP
3 2
GP
1
GP
0
GP
e
e
Type
Reset
07
RW
0
06
RW
0
05
RW
0
04
RW
l
0
e a s
03
RW
0
I -
02
R
RW
02 01
RW
0
00
RW
0
9
RW
0
8
RW
0
7
RW
0
6
RW
0
5
RW
0
4
RW
0
3
RW
0
2
RW
0
Bit(s
)
Mnemon
ic
Re Pi B
Name P Description
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
15 GPO207
l
Re Pi B
GPIO207_DOUT
0: Output 0
1: Output 1
a
14 GPO206
n a n
1: Output 1
Ba
1: Output 1
1: Output 1
1: Output 1
1: Output 1
r
e f o 2
0: Output 0
1: Output 1
s
8 GPO200
l e a
GPIO200_DOUT
P I - R 0: Output 0
1: Output 1
Re Pi B
1: Output 1
6 GPO198
a n a
GPIO198_DOUT
0: Output 0
5 GPO197
Ba n
GPIO197_DOUT
1: Output 1
0: Output 0
1: Output 1
1: Output 1
1: Output 1
1: Output 1

0: Output 0
0 GPO192
e a
GPIO192_DOUT
s e I - R 2
1: Output 1
l
0: Output 0
Re Pi B P 1: Output 1
a n a
n
Ba
MT7623N
f o r
100055D
0
GPIO_DOUT
14
Bit
Nam
e
15
GP
O2
23
14
GP
O2
22
13
GP
O2
21
l
Re Pi B
12
GP
O2
20
GP
P
11
O21
9
10
GP
O21
8
GP
9
O21
7
GP
8
O21
6
GP
7
O21
5
GP
6
O21
4
GP
5
O21
3
GP
4
O21
2
GP
3
O21
1
2
GP
O21
0
1
GP
O2
09
0
GP
O2
08
Type
Reset
RW
0
RW
0
RW
0
a
RW
n0
a RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit(s
)
15:2
Mnemon
ic
Reserved Ba n Name
Reserved
Description
Reserved
1: Output 1
1: Output 1
100055E0
GPIO_DOUT
15
f o r GPIO Data Output Register 15 0000
Bit
Nam
15
GP
14
GP
13
GP
12
GP
e
11
a
GP
s e 10
GP
I - R 2 GP
9
GP
8
GP
7 6
GP
5
GP
4
GP
3
GP
2
GP
1
GP
0
GP
e
Type
Reset
O2
39
RW
0
O2
38
RW
0
O2
37
RW
0
O2
36
RW
0 l
Re Pi B
O2
35
RW
0 P
O2
34
RW
0
O2
33
RW
0
O2
32
RW
0
O2
31
RW
0
O2
30
RW
0
O2
29
RW
0
O2
28
RW
0
O2
27
RW
0
O2
26
RW
0
O2
25
RW
0
O2
24
RW
0
Bit(s
)
Mnemon
ic
Name
a n a Description
15 GPO239
B a n
GPIO239_DOUT
0: Output 0
1: Output 1
1: Output 1
1: Output 1
1: Output 1
f o r Reserved
GPIO_DOUT
e a s e I - R 2
100055F0
Bit
Nam
e
15
GP
O2
14
GP
O2
16
13
GP
O2
l
Re Pi B
12
GP
O2
GP
O2
P
11 10
GP
O2
9
GP
O2
8
GP
O2
7
GP
O2
6
GP
O2
5
GP
O2
4
GP
O2
3
GP
O2
2
GP
O2
1
GP
O2
0000
0
GP
O2
a n a
n
Ba
MT7623N
f o r
100055F0
GPIO_DOUT
16
Type
Reset
55
RW
0
54
RW
0
53
RW
0
l
Re Pi B
52
RW
0
51
RW
0P 50
RW
0
49
RW
0
48
RW
0
47
RW
0
46
RW
0
45
RW
0
44
RW
0
43
RW
0
42
RW
0
41
RW
0
40
RW
0
Bit(s Mnemon
a n a
Name Description
n
) ic
Ba
1: Output 1
1: Output 1
1: Output 1
1: Output 1

0: Output 0
10 GPO250
e a
GPIO250_DOUT
s e I - R 2
1: Output 1
0: Output 0
9 GPO249
l
Re Pi B
0: Output 0
a
1: Output 1
8 GPO248
a n
GPIO248_DOUT
n
0: Output 0
Ba
1: Output 1
1: Output 1
1: Output 1
1: Output 1
r
1: Output 1
e f o 2
0: Output 0
l e a s I - R
1: Output 1
P
Re Pi B
1: Output 1
0: Output 0
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
0 GPO240
l
Re Pi B
0: Output 0
1: Output 1
a n a
10005600
Bit 15
GPIO_DOUT
14
17
Ba
13
n 12 11 10
9 8 7 6 5 4 3 2 1
0000
0
Nam
e
71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
f o r 0: Output 0
1: Output 1
14 GPO270
a
GPIO270_DOUT
e s e I - R 2
0: Output 0
1: Output 1
13 GPO269 l
Re Pi B
GPIO269_DOUT
0: Output 0
1: Output 1
12 GPO268
n a
GPIO268_DOUT
a
0: Output 0
1: Output 1
11 GPO267
Ba n
GPIO267_DOUT
0: Output 0
1: Output 1
1: Output 1
1: Output 1
1: Output 1

0: Output 0
1: Output 1
6 GPO262
a
GPIO262_DOUT
e s e I - R 2 GPIO 262 Data Output Value

0: Output 0
5 GPO261 l
Re Pi B
GPIO261_DOUT P
1: Output 1
0: Output 0
1: Output 1
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
4 GPO260
l
Re Pi B
GPIO260_DOUT
0: Output 0
1: Output 1
a
3 GPO259
n a n
1: Output 1
Ba
1: Output 1
1: Output 1
1: Output 1
GPIO_DOUT
10005610
Bit 15 14
18
13 12
f
11
o r 10
9 8 7 6 5 4 3 2 1
0000
0
Nam
e
e a s e I - R 2 GP
O2
79
GP
O2
78
GP
O2
77
GP
O2
76
GP
O27
5
GP
O2
74
GP
O2
73
GP
O2
72
Type
Reset
l
Re Pi B P RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
a
Bit(s Mnemon
Name Description
)
7
ic
Reserved
n a n
Reserved Reserved
Ba
1: Output 1
1: Output 1
1: Output 1
1 Reserved Reserved
f o r 1: Output 1
Reserved
0 GPO272
a
GPIO272_DOUT
e s e I - R 2
0: Output 0
l
1: Output 1
Re Pi B P
a n a
n
Ba
MT7623N
f o r
10005620
MSDC3_CTR
L6
e a s e I - R 2 MSDC 3 Pad Control Register 00AC
Bit
Nam
e
Type
15 14 13
MS3PAD_BACKUP
RW
l
Re Pi B
12
P
11 10 9 8 7
MS3PAD_RDSEL
RW
6 5 4 3 2
MS3PAD_TDSEL
RW
1 0
Reset 0 0 0
a n a
0 0 0 0 0 1 0 1 0 1 1 0 0
Bit(s
)
15:10
Mnemon
ic
Ba n Name
MS3PAD_BACK
UP
Description
Reserved
9:4 MS3PAD_RDSEL RDSEL control register for MS3 PAD
3:0 MS3PAD_TDSEL TDSEL control register for MS3 PAD
10005630 GPIO_DIN1 GPIO Data Input Register 1 NA

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI
e
Type
Reset
15
RO
X
14
RO
X
13
RO
X
12
RO
X
11
f
RO
X
o r 10
RO
X
9
RO
X
8
RO
X
7
RO
X
6
RO
X
5
RO
X
4
RO
X
3
RO
X
2
RO
X
1
RO
X
0
RO
X
Bit(s Mnemon
e a s e I - R 2
l
Name Description
P
) ic
15
14
GPI15
GPI14
Re Pi B
GPIO15_DIN
GPIO14_DIN
GPIO 15 Data Input Value
13
12
GPI13
GPI12
a n a
GPIO13_DIN
GPIO12_DIN
11
10
9
8
GPI11
GPI10
GPI9
GPI8 Ba nGPIO11_DIN
GPIO10_DIN
GPIO9_DIN
GPIO8_DIN
7 GPI7 GPIO7_DIN GPIO 7 Data Input Value
0 GPI0 GPIO0_DIN
f o r GPIO 0 Data Input Value
10005640 GPIO_DIN2
e a s e I - R 2 GPIO Data Input Register 2 NA

Bit
Nam
e
Type
15
GPI
31
RO
14
GPI
30
RO
13
GPI
29
RO
l
Re Pi B
28
RO
12
GPI
27
RO
P
11
GPI
10
GPI
26
RO
25
RO
9
GPI
24
RO
8
GPI
23
RO
7
GPI
22
RO
6
GPI
5
GPI
21
RO
20
RO
4
GPI
19
RO
3
GPI
2
GPI
18
RO
GPI
17
RO
1 0
GPI
16
RO
a n a
n
Ba
MT7623N
f o r
10005640 GPIO_DIN2
l
Reset X X X X X X X X X X X X X X X X
Bit(s
)
Mnemon
ic Re Pi B
Name P Description
15 GPI31
n a
GPIO31_DIN
a
n
Ba
2 GPI18 GPIO18_DIN
e
0 GPI16 GPIO16_DIN
l e a s I - R 2 GPIO 16 Data Input Value
10005650 GPIO_DIN3
Re Pi B P GPIO Data Input Register 3 NA
Bit
Nam
e
15
GPI
47
14
GPI
46
13
GPI
45
a n
44
a
12
GPI
11
GPI
43
10
GPI
42 41
9
GPI
8
GPI
40
7
GPI
39
6
GPI
38
5
GPI
37
4
GPI
36
3
GPI
35
2
GPI
34
1
GPI
33
0
GPI
32
Type
Reset
Bit(s
RO
X
Mnemon
RO
X
RO
X
Ba n RO
X
Name
RO
X
RO
X
RO
X
RO
X
RO
X
RO
X
RO
X
Description
RO
X
RO
X
RO
X
RO
X
RO
X
) ic
r
8
7
GPI40
GPI39
GPIO40_DIN
GPIO39_DIN
e f o 2
6
5
GPI38
GPI37
l e a
GPIO38_DIN
GPIO37_DINs I - R
4
3
2
GPI36
GPI35
GPI34 Re Pi B
GPIO36_DIN
GPIO35_DIN
GPIO34_DIN
P GPIO 36 Data Input Value
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
1
0
GPI33
GPI32 l
Re Pi B
GPIO33_DIN
GPIO32_DIN
a n a
n
Ba
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
e 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48
Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Bit(s Mnemon
Name Description
) ic
11
10
Reserved
GPI58
Reserved
GPIO58_DIN
f o r Reserved
9
8
GPI57
GPI56
GPIO57_DIN
e a
GPIO56_DIN
s e I - R 2 GPIO 57 Data Input Value
7
6
5
GPI55
GPI54
GPI53
l
Re Pi B
GPIO55_DIN
GPIO54_DIN
GPIO53_DIN
4
3
GPI52
GPI51
a n a
GPIO52_DIN
GPIO51_DIN
2
1
0
GPI50
GPI49
GPI48
Ba n
GPIO50_DIN
GPIO49_DIN
GPIO48_DIN

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
e 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
Bit(s
)
Mnemon
ic
Name
f o r Description
15
14
GPI79
GPI78
GPIO79_DIN
e a
GPIO78_DIN
s e I - R 2 GPIO 79 Data Input Value
13
12
11
GPI77
GPI76
GPI75
l
Re Pi B
GPIO77_DIN
GPIO76_DIN
GPIO75_DIN
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
10
9
8
GPI74
GPI73
GPI72
l
Re Pi B
GPIO74_DIN
GPIO73_DIN
GPIO72_DIN
7
6
GPI71
GPI70
a n a
GPIO71_DIN
GPIO70_DIN
5
4
3
2
GPI69
GPI68
GPI67
GPI66
Ba n
GPIO69_DIN
GPIO68_DIN
GPIO67_DIN
GPIO66_DIN

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
e
Type
95
RO
94
RO
93
RO
92
RO
91
f
RO
o r 90
RO
89
RO
88
RO
87
RO
86
RO
85
RO
84
RO
83
RO
82
RO
81
RO
80
RO
e
Bit(s Mnemon
l e a s I - R 2
P
Name Description
Re Pi B
) ic
13
12
Reserved
Reserved
a n a
Reserved
Reserved
Reserved
Reserved
11
10
9
Reserved
GPI90
GPI89
Ba n Reserved
GPIO90_DIN
GPIO89_DIN
Reserved
0 GPI80 GPIO80_DIN
e a s e I - R 2
10005690
Bit
Nam
e
15
GPI
111
GPIO_DIN7
14
GPI
110
13
GPI
109
l
Re Pi B
12
GPI
108
P
11
GPI
107
10
GPI
106
9
GPI
105
8
GPI
104
7
GPI
103
6
GPI
102
5
GPI
101
4
GPI
100
3
GPI
99
2
GPI
98
1
GPI
97
NA
0
GPI
96
a
Ba
MT7623N
f o r
10005690 GPIO_DIN7
l
Bit(s
)
Mnemon
ic Re Pi B
Name P Description
15 GPI111
n a
GPIO111_DIN
a
n
Ba
2 GPI98 GPIO98_DIN
e
0 GPI96 GPIO96_DIN
l e a s I - R 2 GPIO 96 Data Input Value
100056A
GPIO_DIN8 Re Pi B P GPIO Data Input Register 8 NA
a
0
Bit
Nam
15
GPI
14
GPI
13
GPI
n a n12
GPI
11
GPI
10
GPI
9
GPI
8
GPI
7
GPI
6
GPI
5
GPI
4
GPI
3
GPI
2
GPI
1
GPI
0
GPI
Ba
e 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112
Bit(s Mnemon
Name Description
) ic
9 GPI121 GPIO121_DIN
e
7
6
GPI119
GPI118
GPIO119_DIN
l e a
GPIO118_DIN
s I - R 2 GPIO 119 Data Input Value
5
4
3
GPI117
GPI116
GPI115 Re Pi B
GPIO117_DIN
GPIO116_DIN
GPIO115_DIN
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
2
1
0
GPI114
GPI113
GPI112
l
Re Pi B
GPIO114_DIN
GPIO113_DIN
GPIO112_DIN
a n a
100056B
0
Bit
Nam
15
GPI
GPIO_DIN9
14
GPI
Ba
13
GPI
n 12
GPI
11
GPI
10
GPI
9
GPI
8
GPI
7
GPI
6
GPI
5
GPI
4
GPI
3
GPI
2
GPI
1
GPI
NA
0
GPI
e 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128
Bit(s Mnemon
Name Description
) ic
f o r
100056C0
Bit
Nam
15
GPI
GPIO_DIN10
14
GPI
13
GPI
12
GPI
e a s e11
GPI
I - R 2
10
GPI
9
GPI
8
GPI
7
GPI
6
GPI
5
GPI
4
GPI
3
GPI
2
GPI
1
GPI
NA
0
GPI
e
Type
Reset
159
RO
X
158
RO
X
157
RO
X l
Re Pi B
156
RO
X
155
RO
X
P 154
RO
X
153
RO
X
152
RO
X
151
RO
X
150
RO
X
149
RO
X
148
RO
X
147
RO
X
146
RO
X
145
RO
X
144
RO
X
Bit(s
)
Mnemon
ic
a n a
Name Description
15:0 Reserved
Ba n Reserved Reserved
100056D
GPIO_DIN11 GPIO Data Input Register 11 NA
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
e 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160
r
Bit(s Mnemon
Name Description
o
) ic
s e f 2
Reserved
l e a P I - R
Re Pi B
100056E0 GPIO_DIN12 GPIO Data Input Register 12 NA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
a n a
n
Ba
MT7623N
f o r
100056E0 GPIO_DIN12
l
e 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176
Type
Reset
RO
X
RO
X
RO
X
Re Pi B
RO
X
RO
X
P RO
X
RO
X
RO
X
RO
X
RO
X
RO
X
RO
X
RO
X
RO
X
RO
X
RO
X
Bit(s
)
Mnemon
ic
a n a
Name Description
15
14
13
12
GPI191
GPI190
GPI189
GPI188 Ba n
GPIO191_DIN
GPIO190_DIN
GPIO189_DIN
GPIO188_DIN
100056F0 GPIO_DIN13 GPIO Data Input Register 13 NA

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPI GPI GPI
Nam GPI
20
GPI
20
GPI GPI GPI
20
GPI GPI GPI GPI GPI GPI GPI GPI
e 207
6
205
4
203 202 201
0
199 198 197 196 195 194 193 192
Type
Reset
RO
X
RO
X
RO
X
RO
X
RO
f
X
o r RO
X
RO
X
RO
X
RO
X
RO
X
RO
X
RO
X
RO
X
RO
X
RO
X
RO
X
Bit(s Mnemon
e
Name
a s e I - R 2 Description
l
) ic
15
14
GPI207
GPI206
Re Pi B
GPIO207_DIN
GPIO206_DIN P GPIO 207 Data Input Value
a
12
11
GPI204
GPI203
n a n
GPIO204_DIN
GPIO203_DIN
Ba
r
e f o 2
10005700 GPIO_DIN14
l e a s I - R GPIO Data Input Register 14 NA

Bit
Nam
e
15
GPI
223
14
GPI
222
13
GPI
221
Re Pi B
12
GPI
220
11
GPI
219P 10
GPI
218
9
GPI
217
8
GPI
216
7
GPI
215
6
GPI
214
5
GPI
213
4
GPI
212
3
GPI
211
2
GPI
210
1
GPI
20
9
0
GPI
20
8
Type RO RO RO
a
RO
n a RO RO RO RO RO RO RO RO RO RO RO RO
n
Ba
MT7623N
f o r
10005700 GPIO_DIN14
l
Bit(s
)
Mnemon
ic Re Pi B
Name P Description
15:2 Reserved
n a
Reserved
a
Reserved
n
Ba

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
e 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224
Bit(s Mnemon
Name Description
r
) ic
15
14
GPI239
GPI238
GPIO239_DIN
GPIO238_DIN
e f o 2
13
12
GPI237
GPI236
l e a
GPIO237_DIN
GPIO236_DIN s I - R GPIO 237 Data Input Value
11:0 Reserved
Re Pi B
Reserved
P Reserved
10005720 GPIO_DIN16
a n a GPIO Data Input Register 16 NA

Bit
Nam
e
Type
Reset
15
GPI
255
RO
X
14
GPI
254
RO
X
RO
XBa
13
GPI
253 n 12
GPI
252
RO
X
11
GPI
251
RO
X
10
GPI
250
RO
X
9
GPI
249
RO
X
8
GPI
248
RO
X
7
GPI
247
RO
X
6
GPI
246
RO
X
5
GPI
245
RO
X
4
GPI
244
RO
X
3
GPI
243
RO
X
2
GPI
242
RO
X
1
GPI
241
RO
X
0
GPI
240
RO
X
Bit(s Mnemon
Name Description
) ic
11
10
GPI251
GPI250
GPIO251_DIN
GPIO250_DIN

9
8
GPI249
GPI248
GPIO249_DIN
a
GPIO248_DIN
e s e I - R 2
7
6
5
GPI247
GPI246
GPI245
l
GPIO247_DIN
Re Pi B
GPIO246_DIN
GPIO245_DIN P
a
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
3
2
1
GPI243
GPI242
GPI241
l
Re Pi B
GPIO243_DIN
GPIO242_DIN
GPIO241_DIN
0 GPI240
a
GPIO240_DIN
a n
10005730
Bit 15
GPIO_DIN17
14 Ba
13
n 12 11 10
9 8 7 6 5 4 3 2 1
NA
0
GPI
Nam GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI
26
e 271 270 269 268 267 266 265 264 263 262 261 259 258 257 256
0
Bit(s Mnemon
Name Description
) ic
14
13
GPI270
GPI269
GPIO270_DIN
GPIO269_DIN

12
11
GPI268
GPI267
GPIO268_DIN
GPIO267_DIN
e a s e I - R 2
10
9
8
GPI266
GPI265
GPI264
l
GPIO266_DIN
Re Pi B
GPIO265_DIN
GPIO264_DIN P
7
6
GPI263
GPI262
a n a
GPIO263_DIN
GPIO262_DIN
5
4
3
2
GPI261
GPI260
GPI259
GPI258 Ba n
GPIO261_DIN
GPIO260_DIN
GPIO259_DIN
GPIO258_DIN

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam GPI GPI GPI GPI GPI GPI GPI GPI
e
Type
Reset
f o r 279
RO
X
278
RO
X
277
RO
X
276
RO
X
275
RO
X
274
RO
X
273
RO
X
272
RO
X
Bit(s Mnemon
e a s e I - R 2
l
Name Description
P
) ic
7
6
Reserved
GPI278
Re Pi B
Reserved
GPIO278_DIN
Reserved
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
5
4
3
Reserved
GPI276
GPI275
l
Re Pi B
Reserved
GPIO276_DIN
GPIO275_DIN
P Reserved
2
1
GPI274
Reserved
a n a
GPIO274_DIN
Reserved
Reserved
0 GPI272
Ba n
GPIO272_DIN GPIO 272 Data Input Value
GPIO_MODE
10005760 GPIO Mode Control Register 1 1209
1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam GPIO4_M GPIO3_M GPIO2_M GPIO1_M GPIO0_M
e
Type RW RW RW RW RW
Reset 0 0 1 0 0 1 0 0 0 0 0 1 0 0 1
Bit(s Mnemon
r
Name Description
) ic
e f o 2
GPIO 4 Mode Selection
s
0: GPIO4 (IO)
GPIO4_
l e a P I - R 1: PWRAP_SPICS_B_I (O)
2: Reserved
Re Pi B
14:12 GPIO4_MODE 3: Reserved
M
4: Reserved
5: Reserved
6: Reserved
a n a 7: Reserved
11:9
GPIO3_
M
Ba n
GPIO3_MODE
0: GPIO3 (IO)
1: PWRAP_SPICK_I (O)
2: Reserved
3: Reserved
4: Reserved
5: Reserved
6: Reserved
7: Reserved
0: GPIO2 (IO)
1: PWRAP_INT (I)
GPIO2_ 2: Reserved
M
4: Reserved
5: Reserved
f o r 6: Reserved
7: Reserved
e a s e I - R 2
0: GPIO1 (IO)
1: PWRAP_SPIDI (IO)
5:3
GPIO1_
M
l
Re Pi B
GPIO1_MODE
P
2: PWRAP_SPIDO (IO)
3: Reserved
4: Reserved
5: Reserved
a
6: Reserved
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
Re Pi B P 7: Reserved
0: GPIO0 (IO)
1: PWRAP_SPIDO (IO)
2:0
GPIO0_
M
a n a
GPIO0_MODE
2: PWRAP_SPIDI (IO)
3: Reserved
Ba n 4: Reserved
5: Reserved
6: Reserved
7: Reserved
GPIO_MODE
2
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
e
Type RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1
Bit(s Mnemon
f o r
e
Name Description
) ic
l e a s I - R 2 GPIO 9 Mode Selection

0: GPIO9 (IO)
14:12
GPIO9_
M
Re Pi B
GPIO9_MODE P 1: SPI1_MO (O)
2: SPI1_MI (I)
3: EXT_FRAME_SYNC (I)
4: KCOL2 (IO)
a n a 5: Reserved
6: Reserved
Ba n 7: DBG_MON_B[14] (IO)
0: GPIO8 (IO)
1: SPI1_MI (I)
2: SPI1_MO (O)
GPIO8_
M
4: KCOL1 (IO)
5: Reserved
6: Reserved
7: DBG_MON_B[13] (IO)
0: GPIO7 (IO)
1: SPI1_CS (O)
GPIO7_ 2: Reserved
8:6 GPIO7_MODE
r
M 3: Reserved
o
4: KCOL0 (IO)
s e f 2
5: Reserved
6: Reserved
l e a P I - R GPIO 6 Mode Selection
Re Pi B
0: GPIO6 (IO)
GPIO6_ 1: PWRAP_SPICS2_B_I (O)
5:3 GPIO6_MODE
M 2: Reserved
3: Reserved
a n a 4: Reserved
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
Re Pi B P 5: ANT_SEL0 (O)
6: Reserved
7: DBG_MON_A[0] (IO)
a n a 0: GPIO5 (IO)
1: PWRAP_SPICK2_I (O)
2:0
GPIO5_
M
Ba n
GPIO5_MODE
2: Reserved
3: Reserved
4: Reserved
5: ANT_SEL1 (O)
6: Reserved
GPIO_MODE
3
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
e
Type
Reset 0
RW
0 0
f
0
o r RW
0 1 0
RW
0 1 0
RW
0 1 0
RW
0 1
Bit(s
)
Mnemon
ic
Name
l
Re Pi B P GPIO 14 Mode Selection
0: GPIO14 (IO)
1: URXD2 (I)
2: UTXD2 (O)
a
GPIO14_
M
n a n 4: Reserved
5: SRCCLKENAI2 (I)
Ba
6: Reserved
0: GPIO13 (IO)
1: SRCLKENAI (I)
GPIO13_ 2: Reserved
M
4: Reserved
5: Reserved
6: Reserved
7: Reserved
0: GPIO12 (IO)
r
1: SRCLKENA (O)
o
2: Reserved
f
GPIO12_
M
e a s e I - R 2
4: Reserved
5: Reserved
6: Reserved
5:3
GPIO11_
M
l
Re Pi B
GPIO11_MODE P
7: Reserved
0: GPIO11 (IO)
1: WATCHDOG (O)
a n a 2: Reserved
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
4: Reserved
5: Reserved
6: Reserved
a
7: Reserved
n a n GPIO 10 Mode Selection

0: GPIO10 (IO)
Ba
1: RTC32K_CK (I)
GPIO10_ 2: Reserved
M
4: Reserved
5: Reserved
6: Reserved
7: Reserved
GPIO_MODE
4
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type
GPIO19_M
RW
f o rGPIO18_M
RW
GPIO17_M
RW
GPIO16_M
RW
GPIO15_M
RW
Reset 0 0 0
e a s e 0
I - R 2
0 0 0 0 1 0 0 1 0 0 0
Bit(s
)
Mnemon
ic
l
Re Pi B
Name
P Description

0: GPIO19 (IO)
GPIO19_
a n a 1: PCM_SYNC (IO)
2: MRG_SYNC (IO)
n
M
Ba
4: Reserved
5: CONN_DSP_JINTP (O)
6: WCN_PCM_SYNC (IO)
0: GPIO18 (IO)
1: PCM_CLK0 (IO)
GPIO18_ 2: MRG_CLK (O)
M
4: MM_TEST_CK (I)
5: CONN_DSP_JCK (I)
6: WCN_PCM_CLKO (IO)
f o r 0: GPIO17 (IO)
1: Reserved
8:6
GPIO17_
M
GPIO17_MODE
e a s e I - R 2
2: Reserved
3: PCM_CLK0 (IO)
4: ANT_SEL2 (O)
5:3
GPIO16_
l
Re Pi B
GPIO16_MODE
P
5: Reserved
6: Reserved
7: Reserved
M
a n a 0: GPIO16 (IO)
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
2: Reserved
3: PCM_RX (I)
4: ANT_SEL4 (O)
a
5: Reserved
n a n 6: Reserved
7: Reserved
Ba
0: GPIO15 (IO)
1: UTXD2 (O)
GPIO15_ 2: URXD2 (I)
M
4: Reserved
5: Reserved
6: Reserved
GPIO_MODE
100057A0 GPIO Mode Control Register 5 0000
5
Bit
Nam
15 14 13 12 11
f o r
10 9 8 7 6 5 4 3 2 1 0
e
GPIO24_M GPIO23_M GPIO22_M GPIO21_M GPIO20_M
2
e
Type
Reset 0
RW
0 0
l e a0
s RW
I
0
- R 0 0
RW
0 0 0
RW
0 0 0
RW
0 0
Bit(s
)
Mnemon
ic
Re Pi B
Name P Description
a n a GPIO 24 Mode Selection

0: GPIO24 (IO)
14:12
GPIO24_
M
B a n
GPIO24_MODE
1: UCTS1 (I)
2: Reserved
3: KCOL1 (IO)
4: CONN_MCU_DBGACK_N (O)
5: Reserved
6: Reserved
0: GPIO23 (IO)
1: URTS0 (O)
GPIO23_ 2: Reserved
11:9 GPIO23_MODE 3: KCOL2 (IO)
M
4: CONN_MCU_TDO (O)
6: Reserved
f o r 7: DBG_MON_A[29] (IO)
GPIO22_
e a s e I - R 2
0: GPIO22 (IO)
1: UCTS0 (I)
2: Reserved
8:6
M
l
GPIO22_MODE
Re Pi B P
3: KCOL3 (IO)
4: CONN_DSP_JDO (O)
6: Reserved
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
0: GPIO21 (IO)
1: PCM_TX (O)
2: MRG_TX (O)
a
GPIO21_
5:3 GPIO21_MODE 3: MRG_RX (I)
n
M
4: PCM_RX (I)
n a 5: CONN_DSP_JMS (I)
Ba
6: WCN_PCM_TX (O)
0: GPIO20 (IO)
1: PCM_RX (I)
GPIO20_ 2: MRG_RX (I)
2:0 GPIO20_MODE 3: MRG_TX (O)
M
4: PCM_TX (O)
5: CONN_DSP_JDI (I)
6: WCN_PCM_RX (I)
100057B0
GPIO_MODE
6
f o rGPIO Mode Control Register 6 1000
Bit
Nam
15 14 13
GPIO29_M
12
e
11
a s e 10
I -
GPIO28_M
R 2 9 8 7
GPIO27_M
6 5 4
GPIO26_M
3 2 1
GPIO25_M
0
l
e
Type
Reset 0
RW
0
Re Pi B
1 0
PRW
0 0 0
RW
0 0 0
RW
0 0 0
RW
0 0
Bit(s
)
Mnemon
ic
Name
a n a Description
14:12
GPIO29_
M
B a n
GPIO29_MODE
0: GPIO29 (IO)
1: IDDIG (I)
2: MSDC1_WP (I)
3: KROW0 (IO)
4: CONN_MCU_TMS (I)
5: CONN_MCU_AICE_JMSC (IO)
6: Reserved
0: GPIO28 (IO)
1: DRV_VBUS (O)
GPIO28_ 2: Reserved
11:9 GPIO28_MODE 3: KROW1 (IO)
M
4: CONN_MCU_TRST_B (I)
f o r 5: Reserved
6: Reserved
e

0: GPIO27 (IO)
8:6
GPIO27_
M
Re Pi B
GPIO27_MODE
P 1: URTS3 (O)
2: IDDIG_P1 (I)
3: KROW2 (IO)
4: CONN_MCU_TDI (I)
a n a 5: Reserved
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
0: GPIO26 (IO)
GPIO26_
a n a 1: UCTS3 (I)
2: DRV_VBUS_P1 (O)
n
5:3 GPIO26_MODE 3: KROW3 (IO)
M
Ba
4: CONN_MCU_TCK0 (I)
5: CONN_MCU_AICE_JCKC (I)
6: Reserved
0: GPIO25 (IO)
1: URTS1 (O)
GPIO25_ 2: Reserved
2:0 GPIO25_MODE 3: KCOL0 (IO)
M
4: CONN_MCU_DBGI_N (I)
5: Reserved
6: Reserved
f o r
100057C0
GPIO_MODE
7
e a s e I - R 2 GPIO Mode Control Register 7 1249
Bit
Nam
e
Type
Reset
15 14
0
13
GPIO34_M
RW
0
l12
Re Pi B
1
11
P
0
10
GPIO33_M
RW
0
9
1
8
0
7
GPIO32_M
RW
0
6
1
5
0
4
GPIO31_M
RW
0
3
1
2
0
1
GPIO30_M
RW
0
0
a n a
n
Bit(s Mnemon
Name Description
Ba
) ic
0: GPIO34 (IO)
1: I2S1_DATA_IN (IO)
GPIO34_ 2: Reserved
14:12 GPIO34_MODE 3: PCM_RX (I)
M
4: VDEC_TEST_CK (I)
5: Reserved
6: WCN_PCM_RX (I)
0: GPIO33 (IO)
1: I2S1_DATA (IO)
r
GPIO33_ 2: I2S1_DATA_BYPS (O)
o
11:9 GPIO33_MODE 3: PCM_TX (O)
f
M
4: IMG_TEST_CK (I)
e a s e I - R 2
5: Reserved
6: WCN_PCM_TX (O)
8:6
GPIO32_
M
l
Re Pi B
GPIO32_MODE P GPIO 32 Mode Selection
0: GPIO32 (IO)
1: Reserved
2: Reserved
a n a 3: Reserved
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
5: Reserved
6: Reserved
7: Reserved

0: GPIO31 (IO)
5:3
GPIO31_
M
Ba n
GPIO31_MODE
1: Reserved
2: Reserved
3: Reserved
4: Reserved
5: Reserved
6: Reserved
7: Reserved
0: GPIO30 (IO)
1: Reserved
GPIO30_ 2: Reserved
M
4: Reserved
5: Reserved
6: Reserved
f o r 7: Reserved
100057D GPIO_MODE
e a s e I - R 2
0
Bit
Nam
e
15 14
8
13
GPIO39_M
l
Re Pi B
12
P
11 10
GPIO38_M
9 8 7
GPIO37_M
6 5 4
GPIO36_M
3 2 1
1249
GPIO35_M
0
Type
Reset 0
RW
0
a n a
1 0
RW
0 1 0
RW
0 1 0
RW
0 1 0
RW
0 1
Bit(s
)
Mnemon
ic

0: GPIO39 (IO)
1: JTMS (IO)
GPIO39_ 2: CONN_MCU_TMS (I)
14:12 GPIO39_MODE 3: CONN_MCU_AICE_JMSC (IO)
M
4: DFD_TMS_XI (I)
5: Reserved
6: Reserved
7: Reserved
r
0: GPIO38 (IO)
o
1: Reserved
11:9
GPIO38_
M
GPIO38_MODE
s e f 2
2: Reserved
3: Reserved
4: Reserved
l e a P I - R 5: Reserved
6: Reserved
Re Pi B
7: Reserved
GPIO37_
8:6 GPIO37_MODE 0: GPIO37 (IO)
M
a n a 1: I2S1_MCLK (IO)
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
3: Reserved
4: Reserved
5: Reserved
a
6: Reserved
n a n 7: DBG_MON_B[11] (IO)
Ba
0: GPIO36 (IO)
1: I2S1_LRCK (IO)
GPIO36_ 2: Reserved
5:3 GPIO36_MODE 3: PCM_SYNC (IO)
M
4: Reserved
5: Reserved
6: WCN_PCM_SYNC (IO)
0: GPIO35 (IO)
1: I2S1_BCK (IO)
GPIO35_ 2: Reserved
2:0 GPIO35_MODE 3: PCM_CLK0 (IO)
M
4: Reserved
f o r 5: Reserved
6: WCN_PCM_CLKO (IO)
e a s e I - R 2
100057E0
Bit 15
GPIO_MODE
14
9
13
l
Re Pi B
12
P
11 10
9 8 7 6 5 4 3 2 1
0049
0
Nam
e
GPIO44_M
a n a GPIO43_M GPIO42_M GPIO41_M GPIO40_M
n
Type RW RW RW RW RW
Ba
Reset 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1
Bit(s Mnemon
Name Description
) ic
0: GPIO44 (IO)
1: NCEB1 (O)
GPIO44_ 2: IDDIG (I)
M
4: Reserved
5: Reserved
6: Reserved
7: Reserved
f o r GPIO 43 Mode Selection

0: GPIO43 (IO)
11:9
GPIO43_
M
GPIO43_MODE
e a s e I - R 2
1: NCLE (O)
2: SFLASH_CS_L2 (O)
3: Reserved
l
Re Pi B P
4: Reserved
5: Reserved
6: Reserved
7: Reserved
8:6 GPIO42_
a n a
GPIO42_MODE GPIO 42 Mode Selection
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
Re Pi B P 0: GPIO42 (IO)
1: JTDO (O)
2: CONN_MCU_TDO (O)
3: Reserved
a
4: DFD_TDO (O)
n a n 5: Reserved
6: Reserved
7: Reserved
Ba
0: GPIO41 (IO)
1: JTDI (I)
GPIO41_ 2: CONN_MCU_TDI (I)
M
4: DFD_TDI_XI (I)
5: Reserved
6: Reserved
7: Reserved
0: GPIO40 (IO)
1: JTCK (I)
GPIO40_ 2: CONN_MCU_TCK1 (I)
2:0
M
GPIO40_MODE
f o r 3: CONN_MCU_AICE_JCKC (I)
4: DFD_TCK_XI (I)
5: Reserved
e a s e I - R 2 6: Reserved
7: Reserved
100057F0
GPIO_MODE
l
Re Pi B P GPIO Mode Control Register 10 1000
Bit 15 14
10
13
a n a
12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type
Reset 0
RW
0
Ba
GPIO49_M
n 1 0
GPIO48_M
RW
0 0 0
GPIO47_M
RW
0 0 0
GPIO46_M
RW
0 0 0
GPIO45_M
RW
0 0
Bit(s Mnemon
Name Description
) ic
0: GPIO49 (IO)
1: I2S0_DATA (IO)
GPIO49_ 2: I2S0_DATA_BYPS (O)
14:12 GPIO49_MODE 3: PCM_TX (O)
M
4: Reserved
5: Reserved
f o r 6: WCN_I2S_DO (O)
e
GPIO48_
l e a s I - R 2 0: GPIO48 (IO)
1: NRNB (I)
P
11:9 GPIO48_MODE 2: DRV_VBUS_P1 (O)
Re Pi B
M 3: Reserved
4: Reserved
5: Reserved
6: Reserved
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
0: GPIO47 (IO)
1: NREB (O)
8:6
GPIO47_
M
a n a
GPIO47_MODE
2: IDDIG_P1 (I)
3: Reserved
Ba n 4: Reserved
5: Reserved
6: Reserved
7: Reserved
0: GPIO46 (IO)
1: IR (I)
GPIO46_ 2: Reserved
M
4: Reserved
5: Reserved
6: Reserved
7: Reserved
r
0: GPIO45 (IO)
o
1: NCEB0 (O)
2:0
GPIO45_
M
GPIO45_MODE
s e f 2
2: DRV_VBUS (O)
3: Reserved
4: Reserved
6: Reserved
Re Pi B
7: Reserved
1000580 GPIO_MODE
a n a GPIO Mode Control Register 11 0049

0
Bit
Nam
e
Type
15 14
11
Ba
13
GPIO54_M
RW
n 12 11 10
GPIO53_M
RW
9 8 7
GPIO52_M
RW
6 5 4
GPIO51_M
RW
3 2 1
GPIO50_M
RW
0
Reset 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1
Bit(s Mnemon
Name Description
) ic
0: GPIO54 (IO)
1: SPI0_CK (O)
GPIO54_ 2: Reserved
14:12 GPIO54_MODE
r
M 3: SPDIF_IN1 (I)
o
4: ADC_DAT_IN (I)
s e f 2
5: Reserved
6: Reserved
Re Pi B
0: GPIO53 (IO)
GPIO53_ 1: SPI0_CS (O)
11:9 GPIO53_MODE
M 2: Reserved
3: SPDIF (O)
a n a 4: ADC_CK (O)
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
Re Pi B P 5: PWM1 (O)
6: Reserved
1: Reserved
8:6
GPIO52_
M
Ba n
GPIO52_MODE
2: Reserved
3: Reserved
4: Reserved
5: Reserved
6: Reserved
7: Reserved
0: GPIO51 (IO)
1: Reserved
GPIO51_ 2: Reserved
M
4: Reserved
5: Reserved
6: Reserved
7: Reserved

0: GPIO50 (IO)
2:0
GPIO50_
M
GPIO50_MODE
e a s e I - R 2
1: Reserved
2: Reserved
3: Reserved
l
Re Pi B P
4: Reserved
5: Reserved
6: Reserved
7: Reserved
a n a
10005810
Bit
Nam
15
GPIO_MODE
14
12
Ba
13
n 12 11
10 9 8 7 6 5 4 3 2 1
0240
0
e
Type RW RW RW RW RW
Reset 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
1: SCL1 (IO)
2: Reserved
e
GPIO58_
2
11:9 GPIO58_MODE
s
M 3: Reserved
5: Reserved
Re Pi B
6: Reserved
7: Reserved
GPIO57_ GPIO 57 Mode Selection
8:6 GPIO57_MODE
M 0: GPIO57 (IO)
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
Re Pi B P 1: SDA1 (IO)
2: Reserved
3: Reserved
4: Reserved
a
5: Reserved
n a n 6: Reserved
7: Reserved
Ba
0: GPIO56 (IO)
1: SPI0_MO (O)
GPIO56_ 2: SPI0_MI (I)
5:3 GPIO56_MODE 3: SPDIF_IN0 (I)
M
4: Reserved
5: Reserved
6: Reserved
0: GPIO55 (IO)
1: SPI0_MI (I)
GPIO55_ 2: SPI0_MO (O)
2:0 GPIO55_MODE 3: MSDC1_WP (I)
M
f o r 4: ADC_WS (O)
5: PWM2 (O)
6: Reserved
e a s e I - R 2 7: DBG_MON_A[8] (IO)
10005820
GPIO_MODE
13
l
Bit
Nam
15 14 13
GPIO64_M
a n a
12 11 10
GPIO63_M
9 8 7
GPIO62_M
6 5 4
GPIO61_M
3 2 1
GPIO60_M
0
e
Type
Reset
Bit(s Mnemon
0
RW
0
Ba n 1 0
RW
0 1 0
RW
0 1 0
RW
0 1 0
RW
0 1
Name Description
) ic
0: GPIO64 (IO)
1: WB_SDATA(IO)
GPIO64_ 2: Reserved
M
4: Reserved
5: Reserved
6: Reserved
GPIO63_
e a s e I - R 2
0: GPIO63 (IO)
1: WB_SCLK(O)
2: Reserved
11:9
M
l
GPIO63_MODE
Re Pi B P
3: Reserved
4: Reserved
5: Reserved
6: Reserved
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
0: GPIO62 (IO)
1: Reserved
2: Reserved
a
GPIO62_
n
M
4: Reserved
n a 5: Reserved
Ba
6: Reserved
0: GPIO61 (IO)
1: Reserved
GPIO61_ 2: Reserved
M
4: Reserved
5: Reserved
6: Reserved
0: GPIO60 (IO)
1: WB_RSTB(O)
2:0
GPIO60_
M
GPIO60_MODE
f o r 2: Reserved
3: Reserved
e
4: Reserved
l e a s I - R 2 5: Reserved
6: Reserved
Re Pi B P
10005830
GPIO_MODE
14
a n a GPIO Mode Control Register 14 1249
Bit
Nam
e
Type
Reset
15 14
0
13
RW
0Ba
GPIO69_M
n 12
1
11
0
10
GPIO68_M
RW
0
9
1
8
0
7
GPIO67_M
RW
0
6
1
5
0
4
GPIO66_M
RW
0
3
1
2
0
1
GPIO65_M
RW
0
0
Bit(s Mnemon
Name Description
) ic
0: GPIO69 (IO)
1: WB_CTRL3(IO)
GPIO69_ 2: Reserved
M
4: Reserved
f o r 5: DFD_TDI_XI (I)
6: Reserved
e

0: GPIO68 (IO)
11:9
GPIO68_
M
Re Pi B
GPIO68_MODE
P 1: WB_CTRL2(IO)
2: Reserved
3: Reserved
4: Reserved
a n a 5: DFD_TCK_XI (I)
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
0: GPIO67 (IO)
GPIO67_
a n a 1: WB_CTRL1(IO)
2: Reserved
n
M
Ba
4: Reserved
5: DFD_TMS_XI (I)
6: Reserved
0: GPIO66 (IO)
1: WBC_TRL0(IO)
GPIO66_ 2: Reserved
M
4: Reserved
5: DFD_NTRST_XI (I)
6: Reserved
1: WB_SEN(O)
2:0
GPIO65_
M
GPIO65_MODE
e a s e I - R 2
2: Reserved
3: Reserved
4: Reserved
l
Re Pi B P
5: Reserved
6: Reserved
a n a
10005840
Bit
Nam
e
15
GPIO_MODE
14
15
Ba
13
GPIO74_M
n 12 11 10
GPIO73_M
9 8 7
GPIO72_M
6 5 4
GPIO71_M
3 2 1
1249
GPIO70_M
0
Type RW RW RW RW RW
Reset 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1
Bit(s Mnemon
Name Description
) ic
0: GPIO74 (IO)
1: I2S0_BCK (IO)
r
GPIO74_ 2: Reserved
o
14:12 GPIO74_MODE 3: PCM_CLK0 (IO)
f
M
4: Reserved
e a s e I - R 2
5: Reserved
6: WCN_I2S_BCK (IO)
11:9
GPIO73_
M
l
Re Pi B
0: GPIO73 (IO)
1: I2S0_LRCK (IO)
2: Reserved
a n a 3: PCM_SYNC (IO)
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
5: Reserved
6: WCN_I2S_LRCK (IO)

0: GPIO72 (IO)
8:6
GPIO72_
M
Ba n
GPIO72_MODE
1: I2S0_DATA_IN (IO)
2: Reserved
3: PCM_RX (I)
4: PWM0 (O)
5: DISP_PWM (O)
6: WCN_I2S_DI (I)
0: GPIO71 (IO)
1: WB_CTRL5(IO)
GPIO71_ 2: Reserved
M
4: Reserved
5: Reserved
6: Reserved
GPIO70_
e a s e I - R 2
0: GPIO70 (IO)
1: WB_CTRL4(IO)
2: Reserved
2:0
M
l
GPIO70_MODE
Re Pi B P
3: Reserved
4: Reserved
5: DFD_TDO (O)
6: Reserved
a n a
10005850
Bit 15
GPIO_MODE
14
16
Ba
13
n 12 11
10 9 8 7 6 5 4 3 2 1
1249
0
e
Type RW RW RW RW RW
Reset 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1
Bit(s Mnemon
Name Description
) ic
r
0: GPIO79 (IO)
o
1: URXD0 (I)
14:12
GPIO79_
M
GPIO79_MODE
s e f 2
2: UTXD0 (O)
3: Reserved
4: Reserved
6: Reserved
Re Pi B
7: Reserved
GPIO78_
M
a n a 1: SCL2 (IO)
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
3: Reserved
4: Reserved
5: Reserved
a
6: Reserved
n a n 7: Reserved
Ba
0: GPIO77 (IO)
1: SDA2 (IO)
GPIO77_ 2: Reserved
M
4: Reserved
5: Reserved
6: Reserved
7: Reserved
0: GPIO76 (IO)
1: SCL0 (IO)
GPIO76_ 2: Reserved
M
4: Reserved
f o r 5: Reserved
6: Reserved
7: Reserved
e a s e I - R 2 GPIO 75 Mode Selection

0: GPIO75 (IO)
2:0
GPIO75_
M l
Re Pi B
GPIO75_MODE
P
1: SDA0 (IO)
2: Reserved
3: Reserved
4: Reserved
5: Reserved
a n a 6: Reserved
7: Reserved
10005860
GPIO_MODE Ba n GPIO Mode Control Register 17 0001
17
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
e
Type RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit(s Mnemon
Name Description
) ic

0: GPIO84 (IO)
14:12
GPIO84_
M
GPIO84_MODE
e a s e I - R 2
1: DSI_TE (I)
2: Reserved
3: Reserved
l
Re Pi B P
4: Reserved
5: Reserved
6: Reserved
11:9 GPIO83_
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
1: LCM_RST (O)
2: VDAC_CK_XI (I)
3: Reserved
a
4: Reserved
n a n 5: Reserved
6: Reserved
Ba
0: GPIO82 (IO)
1: UTXD1 (O)
GPIO82_ 2: URXD1 (I)
M
4: Reserved
5: Reserved
6: Reserved
7: Reserved
0: GPIO81 (IO)
1: URXD1 (I)
GPIO81_ 2: UTXD1 (O)
5:3
M
GPIO81_MODE
f o r 3: Reserved
4: Reserved
5: Reserved
7: Reserved
2:0
GPIO80_
l
Re Pi B
GPIO80_MODE
P
0: GPIO80 (IO)
1: UTXD0 (O)
2: URXD0 (I)
3: Reserved
M
a n a 4: Reserved
5: Reserved
Ba n 6: Reserved
7: Reserved
GPIO_MODE
18
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Name
f o r Description
e
GPIO89_
l e a s I - R 2 0: GPIO89 (IO)
1: Reserved
P
14:12 GPIO89_MODE 2: ANT_SEL4 (O)
Re Pi B
M 3: SDA2 (IO)
4: Reserved
5: UTXD1 (O)
6: PWM2 (O)
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
0: GPIO88 (IO)
1: Reserved
11:9
GPIO88_
M
a n a
GPIO88_MODE
2: ANT_SEL3 (O)
3: PWM0 (O)
Ba n 4: Reserved
5: URXD0 (I)
6: PWM1 (O)
7: Reserved
0: GPIO87 (IO)
1: Reserved
GPIO87_ 2: ANT_SEL2 (O)
M
4: Reserved
5: UTXD0 (O)
6: I2SOUT_DATA_OUT (O)
7: Reserved
r
0: GPIO86 (IO)
o
1: Reserved
5:3
GPIO86_
M
GPIO86_MODE
s e f 2
2: ANT_SEL1 (O)
3: SCL1 (IO)
4: Reserved
6: I2SOUT_LRCK (O)
Re Pi B
7: Reserved
0: GPIO85 (IO)
2:0
GPIO85_
a n a
GPIO85_MODE
1: Reserved
2: ANT_SEL0 (O)
n
M 3: SDA1 (IO)
Ba
4: Reserved
5: Reserved
6: I2SOUT_BCK (O)
7: Reserved
GPIO_MODE
19
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
e
Type RW RW RW RW RW
Reset
r
0 0 1 0 0 1 0 0 1 0 0 1 0 0 0
Bit(s Mnemon
Name
e f o 2
Description
)
15:0
ic
Reserved
e a
Reserved
l s I - R Reserved
Re Pi B P
a n a
n
Ba
MT7623N
f o r
10005890
GPIO_MODE
20
e a s e I - R 2GPIO Mode Control Register 20 1249
Bit
Nam
e
Type
15 14 13
GPIO99_M
RW
l
Re Pi B
12
P
11 10
GPIO98_M
RW
9 8 7
GPIO97_M
RW
6 5 4
GPIO96_M
RW
3 2 1
GPIO95_M
RW
0
Reset 0 0
a n a
1 0 0 1 0 0 1 0 0 1 0 0 1
Bit(s
)
Mnemon
ic

0: GPIO99 (IO)
1: MIPI_TDN0 (O)
GPIO99_ 2: Reserved
M
4: Reserved
5: Reserved
6: Reserved
7: Reserved
0: GPIO98 (IO)
r
1: MIPI_TDP1 (O)
o
2: Reserved
f
GPIO98_
M
e a s e I - R 2
4: Reserved
5: Reserved
6: Reserved
l
Re Pi B P
7: Reserved
0: GPIO97 (IO)
1: MIPI_TDN1 (O)
8:6
GPIO97_
M
n a
GPIO97_MODE
a
2: Reserved
3: Reserved
n
4: Reserved
Ba
5: Reserved
6: Reserved
7: Reserved
0: GPIO96 (IO)
1: MIPI_TCP (O)
GPIO96_ 2: Reserved
M
4: Reserved
5: Reserved
6: Reserved
7: Reserved
0: GPIO95 (IO)
GPIO95_
f o r 1: MIPI_TCN (O)
2: Reserved
e
2
M
l e a s I - R
4: Reserved
5: Reserved
6: Reserved
a n a
n
Ba
MT7623N
f o r
100058A
0
GPIO_MODE
21
Bit
Nam
e
Type
15 14
GPIO104_M
13
RW
l
Re Pi B
12
P
11 10
GPIO103_M
RW
9 8 7
GPIO102_M
RW
6 5 4
GPIO101_M
RW
3 2 1
GPIO100_M
RW
0
Reset 0 0
a n a
0 0 0 0 0 0 0 0 0 0 0 0 1
Bit(s
)
Mnemon
ic

0: GPIO104 (IO)
1: SPI2_CK (O)
GPIO104 2: Reserved
_M
4: KROW3 (IO)
5: Reserved
6: Reserved
7: Reserved
0: GPIO103 (IO)
r
1: SPI2_MO (O)
o
2: SPI2_MI (I)
f
GPIO103
_M
e a s e I - R 2
4: KROW2 (IO)
5: Reserved
6: Reserved
l
Re Pi B P
7: Reserved
0: GPIO102 (IO)
1: SPI2_MI (I)
8:6
GPIO102
_M
n a
GPIO102_MODE
a
2: SPI2_MO (O)
3: Reserved
n
4: KROW1 (IO)
Ba
5: Reserved
6: Reserved
7: Reserved
0: GPIO101 (IO)
1: SPI2_CS (O)
GPIO101 2: Reserved
_M
4: KROW0 (IO)
5: Reserved
6: Reserved
7: Reserved
0: GPIO100 (IO)
GPIO100
f o r 1: MIPI_TDP0 (O)
2: Reserved
e
2
_M
l e a s I - R
4: Reserved
5: Reserved
6: Reserved
a n a
n
Ba
MT7623N
f o r
100058B
0
GPIO_MODE
22
Bit
Nam
e
Type
15 14
GPIO109_M
13
RW
l
Re Pi B
12
P
11 10
GPIO108_M
RW
9 8 7
GPIO107_M
RW
6 5 4
GPIO106_M
RW
3 2 1
GPIO105_M
RW
0
Reset 0 0
a n a
1 0 0 1 0 0 1 0 0 1 0 0 1
Bit(s
)
Mnemon
ic

0: GPIO109 (IO)
1: MSDC1_DAT2 (IO)
GPIO109 2: ANT_SEL4 (O)
14:12 GPIO109_MODE 3: SDA2 (IO)
_M
4: Reserved
5: UTXD1 (O)
6: PWM2 (O)
0: GPIO108 (IO)
r
1: MSDC1_DAT1 (IO)
o
2: ANT_SEL3 (O)
f
GPIO108
11:9 GPIO108_MODE 3: PWM0 (O)
_M
e a s e I - R 2
4: Reserved
5: URXD0 (I)
6: PWM1 (O)
l
Re Pi B P
0: GPIO107 (IO)
1: MSDC1_DAT0 (IO)
8:6
GPIO107
_M
n a
GPIO107_MODE
a
2: ANT_SEL2 (O)
3: Reserved
n
4: Reserved
Ba
5: UTXD0 (O)
6: I2SOUT_DATA_OUT (O)
0: GPIO106 (IO)
1: MSDC1_CLK (O)
GPIO106 2: ANT_SEL1 (O)
5:3 GPIO106_MODE 3: SCL1 (IO)
_M
4: Reserved
5: Reserved
6: I2SOUT_LRCK (O)
0: GPIO105 (IO)
GPIO105
f o r 1: MSDC1_CMD (IO)
2: ANT_SEL0 (O)
e
2:0 GPIO105_MODE 3: SDA1 (IO)
2
_M
l e a s I - R
4: Reserved
5: Reserved
6: I2SOUT_BCK (O)
Re Pi B P 7: DBG_MON_B[27] (IO)
a n a
n
Ba
MT7623N
f o r
100058C
0
GPIO_MODE
23
Bit
Nam
e
Type
15 14
GPIO114_M
13
RW
l
Re Pi B
12
P
11 10
GPIO113_M
RW
9 8 7
GPIO112_M
RW
6 5 4
GPIO111_M
RW
3 2 1
GPIO110_M
RW
0
Reset 0 0
a n a
1 0 0 1 0 0 1 0 0 1 0 0 1
Bit(s
)
Mnemon
ic

0: GPIO114 (IO)
1: MSDC0_DAT4 (IO)
GPIO114 2: Reserved
_M
4: NLD4 (IO)
5: Reserved
6: Reserved
7: Reserved
0: GPIO113 (IO)
r
1: MSDC0_DAT5 (IO)
o
2: Reserved
f
GPIO113
_M
e a s e I - R 2
4: NLD5 (IO)
5: Reserved
6: Reserved
l
Re Pi B P
7: Reserved
0: GPIO112 (IO)
1: MSDC0_DAT6 (IO)
8:6
GPIO112
_M
n a
GPIO112_MODE
a
2: Reserved
3: Reserved
n
4: NLD6 (IO)
Ba
5: Reserved
6: Reserved
7: Reserved
0: GPIO111 (IO)
1: MSDC0_DAT7 (IO)
GPIO111_ 2: Reserved
M
4: NLD7 (IO)
5: Reserved
6: Reserved
7: Reserved
0: GPIO110 (IO)
GPIO110
f o r 1: MSDC1_DAT3 (IO)
2: ANT_SEL5 (O)
e
2:0 GPIO110_MODE 3: SCL2 (IO)
2
_M
l e a s I - R
5: URXD1 (I)
6: PWM3 (O)
Re Pi B P 7: DBG_MON_B[23] (IO)
a n a
n
Ba
MT7623N
f o r
100058D
0
GPIO_MODE
24
Bit
Nam
e
Type
15 14
GPIO119_M
13
RW
l
Re Pi B
12
P
11 10
GPIO118_M
RW
9 8 7
GPIO117_M
RW
6 5 4
GPIO116_M
RW
3 2 1
GPIO115_M
RW
0
Reset 0 0
a n a
1 0 0 1 0 0 1 0 0 1 0 0 1
Bit(s
)
Mnemon
ic

0: GPIO119 (IO)
1: MSDC0_DAT2 (IO)
GPIO119 2: Reserved
_M
4: NLD2 (IO)
5: Reserved
6: Reserved
7: Reserved
0: GPIO118 (IO)
r
1: MSDC0_DAT3 (IO)
o
2: Reserved
f
GPIO118
_M
e a s e I - R 2
4: NLD3 (IO)
5: Reserved
6: Reserved
l
Re Pi B P
7: Reserved
0: GPIO117 (IO)
1: MSDC0_CLK (O)
8:6
GPIO117
_M
n a
GPIO117_MODE
a
2: Reserved
3: Reserved
n
4: NWEB (O)
Ba
5: Reserved
6: Reserved
7: Reserved
0: GPIO116 (IO)
1: MSDC0_CMD (IO)
GPIO116 2: Reserved
_M
4: NALE (O)
5: Reserved
6: Reserved
7: Reserved
0: GPIO115 (IO)
GPIO115
f o r 1: MSDC0_RSTB (O)
2: Reserved
e
2
_M
l e a s I - R
4: NLD8 (IO)
5: Reserved
6: Reserved
a n a
n
Ba
MT7623N
f o r
100058E
0
GPIO_MODE
25
Bit
Nam
e
Type
15 14
GPIO124_M
13
RW
l
Re Pi B
12
P
11 10
GPIO123_M
RW
9 8 7
GPIO122_M
RW
6 5 4
GPIO121_M
RW
3 2 1
GPIO120_M
RW
0
Reset 0 0
a n a
1 0 0 1 0 0 1 0 0 1 0 0 1
Bit(s
)
Mnemon
ic

0: GPIO124 (IO)
1: HDMISCK (IO)
GPIO124 2: Reserved
_M
4: SDA1 (IO)
5: PWM3 (O)
6: Reserved
7: Reserved
0: GPIO123 (IO)
r
1: HTPLG (I)
o
2: Reserved
f
GPIO123
_M
e a s e I - R 2
4: SCL2 (IO)
5: UTXD0 (O)
6: Reserved
l
Re Pi B P
7: Reserved
0: GPIO122 (IO)
1: CEC (IO)
8:6
GPIO122
_M
n a
GPIO122_MODE
a
2: Reserved
3: Reserved
n
4: SDA2 (IO)
Ba
5: URXD0 (I)
6: Reserved
7: Reserved
0: GPIO121 (IO)
1: MSDC0_DAT0 (IO)
GPIO121 2: Reserved
_M
4: NLD0 (IO)
5: WATCHDOG (O)
6: Reserved
7: Reserved
0: GPIO120 (IO)
GPIO120
f o r 1: MSDC0_DAT1 (IO)
2: Reserved
e
2
_M
l e a s I - R
4: NLD1 (IO)
5: Reserved
6: Reserved
a n a
n
Ba
MT7623N
f o r
100058F0
GPIO_MODE
26
Bit
Nam
e
Type
15 14
GPIO129_M
13
RW
l
Re Pi B
12
P
11 10
GPIO128_M
RW
9 8 7
GPIO127_M
RW
6 5 4
GPIO126_M
RW
3 2 1
GPIO125_M
RW
0
Reset 0 0
a n a
0 0 0 0 0 0 0 0 0 1 0 0 1
Bit(s
)
14:12
11:9
Mnemon
ic
Reserved
Reserved
Ba n Name
Reserved
Reserved
Description
Reserved
Reserved
0: GPIO126 (IO)
1: I2S0_MCLK (IO)
GPIO126 2: Reserved
_M
4: Reserved
5: Reserved
6: WCN_I2S_MCLK (O)
f o r 7: DBG_MON_B[6] (IO)
e a s e I - R 2
0: GPIO125 (IO)
1: HDMISD (IO)
2: Reserved
l
GPIO125
P
Re Pi B
_M
4: SCL1 (IO)
5: PWM4 (O)
6: Reserved
a
7: Reserved
n a n
10005900
Bit
Nam
e
15
GPIO_MODE
14
27
GPIO134_M
Ba
13 12 11
10
GPIO133_M
9 8 7
GPIO132_M
6 5 4
GPIO131_M
3 2 1
GPIO130_M
0000
Type RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
f o r
10005910
GPIO_MODE
28
Bit
Nam
e
Type
15 14
GPIO139_M
13
RW
l
Re Pi B
12
P
11 10
GPIO138_M
RW
9 8 7
GPIO137_M
RW
6 5 4
GPIO136_M
RW
3 2 1
GPIO135_M
RW
0
Reset 0 0
a n a
0 0 0 0 0 0 0 0 0 0 0 0 0
n
Ba
MT7623N
f o r
Bit(s Mnemon
e a s e I - R 2
)
14:0
ic
Reserved l
Name
Re Pi B
Reserved
P
Description
Reserved
a n a
n
GPIO_MODE
Ba
29
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
10005930
GPIO_MODE
f o r GPIO Mode Control Register 30 0000
e
30
Bit
Nam
15 14
GPIO149_M
13
l
12
e a s 11
I - R 2
10
GPIO148_M
9 8 7
GPIO147_M
6 5 4
GPIO146_M
3 2 1
GPIO145_M
0
P
e
Re Pi B
Type RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
a n a
Name Description
14:0 Reserved
GPIO_MODE
31
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
e
Type RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
)
14:0
ic
Reserved
Name
Reserved
f o r Description
Reserved
e a s e I - R 2
10005950
Bit 15
GPIO_MODE
14
32
13
l
Re Pi B
12
P
11
10 9 8 7 6 5 4 3 2 1
0000
a n a
n
Ba
MT7623N
f o r
10005950
GPIO_MODE
32
Nam
e
Type
Reset 0
GPIO159_M
RW
0
l
Re Pi B
0
P
0
GPIO158_M
RW
0 0 0
GPIO157_M
RW
0 0 0
GPIO156_M
RW
0 0 0
GPIO155_M
RW
0 0
a n a
n
Bit(s Mnemon
Name Description
Ba
) ic
GPIO_MODE
33
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
e
Type RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Name
f o r Description
e a s e I - R 2 Reserved
10005970
GPIO_MODE
l
a
34
Bit
Nam
15 14
GPIO169_M
13
n a n12 11 10
GPIO168_M
9 8 7
GPIO167_M
6 5 4
GPIO166_M
3 2 1
GPIO165_M
0
Ba
e
Type RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
GPIO_MODE
35
Bit
Nam
e
15 14
GPIO174_M
13 12 11
f o r
10
GPIO173_M
9 8 7
GPIO172_M
6 5 4
GPIO171_M
3 2 1
GPIO170_M
0
Type
Reset 0
RW
0 0
e a
0
s e RW
0
I - R 2 0 0
RW
0 0 0
RW
0 0 0
RW
0 0
Bit(s
)
14:0
Mnemon
ic
Reserved
Name
Reserved
l
Re Pi B P Description
Reserved
a n a
n
B a
MT7623N
f o r
e a s e I - R 2
10005990
Bit 15
GPIO_MODE
14
36
13
l
Re Pi B
12
P
11
10 9 8 7 6 5 4 3 2 1
0000
0
Nam
e
GPIO179_M
a n a GPIO178_M GPIO177_M GPIO176_M GPIO175_M
n
Type RW RW RW RW RW
Ba
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
100059A GPIO_MODE
GPIO Mode Control Register 37 0000
0 37
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
r
e
Type
Reset 0
RW
0 0 0
e f o
RW
0
2
0 0
RW
0 0 0
RW
0 0 0
RW
0 0
Bit(s Mnemon
Name
)
14:0
ic
Reserved
Re Pi B
Reserved
P Reserved
a n a
100059B
0
Bit
Nam
e
15
GPIO_MODE
14
38
GPIO189_M B
13
a n
12 11
10
GPIO188_M
9 8 7
GPIO187_M
6 5 4
GPIO186_M
3 2 1
GPIO185_M
1200
Type RW RW RW RW RW
Reset 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
0: GPIO189 (IO)
1: Reserved
r
GPIO189 2:Reserved
o
f
_M
4: Reserved
e a s e I - R 2
5: Reserved
6: Reserved
7: Reserved
11:9
GPIO188
_M
l
Re Pi B
0: GPIO188 (IO)
1: Reserved
2: Reserved
a n a 3: Reserved
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
5: Reserved
6: Reserved
7: Reserved
8:6
5:3
Reserved
Reserved
a n a
Reserved
Reserved
Reserved
Reserved
2:0 Reserved
GPIO_MODE
100059C0 GPIO Mode Control Register 39 1249
39
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
e
Type RW RW RW RW RW
Reset 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1
Bit(s Mnemon
r
Name Description
) ic
e f o 2
s
0: GPIO194 (IO)
GPIO194
2: Reserved
Re Pi B
_M
4: Reserved
5: Reserved
6: Reserved
a n a 7: Reserved
11:9
GPIO193
_M
Ba n
GPIO193_MODE
0: GPIO193 (IO)
1: Reserved
2: Reserved
3: Reserved
4: Reserved
5: Reserved
6: Reserved
7: Reserved
0: GPIO192 (IO)
1: Reserved
GPIO192 2: Reserved
_M
4: Reserved
5: Reserved
f o r 6: Reserved
7: Reserved
e a s e I - R 2
0: GPIO191 (IO)
1: Reserved
5:3
GPIO191
_M
l
Re Pi B
GPIO191_MODE
P
2: Reserved
3: Reserved
4: Reserved
5: Reserved
a
6: Reserved
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
0: GPIO190 (IO)
1: Reserved
2:0
GPIO190
_M
a n a
GPIO190_MODE
2: Reserved
3: Reserved
Ba n 4: Reserved
5: Reserved
6: Reserved
7: Reserved
100059D GPIO_MODE
0 40
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
e
Type RW RW RW RW RW
Reset 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1
Bit(s Mnemon
f o r
e
Name Description
) ic

0: GPIO199 (IO)
14:12
GPIO199
_M
Re Pi B
GPIO199_MODE P 1: SPI1_CK (O)
2: Reserved
4: KCOL3 (IO)
a n a 5: Reserved
6: Reserved
Ba n 7: DBG_MON_B[15] (IO)
0: GPIO198 (IO)
1: Reserved
2: Reserved
GPIO198
_M
4: Reserved
5: Reserved
6: Reserved
7: Reserved
0: GPIO197 (IO)
1: Reserved
GPIO197 2: Reserved
8:6 GPIO197_MODE
r
_M 3: Reserved
o
4: Reserved
s e f 2
5: Reserved
6: Reserved
7: Reserved
Re Pi B
0: GPIO196 (IO)
GPIO196 1: Reserved
5:3 GPIO196_MODE
_M 2: Reserved
3: Reserved
a n a 4: Reserved
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
6: Reserved
7: Reserved
1: Reserved
2:0
GPIO195
_M
Ba n
GPIO195_MODE
2: Reserved
3: Reserved
4: Reserved
5: Reserved
6: Reserved
7: Reserved
GPIO_MODE
100059E0 GPIO Mode Control Register 41 0000
41
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
e
Type
Reset 0
RW
0 0
f
0
o r RW
0 0 0
RW
0 0 0
RW
0 0 0
RW
0 0
Bit(s
)
Mnemon
ic
Name
l
0: GPIO204 (IO)
1: PWM1 (O)
2: CLKM3 (O)
a
GPIO204
_M
n a n 4: Reserved
5: Reserved
Ba
6: Reserved
0: GPIO203 (IO)
1: PWM0 (O)
GPIO203 2: DISP_PWM (O)
_M
4: Reserved
5: Reserved
6: Reserved
0: GPIO202 (IO)
r
1: SPDIF_IN1 (I)
o
2: Reserved
f
GPIO202
_M
e a s e I - R 2
4: Reserved
5: Reserved
6: Reserved
5:3
GPIO201
_M
l
Re Pi B
GPIO201_MODE P
7: Reserved
0: GPIO201 (IO)
1: SPDIF_IN0 (I)
a n a 2: Reserved
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
4: Reserved
5: Reserved
6: Reserved
a

0: GPIO200 (IO)
Ba
1: SPDIF_OUT (O)
GPIO200 2: Reserved
_M
4: Reserved
5: Reserved
6: Reserved
GPIO_MODE
100059F0 GPIO Mode Control Register 42 1200
42
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type
GPIO209_M
RW
f o r
GPIO208_M
RW
GPIO207_M
RW
GPIO206_M
RW
GPIO205_M
RW
Reset 0 0 1
e a s e 0
I - R 2
0 1 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
l
Re Pi B
Name
P Description

0: GPIO209 (IO)
GPIO209
a n a 1: AUD_EXT_CK2 (I)
2: MSDC1_WP (I)
n
_M
Ba
4: Reserved
5: PWM1 (O)
6: Reserved
0: GPIO208 (IO)
1: AUD_EXT_CK1 (I)
GPIO208 2: PWM0 (O)
_M
4: ANT_SEL5 (O)
5: DISP_PWM (O)
6: Reserved
1: PWM4 (O)
8:6
GPIO207
_M
GPIO207_MODE
e a s e I - R 2
2: CLKM0 (O)
4: Reserved
5:3
GPIO206
l
Re Pi B
GPIO206_MODE
P
5: Reserved
6: Reserved
_M
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
Re Pi B P 1: PWM3 (O)
2: CLKM1 (O)
4: Reserved
a
5: Reserved
n a n 6: Reserved
Ba
0: GPIO205 (IO)
1: PWM2 (O)
GPIO205 2: CLKM2 (O)
_M
4: Reserved
5: Reserved
6: Reserved
10005A0 GPIO_MODE
0 43
Bit
Nam
15 14 13 12 11
f o r
10 9 8 7 6 5 4 3 2 1 0
e
2
e
Type
Reset 0
RW
0 0
l e a0
s RW
I
0
- R 0 0
RW
0 0 0
RW
0 0 0
RW
0 0
Bit(s
)
Mnemon
ic
Re Pi B
Name P Description
a n a Reserved
10005A10
GPIO_MODE
44 B a n GPIO Mode Control Register 44 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
f o r
10005A2
0
GPIO_MODE
45
Bit
Nam
e
Type
15 14
GPIO224_M
13
RW
l
Re Pi B
12
P
11 10
GPIO223_M
RW
9 8 7
GPIO222_M
RW
6 5 4
GPIO221_M
RW
3 2 1
GPIO220_M
RW
0
a n a
n
Ba
MT7623N
f o r
10005A2
0
GPIO_MODE
45
Reset
Bit(s Mnemon
0 0
l
Re Pi B
0
P
0 0 0 0 0 0 0 0 0 0 0 0
)
14:0
ic
Reserved
a n a
Name
Reserved
Description
Reserved
10005A3 GPIO_MODE Ba n
0 46
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
f o r Reserved
e a s e I - R 2
10005A4
0
Bit
Nam
15
GPIO_MODE
14
47
13 l
Re Pi B
12 P
11
10 9 8 7 6 5 4 3 2 1
0000
a
e
Type
Reset 0
RW
0
n a n 0 0
RW
0 0 0
RW
0 0 0
RW
0 0 0
RW
0 0
Bit(s
)
14:0
Mnemon
ic
Reserved
Ba Name
Reserved
Description
Reserved
GPIO_MODE
48
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
e
Type
Reset 0
RW
0 0 0
f
RW
o0
r 0 0
RW
0 0 0
RW
0 0 0
RW
0 0
Bit(s
)
Mnemon
ic
Name
14:12
GPIO239
_M
GPIO239_MODE l
0: GPIO239 (IO)
1: SFLASH_IO_0 (IO)
a
2: DRV_VBUS_P1 (O)
B a
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
4: Reserved
5: Reserved
6: Reserved
a
7: Reserved

0: GPIO238 (IO)
Ba
1: SFLASH_IO_1 (IO)
GPIO238 2: IDDIG_P1 (I)
_M
4: Reserved
5: Reserved
6: Reserved
7: Reserved
0: GPIO237 (IO)
1: SFLASH_IO_2 (IO)
GPIO237 2: DRV_VBUS (O)
_M
4: Reserved
5: Reserved
f o r 6: Reserved
7: Reserved
e
l e a s I - R 2 0: GPIO236 (IO)
1: SFLASH_IO_3 (IO)
P
2: IDDIG (I)
Re Pi B
GPIO236
_M
4: Reserved
5: Reserved
6: Reserved
2:0 Reserved
a n a
Reserved
7: Reserved
Reserved
10005A6 GPIO_MODE Ba n
0 49
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
e
Type RW RW RW RW RW
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic

0: GPIO244 (IO)
14:12
GPIO244
e
GPIO244_MODE
a s e I - R 2 1: Reserved
2: Reserved
3: Reserved
_M
l
5: Reserved
6: Reserved
7: Reserved
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
0: GPIO243 (IO)
1: UCTS2 (I)
2: URXD3 (I)
a
GPIO243
11:9 GPIO243_MODE 3: UTXD3 (O)
n
_M
4: SDA1 (IO)
n a 5: Reserved
Ba
6: Reserved
0: GPIO242 (IO)
1: URTS2 (O)
GPIO242 2: UTXD3 (O)
8:6 GPIO242_MODE 3: URXD3 (I)
_M
4: SCL1 (IO)
5: Reserved
6: Reserved
0: GPIO241 (IO)
1: SFLASH_CLK (O)
5:3
GPIO241
_M
GPIO241_MODE
f o r 2: Reserved
3: Reserved
e
4: Reserved
6: Reserved
7: Reserved

0: GPIO240 (IO)
1: SFLASH_CS_L (O)
2:0
GPIO240
_M
n a
GPIO240_MODE
a
2: Reserved
3: Reserved
4: Reserved
Ba n 5: Reserved
6: Reserved
7: Reserved
GPIO_MODE
50
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
e
Type RW RW RW RW RW
Reset 0 0 1 0 0 1 0 0 1 0 0 0 0 0 1
Bit(s Mnemon
Name
f o r Description
e
) ic

0: GPIO249 (IO)
14:12
GPIO249
_M
Re Pi B
GPIO249_MODE
P 1:Reserved
2: Reserved
3: Reserved
4: Reserved
a n a 5: Reserved
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
7: Reserved
0: GPIO248 (IO)
GPIO248
a n a 1: HDMI_TESTOUTP_RX (O)
2: Reserved
n
_M
Ba
4: Reserved
5: Reserved
6: Reserved
7: Reserved
0: GPIO247 (IO)
1: Reserved
GPIO247 2: Reserved
_M
4: Reserved
5: Reserved
6: Reserved
7: Reserved
1: Reserved
5:3
GPIO246
_M
GPIO246_MODE
e a s e I - R 2
2: Reserved
3: Reserved
4: Reserved
l
Re Pi B P
5: Reserved
6: Reserved
7: Reserved
1: Reserved
n
GPIO245 2: Reserved
Ba
_M
4: Reserved
5: Reserved
6: Reserved
7: Reserved
10005A8 GPIO_MODE
0 51
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type
r
RW RW RW RW RW
o
Reset 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1
Bit(s Mnemon
s e f 2
a R
Name Description
) ic
l e P I -
Re Pi B
GPIO254 0: GPIO254 (IO)
_M
2: Reserved
a n a 3: Reserved
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
5: Reserved
6: Reserved
7: Reserved

0: GPIO253 (IO)
11:9
GPIO253
_M
Ba n
GPIO253_MODE
1: Reserved
2: Reserved
3: Reserved
4: Reserved
5: Reserved
6: Reserved
7: Reserved
0: GPIO252 (IO)
1: Reserved
GPIO252 2: Reserved
_M
4: Reserved
5: Reserved
6: Reserved
f o r 7: Reserved
GPIO251
e a s e I - R 2
0: GPIO251 (IO)
1: Reserved
2: Reserved
5:3
_M
l
GPIO251_MODE
Re Pi B P
3: Reserved
4: Reserved
5: Reserved
6: Reserved
7: Reserved
n
0: GPIO250 (IO)
Ba
1: Reserved
GPIO250 2: Reserved
_M
4: Reserved
5: Reserved
6: Reserved
7: Reserved
10005A9 GPIO_MODE
0 52
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
o
e
Type
Reset 0
RW
0 1 0
s e f RW
0
2
1 0
RW
0 1 0
RW
0 1 0
RW
0 1
Bit(s Mnemon
Name
l e a P I - R Description
Re Pi B
) ic
GPIO259
_M
a n a 1: Reserved
n
B a
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
3: Reserved
4: Reserved
5: Reserved
a
6: Reserved
n a n 7: Reserved
Ba
0: GPIO258 (IO)
1: Reserved
GPIO258 2: Reserved
_M
4: Reserved
5: Reserved
6: Reserved
7: Reserved
0: GPIO257 (IO)
1: Reserved
GPIO257 2: Reserved
_M
4: Reserved
f o r 5: Reserved
6: Reserved
7: Reserved
e a s e I - R 2 GPIO 256 Mode Selection

0: GPIO256 (IO)
5:3
GPIO256
_M l
Re Pi B
GPIO256_MODE
P
1: Reserved
2: Reserved
3: Reserved
4: Reserved
5: Reserved
a n a 6: Reserved
7: Reserved
2:0
GPIO255 Ba n
GPIO255_MODE
0: GPIO255 (IO)
1: Reserved
2: Reserved
3: Reserved
_M
4: Reserved
5: Reserved
6: Reserved
7: Reserved
10005AA GPIO_MODE
0 53
Bit
Nam
15 14 13 12 11
f o r 10 9 8 7 6 5 4 3 2 1 0
e
e
Type
Reset 0
RW
0
l
0
e a s 0
I - R 2
RW
0 0 0
RW
0 0 0
RW
0 0 0
RW
0 0
Bit(s
)
Mnemon
ic
Re Pi B
Name P Description
14:12 GPIO264
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
_M
l
1: GE2_TXD2 (IO)
2: Reserved
3: Reserved
a
4: Reserved
n a n 5: Reserved
6: ANT_SEL4 (O)
7: Reserved
Ba
0: GPIO263 (IO)
1: GE2_TXD3 (IO)
GPIO263 2: Reserved
_M
4: Reserved
5: Reserved
6: ANT_SEL5 (O)
7: Reserved
0: GPIO262 (IO)
1: GE2_TXEN (IO)
GPIO262 2: Reserved
8:6
_M
GPIO262_MODE
f o r 3: Reserved
4: Reserved
5: Reserved
7: Reserved
5:3
GPIO261
l
Re Pi B
GPIO261_MODE
P
0: GPIO261 (IO)
1: MSDC1_INS (I)
2: Reserved
3: Reserved
_M
a n a 4: Reserved
5: Reserved
Ba n 6: Reserved
0: GPIO260 (IO)
1: Reserved
GPIO260 2: Reserved
_M
4: Reserved
5: Reserved
6: Reserved
7: Reserved
10005AB
0
GPIO_MODE
54
Bit
Nam
e
15 14
GPIO269_M
13 12
e a s e 11
- R
10
2
GPIO268_M
I
9 8 7
GPIO267_M
6 5 4
GPIO266_M
3 2 1
GPIO265_M
0
Type
Reset 0
RW
0
l
Re Pi B
0
P
0
RW
0 0 0
RW
0 0 0
RW
0 0 0
RW
0 0
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
0: GPIO269 (IO)
1: GE2_RXD0 (IO)
2: Reserved
a
GPIO269
n
_M
4: Reserved
n a 5: Reserved
Ba
6: Reserved
7: Reserved
0: GPIO268 (IO)
1: GE2_RXCLK (IO)
GPIO268 2: Reserved
_M
4: Reserved
5: Reserved
6: Reserved
7: Reserved
0: GPIO267 (IO)
1: GE2_TXCLK (IO)
8:6
GPIO267
_M
GPIO267_MODE
f o r 2: Reserved
3: Reserved
e
4: Reserved
6: Reserved
7: Reserved

0: GPIO266 (IO)
1: GE2_TXD0 (IO)
5:3
GPIO266
_M
n a
GPIO266_MODE
a
2: Reserved
3: Reserved
4: Reserved
Ba n 5: Reserved
6: ANT_SEL2 (O)
7: Reserved
0: GPIO265 (IO)
1: GE2_TXD1 (IO)
GPIO265 2: Reserved
_M
4: Reserved
5: Reserved
6: ANT_SEL3 (O)
7: Reserved
10005AC GPIO_MODE

0
Bit
Nam
15 14
55
13 12
e a s e 11
I - R 2
10 9 8 7 6 5 4 3 2 1 0
e
Type
Reset 0
GPIO274_M
RW
0 l
Re Pi B
0
P
0
GPIO273_M
RW
0 0 0
GPIO272_M
RW
0 0 0
GPIO271_M
RW
0 0 0
GPIO270_M
RW
0 0
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
0: GPIO274 (IO)
1: GE2_RXDV (IO)
2: Reserved
a
GPIO274
n
_M
4: Reserved
n a 5: Reserved
Ba
6: Reserved
7: Reserved
0: GPIO272 (IO)
1: GE2_RXD3 (IO)
GPIO272 2: Reserved
_M
4: Reserved
5: Reserved
6: Reserved
7: Reserved
r
0: GPIO271 (IO)
5:3
GPIO271
GPIO271_MODE
e f o 2
1: GE2_RXD2 (IO)
2: Reserved
3: Reserved
s
_M
R
4: Reserved
l e a P I - 5: Reserved
6: Reserved
Re Pi B
7: Reserved
0: GPIO270 (IO)
GPIO270
a n a 1: GE2_RXD1 (IO)
2: Reserved
n
_M
Ba
4: Reserved
5: Reserved
6: Reserved
7: Reserved
10005AD GPIO_MODE
0 56
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
e
Type RW RW RW RW RW
r
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
e f o 2
s
Name Description
) ic
14:12 -
l e a -
P I - R -
Re Pi B
GPIO278 0: GPIO278 (IO)
11:9 GPIO278_MODE
_M 1: JTAG_RESET (I)
a
2: Reserved
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
4: Reserved
5: Reserved
6: Reserved
a
7: Reserved
8:6 Reserved
n a n
Reserved Reserved
Ba
0: GPIO276 (IO)
1: MDIO (IO)
GPIO276 2: Reserved
_M
4: Reserved
5: Reserved
6: ANT_SEL1 (O)
7: Reserved
0: GPIO275 (IO)
1: MDC (O)
GPIO275 2: Reserved
_M
4: Reserved
f o r 5: Reserved
6: ANT_SEL0 (O)
e
7: Reserved
l e a s I - R 2
10005B10
Bit 15
GPIO_BANK
14 13
Re Pi B
12 P
11 10
GPIO Misc Control Register
9 8 7 6 5 4 3 2 1
F801
0
a
CP
GP
n
UM
S_ GPI
a
_M
Nam GPIO_MISC_REG SY O_
e
Type
Reset 1 1
RW
Ba
1
n 1
RO
1
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
IPI
_G
PI_
EN
RW
0
NC
_S
EL
RW
0
BA
NK
RW
1
Bit(s Mnemon
Name Description
) ic
GPIO Reserved Control register
GPIO_MISC_RE
15:3 0: Reserved
G
1: Reserved
CPUM_MIPI_GP 0: Disable
2
I_EN 1: Enable
1 GPS_SYNC_SEL
f o r 0: internal frame sync

1: external frame sync
a
GPIO_BANK
e s e I - R 2
GPIO Reserved Control register
0: Reserved
l
1: Reserved
Re Pi B P
a n a
n
Ba
MT7623N
f o r
10005B2
0
IES_EN0
e a s e I - R 2 GPIO IES Control Register 0 FFFF
Bit
Nam
e
Type
15 14 13
l
Re Pi B
12
P
11 10 9 8
IES0
RW
7 6 5 4 3 2 1 0
Reset 1 1 1
a n a
1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s
)
15:0
Mnemon
ic
Ba n Name
IES0
Description
GPIO Input Enable Control register

0: Disable
1: Enable
10005B3
IES_EN1 GPIO IES Control Register 1 FFFF
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam IES1
e
Type
Reset 1 1 1 1 1
f o r
1 1 1
RW
1 1 1 1 1 1 1 1
Bit(s Mnemon
Name
)
15:0
ic
IES1 l
Re Pi B P GPIO Input Enable Control register
0: Disable
1: Enable
a n a
10005B4
0
Bit 15 14
IES_EN2
B
13
a n
12 11 10
9 8 7 6 5 4 3 2 1
FFFF
0
Nam
IES2
e
Type RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s Mnemon
Name Description
) ic
GPIO Input Enable Control register
15:0 IES2 0: Disable
f o r 1: Enable
10005B50 SMT_EN0
e a s e I - R 2 GPIO SMT Control Register 0 0000

Bit
Nam
e
Type
15 14 13
l
Re Pi B
12
P
11 10 9 8
SMT0
RW
7 6 5 4 3 2 1 0
a n a
n
Ba
MT7623N
f o r
10005B50 SMT_EN0
e a s e I - R 2 GPIO SMT Control Register 0 0000
l
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic Re Pi B
Name P Description
15:0
a n a
SMT0
GPIO Schmitter Trigger Control Register
0: Disable
Ba n 1: Enable
10005B6
SMT_EN1 GPIO SMT Control Register 1 0000
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam SMT1
e
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
r
Name Description
) ic
15:0 SMT1
e f o 2
s
0: Disable
10005B70 SMT_EN2
Re Pi B GPIO SMT Control Register 2 0000
Bit
Nam
15 14 13
a n a
12 11 10 9 8
SMT2
7 6 5 4 3 2 1 0
n
e
Ba
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
15:0 SMT2 0: Disable
1: Enable
10005B8
TDSEL0 GPIO TDSEL Control Register 0 0000
0
Bit 15 14 13 12 11
f o r
10 9 8 7 6 5 4 3 2 1 0
e
Nam
2
TDSEL0
e
Type
Reset 0 0 0 0
l e a0
s I0
- R 0 0
RW
0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Re Pi B
Name P Description
a n a
n
B a
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
15:0
l
Re Pi B
TDSEL0
P TDSEL control register
10005B9
0
TDSEL1
a n a GPIO TDSEL Control Register 1 0000
Bit
Nam
e
Type
15 14
Ba
13
n 12 11 10 9 8
TDSEL1
RW
7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
15:0 TDSEL1 TDSEL control register
r
10005BA
0
Bit 15 14 13 12
e f
11
o 10
2
9 8 7 6 5 4 3 2 1 0
Nam
e
Type
l e a s I - R
TDSEL2
RW
Reset
Bit(s
0
Mnemon
0 0
Re Pi B
0
P
0 0 0 0 0 0 0 0 0 0 0 0
a
Name Description
) ic
15:0
n a n
TDSEL2 TDSEL control register
10005BB
0
Bit 15 14
TDSEL3 Ba
13 12 11
10 9 8 7 6 5 4 3 2 1
0000
0
Nam TDSEL3
e
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
15:0 TDSEL3
f o r TDSEL control register
e a s e I - R 2
10005BC
0
Bit
Nam
15 14
TDSEL4
13 l
Re Pi B
12 P
11
10 9 8
TDSEL4
7 6 5 4 3 2 1
0000
a n a
n
Ba
MT7623N
f o r
10005BC
0
TDSEL4
e a s e I - R 2GPIO TDSEL Control Register 4 0000
Type
Reset 0 0 0 l
Re Pi B
0
P
0 0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
a n a
Name Description
15:0
Ba n TDSEL4 TDSEL control register
10005BD
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam TDSEL5
e
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
r
Name Description
) ic
15:0 TDSEL5
e f o 2
TDSEL control register
l e a s I - R
10005BE
0
Bit 15
OD33_CTRL
14
4
13 Re Pi B
12
P
11
10
Register 4
9 8 7 6 5 4 3 2 1
0000
0
Nam
e
Type
OD33_BACKUP4
a n a OD33_RDSEL4 OD33_TDSEL4
n
RW RW RW
Ba
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
15:10 OD33_BACKUP4 OD33 Control Reserve Registers
10005BF OD33_CTRL 18OD33 IO Group TDSEL/RDSEL Control

0000
0 5 Register 5
Bit
Nam
15 14 13 12 11
f o r
10 9 8 7 6 5 4 3 2 1 0
e
2
e
Type
Reset 0 0 0
RW
0
l e a0
s I
0
- R 0 0 0
RW
0 0 0 0 0
RW
0 0
Bit(s
)
Mnemon
ic
Re Pi B
Name P Description
a n a
n
B a
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
15:10
9:4
3:0
l
Re Pi B
OD33_BACKUP5
OD33_RDSEL5
OD33_TDSEL5
P OD33 Control Reserve Registers
a n a
10005C0
0
Bit
Nam
15
OD33_CTRL
14
6
Ba
13
n 12 11
10
Register 6
9 8 7 6 5 4 3 2 1
0000
0
e
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
9:4 OD33_RDSEL6
3:0 OD33_TDSEL6
f o r eint0_tdsel and eint5_tdsel
e a s e I - R 2
10005C10
OD33_CTRL
7
l
Re Pi B P18OD33 IO Group TDSEL/RDSEL Control
Register 7
0000
Bit
Nam
e
15 14 13
OD33_BACKUP7
a n a
12 11 10 9 8 7
OD33_RDSEL7
6 5 4 3 2
OD33_TDSEL7
1 0
Type
Reset
Bit(s
0
Mnemon
0
Ba
0
nRW
0
Name
0 0 0 0 0
RW
0 0
Description
0 0 0
RW
0 0
) ic
10005C20 RDSEL0 GPIO RDSEL Control Register 0 0000

Bit
Nam
15 14 13 12 11
f o r 10 9 8
RDSEL0
7 6 5 4 3 2 1 0
e
e
Type
Reset 0 0 0
l
0
e a s 0
I - R 20 0 0
RW
0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Re Pi B
Name
P Description
a
15:0 RDSEL0 RDSEL control register
Ba
MT7623N
f o r
e a s e I - R 2
10005C30
Bit
Nam
15 14
RDSEL1
13 l
Re Pi B
12 P
11
GPIO RDSEL Control Register 1
10 9 8 7 6 5 4 3 2 1
0000
0
a
RDSEL1
e
Type
Reset 0 0 0
n a n 0 0 0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s
)
15:0
Mnemon
ic
Ba Name
RDSEL1
Description
RDSEL control register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam RDSEL2
e
Type RW
r
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
e f o 2
s
Name Description
) ic
15:0
l e
RDSEL2
a P I - R RDSEL control register
Re Pi B
10005C50
Bit 15 14
RDSEL3
13
a n a
12 11
GPIO RDSEL Control Register 3
10 9 8 7 6 5 4 3 2 1
0000
0
Nam
e
Type
Reset 0 0
Ba
0
n 0 0 0 0
RDSEL3
0
RW
0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type
f o r RDSEL4
RW
Reset 0 0 0 0
e a s e 0
I - R 2
0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
15:0
Mnemon
ic
l
Re Pi B
Name
RDSEL4 P Description
RDSEL control register
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
10005C70
Bit
Nam
e
15 14
RDSEL5
13
l
Re Pi B
12
P
11
GPIO RDSEL Control Register5
10 9 8
RDSEL5
7 6 5 4 3 2 1
0000
0
a
Type RW
n
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n a
Ba
Bit(s Mnemon
Name Description
) ic
10005C8
DRVN0_EN GPIO Control DDR Register 0000
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
DRVN0_EN
e
Type RW
Reset 0 0 0 0 0 0 0 0 0 0
r
0 0 0 0 0 0
Bit(s Mnemon
Name
e f o 2
Description
)
15:0
ic
e a
Reserved
l s I - R Reserved
Re Pi B P
a
MSDC3_CTR
10005C90 MSDC 3 CLK Pad Control Register 0314
Bit 15 14
L0
13
n a n12 11 10 9 8 7 6 5 4 3 2 1 0
Ba
MS MS
MS MS MS MS MS MS MS
3C 3C
Nam MS3CK_BACKUP1 K_
3C 3C
K_
MS3CK_BACKU 3C 3C 3C 3C 3C
e SM
K_ K_
PU
P0 K_I K_ K_ K_ K_
R0 R1 ES SR E8 E4 E2
T PD
Type RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0
Bit(s Mnemon
Name Description
) ic
MS3CK_BACKU
15:12 Reserved
P1
11 MS3CK_SMT
f o r 0:Disable
1:Enable
10
9
MS3CK_R0
e a
MS3CK_R1
s e I - R 2
8
7:5
4
l
MS3CK_PUPD
Re Pi B
MS3CK_BACKU
P0
MS3CK_IES
P
Reserved
Input enable control
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
3
l
Re Pi B
MS3CK_SR
P Output Slew Rate Control.
1: slower slew
a
n a n 000 : 2mA
001: 4mA
Ba
010: 6mA
2:0 MS3CK_DRV 011: 8mA
100: 10mA
101: 12mA
110: 14mA
111: 16mA
10005CA
DRVP0_EN GPIO Control DDR Register 0000
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type
f o r DRVP0_EN
RW
Reset 0 0 0 0
e a s e 0
I - R 2
0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
15:0
Mnemon
ic
l
Re Pi B
Name
Reserved
a n a
10005CB
0
Bit 15
MSDC3_CTR
14
L1
Ba
13
n 12 11
MS
10
MS MS
9
MS
8 7 6 5
MS
4 3
MS
2
MS
1
MS
0314
0
MS
3C
3C 3C 3C 3C 3C 3C 3C 3C
Nam MD MS3CMD_BAC
MS3CMD_BACKUP1 MD MD MD MD MD MD MD MD
e _P KUP0
_S _R _R _IE _S _E _E _E
UP
MT 0 1 S R 8 4 2
D
Reset 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0
Bit(s Mnemon
Name Description
) ic
15:12
MS3CMD_BACK
UP1
f o r Reserved
11 MS3CMD_SMT
e a s e I - R 2 Schmitter Trigger Control

0:Disable
10
9 l
Re Pi B
MS3CMD_R0
MS3CMD_R1 P
1:Enable
a
8 MS3CMD_PUPD pull-up(0)/pull-down(1) control
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
7:5
4
UP0
l
Re Pi B
MS3CMD_BACK
MS3CMD_IES P Reserved
a
3
n a n
MS3CMD_SR 1: slower slew
Ba
000 : 2mA
001: 4mA
010: 6mA
2:0 MS3CMD_DRV 011: 8mA
100: 10mA
101: 12mA
110: 14mA
111: 16mA
10005CC
0
MSDC0_CTR
L0
f o r MSDC 0 CLK Pad Control Register 0311
Bit
Nam
15 14 13 12
e a s e 11
MS
0C
I - R
10
2
MS MS
9
MS
0C
8 7 6 5
MS
4 3
MS
2
MS
1
MS
0
MS
l
0C 0C MS0CK_BACKU 0C 0C 0C 0C 0C
P
MS0CK_BACKUP1 K_ K_
Re Pi B
e K_ K_ P0 K_I K_ K_ K_ K_
SM PU
T PD
Reset 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1
a n a
n
Bit(s Mnemon
Name Description
Ba
) ic
MS0CK_BACKU
15:12 Reserved
P1
11 MS0CK_SMT 0:Disable
1:Enable
10 MS0CK_R0 10K resistot control
9 MS0CK_R1 50K resistor control
8 MS0CK_PUPD pull-up(0)/pull-down(1) control
MS0CK_BACKU
7:5 Reserved
P0
4 MS0CK_IES
r
3 MS0CK_SR
e f o 2
1: slower slew
l e a s I - R
2:0
Re Pi B
MS0CK_DRV
P 000 : 2mA
001: 4mA
010: 6mA
011: 8mA
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
Re Pi B P 100: 10mA
101: 12mA
110: 14mA
111: 16mA
a n a
10005CD
0
Bit 15
MSDC0_CTR
14
L1
Ba
13
n 12 11
10 9 8 7 6 5 4 3 2 1
0411
0
MS
MS MS MS MS MS MS MS MS
0C
0C 0C 0C 0C 0C 0C 0C 0C
Nam MS0CMD_BACKUP1 MD MD MD
MD MS0CMD_BAC
MD MD MD MD MD
e _S _R _R
_P KUP0
_IE _S _E _E _E
UP
MT 0 1 S R 8 4 2
D
Reset 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1
Bit(s Mnemon
r
Name Description
) ic
15:12
MS0CMD_BACK
UP1
e f o 2
Reserved
11
l e
MS0CMD_SMT
a s I - R Schmitter Trigger Control
0:Disable
10
9 Re Pi B
MS0CMD_R0
MS0CMD_R1
P 1:Enable
8
n a
MS0CMD_PUPD
a
n
MS0CMD_BACK
7:5 Reserved
Ba
UP0
4 MS0CMD_IES Input enable control
3 MS0CMD_SR 1: slower slew
000 : 2mA
001: 4mA
010: 6mA
100: 10mA
101: 12mA
f o r 110: 14mA
111: 16mA
e a s e I - R 2
10005CE
0
Bit 15
MSDC0_CTR
14
L2
13
l
Re Pi B
12
P
11
10 9 8 7 6 5 4 3 2 1
0011
0
Nam
a n a MS0DAT_BACKUP MS MS MS MS MS
n
Ba
MT7623N
f o r
10005CE
0
MSDC0_CTR
L2
e a s e I - R 2
MSDC 0 DATA Pad Control Register 0 0011
e
l
Re Pi B P 0D
AT
_IE
S
0D
AT
_S
R
0D
AT
_E
8
0D
AT
_E
4
0D
AT
_E
2
Type
Reset 0 0 0
a n a
0 0
RW
0 0 0 0 0 0
RW
1
RW
0
RW
0
RW
0
RW
1
Bit(s
)
15:5
Mnemon
ic
Ba n Name
MS0DAT_BACK
Description
Reserved
UP
4 MS0DAT_IES Input enable control
3 MS0DAT_SR 1: slower slew
000 : 2mA
001: 4mA
r
010: 6mA
2:0 MS0DAT_DRV
e f o 2
011: 8mA
100: 10mA
l e a s I - R
101: 12mA
110: 14mA
P
111: 16mA
Re Pi B
10005CF
0
MSDC0_CTR
L3
a n a MSDC 0 DATA Pad Control Register 1 4444
Bit
Nam
e
15
MS
0D
AT
3_
14
MS
0D
AT
MS
0D
ATBa
13
n 12
MS
0D
AT
3_
11
MS
0D
AT
2_
10
MS
0D
AT
MS
0D
AT
9
MS
0D
AT
2_
8
MS
0D
7
AT1
MS
0D
6
AT1
MS
0D
5
AT1
MS
0D
4
AT1
_P
3
MS
0D
AT
0_
2
MS
0D
AT
1
MS
0D
AT
0
MS
0D
AT
0_
3_ 3_ 2_ 2_ _S _R _R 0_ 0_
SM PU SM PU UP SM PU
R0 R1 R0 R1 MT 0 1 R0 R1
T PD T PD D T PD
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
Bit(s Mnemon
Name Description
) ic
14 MS0DAT3_R0
f o r 1:Enable
13 MS0DAT3_R1
e
MS0DAT3_PUP
a s e I - R 2 50K resistor control
l
12 pull-up(0)/pull-down(1) control
P
D
Re Pi B
a
1:Enable
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
10
9
8
l
Re Pi B
MS0DAT2_R0
MS0DAT2_R1
MS0DAT2_PUP
P 10K resistot control
a
D
n a n
MS0DAT1_SMT
0:Disable
Ba
1:Enable
1:Enable
MS0DAT0_PUP
D
f o r
10005D0
0
MSDC0_CTR
L4
e a s e I - R 2
Bit
Nam
15
MS
0D
14
MS
0D
13
MS
0D
l
Re Pi B
12
MS
0D
AT
MS
0D
AT
P
11 10
MS
0D
MS
0D
9
MS
0D
AT
8
MS
0D
7 6
MS
0D
5
MS
0D
4
MS
0D
AT
MS
0D
3 2
MS
0D
1
MS
0D
0
MS
0D
AT
a
AT AT AT AT AT AT AT AT AT AT AT
e 7_P 6_ 6_ 5_ 4_
n
7_S 7_ 7_ 6_ 6_ 5_S 5_ 5_ 4_S 4_ 4_
UP SM PU PU PU
a
MT R0 R1 R0 R1 MT R0 R1 MT R0 R1
D T PD PD PD
Type
Reset
Bit(s
RW
0
Mnemon
RW
1
RW
Ba
0
n RW
0
Name
RW
0
RW
1
RW
0
RW
0
RW
0
RW
1
RW
0
Description
RW
0
RW
0
RW
1
RW
0
RW
0
) ic
1:Enable
11 MS0DAT6_SMT
f o r 0:Disable
1:Enable
10
9
MS0DAT6_R0
MS0DAT6_R1
e a s e I - R 2
8
7
D
l
MS0DAT6_PUP
Re Pi B
MS0DAT5_SMT
P pull-up(0)/pull-down(1) control
0:Disable
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
6
5
l
Re Pi B
MS0DAT5_R0
MS0DAT5_R1 P 1:Enable
4
a n a
MS0DAT5_PUPD pull-up(0)/pull-down(1) control
3
2
1 Ba n
MS0DAT4_SMT
MS0DAT4_R0
MS0DAT4_R1
0:Disable
1:Enable
MS0DAT4_PUP
D
MSDC0_CTR
10005D10 MSDC 0 DATA Pad Control Register 3 0004
L5
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
MS MS
MS MS
o
0R 0R
f
0R 0R
Nam MS0DAT_BACKUP
ST
ST ST
ST
e
e B_ B_
2
B_ B_
s
SM PU
R0 R1
Type
l e a P I - R RW
T
RW RW RW
PD
RW
Re Pi B
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Bit(s Mnemon
Name Description
)
15:4
ic
a n a
MS0DAT_BACK
Reserved
3
Ba n
UP
MS0RSTB_SMT
0:Disable
1:Enable
2 MS0RSTB_R0 10K resistot control
1 MS0RSTB_R1 50K resistor control
0 MS0RSTB_PUPD pull-up(0)/pull-down(1) control
10005D2 MSDC0_CTR
MSDC 0 Pad Control Register 000A
0 L6
Bit
Nam
e
15 14 13
MS0PAD_BACKUP
12 11
f o r
10 9 8 7
MS0PAD_RDSEL
6 5 4 3 2
MS0PAD_TDSEL
1 0
Type
Reset 0 0 0
RW
0
e a
0
s e I
0
- R 2 0 0 0
RW
0 0 0 1 0
RW
1 0
Bit(s
)
15:10
Mnemon
ic
Name
MS0PAD_BACK
l
Reserved
a n a
n
B a
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
9:4
3:0
l UP
Re Pi B
MS0PAD_RDSEL
MS0PAD_TDSEL P BIAS PAD TUNE Control
a n a
10005D3
0
Bit 15
MSDC1_CTR
14
L0
Ba
13
n 12 11
MS
MSDC 1 CLK Pad Control Register
10 9
MS
8 7 6 5 4 3 2 1
0311
0
1C 1C
Nam MS1CK_BACKUP1 K_
1C 1C
K_
MS1CK_BACKU 1C 1C 1C 1C 1C
e SM
K_ K_
PU
P0 K_I K_ K_ K_ K_
T PD
Reset 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1
Bit(s Mnemon
Name Description
) ic
15:12
MS1CK_BACKUP
1
f o r Reserved
11
a
MS1CK_SMT
e s e I - R 2
0:Disable
l
1:Enable
10
9
8
Re Pi B
MS1CK_R0
MS1CK_R1
MS1CK_PUPD
7:5
a
0
n a
MS1CK_BACKUP
Reserved
4
3
Ba nMS1CK_IES
MS1CK_SR
1: slower slew
000 : 2mA
001: 4mA
010: 6mA
2:0 MS1CK_DRV 011: 8mA
100: 10mA
101: 12mA
110: 14mA
r
111: 16mA
e f o 2
10005D4 MSDC1_CTR
l e a s I - RMSDC 1 CMD Pad Control Register 0211

0
Bit
Nam
e
15 14
L1
MS1CMD_BACKUP1
13
Re Pi B
12
MS
1C
P
11 10
MS
1C
MS
1C
9 8
MS
1C
7
MS1CMD_BACK
UP0
6 5 4
MS
1C
3
MS
1C
2
MS
1C
1
MS
1C
0
MS
1C
a n a
n
Ba
MT7623N
f o r
10005D4
0
MSDC1_CTR
L1
e a s e I - R 2
MSDC 1 CMD Pad Control Register 0211
l
Re Pi B
MD
_S
MTP MD
_R
0
MD
_R
1
MD
_P
UP
D
MD
_IE
S
MD
_S
R
MD
_E
8
MD
_E
4
MD
_E
2
Type
Reset 0 0
RW
0
a n a
0
RW
0
RW
0
RW
1
RW
0 0
RW
0 0
RW
1
RW
0
RW
0
RW
0
RW
1
Bit(s
)
15:12
Mnemon
ic
Ba n Name
MS1CMD_BACK
Description
Reserved
UP1
11 MS1CMD_SMT 0:Disable
1:Enable
10 MS1CMD_R0 10K resistot control
9 MS1CMD_R1 50K resistor control
8 MS1CMD_PUPD pull-up(0)/pull-down(1) control
MS1CMD_BACK
7:5
r
Reserved
UP0
4 MS1CMD_IES
e f o 2
3
l e a
MS1CMD_SR
s I - R
1: slower slew
Re Pi B P Driving Strength Control

000 : 2mA
001: 4mA
2:0
a n a
MS1CMD_DRV
010: 6mA
011: 8mA
Ba n 100: 10mA
101: 12mA
110: 14mA
111: 16mA
10005D5 MSDC1_CTR
0 L2
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MS MS MS MS MS
1D 1D 1D 1D 1D
Nam
MS1DAT_BACKUP0 AT AT AT AT AT
e
_IE _S _E _E _E
Type
f o r RW
S
RW
R
RW
8
RW
4
RW
2
RW
e
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1
Bit(s Mnemon
l e a s I - R 2
P
Name Description
Re Pi B
) ic
MS1DAT_BACKU
15:5 Reserved
P0
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
3
l
Re Pi B
MS1DAT_IES
MS1DAT_SR P Input enable control

1: slower slew
a
n a n Driving Strength Control

000 : 2mA
Ba
001: 4mA
010: 6mA
2:0 MS1DAT_DRV 011: 8mA
100: 10mA
101: 12mA
110: 14mA
111: 16mA
10005D6 MSDC1_CTR
0 L3
Bit 15
MS
14
MS
13
MS
12
MS
11
f
MS
o r 10
MS MS
9
MS
8
MS
7
MS
6
MS
5
MS
4 3
MS
2
MS
1
MS
0
MS
e
1D 1D 1D 1D 1D 1D 1D
2
1D 1D 1D 1D 1D 1D 1D 1D 1D
s
Nam AT
AT AT
AT AT
AT AT
AT
AT1 AT1 AT1
AT1 AT
AT AT
AT
e 3_
SM
T
3_
R0
3_
R1
3_
PU
l
PD
e a
2_
SM
T
P I - R2_
R0
2_
R1
2_
PU
PD
_S
MT
_R
0
_R
1
_P
UP
D
0_
SM
T
0_
R0
0_
R1
0_
PU
PD
Re Pi B
Reset 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0
Bit(s
)
Mnemon
ic
a n a
Name Description
15
14 Ba n
MS1DAT3_SMT
MS1DAT3_R0
0:Disable
1:Enable
1:Enable
r
7 MS1DAT1_SMT
e f o 2
0:Disable
e
MS1DAT1_R0
l a s I - R
1:Enable
5
4
3
Re Pi B
MS1DAT1_R1
MS1DAT1_PUPD
MS1DAT0_SMT
P 50K resistor control
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
2
l
Re Pi B
MS1DAT0_R0 P 0:Disable
1:Enable
a
0
n a n
MS1DAT0_PUPD pull-up(0)/pull-down(1) control
10005D7
0
Bit 15
MSDC1_CTR
14
L4
Ba
13 12 11
10 9 8 7 6 5 4 3 2 1
0000
0
Nam MS1DAT_BACKUP
e
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
15:0
MS1DAT_BACKU
P
f o r Reserved
e a s e I - R 2
10005D8
0
Bit
Nam
15
MSDC1_CTR
14
L5
13
l
Re Pi B
12 P
11 10
MSDC 1 Pad Control Register
9 8 7 6 5 4 3 2 1
00CA
e
Type
MS1PAD_BACKUP
a
RW
n a MS1PAD_RDSEL
RW
MS1PAD_TDSEL
RW
Reset
Bit(s
)
0
Mnemon
ic
0 0
Ba n 0
Name
0 0 0 0 1 1 0
Description
0 1 0 1 0
MS1PAD_BACKU
15:10 Reserved
P
9:4 MS1PAD_RDSEL BIAS PAD TUNE Control
3:0 MS1PAD_TDSEL BIAS PAD TUNE Control
10005D9 MSDC2_CTR
MSDC 2 CLK Pad Control Register 0411
0
Bit 15 14
L0
13 12 11
f o r
10 9 8 7 6 5 4 3 2 1 0
e
MS MS
2
s
2C 2C
Nam 2C 2C MS2CK_BACKU 2C 2C 2C 2C 2C
e
MS2CK_BACKUP1
l e a
K_
SM
P
K_
I
R0
- R K_
R1
K_
PU
P0 K_I
ES
K_
SR
K_
E8
K_
E4
K_
E2
Re Pi B
T PD
Reset 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1
a n a
n
B a
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
15:12
P1
l
Re Pi B
MS2CK_BACKU
P Reserved
a
11 MS2CK_SMT 0:Disable
10
n a n
MS2CK_R0
1:Enable
Ba
9 MS2CK_R1 50K resistor control
8 MS2CK_PUPD pull-up(0)/pull-down(1) control
MS2CK_BACKU
7:5 Reserved
P0
4 MS2CK_IES Input enable control
3 MS2CK_SR 1: slower slew
000 : 2mA
001: 4mA
r
010: 6mA
2:0 MS2CK_DRV
e f o 2
011: 8mA
100: 10mA
s
101: 12mA
l e a P I - R 110: 14mA
111: 16mA
Re Pi B
10005DA
0
MSDC2_CTR
L1
a n a MSDC 2 CMD Pad Control Register 0511
Bit
Nam
e
15 14
MS2CMD_BACKUP1 Ba
13
n 12 11
MS
2C
MD
_S
10
MS
2C
MD
_R
MS
2C
MD
_R
9
MS
2C
MD
_P
8 7
MS2CMD_BAC
KUP0
6 5
MS
2C
MD
4
_IE
3
MS
2C
MD
_S
2
MS
2C
MD
_E
1
MS
2C
MD
_E
0
MS
2C
MD
_E
UP
MT 0 1 S R 8 4 2
D
Reset 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 1
Bit(s Mnemon
Name Description
) ic
MS2CMD_BACK
15:12 Reserved
UP1
11 MS2CMD_SMT
f o r Schmitter Trigger Control

0:Disable
10 MS2CMD_R0
e a s e I - R 2
1:Enable
9
8
7:5
l
MS2CMD_R1
Re Pi B
MS2CMD_PUPD
MS2CMD_BACK
UP0
P
Reserved
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
3
l
Re Pi B
MS2CMD_IES
MS2CMD_SR P Input enable control

1: slower slew
a
n a n Driving Strength Control

000 : 2mA
Ba
001: 4mA
010: 6mA
100: 10mA
101: 12mA
110: 14mA
111: 16mA
10005DB MSDC2_CTR
0 L2
Bit 15 14 13 12 11
f o r 10 9 8 7 6 5 4
MS
3
MS
2
MS
1
MS
0
MS
e
2D 2D 2D 2D 2D
Nam
e
l e a s I - R 2
MS2DAT_BACKUP0 AT
_IE
S
AT
_S
R
AT
_E
8
AT
_E
4
AT
_E
2
Type
Reset 0 0 0
Re Pi B
0
P
0
RW
0 0 0 0 0 0
RW
1
RW
0
RW
0
RW
0
RW
1
a
Bit(s Mnemon
Name Description
)
15:5
ic
n a n
MS2DAT_BACK
Reserved
Ba
UP0
4 MS2DAT_IES Input enable control
3 MS2DAT_SR 1: slower slew
000 : 2mA
001: 4mA
010: 6mA
100: 10mA
101: 12mA
f o r 110: 14mA
111: 16mA
e a s e I - R 2
10005DC
0
Bit 15
MSDC2_CTR
14
L3
13
l
Re Pi B
12
P
11
10 9 8 7 6 5 4 3 2 1
5555
0
Nam MS MS MS
a
MS
n a MS MS MS MS MS MS MS MS MS MS MS MS
n
Ba
MT7623N
f o r
10005DC
0
MSDC2_CTR
L3
e a s e I - R 2
e 2D
AT
3_
SM
2D
AT
3_
R0
2D
AT
3_
R1
l
Re Pi B
2D
AT
3_
PU
2D
AT
2_
SM
P 2D
AT
2_
R0
2D
AT
2_
R1
2D
AT
2_
PU
2D
AT1
_S
MT
2D
AT1
_R
0
2D
AT1
_R
1
2D
AT1
_P
UP
2D
AT
0_
SM
2D
AT
0_
R0
2D
AT
0_
R1
2D
AT
0_
PU
Type
Reset
T
RW
0
RW
1
RW
0
a
PD
n
RW
1a T
RW
0
RW
1
RW
0
PD
RW
1
RW
0
RW
1
RW
0
D
RW
1
T
RW
0
RW
1
RW
0
PD
RW
1
Bit(s
)
Mnemon
ic

1:Enable
10 MS2DAT2_R0
f o r 1:Enable
9
8
MS2DAT2_R1
MS2DAT2_PUPD
e a s e I - R 2
6
l
Re Pi B
MS2DAT1_SMT
MS2DAT1_R0
P
0:Disable
1:Enable
5
4
a n a
MS2DAT1_R1
MS2DAT1_PUPD
n
Ba
1:Enable
MS2DAT0_PUP
D
10005DD MSDC2_CTR
0 L4
Bit
Nam
15 14 13 12 11
f o r 10 9 8
MS2DAT_BACKUP
7 6 5 4 3 2 1 0
e
Type
Reset 0 0 0 0
e a s e 0
I - R 20 0 0
RW
0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
l
Re Pi B
Name
P Description
a
15:0 MS2DAT_BACK Reserved
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l UP
Re Pi B P
10005DE
0
MSDC2_CTR
L5
a n a MSDC 2 Pad Control Register 0000
Bit
Nam
e
Type
Reset
15
0
14
0
Ba
13
MS2PAD_BACKUP
0
nRW
12
0
11
0
10
0
9
0
8
0
7
MS2PAD_RDSEL
0
RW
6
0
5
0
4
0
3
0
2
MS2PAD_TDSEL
0
RW
1
0
0
Bit(s Mnemon
Name Description
) ic
MS2PAD_BACK
15:10 Reserved
UP
9:4 MS2PAD_RDSEL BIAS PAD TUNE Control
3:0 MS2PAD_TDSEL BIAS PAD TUNE Control
f o r
10005DF
0
GPIO_TM
e a s e I - R 2
GPIO DIR Status Selection Register 0000
Bit
Nam
e
15 14 13
l
Re Pi B
12
P
11 10 9 8 7 6 5 4 3 2 1 0
TM
_D
IR
a
Type RW
Reset
n a n 0
Ba
Bit(s Mnemon
Name Description
) ic
select gpio_dir or gpio_padoe for register read in address
GPIO_DIR 1~9
0 TM_DIR
0: select gpio_dir for register read
1: select gpio_padoe for register read
10005E0
GPIO_USB USB IDDIG GPIO PULLUP Control Register 0069
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
f o r MS
US
B2
0_
US
B2
0_
US
B2
0_
e
_B
2
AG GPI GPI GPI
s
MO S_ SE
Nam PIO O4 O3 O3
e
l e a P I - R _S
EL
DE
18V
PR
E_
SE
LS
D
9_I
DP
4_I
DP
8_I
DP
Re Pi B
UL UL UL
L
LU LU LU
P P P
Type RW RW RW RW RW RW RW
Reset
a n a 1 1 0 1 0 0 1
n
B a
MT7623N
f o r
Bit(s Mnemon
e a s e I - R 2
)
6
5
ic
l
Name
Re Pi B
AGPIO_SEL
MODE18V
P
Description
Reserved
Reserved
4
L
a a
MS_BS_PRE_SE
n Reserved
2
Ba n SELSD
USB20_GPIO49_
IDPULLUP
PAD_IDDIG pupd by DA_USB signal when usb_mode is
set
1: by DA_USB signal
0: by register
USB20_GPIO34_ set
1
IDPULLUP 1: by DA_USB signal
0: by register
USB20_GPIO38 set
0
_IDPULLUP 1: by DA_USB signal
0: by register
OD33_CTRL
f o r
10005E10
Bit 15 14
0
13
e
12
a s e 11
I - R 2
10
Register 0
9 8 7 6 5 4 3 2 1
0000
0
Nam
e
Type
Reset 0 0 0
RW l
Re Pi B
OD33_BACKUP0
0 P
0 0 0 0
OD33_RDSEL0
0
RW
0 0 0 0
OD33_TDSEL0
0
RW
0 0
Bit(s Mnemon
a n a
Name Description
)
15:10
9:4
ic
Ba n
OD33_BACKUP0
OD33_RDSEL0
3:0 OD33_TDSEL0

10005E20 0000
1 Register 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type
OD33_BACKUP1
RW
f o r OD33_RDSEL1
RW
OD33_TDSEL1
RW
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
l e a s I - R 2
P
Name Description
Re Pi B
) ic
a n a
n
B a
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
3:0
l
Re Pi B
OD33_TDSEL1
P TDSEL control register for eint12_tdsel
10005E30
OD33_CTRL
2
a n a 18OD33 IO Group TDSEL/RDSEL Control
Register 2
0000
Bit
Nam
e
Type
15 14
Ba
13
n
OD33_BACKUP2
RW
12 11 10 9 8 7
OD33_RDSEL2
RW
6 5 4 3 2
OD33_TDSEL2
RW
1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
f o r
10005E40
OD33_CTRL
3
e a s e 18OD33 IO Group TDSEL/RDSEL Control
I - R 2 Register 3
0000
l
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type
Reset 0 0 0
Re Pi B
OD33_BACKUP3
RW
0
P
0 0 0 0
OD33_RDSEL3
0
RW
0 0 0 0
OD33_TDSEL3
0
RW
0 0
Bit(s Mnemon
a n a
)
15:10
9:4
ic
Ba n Name
OD33_BACKUP3
OD33_RDSEL3
Description

3:0 OD33_TDSEL3
KPAD_CTRL Keypad ROW Pad R0/R1/PUPD Control

10005E50 0555
0 Register 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
KP KP
Nam
e f o
RO
W2
2
AD
_C
TR
RO
W1
AD
_C
TR
RO
W0
s
ROW2_R ROW1_R1 ROW0_R
KPAD_CTRL0_BACKUP2 _P L0 _P L0 _P
a R
e 1R0 R0 1R0
-
UP _B UP _B UP
Type
Reset 0 0
RW
0 0
l e
Re Pi B 0
P
D
I
RW
1 0
RW
1
AC
KU
P1
RW
0
D
RW
1 0
RW
1
AC
KU
P0
RW
0
D
RW
1 0
RW
1
a n a
n
B a
MT7623N
f o r
Bit(s Mnemon
e a s e I - R 2
)
15:11
ic
l
Name
Re Pi B
KPAD_CTRL0_B
ACKUP2 P
Description
Reserved
10
a n a
ROW2_PUPD pull-up(0)/pull-down(1) control
00:High Z
9:8
7 Ba n
ROW2_R1R0
KPAD_CTRL0_B
ACKUP1
01: 10K
10: 50K
11:10K//50K
Reserved
6 ROW1_PUPD pull-up(0)/pull-down(1) control
00:High Z
01: 10K
5:4 ROW1_R1R0
10: 50K
11:10K//50K
KPAD_CTRL0_B
3 Reserved
ACKUP0
2 ROW0_PUPD pull-up(0)/pull-down(1) control
f o r 00:High Z
01: 10K
1:0 ROW0_R1R0
e a s e I - R 2 10: 50K
11:10K//50K
KPAD_CTRL
l
Re Pi B P Keypad COL Pad R0/R1/PUPD Control
10005E60
Bit 15 14
1
13
a n a
12 11 10
Register 1
9 8 7 6 5 4 3 2 1
0551
Nam
e Ba
KPAD_CTRL1_BACKUP2
n CO
L2
_P
COL2_R1
R0
KP
AD
_C
TR
L1_
CO
L1_
PU
COL1_R1
R0
KP
AD
_C
TR
L1_
CO
L0
_P
COL0_R1
R0
UP BA BA UP
PD
D CK CK D
UP UP
1 0
Reset 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 1
Bit(s Mnemon
Name Description
) ic
KPAD_CTRL1_B
15:11
10
ACKUP2
COL2_PUPD
f o r Reserved
e a s e I - R 2 00:High Z
01: 10K
l
9:8 COL2_R1R0
P
10: 50K
Re Pi B
11:10K//50K
KPAD_CTRL1_B
7 Reserved
ACKUP1
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
5:4
l
Re Pi B
COL1_PUPD
COL1_R1R0
P pull-up(0)/pull-down(1) control
00:High Z
01: 10K
a
10: 50K
n a n
KPAD_CTRL1_B
11:10K//50K
Ba
Reserved
ACKUP0
2 COL0_PUPD pull-up(0)/pull-down(1) control
00:High Z
01: 10K
1:0 COL0_R1R0
10: 50K
11:10K//50K
EINT_CTRL
10005E70 EINT Pad R0/R1/PUPD Control Register 0 1115
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EI
NT
EI
NT
f o r EI
NT
EI
NT
e
_C EI _C EI _C EI _C EI
Nam
e
TR
L0
_B
NT
17_
PU
EINT17_R
1R0
l e a s
TR
L0
_B
I -
NT
R
PU
2
16_
EINT16_
R1R0
TR
L0
_B
NT
15_
PU
EINT15_R
1R0
TR
L0
_B
NT
14_
PU
EINT14_
R1R0
P
AC PD AC PD AC PD AC PD
Re Pi B
KU KU KU KU
P3 P2 P1 P0
Type RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 1
a n a
n
Bit(s Mnemon
Name Description
Ba
) ic
EINT_CTRL0_B
15 Reserved
ACKUP3
14 EINT17_PUPD pull-up(0)/pull-down(1) control
00:High Z
01: 10K
13:12 EINT17_R1R0
10: 50K
11:10K//50K
EINT_CTRL0_B
11 Reserved
ACKUP2
r
00:High Z
9:8 EINT16_R1R0
e f o 2
01: 10K
10: 50K
s
11:10K//50K
7
EINT_CTRL0_B
l
ACKUP1
e a P I - R Reserved
Re Pi B
00:High Z
5:4 EINT15_R1R0
01: 10K
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
3
l
Re Pi B
EINT_CTRL0_B
ACKUP0
P 10: 50K
11:10K//50K
Reserved
2
n a
EINT14_PUPD
a
n
00:High Z
Ba
01: 10K
1:0 EINT14_R1R0
10: 50K
11:10K//50K
10005E8
EINT_CTRL1 EINT Pad R0/R1/PUPD Control Register 1 0001
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EI
NT
Nam EINT_CTRL1_BACKUP0 21_
EINT21_
e PU
R1R0
Type
Reset 0 0 0 0 0
f o r
0
RW
0 0 0 0 0 0 0
PD
RW
0 0
RW
1
Bit(s Mnemon
e a s e I - R 2
l
Name Description
P
) ic
15:3
CKUP0
Re Pi B
EINT_CTRL1_BA
Reserved
a
1:0
n a
EINT21_R1R0 n 00:High Z
01: 10K
B a 10: 50K
11:10K//50K
10005EB
BIAS_CTRL0 18OD33 IO Group BIAS Control Register 0 0000
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
I2S_BIAS2_CTRL I2S_BIAS1_CTRL GATE_MC2_B_CTRL GATE_MS2_CTRL
e
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Name
f o r Description
15:12
I2S_BIAS2_CTR
L
e a s e I - R 2 BIAS PAD TUNE Control
11:8
7:4
L
l
Re Pi B
I2S_BIAS1_CTR
GATE_MC2_B_C
TRL
P BIAS PAD TUNE Control
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
3:0
l
Re Pi B
GATE_MS2_CTR
L
P BIAS PAD TUNE Control
10005EC
a n a
0
Bit
Nam
e
15
BIAS_CTRL1
14
SPDIF_BIAS1B_CTRL
Ba
13 n 12
11 10
SPDIF_BIAS1_CTRL
9 8 7 6
I2S_BIAS4_CTRL
5 4 3 2
I2S_BIAS3_CTRL
1
0000
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
SPDIF_BIAS1B_
CTRL
SPDIF_BIAS1_C
TRL
7:4
I2S_BIAS4_CTR
L
3:0
I2S_BIAS3_CTR
L
e a s e I - R 2 BIAS PAD TUNE Control
10005ED
BIAS_CTRL2
l
Re Pi B P
18OD33 IO Group BIAS Control Register 2 0000
0
Bit 15 14 13
a n a
12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type
Reset
GATE_DPIB_CTRL
0 0
RW
Ba
0
n 0 0
GATE_DPI_CTRL
0
RW
0 0
U_RGM2_BIASB_CTR
0 0
L
RW
0 0
U_RGM2_BIAS_CTRL
0 0
RW
0 0
Bit(s Mnemon
Name Description
) ic
GATE_DPIB_CT
RL
GATE_DPI_CTR
L
U_RGM2_BIASB
_CTRL
3:0
U_RGM2_BIAS_
CTRL
e a s e I - R 2
10005F00
Bit
Nam
e
15
DRV_SEL10
14 13
l
Re Pi B
12
P
11
10 9 8
DRV_SEL10
7 6 5 4 3 2 1
0000
0
a n a
n
Ba
MT7623N
f o r
10005F00 DRV_SEL10
e a s e I - R 2
GPIO Driving Control Register 10 0000
l
Type RW
Reset
Bit(s
0
Mnemon
0 0
Re Pi B
0
P
0 0 0 0 0 0 0 0 0 0 0 0
a
Name Description
) ic
15:0
n a n
DRV_SEL10 Driving strength control, refer to Table1-3 for detail
10005F10
Bit
Nam
15
DRV_SEL11
14
Ba
13 12 11
10 9 8 7 6 5 4 3 2 1
0000
0
DRV_SEL11
e
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
15:0 DRV_SEL11 Driving strength control, refer to Table1-3 for detail
f o r
10005F30 DRV_SEL12
e a s e I - R 2
GPIO Driving Control Register 12 0000
Bit
Nam
e
Type
Reset
15 14 13
l12
Re Pi B P
11 10 9 8
DRV_SEL12
RW
7 6 5 4 3 2 1 0
a
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
n a n
Name Description
Ba
) ic
MSDC3_CTR
10005F40 MSDC 3 DATA Pad Control Register 1 4444
L3
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MS MS MS MS MS MS MS MS MS
3D 3D 3D 3D 3D 3D 3D
3D 3D 3D 3D 3D 3D 3D 3D 3D
Nam AT
AT AT
AT AT
AT AT
AT
AT1 AT1 AT1
AT1 AT
AT AT
AT
e 3_
3_ 3_
3_ 2_
2_ 2_
2_
_S _R _R
_P 0_
0_ 0_
0_
SM PU SM PU UP SM PU
r
R0 R1 R0 R1 MT 0 1 R0 R1
T PD T PD D T PD
Type
Reset
RW
0
RW
1
RW
0
RW
0
RW
0
e f o
RW
1
2
RW
0
RW
0
RW
0
RW
1
RW
0
RW
0
RW
0
RW
1
RW
0
RW
0
Bit(s Mnemon
Name
)
15
ic
Re Pi B
MS3DAT3_SMT P Schmitter Trigger Control
0:Disable
a
1:Enable
B a
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
14
13
12
l
Re Pi B
MS3DAT3_R0
MS3DAT3_R1
MS3DAT3_PUPD
11
a n a
MS3DAT2_SMT
0:Disable
10
9
8 Ba n
MS3DAT2_R0
MS3DAT2_R1
MS3DAT2_PUPD
1:Enable
1:Enable
2 MS3DAT0_R0
f o r 1:Enable
1 MS3DAT0_R1
e
MS3DAT0_PUP
a s e I - R 2 50K resistor control
l
P
D
Re Pi B
10005F50
Bit 15
DRV_SEL0
14 13
a n a
12 11
10 9 8 7 6 5 4 3 2 1
0000
0
Nam
e
Type
Reset 0 0
Ba
0
n 0 0 0 0
DRV_SEL0
0
RW
0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
10005F60 DRV_SEL1 GPIO Driving Control Register 1 0000
r
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type
e f o 2
DRV_SEL1
RW
Reset 0 0 0
l
0
e a s 0
I - R
0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
15:0
Mnemon
ic
Re Pi B
Name
DRV_SEL1
P Description
Driving strength control, refer to Table1-3 for detail
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
10005F70
Bit
Nam
15
DRV_SEL2
14 13 l
Re Pi B
12 P
11
10 9 8 7 6 5 4 3 2 1
0000
0
a
DRV_SEL2
e
Type
Reset 0 0 0
n a n 0 0 0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s
)
15:0
Mnemon
ic
Ba Name
DRV_SEL2
Description
10005F80 DRV_SEL3 GPIO Driving Control Register 3 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam DRV_SEL3
e
Type RW
r
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
e f o 2
s
Name Description
) ic
15:0
l e a
DRV_SEL3
P I - R Driving strength control, refer to Table1-3 for detail
Re Pi B
10005F90
Bit 15
DRV_SEL4
14 13
a n a
12 11
10 9 8 7 6 5 4 3 2 1
0000
0
Nam
e
Type
Reset 0 0
Ba
0
n 0 0 0 0
DRV_SEL4
0
RW
0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
10005FA
DRV_SEL5 GPIO Driving Control Register 5 0000
0
Bit
Nam
15 14 13 12 11
f o r 10 9 8
DRV_SEL5
7 6 5 4 3 2 1 0
e
e
Type
Reset 0 0 0
l
0
e a s 0
I - R 20 0 0
RW
0 0 0 0 0 0 0 0
Bit(s
)
15:0
Mnemon
ic
Re Pi B
Name
DRV_SEL5
P Description
a
Ba
MT7623N
f o r
e a s e I - R 2
10005FB
0
Bit 15
DRV_SEL6
14 13
l
Re Pi B
12
P
11
10 9 8 7 6 5 4 3 2 1
0000
0
Nam
e
a n a DRV_SEL6
n
Type RW
Ba
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
10005FC MSDC3_CTR
0 L2
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MS MS MS MS MS
Nam
e
f o r
MS3DAT_BACKUP
3D
AT
_IE
3D
AT
_S
3D
AT
_E
3D
AT
_E
3D
AT
_E
Type
Reset 0 0 0
e
0
a s e 0
I - R 2
RW
0 0 0 0 0 0
S
RW
1
R
RW
0
8
RW
1
4
RW
0
2
RW
0
Bit(s
)
Mnemon
ic
l
Re Pi B
Name P Description
15:5
UP
a a
MS3DAT_BACK
n Reserved
4
3 n
MS3DAT_IES
Ba MS3DAT_SR
1: slower slew
000 : 2mA
001: 4mA
010: 6mA
100: 10mA
101: 12mA
110: 14mA
111: 16mA
f o r
10005FD
DRV_SEL8
e a s e I - R 2GPIO Driving Control Register 8 0000

0
Bit
Nam
e
15 14 13
l
Re Pi B
12
P
11 10 9 8
DRV_SEL8
7 6 5 4 3 2 1 0
a
Type RW
Ba
MT7623N
f o r
10005FD
0
DRV_SEL8
e a s e I - R 2GPIO Driving Control Register 8 0000
Reset
Bit(s
0
Mnemon
0 0
l
Re Pi B
0
P
0 0 0 0 0 0 0 0 0 0 0 0
)
15:0
ic
a n a
Name
DRV_SEL8
Description
10005FE Ba n
DRV_SEL7 GPIO Driving Control Register 7 0000
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
DRV_SEL7
e
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
15:0 DRV_SEL7
f o r Driving strength control, refer to Table1-3 for detail
e a s e I - R 2
10005FF0
Bit
Nam
e
15
DRV_SEL9
14 13
l
Re Pi B
12
P
11
10 9 8
DRV_SEL9
7 6 5 4 3 2 1
0000
0
Type
Reset 0 0 0
a n a
0 0 0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s
)
15:0
Mnemon
ic
Ba n Name
DRV_SEL9
Description
f o r
e a s e I - R 2
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
2 Top Clock Generator
e a s e I - R 2
2.1 Introduction
l
Re Pi B P
a n a
This chapter introduces the top clock generator (TOPCKGEN) and the clock architecture
2.2 Feature list

Ba n
TOPCKGEN is responsible for generating the following clock signals:
 Free clock generation for whole chip
 Cortex-A7 CPU clock
 Infrastructure and peripheral system clock, including the top level AXI fabric clock
 Multimedia system clock
 Pad clocks to be synchronized with one of the above system
The module TOPCKGEN provides clock source selection. Each clock has several clock source
o r
selections and can be turned off as well. When switching certain clock from frequency A to frequency
f
B, make sure frequency A and B are available.
e a s e I - R 2
It comprises glitch-free clock MUX and digital clock divider to generate various clock frequencies.
l
Re Pi B P
2.3 Block Diagram
a n a
2.3.1
Ba n
Clock Architecture
The clock generator is not only in the top level but also in every partition / system. Below is the
location of the top level clock generator
f o r
e a s e I - R 2
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2 External Clock
Source
l
Re Pi B P PLL
a n a topckgen
Ba
global_con
n clock_gen global_con global_con
PAD INFRA & PERIPHERAL

MACRO SYSTEM MCU SYSTEM MULTIEMEIDA SYSTEM MFG SYSTEM
Figure 2-1: Block diagram of clock architecture
2.3.2 Clock Multiplixer
f o r
e
Clock selection and generation have similar structure. Several clock sources are provided. Choose on
a s R 2
by specified register setting. The turn-off bit is provided as well to stop the clock output.
l e I -
Re Pi B P
a n a
Ba n
Figure 2-2: Example of Clock Multiplixer
f o r
e a s e I - R 2
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
2.4 Clock PLL
e a s e I - R 2
RG_{name}PLL_EN
l
Re Pi B P
({name}PLL stand for PLL name used in PLLGP
ARMPLL
(ARMPLL)
VCORE
NS_ARMPLL_CK
VPROC
A2D_ACCoup
AD_ARMPLL_CK
A2D_PLL
a
1339MHz le_PLL
1339MHz
n a n MAINPLL
(SDMPLL)
NS_MAINPLL_CK
A2D_PLL
AD_MAINPLL_CORE_CK
Ba
2184MHz 1092MHz
AD_MAINPLL_PRO_CK
A2D_ACCoup
A2D_PLL
le_PLL
MMPLL
AD_MMPLL_CK
(SDMPLL)
2002MHz 500.5MHz
VENCPLL
AD_VENCPLL_CK
(SDMPLL)
1183MHz 295.75MHz
UNIVPLL AD_USB20_48M_CK
AD_UNIVPLL_CK
(SDMPLL) DIV26
1248MHz 1248MHz RG_UNIV48M_EN
RG_USB48M_EN AD_UNIV_48M_CK
MSDCPLL
AD_MSDCPLL_CK
NS_PLLGP_REF_BUF_CK
r
(SDMPLL)
400MHz
o
1600MHz
s e f TRGPLL
(SDMPLL)
2
1450MHz
AD_TRMII_CK
725MHz
l e a P I - R
ETHPLL
(SDMPLL)
AD_ETHPLL_500M_CK
Re Pi B
2000MHz
500MHz
VDECPLL AD_VDECPLL_CK
(SDMPLL)
1352MHz
338MHz
a
AD_AUD1PLL_294M_CK
A2D_PLL
n
NS_AUD1PLL_REF_BUF_CK AUD1PLL NS_AUD1PLL_CK 294MHz
a
(SDMPLL)
n
1573MHz 294MHz AD_AUD1PLL_98M_CK
Ba
DIV3
RG_AUD1PLL_98M_EN 98MHz
NS_TVDPLL_REF_BUF_CK TVDPLL
AD_TVDPLL_CK
(SDMPLL)
1188MHz 148.5MHz AD_HADDS2PLL_294M_CK
A2D_PLL
NS_HADDS2PLL_REF_BUF_CK HADDS2PLL NS_HADDS2PLL_CK 294MHz
(SDMPLL) AD_HADDS2_98M_CK
1180MHz
294MHz
DIV3
98MHz
RG_HADDS2PLL_98M_EN AD_HADDS2_FBCLK
AD_AUD2PLL_270M_CK
A2D_PLL
NS_AUD2PLL_REF_BUF_CK AUD2PLL NS_AUD2PLL_CK 270MHz
(SDMPLL)
1084MHz 270MHz AD_AUD2PLL_90M_CK
DIV3
NS_TVD2PLL_REF_BUF_CK TVD2PLL
RG_AUD2PLL_90M_EN 90MHz
AD_TVD2PLL_CK
(SDMPLL)
r
1188MHz 297MHz
e f o 2
l e a s I - R
Figure 2-3: PLL block diagram
Re Pi B P
a n a
n
Ba
MT7623N
f o r
2.5 PLL Related Control
e a s e I - R 2
l
Re Pi B P
The following table lists all PLLs inside the application system.
The enabling of PLL can be switched between software control and hardware control. The hardware
control is from SCPSYS.
a n a
Ba n
The hopping and SSC features can be switched between software control and hardware control. The
hardware control is from FHCTL
Table 2-1: PLL related control

PLL
PLL ABB FHCTL SCPSYS Main usage
capability
AMRPLL Hopping, SSC Y Y Y MCU
MAINPLL Hopping, SSC Y Y Y (backup) Command bus, peri.
MMPLL Hopping, SSC Y Y - 3D
VENCPLL SSC Y Y (SSC) - Multi-media
UNIVPLL Fix
f o r Y - Y (backup) USB
e
MSDCPLL Hopping, SSC Y Y - MSDC
MEMPLL
(DDRPHY)
Hopping, SSC
l e a s I - R-
2 - Y
Memory bus, EMI,
DDRPHY
MIPIPLL (MIPI)
USB_PHYA (USB)
Re Pi B
Hopping, SSC
Fix P -
-
-
-
-
-
Display
USB PHY
TRGPLL
ETHPLL
SSC
SSC
a n a -
-
-
-
-
-
ETHIFSYS
ETHIFSYS
VDECPLL
TVDPLL
AUD1PLL
B a n
SSC
SSC
Fix
-
-
-
-
-
-
-
-
-
VDEC
TVE
AUDIO
AUD2PLL Fix - - - AUDIO
TVD2PLL SSC - - - NR TVE
HADDS2PLL Fix - - - AUDIO HDMI
2.6 Clock Gating
r
The clock gating for module TOPCKGEN is listed in the table below where DCM and turn-off settings
are provided.
e f o 2
l e a s I - R
Table 2-2: Clock gating settings
Register name
CLK_MODE
Re Pi B
Bit
8
Default
1’b0P Function name
pdn_md_32k
MD
Description
Turns off 32K clock source to
a n a
n
Ba
MT7623N
f o r
Register name Bit
e a s e
Default
I - R 2 Function name Description
l
Turns off 32K clock source to
DCM_CFG
Re Pi B
10
[7]
1’b0
1’b0P pdn_conn_32k
dcm_enable
CONN
Enables hf_faxi_ck DCM
a
Turns on scpsys control path to
CLK_SCP_CFG_0 [0] 1’b0 sc_26ck_off_en
n a
[1] n 1’b0 sc_mem_ck_off_en
gate 26MHz
Ba
gate DDRPHY
[2] 1’b0 sc_axick_off_en
gate hf_faxi_ck
[4] 1’b0 sc_armck_off_en
gate hf_farm_ck
[5] 1’b0 sc_md_32k_off_en
gate MD 32kHz
[7] 1’b0 sc_conn_32k_off_en
gate CONN 32kHz
[9] 1’b0 sc_mac_26m_off_en
gate MIPI 26MHz
CLK_SCP_CFG_1 [0]
f
1’b0
o r sc_axi_26m_sel_en
switch hf_faxi_ck to 26MHz
[4]
e a s e
1’b0
I - R 2sc_axick_dcm_dis_en
disable DCM of hf_faxi_ck
2.7 Frequency Meter

l
Re Pi B P
a n a
There are two frequency meters inside TOPCKGEN. One is for PLLs and TEST clock called
Ba n
abist_fmeter. The other is for clocks generated from TOPCKGEN called ckgen_fmeter.
Both structures have PAD output that can observe frequency directly instead of reading results from
the frequency meter. Abist_fmeter is outputted to CLKM[0], and ckgen_fmeter is outputted to
DEBUG_MON[2].
abist
CKSW
Divider
clocks
CKSW
fmeter
abist_clk_sel
f o r (abist_k1 == 0)
CLKM[0]
abist_k1
e a s e I - R 2
l P
Figure 2-4: ABIST FMETER structure
Re Pi B
a n a
n
B a
MT7623N
f o r
ckgen
e a s e I - R 2
CKSW
l
Divider
clocks
Re Pi B P
CKSW
fmeter
a n
ckgen_clk_sel
a (ckgen_k1 == 0)
DEBUG[2]
Ba n
ckgen_k1
Figure 2-5: CKGEN FMETER structure

Module name: TOPCKGEN Base address: (+10000000h)
Address Name Width Register Function

10000000 CLK_MODE 32 Clock 26M, 32K PDN Control Register
10000004 DCM_CFG 32 AXI Bus Clock DCM Control Register
10000040
10000044
CLK_CFG_0
CLK_CFG_0_S
f
32
o r
32
Function Clock Selection Register 0
SET control of CLK_CFG_0
e
ET
10000048 CLK_CFG_0_C
LR
l e a s 32
I - R 2 CLR control of CLK_CFG_0

10000050
10000054
CLK_CFG_1
CLK_CFG_1_S
ET
CLK_CFG_1_C Re Pi B P 32
32
Function clock selection register 1
10000058
10000060
LR
CLK_CFG_2
a n a 32
32
CLR control of CLK_CFG_1
10000064
10000068
CLK_CFG_2_S
ET
CLK_CFG_2_C
LR
Ba n 32
32

10000070 CLK_CFG_3 32 Function clock selection register 3
10000074 CLK_CFG_3_S 32 SET control of CLK_CFG_3
ET
10000078 CLK_CFG_3_C 32 CLR control of CLK_CFG_3
LR
10000084 CLK_CFG_4_S 32 SET control of CLK_CFG_4
ET
10000088 CLK_CFG_4_C 32 CLR control of CLK_CFG_4
10000090
LR
CLK_CFG_5
f o r
32 Function clock selection register 5
10000094 CLK_CFG_5_S
ET
CLK_CFG_5_C
e a s e 32
I - R 2 SET control of CLK_CFG_5
l
10000098 32 CLR control of CLK_CFG_5
P
LR
Re Pi B
100000A0 CLK_CFG_6 32 Function clock selection register 6
100000A4 CLK_CFG_6_S 32 SET control of CLK_CFG_6
ET
a n a
n
Ba
MT7623N
f o r
100000A8 CLK_CFG_6_C
LR
e a s e I
32
- R 2 CLR control of CLK_CFG_6

100000B0
100000B4
CLK_CFG_7
CLK_CFG_7_S
ET
CLK_CFG_7_C
l
Re Pi B P
32
32
a
100000B8 LR 32 CLR control of CLK_CFG_7
100000C0 CLK_CFG_12
CLK_CFG_12_
n a n 32 Function clock selection register 12
Ba
100000C4 SET 32 SET control of CLK_CFG_12
100000C8 CLK_CFG_12_ 32 CLR control of CLK_CFG_12

CLR
100000D0 CLK_CFG_13 32 Function clock selection register 13
100000D4 CLK_CFG_13_ 32 SET control of CLK_CFG_13
SET
100000D8 CLK_CFG_13_ 32 CLR control of CLK_CFG_13
CLR
100000E0 CLK_CFG_14 32 Function clock selection register 14
100000E4 CLK_CFG_14_ 32 SET control of CLK_CFG_14
SET
100000E8 CLK_CFG_14_ 32 CLR control of CLK_CFG_14
r
CLR
100000F0
100000F4
CLK_CFG_15
CLK_CFG_15_
e f o 32
32
2
100000F8
SET
CLK_CFG_15_
l e a s I -
32
R CLR control of CLK_CFG_15
P
CLR
Re Pi B
a
10000108 CLK_CFG_10 32 Debug monitor clock selection register
1000010C
10000120
CLK_CFG_11
CLK_AUDDIV_
n a n 32
32
Debug monitor divider control register
audio clock divider control register0
Ba
0
10000124 CLK_AUDDIV_ 32 audio clock divider control register1
1
10000128 CLK_AUDDIV_ 32 audio clock divider control register2
2
1000012C CLK_AUDDIV_ 32 audio clock divider control register3
3
10000150 CLK_8BDAC_C 32 8bdac clock divider control register
FG
10000200 CLK_SCP_CFG 32 SCP control register 0
_0
10000204 CLK_SCP_CFG 32 SCP control register 1
_1
10000210 CLK_MISC_CF
G_0
f o r
32 Internal clk_rtc divider control register
e
CLK_MISC_CF
2
10000214 32 Frequency meter divider control register
s
G_1
10000220
10000224
CLK26CALI_0
CLK26CALI_1
l e a P I -
32
32
R Frequency meter control register 0
Frequency meter control register 1
Re Pi B
10000228 CLK26CALI_2 32 Frequency meter control register 2
1000022C CKSTA_REG 32 Function clock selection status register
a
10000230 TEST_MODE_C 32 Test mode control register
Ba
MT7623N
f o r
1000030C
FG
MBIST_CFG_1
e a s e I -
32
R 2 Debug monitor selection register 1
10000310
10000314
10000318
RESET_DEGLI
TCH_KEY
MBIST_CFG_3
BOOT_TRAP
l
Re Pi B P 32
32
32
Reset deglitch enable key register
Debug monitor selection register 3
Boot strap register
a n a
10000000
Bit
Name
31
CLK_MODE
30 29
Ba n
Clock 26M, 32K PDN Control Register
28 27 26 25 24 23 22 21 20 19 18
00000000
17 16
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
pdn_ pdn_ topc
Name conn md_ kgen
_32k 32k _en
Type RW RW RW
Reset 0 0 0
r
Bit(s) Name Description
10 pdn_conn_32k
f o
Turns off 32K clock source to CONN
e
Turn off this clock in flight mode
2
s
1: Enable turn-off
8 pdn_md_32k
l e a I - R
Turns off 32K clock source to MD
P
Turn off this clock in flight mode
Re Pi B
1: Enable turn-off
0 topckgen_en Enables TOPCKGEN
0: Enable
a n a 1: Disable
10000004
Bit 31
DCM_CFG
30 29 Ba n
AXI Bus Clock DCM Control Register
28 27 26 25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
dcm dcm
Name _dbc
_ena dcm_dbc_cnt _ena dcm_full_fsel
ble ble
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
f o r
Description
15 dcm_dbc_enable
e a s e
Enables DCM de-bounce counter
I - R 2
1: Enable DCM de-bounce counter
l
14:8 dcm_dbc_cnt DCM de-bounce counter
7
4:0
dcm_enable
dcm_full_fsel Re Pi B P
Enables hf_faxi_ck DCM
1: Enable DCM
Selects hf_faxi_ck DCM clock
a n a
n
Ba
MT7623N
f o r
Bit(s) Name
e a s e
Description
I - R 2
1xxxx: hd_faxi_ck = hf_faxi_ck
l
Re Pi B P
01xxx: hd_faxi_ck = hf_faxi_ck/2
001xx: hd_faxi_ck = hf_faxi_ck/4
0001x: hd_faxi_ck = hf_faxi_ck/8
00001: hd_faxi_ck =hf_faxi_ck/16
a
00000: hd_faxi_ck = hf_faxi_ck/32
n a n
10000040
Bit 31
Name pdn_
CLK_CFG_0
30 29
Ba
Function Clock Selection Register 0
28 27 26 25
clk_
mm_
24 23 22 21
clk_mm_sel
pdn_
ddrp
20
clk_
ddrp
hycf
19 18
00000000
17 16
clk_
ddrp
hycf
mm inv hycf g_in g_se
g v l
Type RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
clk_ clk_ pdn_ clk_a
Name pdn_
mem mem mem axi xi_in clk_axi_sel
_inv _sel v
Reset 0 0
f o r 0 0 0 0 0 0
Bit(s) Name
31 pdn_mm
e a s e
Description
I - R 2
28 clk_mm_inv
26:24 clk_mm_sel
l
Re Pi B P
Inverts hf_fmm_ck clock phase
1: Enable phase inversion
Selects hf_fmm_ck clock mux
a n a 0: clk26m
1: vencpll_ck
2: syspll1_d2
Ba n 3: syspll_d5
4: syspll1_d4
5: univpll_d5
6: univpll2_d2
7: dmpll_ck
23 pdn_ddrphycfg Turns off hf_fddrphycfg_ck
1: Enable clock-off
20 clk_ddrphycfg_inv Inverts hf_fddrphycfg_ck clock phase
16 clk_ddrphycfg_sel Selects hf_fddrphycfg_ck clock mux
0: clk26m
1: syspll1_d8
15 pdn_mem Turns off hf_fmem_ck
12 clk_mem_inv
f r
1: Enable clock-off
o
Inverts hf_fmem_ck clock phase
8 clk_mem_sel
e a s e - R 2
Selects hf_fmem_ck clock mux
I
7 pdn_axi l
Re Pi B
0: clk26m
P
1: dmpll_ck
Turns off hf_faxi_ck
1: Enable clock-off
a n a
n
Ba
MT7623N
f o r
Bit(s) Name
4 clk_axi_inv
e a s e
Description
I - R 2
Inverts hf_faxi_ck clock phase
2:0 clk_axi_sel l
Re Pi B P
Selects hf_faxi_ck clock mux
0: clk26m
a
1: syspll1_d2
n a n 2: syspll_d5
3: syspll1_d4
4: univpll_d5
Ba
5: univpll2_d2
6: dmpll_ck
7: dmpll_d2
CLK_CFG_0_SE
10000044 SET control of CLK_CFG_0 00000000
T
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name clk_cfg_0_set[31:16]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
f o r
clk_cfg_0_set[15:0]
WO
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
l e a s I - R
Description 2
31:0 clk_cfg_0_set
Re Pi B P
Sets the correspondent bit of CLG_CFG_SEL_0
0: Unchanged
1: Set 1'b1 to the correspondent bit
a n a
10000048
Bit
Name
31
R
30 29
Ba
CLK_CFG_0_CL
n
28 27 26 25 24 23 22
clk_cfg_0_clr[31:16]
21 20 19 18
00000000
17 16
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name clk_cfg_0_clr[15:0]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
r
31:0 clk_cfg_0_clr Clears the correspondent bit of CLG_CFG_SEL_0
o
0: Unchanged
f
e 2
l e a s I - R
10000050
Bit 31
pdn_
Name camt
CLK_CFG_1
30 29
clk_c
Re Pi B
28 27 26 25 P
24 23 22 21 20
pdn_
clk_camtg_sel mfg clk_
19 18
00000000
17 16
clk_mfg_sel
amtg
a n a mfg_
n
Ba
MT7623N
f o r
g
Type RW
_inv
RW
e a s e RW
I - R 2 RW
inv
RW RW
l
Reset 0 0 0 0 0 0 0 0 0 0
Bit 15
Name pdn_
vdec
14 13
Re Pi B
12
clk_v
dec_
inv
11 10
P 9
clk_vdec_sel
8 7
pdn_
pwm
6 5 4
clk_
pwm
_inv
3 2 1
clk_pwm_
sel
0
Type RW
Reset 0
RW
a
0
n a0 0
RW
0 0
RW
0
RW
0 0
RW
0
Bit(s) Name
31 pdn_camtg
Ba n Description
Turns off hf_fcamtg_ck
1: Enable clock-off
28 clk_camtg_inv Inverts hf_fcamtg_ck clock phase
26:24 clk_camtg_sel Selects hf_fcamtg_ck clock mux
0: clk26m
1: univpll_d26
2: univpll2_d2
3: syspll3_d2
4: syspll3_d4
5: msdcpll_d2
r
6: mmpll_d2
23 pdn_mfg
f o
Turns off hf_fmfg_ck
e
1: Enable clock-off
2
20 clk_mfg_inv
l e a s I - R
Inverts hf_fmfg_ck clock phase
18:16 clk_mfg_sel
Re Pi B P
Selects hf_fmfg_ck clock mux
0: clk26m
1: mmpll_ck
2: dmpll_x2_ck
a n a 3: msdcpll_ck
4: clk26m
15 pdn_vdec
Ba n 5: syspll_d3
6: univpll_d3
7: univpll1_d2
turns off hf_fvdec_ck
1: Enable clock-off
12 clk_vdec_inv Inverts hf_fvdec_ck clock phase
11:8 clk_vdec_sel Selects hf_fvdec_ck clock mux
0: clk26m
1: AD_VDECPLL_CK
2: syspll_d5
3: syspll1_d4
4: univpll_d5
5: univpll2_d2
f o r
6: AD_VENCPLL_CK
7: msdcpll_d2
e
8: mmpll_d2
7 pdn_pwm
l e a s I - 2
Turns off f_fpwm_ck
R
1: Enable clock-off
4
1:0
clk_pwm_inv
clk_pwm_sel
Re Pi B P
Inverts f_fpwm_ck clock phase
Selects f_fpwm_ck clock mux
a n a 0: clk26m
n
Ba
MT7623N
f o r
Bit(s) Name
e a s e
Description
I - R 2
1: univpll2_d4
l
Re Pi B P
2: univpll3_d2
3: univpll1_d4
CLK_CFG_1_SE
a n a
n
T
Ba
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31:0 clk_cfg_1_set Sets the correspondent bit of CLG_CFG_SEL_1
0: Unchanged
r
e f o 2
10000058
CLK_CFG_1_CL
l e a s I - R
CLR control of CLK_CFG_1 00000000
P
R
Bit
Name
Type
31 30 29
Re Pi B
28 27 26 25 24 23 22
WO
21 20 19 18 17 16
Reset
Bit
0
15
0 0
14 13
0
12
0
11
a n a
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
n
Ba
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0: Unchanged
10000060 CLK_CFG_2 Function clock selection register 2 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
pdn_
msd
Name c30_
clk_
msd
c30_
f
clk_msdc30_0_ pdn_
o r
usb2
clk_
usb2 clk_usb20
e
sel 0_in _sel
2
0_in 0
s
0 v v
Type RW
Reset 0
RW
0 0
l
RW
e
0
a 0
P
RW
I
0
- R RW
0 0
RW
0
Re Pi B
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
clk_s clk_ clk_
Name pdn_
spi0 pi0_i clk_spi0_sel pdn_
uart uart_ uart_
nv inv sel
a n a
n
B a
MT7623N
f o r
Type RW
Reset 0
RW
0
e a s e I - R 20
RW
0 0
RW
0
RW
0
RW
0
Bit(s) Name
31 pdn_msdc30_0
l
Re Pi B P
Description
Turns off hf_fmsdc30_0_ck
a
1: Enable clock-off
28 clk_msdc30_0_inv
n a n Inverts hf_fmsdc30_0_ck clock phase

Ba
26:24 clk_msdc30_0_sel Selects hf_fmsdc30_0_ck clock mux
0: clk26m
1: msdcpll_d2
2: syspll2_d2
3: syspll1_d4
4: univpll1_d4
5: univpll2_d4
23 pdn_usb20 Turns off f_fusb20_ck
1: Enable clock-off
20 clk_usb20_inv Inverts f_fusb20_ck clock phase
17:16 clk_usb20_sel Selects f_fusb20_ck clock mux
r
0: clk26m
o
1: univpll1_d8
f
2: univpll3_d4
e 2
s
15 pdn_spi0 Turns off hf_fspi0_ck
12 clk_spi0_inv
l e a P - R
1: Enable clock-off
I
Inverts hf_fspi0_ck clock phase
Re Pi B
10:8 clk_spi0_sel Selects hf_fspi0_ck clock mux
0: clk26m
a n a 1: syspll3_d2
2: syspll4_d2
7 pdn_uart
Ba n 3: univpll2_d4
4: univpll1_d8
Turns off f_fuart_ck
1: Enable clock-off
4 clk_uart_inv Inverts f_fuart_ck clock phase
0 clk_uart_sel Selects f_fuart_ck clock mux
0: clk26m
1: univpll2_d8
CLK_CFG_2_SE
r
o
T
Bit
Name
31 30 29 28 27 26 25 24 23 22
e f
clk_cfg_2_set[31:16]
s 2
21 20 19 18 17 16
a R
Type WO
Reset
Bit
0
15
0 0
14 13
0
12
0
11
0
10
l e
0
9
0
8
P
0
7
I - 0
6
0
5
0
4
0
3
0
2
0
1
0
0
Re Pi B
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
a n a
n
B a
MT7623N
f o r
Bit(s) Name
31:0 clk_cfg_2_set
e a s e
Description
I - R 2
l
Re Pi B P
0: Unchanged
CLK_CFG_2_CL
a n a
10000068
Bit
Name
Type
31
R
30 29
Ba n
28 27 26 25 24 23 22
WO
21 20 19 18
00000000
17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0: Unchanged
f o r
e a s e I - R 2
l
Bit 31
pdn_
aud_
Name intbu
30 29
ud_i
ntbu Re Pi B
28 27 26 25
clk_a
P24 23 22 21 20
clk_aud_intbus pdn_
audi
clk_a
udio
19 18 17 16
clk_
audi
a
s_in _sel o _inv o_se
n
s v l
Type RW RW
n a RW RW RW RW
Ba
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
pdn_ clk_ pdn_ clk_
msd msd clk_msdc30_2_ msd msd clk_msdc30_1_
Name c30_ c30_ sel c30_ c30_ sel
2 2_in 1 1_in
v v
Reset 0 0 0 0 0 0 0 0 0 0

31 pdn_aud_intbus Turns off hf_faud_intbus_ck
1: Enable clock-off
r
28 clk_aud_intbus_inv Inverts hf_faud_intbus_ck clock phase
26:24 clk_aud_intbus_sel
o
f
Selects hf_faud_intbus_ck clock mux
e 2
l e a s0: clk26m
- R
1: syspll1_d4
I
2: syspll3_d2
Re Pi B P
3: syspll4_d2
4: univpll3_d2
5: univpll2_d4
a
23 pdn_audio Turns off hf_faudio_ck
Ba
MT7623N
f o r
Bit(s) Name
e a s e
Description
I - R 2
1: Enable clock-off
20
16
clk_audio_inv
clk_audio_sel
l
Re Pi B P
Inverts hf_faudio_ck clock phase
Selects hf_faudio_ck clock mux
a n a 0: f_f26m_ck
1: syspll1_d16
n
15 pdn_msdc30_2 Turns off hf_fmsdc30_2_ck
Ba
1: Enable clock-off
12 clk_msdc30_2_inv Inverts hf_fmsdc30_2_ck clock phase
0: clk26m
1: msdcpll_d2
2: syspll2_d2
3: syspll1_d4
4: univpll1_d4
5: univpll2_d4
1: Enable clock-off
r
2:0 clk_msdc30_1_sel
f o
e
Selects hf_fmsdc30_1_ck clock mux
2
l e a s0: clk26m
I - R
1: msdcpll_d2
P
2: syspll2_d2
Re Pi B
3: syspll1_d4
4: univpll1_d4
5: univpll2_d4
a n a
10000074
Bit
Name
31
T
30 29
Ba
CLK_CFG_3_SE
n
28 27 26 25 24 23 22
21 20 19 18
00000000
17 16
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

o r
0: Unchanged
f
e a s e I - R 2
10000078
Bit 31
CLK_CFG_3_CL
R
30 29
l
Re Pi B
28 27 26 25 24 23 22
P
21 20 19 18
00000000
17 16
Name
a n a clk_cfg_3_clr[31:16]
n
Ba
MT7623N
f o r
Type
Reset 0 0 0 0
e a s e 0
I - R 20 0 0 0
WO
0 0 0 0 0 0 0
l
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset 0 0 0
Re Pi B
0 P
0 0
clk_cfg_3_clr[15:0]
0 0
WO
0 0 0 0 0 0 0 0
Bit(s) Name
a n a Description
31:0 clk_cfg_3_clr
Ba n Clears the correspondent bit of CLG_CFG_SEL_3

0: Unchanged

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
clk_ clk_
Name pdn_
dpi1 dpi1 clk_dpi1_s pdn_
el dpi0 dpi0 clk_dpi0_sel
_inv _inv
Reset 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name pdn_
scp
clk_s
cp_i
nv
f o r clk_scp_s
el
clk_
pdn_pmicspi pmic
spi_i clk_pmicspi_sel
Type RW
Reset 0
RW
0
e a s e I - R 2 0
RW
0 0
RW
0 0
nv
RW
0 0 0
RW
0 0
Bit(s) Name
31 pdn_dpi1
l
Re Pi B P
Description
Turns off hf_fdpi1_ck
28 clk_dpi1_inv
a n a 1: Enable clock-off
Inverts hf_fdpi1_ck clock phase
25:24 clk_dpi1_sel
Ba n 1: Enable phase inversion

Selects hf_fdpi1_ck clock mux
0: clk26m
1: tvdpll
2: tvdpll_d2
3: tvdpll_d4
23 pdn_dpi0 Turns off hf_fdpi0_ck
1: Enable clock-off
20 clk_dpi0_inv Inverts hf_fdpi0_ck clock phase
18:16 clk_dpi0_sel Selects hf_fdpi0_ck clock mux
0: clk26m
1: mipipll
f r
2: mipipll_d2
o
3: mipipll_d4
4: f_f26m_ck
e a s e
5: tvdpll_ck
R
6: tvdpll_d2
I -
7: tvdpll_d4
2
15
12
pdn_scp
clk_scp_inv
l
Re Pi B P
Turns off hf_fscp_ck
1: Enable clock-off
Inverts hf_fscp_ck clock phase
a n a
n
Ba
MT7623N
f o r
Bit(s) Name
e a s e
Description
I - R 2
9:8 clk_scp_sel
l
Re Pi B P
Selects hf_fscp_ck clock mux
0: clk26m
1: syspll1_d8
2: dmpll_d2
7:5 pdn_pmicspi
a n a 3: dmpll_d4
Turns off hf_fpmicspi_ck
3:0
clk_pmicspi_inv
clk_pmicspi_selBa n 1: Enable clock-off

Inverts hf_fpmicspi_ck clock phase
Selects hf_fpmicspi_ck clock mux
0: clk26m
1: syspll1_d8
2: syspll2_d4
3: syspll4_d2
4: syspll3_d4
5: syspll2_d8
6: syspll1_d16
7: univpll3_d4
8: univpll_d26
9: dmpll_d2
f o r
10: dmpll_d4
CLK_CFG_4_SE
e a s e I - R 2
10000084
Bit
Name
31
T
30 29 l
Re Pi B
28 27 26 25 24 23 22
P
21 20 19 18
00000000
17 16
a
Type WO
n
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
15 14 13 12 11
n a 10 9 8 7 6
clk_cfg_4_set[15:0]
5 4 3 2 1 0
Ba
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0: Unchanged
CLK_CFG_4_CL
10000088 CLR control of CLK_CFG_4 00000000
R
Bit
Name
31 30 29 28 27 26 25 24 23 22
f o r
21 20 19 18 17 16
Type
Reset
Bit
0
15
0 0
14 13
0
12
0
11
0
10
e a s0
9e 0
8
I
WO
-
0
R
7
2 0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
Reset 0 0 0 0 0 l
Re Pi B
0 0
P
clk_cfg_4_clr[15:0]
0
WO
0 0 0 0 0 0 0 0
a n a
n
Ba
MT7623N
f o r
Bit(s) Name
31:0 clk_cfg_4_clr
e a s e
Description
I - R 2
Clears the correspondent bit of CLG_CFG_SEL_4
l
Re Pi B P
0: Unchanged
10000090 CLK_CFG_5
a n a
Function clock selection register 5 00000000
Bit 31
pdn_
Name dpilv
ds
30 29
Ba
dpilv
ds_i
nv
n
28 27 26 25
clk_
24 23 22 21 20
clk_dpilvds_sel pdn_
apll
clk_a
pll_i
nv
19 18 17 16
clk_apll_sel
Reset 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
pdn_ clk_ clk_hdmi_ pdn_ clk_t
Name hdmi hdmi sel tve ve_i clk_tve_sel
_inv nv
Reset 0 0 0 0 0 0 0 0 0
r
31 pdn_dpilvds
f o
Turns off hf_fdpilvds_ck
e
1: Enable clock-off
2
28 clk_dpilvds_inv
l e a s R
Inverts hf_fdpilvds_ck clock phase
I -
26:24 clk_dpilvds_sel
Re Pi B P
Selects hf_fdpilvds_ck clock mux
0: clk26m
1: lvdspll
a
2: lvdspll_d2
n
3: lvdspll_d4
n a 4: lvdspll_d8
5: fpc_ck
Ba
6: clk26m
7: clk26m
23 pdn_apll Turns off f_fapll_ck
1: Enable clock-off
20 clk_apll_inv Inverts f_fapll_ck clock phase
18:16 clk_apll_sel Selects f_fapll_ck clock mux
0: clk26m
1: audpll
2: audpll_d4
3: audpll_d8
4: audpll_d16
5: audpll_d24
o r
6: clk26m
f
7: clk26m
15 pdn_hdmi
e a s e I - R 2
Turns off hf_fhdmi_ck
1: Enable clock-off
12
9:8
clk_hdmi_inv
clk_hdmi_sel l
Re Pi B
Inverts hf_fhdmi_ck clock phase
P
Selects hf_fhdmi_ck clock mux
0: clk26m
a n a 1: hdmipll
n
Ba
MT7623N
f o r
Bit(s) Name
e a s e
Description
I - R 2
2: hdmipll_d2
7 pdn_tve
l
Re Pi B P
3: hdmipll_d3
Turns off f_ftve_ck
1: Enable clock-off
a
4 clk_tve_inv Inverts f_ftve_ck clock phase
2:0 clk_tve_sel
n a n 1: Enable phase inversion

Selects f_ftve_ck clock mux
Ba
0: clk26m
1: mipipll
2: mipipll_d2
3: mipipll_d4
4: clk_26m
5: tvdpll
6: tvdpll_d2
7: tvdpll_d4
CLK_CFG_5_SE
T
Bit
Name
Type
31 30 29 28 27 26 25 24 23 22
f o r
WO
21 20 19 18 17 16
Reset
Bit
0
15
0 0
14 13
0
12
0
11
0
10
e a s e
0
9
0
8
I - R
0
7
2
0
6
0
5
0
4
0
3
0
2
0
1
0
0
l
Type
Reset 0 0 0 0
Re Pi B
0 0 0
P 0
WO
0 0 0 0 0 0 0 0
a
31:0 clk_cfg_5_set
n a n Sets the correspondent bit of CLG_CFG_SEL_5

0: Unchanged
Ba
CLK_CFG_5_CL
10000098 CLR control of CLK_CFG_5 00000000
R
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type WO
Reset 0 0 0 0 0 0 0
f
0
o r 0 0 0 0 0 0 0 0
Bit(s) Name
31:0 clk_cfg_5_clr
e a s e
Description
- R 2
I
l
Re Pi B
0: Unchanged
P
a n a
n
Ba
MT7623N
f o r
100000A0 CLK_CFG_6
a s e R 2
e I -
00000000
l
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
pdn_
Name emm
c_hc
lk
Re Pi B P
clk_emmc pdn_
_hclk_sel eth_
50m
clk_e
th_5
0m_i
nv
clk_eth_50m_se
l
Type RW
Reset 0
Bit 15 14 13 12 11
a n a
10
0
9
RW
0
8
RW
0
7 6 5
RW
0
4 3
0
2
RW
0
1
0
0
Name pdn_
nfi2x
Type RW
Reset 0
clk_
nfi2x
_inv
RW
0 Ba n clk_nfi2x_sel pdn_
0
RW
0 0
rtc
RW
0
clk_r
tc_in
RW
v
0
clk_rtc_se
0
l
RW
0

31 pdn_emmc_hclk Turns off hf_f_emmc_hclk_ck
1: Enable clock-off
25:24 clk_emmc_hclk_sel Selection hf_f_emmc_hclk_ck
0: clk26m
1: syspll1_d2
2: syspll1_d4
23 pdn_eth_50m
f r
3: syspll2_d2
o
Turns off f_feth_50m_ck
20 clk_eth_50m_inv
e a s e
1: Enable clock-off
R 2
Inverts f_feth_50m_ck clock phase
I -
l
18:16 clk_eth_50m_sel
Re Pi B P
Selects f_feth_50m_ck clock mux
0: clk26m
1: syspll3_d4
a
2: univpll2_d8
n
3: lvdspll_eth
n a 4: univpll_d26
5: syspll2_d8
Ba
6: syspll4_d4
7: univpll3_d8
15 pdn_nfi2x Turns off hf_fnfi2x_ck
1: Enable clock-off
12 clk_nfi2x_inv Inverts hf_fnfi2x_ck clock phase
10:8 clk_nfi2x_sel Selects hf_fnfi2x_ck clock mux
0: clk26m
1: syspll2_d2
2: syspll_d7
3: univpll3_d2
4: syspll2_d4
5: univpll3_d4
o r
6: syspll4_d4
f
7: clk26m
7 pdn_rtc
e a s e I - R 2
Turns off f_frtc_ck
1: Enable clock-off
4
1:0
clk_rtc_inv
clk_rtc_sel l
Re Pi B
Inverts f_frtc_ck clock phase
P
Selects f_frtc_ck clock mux
0: 32k_internal
a n a
n
Ba
MT7623N
f o r
Bit(s) Name
e a s e
Description
I - R 2
1: 32k_external
l
Re Pi B P
2: clk26m
3: univpll3_d8
CLK_CFG_6_SE
a n a
n
100000A4 SET control of CLK_CFG_6 00000000
T
Ba
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0: Unchanged
r
e f o 2
100000A8
CLK_CFG_6_CL
l e a s I - R
P
R
Bit
Name
Type
31 30 29
Re Pi B
28 27 26 25 24 23 22
WO
21 20 19 18 17 16
Reset
Bit
0
15
0 0
14 13
0
12
0
11
a n a
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
n
Ba
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0: Unchanged
100000B0 CLK_CFG_7 Function clock selection register 7 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name pdn_
osd
clk_
osd_
inv
clk_osd_sel pdn_
f o r
nr
clk_
nr_in
v
clk_nr_sel
Type RW
Reset 0
Bit 15 14 13
RW
0
12 11
0
10
RW
0
e
9
a s e
0
8
RW
I
0
7
- R
6
2 5
RW
0
4 3
0
2
RW
0
1
0
0
pdn_
Name di
Type RW
Reset 0
clk_
di_in
RW
v
0
l
Re Pi B
0
RW
0
P
pdn_
clk_di_sel flash
RW
0
clk_f
lash
_inv
RW
0
clk_flash_sel
0
RW
0 0
a n a
n
B a
MT7623N
f o r
Bit(s) Name
e a s e I - R
Description
2
31
28
pdn_osd
clk_osd_inv
l
Re Pi B P
Turns off hf_fosd_ck
1: Enable clock-off
Inverts hf_fosd_ck clock phase
26:24 clk_osd_sel
a n a 1: Enable phase inversion

Selects hf_fosd_ck clock mux
Ba n 0: clk26m
1: AD_VENCPLL_CK
2: syspll1_d2
3: syspll1_d4
4: univpll_d5
5: univpll1_d2
6: univpll2_d2
7: dmpll_ck
23 pdn_nr Turns off f_fnr_ck
1: Enable clock-off
20 clk_nr_inv Inverts f_fnr_ck clock phase
18:16 clk_nr_sel Selects f_fnr_ck clock mux
r
0: clk26m
o
1: AD_VENCPLL_CK
s f
2: syspll1_d2
e
3: syspll1_d4
2
4: univpll_d5
l e a P I - R
5: univpll1_d2
6: univpll2_d2
Re Pi B
7: dmpll_ck
15 pdn_di Turns off hf_fdi_ck
1: Enable clock-off
12 clk_di_inv
a n a Inverts hf_fdi_ck clock phase

9:8 clk_di_sel
Ba n Selects hf_fdi_ck clock mux

0: clk26m
1: tvd2pll_ck
2: tvd2pll_d2
3: clk26m
7 pdn_flash Turns off f_fflash_ck
1: Enable clock-off
4 clk_flash_inv Inverts f_fflash_ck clock phase
2:0 clk_flash_sel Selects f_fflash_ck clock mux
0: clk26m_d8
1: clk26m
2: syspll2_d8
f o r
3: syspll3_d4
4: univpll3_d4
e
5: syspll4_d2
l e a s I - 2
6: syspll2_d4
R
7: univpll2_d4
100000B4
Re Pi B P
CLK_CFG_7_SE SET control of CLK_CFG_7 00000000
a n a
n
Ba
MT7623N
f o r
Bit 31
T
30 29
e
28
a s e 27
I - R 2
26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit
0
15
0
14
0
13
l
Re Pi B
0
12 P
0
11
0
10
0
9
0
8
WO
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
a
n
Type WO
Reset 0 0 0
n a 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
31:0 clk_cfg_7_set
Ba Description
0: Unchanged
CLK_CFG_7_CL
100000B8 CLR control of CLK_CFG_7 00000000
R
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
r
Type WO
o
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
15 14 13 12 11 10 9
e f
8 7
2
6
clk_cfg_7_clr[15:0]
s
5 4 3 2 1 0
R
Type WO
Reset 0 0 0 0 0 0
l e a0 0
P I -
0 0 0 0 0 0 0 0
Bit(s) Name
31:0 clk_cfg_7_clr
Re Pi B Description
a n a 0: Unchanged
100000C0
Ba n
CLK_CFG_12 Function clock selection register 12 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
pdn_ clk_a
Name asm sm_ clk_asm_ pdn_
asm
clk_a
sm_l clk_asm_l
_m m_in m_sel _l _inv _sel
v
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
pdn_ clk_
pdn_ clk_i clk_intdir_ hdmi hdmi clk_hdmirx_bist
Name intdi ntdir sel rx_bi rx_bi _sel
Type RW
r _inv
RW RW
f o rst
RW
st_in
RW
v
RW
Reset 0 0
e
0
a s e 0
I
0
- R 2
0 0 0 0
Bit(s) Name
31 pdn_asm_m
l
Re Pi B P
Description
Turns off hf_fasm_m_ck
1: Enable clock-off
a
28 clk_asm_m_inv Inverts hf_fasm_m_ck clock phase
Ba
MT7623N
f o r
Bit(s) Name
e a s e
Description
I - R 2
25:24 clk_asm_m_sel
l
Re Pi B P
Selects hf_fasm_m_ck clock mux
0: clk26m
1: univpll2_d4
2: univpll2_d2
23 pdn_asm_l
a n a 3: syspll_d5
Turns off f_fasm_l_ck
20 clk_asm_l_inv
17:16 clk_asm_l_sel Ba n 1: Enable clock-off

Inverts f_fasm_l_ck clock phase
Selects f_fasm_l_ck clock mux
0: clk26m
1: univpll2_d4
2: univpll2_d2
3: syspll_d5
15 pdn_intdir Turns off hf_fint_dir_ck
1: Enable clock-off
12 clk_intdir_inv Inverts hf_fintdir_ck clock phase
r
9:8 clk_intdir_sel Selects hf_fintdir_ck clock mux
f o
0: clk26m
1: mmpll_ck
e 2
s
2: syspll_d2
a R
3: univpll_d2
7 pdn_hdmirx_bist
l e I -
Turns off f_fhdmirx_bist_ck
P
Re Pi B
1: Enable clock-off
4 clk_hdmirx_bist_inv Inverts f_fhdmirx_bist_ck clock phase
2:0 clk_hdmirx_bist_sel
a n a Selects f_fhdmirx_bist_ck clock mux

0: clk26m
Ba n 1: syspll_d3
2: clk26m
3: syspll1_d16
4: syspll4_d2
5: syspll1_d4
6: AD_VENCPLL_CK
7: clk26m
CLK_CFG_12_S
100000C4 SET control of CLK_CFG_12 00000000
ET
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type
Reset 0 0 0 0 0 0 0 0
WO
f o
0
r 0 0 0 0 0 0 0
e
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset 0 0 0 0 0 0
l e
0
s0
WO
0
I 0 2
a - R 0 0 0 0 0 0
Bit(s) Name
31:0 clk_cfg_12_set Re Pi B P
Description
a n a
n
B a
MT7623N
f o r
Bit(s) Name
e a s e
Description
I - R
0: Unchanged
2
l
Re Pi B P
100000C8
CLK_CFG_12_C
LR
a n a
Bit
Name
Type
Reset
Bit
31
0
15
30 29
0 0
14 13
0
12 Ba n
28 27 26 25 24 23 22 21
0
11
0
10
0
9
0
8
WO
0
7
0
6
0
5
20
0
4
19
0
3
18
0
2
17
0
1
16
0
0
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0: Unchanged
f o r
100000D0
e a s e I - R 2
CLK_CFG_13 Function clock selection register 13 00000000
l
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
pdn_
Name ethif
_m Re Pi B
clk_e
thif_i
nv
P clk_ethif_sel
pdn_
ms_
card
clk_
ms_
26m clk_ms_ca
_13 rd_sel
a
m_s
n
el
a
Reset 0
Bit 15
pdn_
Name host
_spi
14
Ba
13
n0
12
clk_
host
_spi
_inv
11
0
10
0
9
clk_host_spi_se pdn_
l asm
_h
0
8
0
7 6 5 4
clk_a
sm_
h_in
v
3
0
2
0
1
0
0
clk_asm_
h_sel
Reset 0 0 0 0 0 0 0 0 0

31 pdn_ethif_m Turns off hf_fethif_ck
1: Enable clock-off
28 clk_ethif_inv Inverts hf_fethif_ck clock phase
26:24 clk_ethif_sel
o r
Selects hf_fethif_ck clock mux
f
0: clk26m
e a s e
1: syspll1_d2
R
2: syspll_d5
I -
3: syspll1_d4
2
l
Re Pi B P
4: univpll_d5
5: univpll1_d2
6: dmpll_ck
7: dmpll_d2
a n a
n
Ba
MT7623N
f o r
Bit(s) Name
23 pdn_ms_card
Description
e a s e I -
Turns off f_fms_card_ck
R 2
18 l
Re Pi B P
1: Enable clock-off
clk_ms_26m_13m_s Select clk_26m_13m_ck
el 0: clk26m
a
1: clk26m_d4
17:16 clk_ms_card_sel
n a n
Selects f_fms_card_ck clock mux
0: clk26m_d2
Ba
1: univpll3_d8
2: syspll4_d4
3: clk_26m_13m_ck
15 pdn_host_spi Turns off hf_fhost_spi_ck
1: Enable clock-off
12 clk_host_spi_inv Inverts hf_fhost_spi_ck clock phase
10:8 clk_host_spi_sel Selects hf_fintdir_ck clock mux
0: clk26m
1: syspll3_d4
2: syspll2_d4
3: syspll4_d2
4: syspll1_d4
5: univpll2_d2
6: univpll3_d2
f o r
e
7: syspll2_d8
7 pdn_asm_h
e a s
Turns off f_fasm_h_ck
1: Enable clock-off
l I - R 2
4 clk_asm_h_inv
1:0 clk_asm_h_sel
Re Pi B P
Inverts f_fasm_h_ck clock phase
Selects f_fasm_h_ck clock mux
0: clk26m
n a
1: univpll2_d4
a
2: univpll2_d2
n
3: syspll_d5
Ba
CLK_CFG_13_S
100000D4 SET control of CLK_CFG_13 00000000
ET
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
f o r
e
31:0 clk_cfg_13_set
l e a s I - R
0: Unchanged
2
Re Pi B P
a n a
n
Ba
MT7623N
f o r
100000D8
CLK_CFG_13_C
e a s e I - R 2
l
LR
Bit
Name
Type
Reset
31
0
30 29
0 0 0 Re Pi B
0 0 0
P
28 27 26 25 24 23 22 21
0
WO
0 0 0
20
0
19
0
18
0
17
0
16
0
Bit
Name
15 14 13 12 11
a n a
10 9 8 7 6
5 4 3 2 1 0
Type
Reset 0
Bit(s) Name
0 0 0
Ba n0 0 0 0
WO
0
Description
0 0 0 0 0 0 0

0: Unchanged
100000E0 CLK_CFG_14 Function clock selection register 14 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
clk_c
r
clk_s pdn_
Name pdn_ msy
spi2 pi2_i
nv
e f o 2
clk_spi2_sel cms
ys s_in
v
clk_cmsys_sel
s
a R
Reset 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12
l e
11
P I - 10 9 8 7 6 5 4 3 2 1 0
Re Pi B
clk_ clk_
pdn_ msd hdmi
msd
Name c30_ c30_ clk_msdc30_3_ rx_2
3_in sel 6m_
a
3 v 24m
n
_sel
a
Type RW RW RW RW
n
Reset 0 0 0 0 0 0
Bit(s) Name
31 pdn_spi2 Ba Description
Turns off hf_fspi2_ck
1: Enable clock-off
28 clk_spi2_inv Inverts hf_fspi2_ck clock phase
26:24 clk_spi2_sel Selects hf_fspi2_ck clock mux
0: clk26m
1: syspll3_d2
2: syspll4_d2
3: univpll2_d4
4: univpll1_d8
f o r
5: clk26m
6: clk26m
e
7: clk26m
23 pdn_cmsys
l e a s I - 2
Turns off f_cmsys_ck
R
1: Enable clock-off
20 clk_cmsys_inv
19:16 clk_cmsys_sel
Re Pi B P
Inverts hf_fcmsys_ck clock phase
Selects f_fcmsys_ck clock mux
a n a 0: clk26m
n
Ba
MT7623N
f o r
Bit(s) Name
e a s
Description
e
1: syspll1_d2
I - R 2
l
2: univpll1_d2
Re Pi B
3: univpll_d5
4: syspll_d5
5: syspll2_d2 P
a
6: syspll1_d4
n
7: syspll3_d2
a
8: syspll2_d4
n
9: syspll1_d8
Ba
10: syspll2_d8
11: clk26m
12: clk26m
13: clk26m
14: clk26m
15: clk26m
1: Enable clock-off
0: clk26m
r
1: msdcpll_ck
o
2: syspll2_d2
3: syspll1_d4
e
4: univpll1_d4
s
5: msdcpll_d2 f 2
l e a
6: msdcpll_d4
7: msdcpll_d8
P I - R
Re Pi B
0 clk_hdmirx_26m_24 Selects f_fasm_h_ck clock mux
m_sel 0: clk26m
1: univpll_d52
a n a
100000E4
Bit 31
ET
30 29 Ba
CLK_CFG_14_S
n
28 27 26 25 24 23 22 21 20 19 18
00000000
17 16
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31:0 clk_cfg_14_set
f o r
0: Unchanged
e a s e I - R 2
100000E8
CLK_CFG_14_C
LR l
Re Pi B P
a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Ba
MT7623N
f o r
Name
Type
e a s e I - R 2 clk_cfg_14_clr[31:16]
WO
l
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
Type
Reset
15
0
14
0
13
0
Re Pi B
12
0
P
11
0
10
0
9 8 7 6
0 0
WO
0 0
5
0
4
0
3
0
2
0
1
0
0
Bit(s) Name
a n a Description
31:0 clk_cfg_14_clr
Ba n Clears the correspondent bit of CLG_CFG_SEL_14

0: Unchanged
100000F0 CLK_CFG_15 Function clock selection register 15 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
pdn_ clk_
Name aud2 aud2
dvd dvd_
sel
Type RW RW
r
Reset 0 0
o
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
pdn_
Name 8bda
c
clk_8
bdac
_inv
s e f 2
clk_8bdac pdn_
_sel spi1
clk_s
pi1_i
nv
clk_spi1_sel
Type RW
Reset 0
RW
l e
0
a P I - R 0
RW
0
RW
0
RW
0 0
RW
0 0
Bit(s) Name
Re Pi B Description
a
23 pdn_aud2dvd Turns off f_faud2dvd_ck
16 clk_aud2dvd_sel
n a n 1: Enable clock-off
Selects f_faud2dvd_ck clock mux
Ba
0: hf_fa1sys_hp_ck_d4
1: hf_fa2sys_hp_ck_d4
15 pdn_8bdac Turns off hf_f8bdac_ck
1: Enable clock-off
12 clk_8bdac_inv Inverts hf_f8bdac_ck clock phase
9:8 clk_8bdac_sel Selects hf_f8bdac_ck clock mux
0: clkrtc_int
1: f_8bdac_ck_pre
2: clk26m
3: clk26m
7 pdn_spi1 Turns off f_fspi1_ck
4 clk_spi1_inv
f r
1: Enable clock-off
o
Inverts f_fspi1_ck clock phase
2:0 clk_spi1_sel
e a s e
R 2
Selects f_fspi1_ck clock mux
I -
l
0: clk26m
Re Pi B P
1: syspll3_d2
2: syspll4_d2
3: univpll2_d4
4: univpll1_d8
a n a 5: clk26m
n
Ba
MT7623N
f o r
Bit(s) Name
e a s e
Description
I -
6: clk26m
R 2
l
Re Pi B P
7: clk26m
100000F4
CLK_CFG_15_S
ET
a n a
SET control of CLK_CFG_15 00000000
Bit
Name
Type
Reset
Bit
31
0
15
30 29
0 0
14 13
0
12Ba n
28 27 26 25 24 23 22 21
0
11
0
10
0
9
0
8
WO
0
7
0
6
0
5
20
0
4
19
0
3
18
0
2
17
0
1
16
0
0
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0: Unchanged
f o r
100000F8
CLK_CFG_15_C
LR
e a s e I - R
2 00000000
Bit
Name
Type
Reset 0
31 30 29
0 0 0 0
l
Re Pi B
0 0 0
P
28 27 26 25 24 23 22 21
WO
0 0 0
20
0
19
0
18
0
17
0
16
0
Bit
Name
15 14 13 12 11
a
10
n a 9 8 7 6
5 4 3 2 1 0
n
Type WO
Ba
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0: Unchanged

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8
f7
o r 6 5 4 3 2 1 0
Name
a s e
abist_clk_sel
e I - R 2 clk_
pad
mclk
clk_padmclk_se
l
Type
Reset 0 0 l
Re Pi B 0
RW
P 0 0 0
_inv
RW
0 0 0 0
a n a
n
B a
MT7623N
f o r
Bit(s) Name
13:8 abist_clk_sel
e a s e
Description
I - R 2
Selects f_fabist_ck clock mux (not glitch free)
l
Re Pi B P
01: AD_MAIN_H546M_CK
03: AD_MAIN_H218P4M_CK
a n a 05: AD_UNIV_624M_CK
06: AD_UNIV_416M_CK
n
07: AD_UNIV_249P6M_CK
Ba
09: AD_UNIV_48M_CK
10: AD_USB_48M_CK
11: AD_MMPLL_CK
12: AD_MSDCPLL_CK
13: AD_DPICLK
14: clkph_MCK_o
15: AD_MEMPLL2_CKOUT0_PRE_ISO
16: AD_HADDS2PLL_294M_CK
17: AD_AUD2PLL_270M_CK
18: AD_HDMI_RX_CK
19: AD_USB20_CLK480M
20: rtc32k_ck_i
21: AD_SYS_26M_CK
22: AD_VENCPLL_CK
f o r
23~32: Reserved
33: abist_clk1 (AD_MIPI_26M_CK)
e
34: abist_clk2 (AD_AUD1PLL_294M_CK)
l e a s - 2
35: abist_clk3 (AD_MEM_26M_CK)
R
36: abist_clk4 (AD_PLLGP_TST_CK)
I
37: abist_clk5 (AD_DSI0_LNTC_DSICLK)
Re Pi B P
38: abist_clk6 (AD_MPPLL_TST_CK)
39: abist_clk7 (armpll_occ_mon)
40: abist_clk8 (AD_MEM2MIPI_26M_CK)
41: abist_clk9 (AD_MEMPLL_MONCLK)
a n a 42: abist_clk10 (AD_MEMPLL2_MONCLK)

43: abist_clk11 (AD_MEMPLL3_MONCLK)
n
44: abist_clk12 (AD_MEMPLL4_MONCLK)
Ba
45: abist_clk13 (AD_MEMPLL2_REFCLK)
46: abist_clk14 (AD_MEMPLL2_FBCLK)
47: abist_clk15 (AD_BBDAC_BGCHOP_26M_CLK)
50: abist_clk18 (AD_ETHPLL_500M_CK)
51: abist_clk19 (AD_HADDS2_98M_CLK)
52: abist_clk20 (AD_HDMI_0_ABIST_300MCK)
53: abist_clk21 (AD_HDMIRX_26M_CLK)
54: abist_clk22 (AD_TVDPLL_CK)
55: abist_clk23 (AD_TVD2PLL_CK)
56: abist_clk24 (AD_HDMITX_MONCLK)
57: abist_clk25 (Reserved)
58: abist_clk26 (AD_TRMII_CK)
f r
o
61: abist_clk29 (AD_TVDPLL_CK)
4 clk_padmclk_inv
e a s e - 2
63: abist_clk31 (AD_LVDSPLL_ETH_CK)
R
Inverts hf_padmclk_ck clock phase
I
2:0 clk_padmclk_sel
l
Re Pi B P
select clk_padmclk clock mux
0: clk26m
1: univpll_d26
a n a
n
Ba
MT7623N
f o r
Bit(s) Name
e a s e
Description
I - R 2
2: univpll_d52
l
Re Pi B P
3: univpll_d108
4: univpll2_d8
5: univpll2_d16
6: univpll2_d32
a n a
10000104
Bit
Name
Type
31
CLK_CFG_9
30 29
Ba n
28 27 26 25 24 23 22 21 20 19
00000000
18 17 16
ckgen_clk_sel
RW
Reset 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset

21:16 ckgen_clk_sel Selects f_fckgen_ck clock mux (not glitch free)
r
01: hf_faxi_ck
o
02: hd_faxi_ck
s f
03: hf_fnfi2x_ck
e
04: hf_fddrphycfg_ck
2
05: hf_fmm_ck
l e a P I - R
06: f_fpwm_ck
07: hf_fvdec_ck
Re Pi B
08: hf_fmfg_ck
09: hf_fcamtg_ck
10: f_fuart_ck
11: hf_fspi0_ck
a n a 12: f_fusb20_ck
13: hf_fmsdc30_0_ck
Ba n 14: hf_fmsdc30_1_ck
15: hf_fmsdc30_2_ck
16: hf_faudio_ck
17: hf_faud_intbus_ck
18: hf_fpmicspi_ck
19: f_frtc_ck
20: f_f26m_ck
21: f_f32k_md1_ck
22: f_frtc_conn_ck
23: hf_feth_50m_ck
24: hf_emmc_hclk_ck
25: hd_haxi_nli_ck
26: hd_qaxidcm_ck
27: f_ffpc_ck
28: hf_fdpi0_ck
r
29: f_fckbus_ck_scan
o
30: f_fckrtc_ck_scan
s f
31: hf_fdpilvds_ck
e
32: hf_fflash_ck
2
33: hf_fdi_ck
l e a I - R
34: hf_fnr_ck
35: hf_fosd_ck
P
Re Pi B
36: hf_fhdmirx_bist_ck
37: hf_fa1sys_hp_ck
38: hf_fa2sys_hp_ck
39: hf_fi2s1_mclk
a n a
n
Ba
MT7623N
f o r
Bit(s) Name
e a s e
Description
I - R 2
40: hf_fi2s2_mclk
l
Re Pi B P
41: hf_fi2s3_mckj
42: hf_fi2s4_mclk
43: hf_fi2s5_mclk
44: hf_fi2s6_mclk
a
45: hf_fintdir_ck
n a n 46: hf_fasm_l_ck
47: hf_fasm_m_ck
48: hf_fasm_h_ck
Ba
49: hf_fhost_spi_ck
50: hf_fspi1_ck
51: hf_fspi2_ck
52: hf_fmsdc30_3_ck
53: hf_f8bdac_ck
10000108 CLK_CFG_10 Debug monitor clock selection register 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name clk_ckmon3_sel
Type RW
Reset 0 0 0 0
Bit
Name
Type
15 14 13 12 11 10 9
clk_ckmon2_sel
RW
8
f o r
7 6 5 4 3 2 1
clk_ckmon1_sel
RW
0
Reset 0 0
e
0
a s e0
I - R 2
0 0 0 0
Bit(s) Name
19:16 clk_ckmon3_sel
l
Re Pi B P
Description
Selects f_fckmon3_ck clock mux (not glitch free)
1: AD_SYS_26M_CK
2: rtc32k_ck_i
a n a 3: AD_WHPLL_2505P25M_CK (abist_clk_en = 1'b1)

4: AD_WPLL_245P76M_CK (abist_clk_en = 1'b1)
Ba n 5: AD_MDPLL1_416M_CK (abist_clk_en = 1'b1)

6: AD_MCUPLL1_H481M_CK (abist_clk_en = 1'b1)
7: clkph_MCLK_o
8: AD_DPICLK
9: AD_MSDCPLL_CK
10: AD_MMPLL_CK
13: AD_VENCPLL_CK
14: AD_LVDSPLL_CK
15: AD_LVDSPLL_ETH_CK
11:8 clk_ckmon2_sel Selects f_fckmon2_ck clock mux (not glitch free)
1: AD_SYS_26M_CK
2: rtc32k_ck_i
3: AD_WHPLL_2505P25M_CK (abist_clk_en = 1'b1)
f r
4: AD_WPLL_245P76M_CK (abist_clk_en = 1'b1)
o
5: AD_MDPLL1_416M_CK (abist_clk_en = 1'b1)
e a s e
8: AD_DPICLK
I - 2
7: clkph_MCLK_o
R
l
9: AD_MSDCPLL_CK
Re Pi B P
10: AD_MMPLL_CK
13: AD_VENCPLL_CK
a n a 14: AD_LVDSPLL_CK
n
Ba
MT7623N
f o r
Bit(s) Name
e a s e
Description
I - R 2
3:0 clk_ckmon1_sel
l
Re Pi B P
Selects f_fckmon1_ck clock mux (not glitch free)
1: AD_SYS_26M_CK
2: rtc32k_ck_i
3: AD_WHPLL_2505P25M_CK (abist_clk_en = 1'b1)
a n a 4: AD_WPLL_245P76M_CK (abist_clk_en = 1'b1)

5: AD_MDPLL1_416M_CK (abist_clk_en = 1'b1)
n
Ba
7: clkph_MCLK_o
8: AD_DPICLK
9: AD_MSDCPLL_CK
10: AD_MMPLL_CK
13: AD_VENCPLL_CK
14: AD_LVDSPLL_CK
1000010C CLK_CFG_11 Debug monitor divider control register 00000000
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
o
Name ckmon3_k1
Type
Reset
Bit 15 14 13 12 11 10 9
s e
8 f 0
7
0
2
6
0
5
0
4
RW
0
3
0
2
0
1
0
0
Name
Type
ckmon2_k1
RW
l e a P I - R ckmon1_k1
RW
Re Pi B
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

23:16 ckmon3_k1
a n a
n
15:8 ckmon2_k1
Ba
7:0 ckmon1_k1
10000120 CLK_AUDDIV_0 audio clock divider control register0 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name audio_a2sys_hp_k1 audio_a1sys_hp_k1
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name audio_ext2_k1 audio_ext1_k1
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
f o r
Description
31:24
23:16
audio_a2sys_hp_k1
audio_a1sys_hp_k1
e a s e I - 2
Divider setting of a2sys_hp_ck
R
divider setting of a1sys_hp_ck
15:8
7:0
audio_ext2_k1
audio_ext1_k1 l
Re Pi B P
divider setting of audio_ext2_div_ck
divider setting of audio_ext1_div_ck
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
10000124
Bit
Name
Type
31
audio_k4
RW
l
CLK_AUDDIV_1 audio clock divider control register1
Re Pi B
30 29 28 27 26 25
P
24 23 22 21 20 19
audio_k3
RW
18
00000000
17 16
a
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
Type
15 14 13 12 11
audio_k2
RW
n a n
10 9 8 7 6 5 4 3
audio_k1
RW
2 1 0
Ba
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31:24 audio_k4 divider setting of i2s4_mclk
10000128 CLK_AUDDIV_2 audio clock divider control register2 00000000

Bit
Name
31 30 29 28 27 26 25
f o
24
r 23 22 21 20 19 18 17 16
Type
Reset
Bit 15 14 13 12 11 10
e a s
9 e 8
I - R
7
2 6 5 4 3 2 1 0
Name
Type
Reset 0 0 0
audio_k6
0
RW
0 l
Re Pi B
0 0
P0 0 0 0
audio_k5
0
RW
0 0 0 0
Bit(s) Name
15:8 audio_k6
a n a Description
divider setting of i2s6_mclk
7:0 audio_k5
Ba n Divider setting of i2s5_mclk
1000012C CLK_AUDDIV_3 audio clock divider control register3 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
pdn_ pdn_ pdn_ pdn_ pdn_ pdn_ pdn_ pdn_ pdn_ pdn_ audi audi audi audi audi
Name aud2 aud1 i2s6_ i2s5_ i2s4_ i2s3_ i2s2_ i2s1_ a2sy a1sy o_k6 o_k5 o_k4 o_k3 o_k2
_apll _apll mclk mclk m m m m s_hp s_hp _src _src _src _src _src
_ref _ref _sel _sel _sel _sel _sel
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
audi
Name o_k1
_src
_sel
mux_sel mux_sel
f o r
aud2_apll_ref_ aud1_apll_ref_ audio_apll_mux audio_ck_mux2 audio_ck_mux1
_sel _sel _sel
Type RW
Reset 0 0
RW
0 0 0
e
RW
a s
0
e 0
I - R
0
2
RW
0 0 0
RW
0 0 0
RW
0 0
Bit(s) Name
30 pdn_aud2_apll_ref l
Re Pi B P
Description
Enable clock off
1: Enable aud2_apll_ref_ck off
a n a
n
Ba
MT7623N
f o r
Bit(s) Name
29 pdn_aud1_apll_ref
Description
e a s e
Enable clock off
I - R 2
28 pdn_i2s6_mclk l
Re Pi B
Enable clock off
P
1: Enable aud1_apll_ref_ck off
1: Enable i2s6_mclk off

27 pdn_i2s5_mclk
a
Enable clock off
a n
1: Enable hf_fi2s5_mclk off
26
25
pdn_i2s4_m
pdn_i2s3_m
Ba n
Enable clock off
Enable clock off
24 pdn_i2s2_m Enable clock off
23 pdn_i2s1_m Enable clock off
22 pdn_a2sys_hp Enable clock off
1: Enable hf_fa2sys_hp_ck off
21 pdn_a1sys_hp Enable clock off
1: Enable hf_fa1sys_hp_ck off
20 audio_k6_src_sel i2s6_mclk selection
f
0: audio_mux1_ck
o r
19 audio_k5_src_sel
a s e
1: audio_mux2_ck
i2s5_mclk selection
e I - R 2
l
0: audio_mux1_ck
18 audio_k4_src_sel
Re Pi B
1: audio_mux2_ck
P
i2s4_mclk selection
0: audio_mux1_ck
a
1: audio_mux2_ck
17 audio_k3_src_sel
n
i2s3_mclk_selection
n a
0: audio_mux1_ck
Ba
1: audio_mux2_ck
16 audio_k2_src_sel i2s2_mclk selection
0: audio_mux1_ck
1: audio_mux2_ck
15 audio_k1_src_sel i2s1_mclk selction
0: audio_mux1_ck
1: audio_mux2_ck
14:12 aud2_apll_ref_mux_ aud2_apll_ref_ck selection
sel 0: clk26m
1: ext_i2s1_mck
2: ext_i2s2_mck
3: ext_i2s3_mck
4: ext_i2s4_mck
5: ext_i2s5_mck
6: ext_i2s6_mck
f o r
e
11:9 aud1_apll_ref_mux_ aud1_apll_ref_ck selection
sel 0: clk26m
e a s
1: ext_i2s1_mck
l I - R 2
P
2: ext_i2s2_mck
Re Pi B
3: ext_i2s3_mck
4: ext_i2s4_mck
5: ext_i2s5_mck
a
6: ext_i2s6_mck
Ba
MT7623N
f o r
e a s e I - R 2
8:6 audio_apll_mux_sel audio_apll_mux_ck selection
l
Re Pi B
0: clk26m
P
n a
4: audio_ext1_div_ck
a
n
5:3 audio_ck_mux2_sel audio_mux2_ck selection
Ba
0: clk26m
2:0 audio_ck_mux1_sel audio_mux1_ck selection
0: clk26m
f o r
10000150
CLK_8BDAC_C
FG
a s e R 2
8bdac clock divider control register
e I -
00000033
Bit
Name
Type
Reset
31 30 29
l
Re Pi B P
28 27 26 25 24 23 22 21 20 19 18 17 16
a
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset 0 0 0 0 0
n a0n 0
Clk_8bdac_cfg
0
RW
0 0 1 1 0 0 1 1
Bit(s) Name
15:0 Clk_8bdac_cfg Ba Description
Divider setting of f_8bdac_ck
CLK_SCP_CFG
10000200 SCP control register 0 00000000
_0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
r
Reset
o
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
s e f 2
sc_
mac
_26
sc_c
onn_
32k_
sc_ sc_a
md_
32k_ rmck
sc_a sc_ sc_2
xick_ mem 6ck_
a R off_e _off_ off_e ck_o off_e
-
m_of off_e
e I
en n ff_en n
l
f_en n n
Type
Reset
Re Pi B P RW
0
RW
0
RW RW
0 0
RW RW RW
0 0 0
a n a
n
Ba
MT7623N
f o r
Bit(s) Name
9 sc_mac_26m_off_e
e a s e
Description
I - R 2
0: Disable scpsys clock-off control
7
n
sc_conn_32k_off_en
l
Re Pi B P
1: Enable scpsys clock-off control
a
5 sc_md_32k_off_en 0: Disable scpsys clock-off control
4 sc_armck_off_en
n a n 1: Enable scpsys clock-off control

Ba
2 sc_axick_off_en 0: Disable scpsys clock-off control
1 sc_memck_off_en 0: Disable scpsys clock-off control
0 sc_26ck_off_en 0: Disable scpsys clock-off control
CLK_SCP_CFG
10000204 SCP control register 1 00000000
_1
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
e f o 2
Bit 15 14 13
l
12
e a s 11
I - R
10 9 8 7 6 5 4
sc_a
3 2 1 0
sc_a
P
xick
Re Pi B
xick_ _26
Name dcm m_s
_dis el_e
_en n
Type
Reset
a n a RW
0
RW
0
Bit(s) Name
4
Ba
sc_axick_dcm_dis_e
n
n Description
0 sc_axick_26m_sel_ 0: Disable scpsys clock-off control
en 1: Enable scpsys clock-off control
CLK_MISC_CFG
10000210 Internal clk_rtc divider control register 5D3F0000
_0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
r
clkrt
o
Name c_int clkrtc_int_residual
Type
Reset
_en
RW
1 0 1 1 1
s e0f 1
2 0
RW
0 1 1 1 1 1 1
Bit
Name
15 14 13 12 11
l
10
e a 9
P I -
8
R 7 6 5 4 3 2 1 0
Re Pi B
Type
Reset
a n a
n
Ba
MT7623N
f o r
Bit(s) Name
30 clkrtc_int_en
e a s e
Description
I - R 2
Enable internal clkrtc
29:16 clkrtc_int_residual
l
Re Pi B P
Setting residual of internal clkrtc divider
Ex: 26M/32768 = 793.45703125
a n a
n
CLK_MISC_CFG
10000214 Frequency meter divider control register FF00FFFF
Ba
_1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name ckgen_k1
Type RW
Reset 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name arm_k1 abist_k1
Type RW RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

31:24 ckgen_k1 Divider setting of f_fckgen_ck
r
15:8 arm_k1 Divider setting of hf_farm_ck
7:0 abist_k1
f o
Divider setting of f_fabist_ck
e 2
l e a s I - R
P
10000220 CLK26CALI_0 Frequency meter control register 0 00000000
Bit
Name
Type
31 30 29
Re Pi B
28 27 26 25 24 23 22 21 20 19 18 17 16
Reset
Bit 15 14 13 12 11 10
a
9
n a 8 7 6 5 4 3 2 1 0
n fmet ckge ckge abist abist
Ba
Name er_e n_cl n_tri _clk_ pll_t _tri_
n k_ex _cal exc est cal
c
Reset 0 0 0 0 0 0

7 fmeter_en 0: Disable fmeter
1: Enable fmeter
5 ckgen_clk_exc Selects measuring clock
0: f_fckgen_ck
1: CLK26M
4 ckgen_tri_cal Triggers frequency meter on f_fckgen_ck.
o r
Auto-cleared when calibration is done.
f
0: Disable
e
1: Enable
2 abist_clk_exc
l e a s R 2
Selects measuring clock
I -
0: f_fabist_ck
1 pll_test
Re Pi B P
1: CLK26M
Selects clock divider test clock
0: PLL
a
1: Test clock (26MHz)
Ba
MT7623N
f o r
Bit(s) Name
0 abist_tri_cal
e a s e
Description
I - R 2
Triggers frequency meter on f_fabist_ck
l
Re Pi B P
Auto-cleaedr when calibration is done.
0: Disable
1: Enable
a n a
10000224
Bit
Name
Type
Reset
31 30 29
Ba n
CLK26CALI_1 Frequency meter control register 1
28 27 26 25 24 23 22 21 20
1 1 1 1
abist_load_cnt
1
RW
1
19
1
18
1
03FF0000
17 16
1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name cal_cnt
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

25:16 abist_load_cnt Set to 0x3FF if ABIST is used.
15:0 cal_cnt Frequency meter result of f_fabist_ck
o r
Frequency = (26MHz*cal_cnt)/1024
f
e a s e I - R 2
l
10000228 CLK26CALI_2 Frequency meter control register 2 03FF0000
Bit
Name
Type
31 30 29
Re Pi B P
28 27 26 25 24 23 22 21 20 19
ckgen_load_cnt
RW
18 17 16
a
Reset 1 1 1 1 1 1 1 1 1 1
n
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
n a ckgen_cal_cnt
RO
Ba
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

25:16 ckgen_load_cnt Set to 0x3FF if fmeter is used
15:0 ckgen_cal_cnt Frequency meter result of f_fckgen_ck
Frequency = (26MHz*cal_cnt)/1024
1000022C CKSTA_REG Function clock selection status register 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
r
Name
Type
Reset
Bit 15 14 13 12 11 10 9
e f
8 o 7
2
6 5 4 3 2 1 0
Name
l e a s I - R
chg_
sta
P
Type RU
Re Pi B
Reset 0
a n a
n
Ba
MT7623N
f o r
Bit(s) Name
0 chg_sta
e a s e
Description
I - R 2
Clock switches changing in progress
l
Re Pi B P
a
TEST_MODE_C
n
10000230 Test mode control register 00000200
FG
Bit 31 30 29
n a
28 27 26 25 24 23 22 21 20 19 18 17 16
Ba
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rg_c rg_c rg_c
onn_ onn_ onn_
top2 top1 top2
Name _test _test _test
_me _me
m_p m_p _pwr
d d _on
Type RW RW RW
Reset 0 0 1
r
11 rg_conn_top2_test_
mem_pd
e f o 2
mem_pd
l e a s I - R
pwr_on
Re Pi B P
1000030C
a n a
MBIST_CFG_1 Debug monitor selection register 1 00000000
Bit
Name
Type
Reset
Bit
31
15
30 29
14 13 12 Ba
11
n
28 27 26 25 24 23 22 21
10 9 8 7 6 5
20 19
4 3
18
2
17 16
1 0
Name ckgen_byte_sel
Type RW
Reset 0 0 0

6:4 ckgen_byte_sel Selects TOPCKGEN debugging monitor
10000310
RESET_DEGLIT
f o r
Reset deglitch enable key register FFFFFFFF
Bit 31
CH_KEY
30 29
a s
28 27 26 25 24 23 22 21
e e I - R 2 20 19 18 17 16
l
Name dgrst_en_key[31:16]
Type
Reset
Bit
Name
x
15
x
14 13
x x
12
x
11
Re Pi B
x
10
x
9 8
x
P
RW
x
7
x
6
dgrst_en_key[15:0]
x
5
x
4
x
3
x
2
x
1
x
0
Type
a n a RW
n
B a
MT7623N
f o r
Reset x x x x
e a s e x
I - R 2x x x x x x x x x x x
Bit(s) Name
31:0 dgrst_en_key l
Re Pi B P
Description
Write 0x67D2_A357 to enable reset deglitch.
a n a
10000314
Bit
Name
Type
Reset
31 30 29
Ba n
MBIST_CFG_3 Debug monitor selection register 3
28 27 26 25 24 23 22 21 20 19 18
00000000
17 16
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name usb_gpio_reg
Type RW
Reset 0 0 0 0 0 0 0 0

15:8 usb_gpio_reg Selects usb_i2c_mode
10000318 BOOT_TRAP Boot strap register

f o r 00000000
Bit
Name
31 30 29 28 27 26 25 24
e a s e I - R 2 23 22 21 20 19 18 17 16
Type
Reset
Bit
Name
15 14 13 12 11 10l
Re Pi B 9 8
P 7 6 5 4 3 2 1 0
Boot_stra
p
Type
Reset
a n a 0
RO
0
Bit(s) Name
1:0 Boot_strap
Ba n Description
Strapping boot
2.9 Programming Guide
2.9.1 Clock Off

 The clock can be turned on/off through changing the value of pdn_*. However, this control cannot
be switched along with clk_*_sel and clk_*_inv.
 It is recommended to
r
change pdn_* with SET and CLEAR function provided by
f o
CLK_CFG_*_SET and CLK_CFG_*_CLR. Because there may be clock with multi-bit pdn_*
CONNSYS) at the same time.
e a s e I - 2
which are planned to avoid read modify write from different sub-systems (APSYS, MDSYS and
R

l
Re Pi B P
SET and CLEAR function of CLK_CFG_* is a solution to avoid read modify write from different
sub-systems.
a n a
n
Ba
MT7623N
f o r
2.9.2 Clock Switching
e a s e I - R 2

l P
Make sure clock A and clock B are available before changing the setting of clk_*_sel. If switched
Re Pi B
to a non-exist clock, the clock switch will be stuck until non-exist clock is turned on to free the
clock switch.

a
Supports multi-clock switching at the same time (without changing pdn_*)
a n
1.
2.
n
Switching from clock A to clock B
Ba
Make sure clock B is ready.
Change clk_*_sel.
3. Wait until chg_sta = 1’b0 (optional).
4. Turn off clock A (optional).
2.9.3 Switch AXI to 26MHz by SCPSYS

The reflection time is about 17T 26MHz if all clocks are counted as 26MHz. Refer to the following
formula:
f o r
4T Bus Clock(*1) + 4T Current Clock(*2) + 5T Reference Clock(*3) + 1T Bus Clock(*4) + 3T Target Clock(*5)
a s
Comment
e e I - R 2 Description
l
Re Pi B
Bus clock
Ref clock
*1
P 26MHz (in current project)
26MHz, balance with bus clock
2T Sync + 1 T Control
*2
a n a 3T sync
Ba n
*3
*4
4T sync
1T control. For async CLKSW like
hf_fmem_ck used, it will be 2T
sync.
*5 2T sync
2.9.4 Frequency Meter

There are two frequency meters embedded inside TOPCKGEN.
1. Set fmeter_en to 1’b1.
f o r
2. Choose target clock by changing abist_clk_sel / ckgen_clk_sel.
3. Change abist_k1 / ckgen_k1 for dividing target clock (optional).
e a s e I - R 2
4. Change reference clock by changing clk_exec / ckgen_exec (optional).
l
5. Trigger frequency meter by set tri_cal / ckgen_tri_cal = 1b’1.
Re Pi B P
6. Wait until tri_cal / ckgen_tri_cal = 1’b0.
7. Read frequency meter result from cal_cnt / ckgen_cal_cnt.
a n a
n
Ba
MT7623N
f o r

s e R 2
freq(target) = (abist_k1 + 1)*[freq(reference clock)*cal_cnt]/1024
e a I -

l
freq(target) = (ckgen_k1 + 1)*[freq(reference clock)*ckgen_cal_cnt]/1024
Re Pi B P
2.10
n a
PLL Related Register Definition
a
10209000 Ba
AP_PLL_CON0
n
Module name: APMIXEDSYS Base address: (+10209000h)
Address Name Width

32 AP PLL Control Register 0
Register Function
10209004 AP_PLL_CON1 32 AP PLL Control Register 1

10209008 AP_PLL_CON2 32 AP PLL Control Register 2
10209014 PLL_HP_CON0 32 PLL Hopping Control Register 0
10209038 PLL_TEST_CON0 32 PLL Test Control Register 0
10209100 HDMI_CON0 32 HDMI control register 0
1020910C
10209110
HDMI_CON3
HDMI_CON4
f o r
32
32
HDMI control register 3
10209114
10209118
HDMI_CON5
HDMI_CON6
e a s e I
32
32
- R 2
l
1020911C HDMI_CON7 32 HDMI control register 7
10209120
10209200
10209204
HDMI_CON8
ARMPLL_CON0
ARMPLL_CON1 Re Pi B P 32
32
32
ARMPLL Control Register 0
ARMPLL Control Register 1
1020920C
ARMPLL_PWR_C
ON0
a n a 32 ARMPLL Power Control Register 0
10209210
10209214
1020921C
Ba
MAINPLL_CON0
MAINPLL_CON1
MAINPLL_PWR_
CON0
n 32
32
32
MAINPLL Control Register 0
MAINPLL Control Register 1
MAINPLL Power Control Register 0
10209220 UNIVPLL_CON0 32 UNIVPLL Control Register 0

10209224 UNIVPLL_CON1 32 UNIVPLL Control Register 1
UNIVPLL_PWR_
1020922C CON0 32 UNIVPLL Power Control Register 0
10209230 MMPLL_CON0 32 MMPLL Control Register 0

10209234 MMPLL_CON1 32 MMPLL Control Register 1
1020923C MMPLL_PWR_C 32 MMPLL Power Control Register 0

ON0
r
10209240 MSDCPLL_CON0 32 MSDCPLL Control Register 0
10209244 MSDCPLL_CON1
MSDCPLL_PWR_
e f o 32
2
MSDCPLL Control Register 1
s
1020924C CON0 32 MSDCPLL Power Control Register 0
10209250 TVDPLL_CON0
l e a P I -
32
R TVDPLL Control Register 0
Re Pi B
10209254 TVDPLL_CON1 32 TVDPLL Control Register 1
1020925C TVDPLL_PWR_C 32 TVDPLL Power Control Register 0

ON0
a
10209260 TVDPLL_SSC_C 32 TVDPLL SSC Control Register 0
Ba
MT7623N
f o r
ON0
TVDPLL_SSC_C
e a s e I - R 2
l
10209264 32 TVDPLL SSC Control Register 1
P
ON1
Re Pi B
10209270 AUD1PLL_CON0 32 AUD1PLL Control Register 0
10209274 AUD1PLL_CON1 32 AUD1PLL Control Register 1
a
1020927C AUD1PLL_PWR_ 32 AUDPLL Power Control Register 0
n
CON0
10209280 TRGPLL_CON0
n a 32 TRGPLL Control Register 0
Ba
10209284 TRGPLL_CON1 32 TRGPLL Control Register 1
TRGPLL_PWR_C
1020928C ON0 32 TRGPLL Power Control Register 0
10209290 ETHPLL_CON0 32 ETHPLL Control Register 0

10209294 ETHPLL_CON1 32 ETHPLL Control Register 1
1020929C ETHPLL_PWR_C 32 ETHPLL Power Control Register 0

ON0
102092A0 VDECPLL_CON0 32 VDECPLL Control Register 0
102092A4 VDECPLL_CON1 32 VDECPLL Control Register 1
VDECPLL_PWR_
102092AC CON0 32 VDECPLL Power Control Register 0
102092B0 HADDS2PLL_CO 32 HADDS2PLL Control Register 0
r
N0
102092B4
HADDS2PLL_CO
N1
e f o 32
2
HADDS2PLL Control Register 1
s
102092BC HADDS2PLL_PW 32 HADDS2PLL Power Control Register 0
a R
R_CON0
102092C0 AUD2PLL_CON0
l e P I -
32 AUD2PLL Control Register 0
Re Pi B
102092C4 AUD2PLL_CON1 32 AUD2PLL Control Register 1
AUD2PLL_PWR_
102092CC CON0 32 AUD2PLL Power Control Register 0
102092D0
102092D4
TVD2PLL_CON0
TVD2PLL_CON1
a n a 32
32
TVD2PLL Control Register 0
TVD2PLL Control Register 1
102092DC
102092F0
CON0
Ba
TVD2PLL_PWR_
TVD2PLL_SSC_C
ON0
n 32
32
TVD2PLL Power Control Register 0
TVD2PLL SSC Control Register 0
102092F4 TVD2PLL_SSC_C 32 TVD2PLL SSC Control Register 1

ON1
AP_AUXADC_CO
10209400 N0 32 AUXADC Control Register 0
10209404 AP_AUXADC_CO 32 AUXADC Control Register 1

N1
AP_AUXADC_CO
1020940C N2 32 AUXADC Control Register 2
10209600 TS_CON0 32 Thermal Sensor Control Register 0
r
10209604 TS_CON1 32 Thermal Sensor Control Register 1
1000F800
1000F804
VENCPLL_CON0
VENCPLL_CON1
e f o 32
32
2
VENCPLL Control Register 0
VENCPLL Control Register 1
1000F80C VENCPLL_PWR_
CON0
l e a s I -
32
R VENCPLL Power Control Register 0
Re Pi B P
a
10209000 AP_PLL_CON0 AP PLL Control Register 0 7E00E131
Ba
MT7623N
f o r
Bit 31 30 29 28
e a s e 27
I -
AP_D AP_D AP_D AP_D AP_D AP_D TVDP
R 2
26 25 24 23 22 21 20 19 18 17 16
Mne
Type
Reset
5
RW
1
4
RW
1
3
RW
1
2
l
Re Pi B
RW
1
1
RW
1
0
P
UMMY UMMY UMMY UMMY UMMY UMMY LL_RE
RW
1
F_SEL
RW
0
a
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
n a
AUD1 AUD2 HADD AUD1 AUD2
n
PLL_9 PLL_9 S2PLL PLL_R PLL_R
TVD2
PLL_R
RG_S
SUSB
MIPI_2 MEM_
6M_O 26M_
Mne 8M_E 0M_E _98M_ EF_SE EF_SE CLKSQ1_HYS_SEL EF_SE _SR_ UT_E OUT_
CLKS
Q1_M
RG_S
SUSB CLKS CLKS
_SR_ Q1_LP Q1_E
Ba
ON_E
DRIVE GATE F_EN N
N N EN L L L N EN N
R_EN _ENB
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 1 1 1 0 0 0 0 1 0 0 1 1 0 0 0 1
Bit(s) Mnemonic Name Description

30 AP_DUMMY AP_DUMMY5 set this dummy bit to 0.
5
4
3
27 AP_DUMMY AP_DUMMY2
2
f o r set this dummy bit to 0.
26 AP_DUMMY AP_DUMMY1
1
e a s e I - R 2
set this dummy bit to 0.
l
24
0
Re Pi B
TVDPLL_RE TVDPLL_REF_SEL
F_SEL
P
15
n
AUD1PLL_9 AUD1PLL_98M_EN
8M_EN
a a
14
13
0M_EN
n
AUD2PLL_9 AUD2PLL_90M_EN
Ba
HADDS2PLLHADDS2PLL_98M_
_98M_EN EN
12 AUD1PLL_R AUD1PLL_REF_SE
EF_SEL L
11 AUD2PLL_R AUD2PLL_REF_SE
EF_SEL L
10:8 CLKSQ1_HYCLKSQ1_HYS_SEL Clock square hysterisis level selection
S_SEL
7 TVD2PLL_R TVD2PLL_REF_SE
EF_SEL L
6 RG_SSUSB RG_SSUSB_SR_D
_SR_DRIVE RIVER_EN
R_EN
f o r
5
4
MIPI_26M_O MIPI_26M_OUT_E
UT_EN N
e a s e I - R
Enables MIPI 26MHz clock source
2
MEM_26M_ MEM_26M_OUT_E Enables DDR 26MHz clock source
3
OUT_EN N
l
Re Pi B P
CLKSQ1_M CLKSQ1_MON_EN Enables clock square monitor
ON_EN 0: Disable
a
1: Enable
Ba
MT7623N
f o r
Bit(s) Mnemonic Name
e a s e I - R 2
Description
l
2 RG_SSUSB RG_SSUSB_SR_G
1
_SR_GATE_ ATE_ENB
ENB
Re Pi B
CLKSQ1_LP CLKSQ1_LPF_EN
F_EN
P Enables clock square1 low-pass filter
0 CLKSQ1_ENCLKSQ1_EN
a n a Enables clock square1
10209004
Bit 31 30 Ba
29
n
AP_PLL_CON1 AP PLL Control Register 1
28 27 26 25 24 23 22 21 20 19 18
00FF03F3
17 16
UNIVP MAIN ARMP UNIVP MAIN ARMP
MMPL MMPL
LL_IS PLL_I LL_IS LL_P PLL_P LL_P
Name L_ISO
O_SE SO_S O_SE
L_PW
WR_S WR_S WR_S
_SEL R_SEL
L EL L EL EL EL
Reset 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAIN UNIVD MAIN CLKS CLKS
MMPL UNIVP ARMP
ABI_REF_CLK_DIV DIV_R IV_RS PLL_E Q1_LP Q1_E
Name L_EN_ LL_EN LL_EN
_SLE STB_ TB_S N_SE F_EN_ N_SE
SEL _SEL _SEL
r
SEL EL L SEL L
o
Reset 0 0
s e f0 1
2
1 1 1 1 1 1 1
Bit(s) Mnemonic
23
Name
MMPLL_ISO MMPLL_ISO_SEL
MMPLL ISO_EN control selection
Re Pi B
_SEL 0: Sleep control
1: Register control
22 UNIVPLL_IS UNIVPLL_ISO_SEL UNIVPLL ISO_EN control selection
O_SEL
a n a 0: Sleep control
1: Register control
21
20
O_SEL
Ba n
MAINPLL_IS MAINPLL_ISO_SEL MAINPLL ISO_EN control selection
0: Sleep control
1: Register control
ARMPLL_IS ARMPLL_ISO_SEL ARMPLL ISO_EN control selection
O_SEL 0: Sleep control
1: Register control
19 MMPLL_PW MMPLL_PWR_SEL MMPLL PWR_ON control selection
R_SEL 0: Sleep control
1: Register control
18 UNIVPLL_P UNIVPLL_PWR_SE UNIVPLL PWR_ON control selection
WR_SEL L 0: Sleep control
1: Register control
17 MAINPLL_P MAINPLL_PWR_S MAINPLL PWR_ON control selection
WR_SEL EL
f o r 0: Sleep control
1: Register control
16
WR_SEL L
e a s e I -
0: Sleep control
2
ARMPLL_P ARMPLL_PWR_SE ARMPLL PWR_ON control selection
R
l
1: Register control
Re Pi B
12:10 ABI_REF_C ABI_REF_CLK_DIV
LK_DIV_SL _SLE
E P
a
9 MAINDIV_R MAINDIV_RSTB_S MAINPLL DIV_RSTB control selection
Ba
MT7623N
f o r
Bit(s) Mnemonic
STB_SEL
Name
EL
e a s e I - R 2
Description
0: Sleep control
8
l
Re Pi B
UNIVDIV_RSUNIVDIV_RSTB_S
TB_SEL EL P
1: Register control
UNIVPLL DIV_RSTB control selection
0: Sleep control
1: Register control
7 MMPLL_EN MMPLL_EN_SEL
_SEL
a n a MMPLL enable control selection

0: Sleep control
Ba n
UNIVPLL_E UNIVPLL_EN_SEL
N_SEL
1: Register control
UNIVPLL enable control selection
0: Sleep control
1: Register control
5 MAINPLL_E MAINPLL_EN_SEL MAINPLL enable control selection
N_SEL 0: Sleep control
1: Register control
4 ARMPLL_E ARMPLL_EN_SEL ARMPLL enable control selection
N_SEL 0: Sleep control
1: Register control
1 CLKSQ1_LP CLKSQ1_LPF_EN_ CLKSQ LPF_EN control selection
F_EN_SEL SEL 0: Sleep control
1: Register control
0 CLKSQ1_ENCLKSQ1_EN_SEL
_SEL
f o r CLKSQ enable control selection

0: Sleep control
e a s e I - R 2
1: Register control
10209008
Bit 31 30 29
l
Re Pi B
28
P
AP_PLL_CON2 AP PLL Control Register 2
27 26 25 24 23 22 21 20 19 18
00000007
17 16
Name
Type
a n a
n
Reset
Ba
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNIVP MAIN ARMP
UNIVP MAIN ARMP
LL_O PLL_ LL_O
LL_O PLL_ LL_O
Name UT_O OUT_ UT_O
UT_O OUT_ UT_O
FF_SE OFF_ FF_SE
FF OFF FF
L SEL L
Reset 0 0 0 1 1 1

6 UNIVPLL_O UNIVPLL_OUT_OF UNIVPLL CG register control
UT_OFF F
5 MAINPLL_O MAINPLL_OUT_OF MAINPLL CG register control
r
UT_OFF F
4
UT_OFF F
e f o
ARMPLL_O ARMPLL_OUT_OF ARMPLL CG register control
2
2
UT_OFF_SE F_SEL
L
l a s
UNIVPLL_O UNIVPLL_OUT_OF UNIVPLL CG control selection
- R
0: Sleep control
e I
P
1: Register control
Re Pi B
1 MAINPLL_O MAINPLL_OUT_OF MAINPLL CG control selection
UT_OFF_SE F_SEL 0: Sleep control
L 1: Register control
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
Description
l
0 ARMPLL_O ARMPLL_OUT_OF ARMPLL CG control selection
UT_OFF_SE F_SEL
L
Re Pi B P
0: Sleep control
1: Register control
10209014
a n a
PLL_HP_CON0 PLL Hopping Control Register 0 00000000
Bit
Name
Type
Reset
31 30
Ba
29
n 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TVDP VENC MSDC MEMP MMPL MAIN ARMP
Name LL_HP PLL_H PLL_H LL_HP L_HP_ PLL_H LL_H
_EN P_EN P_EN _EN EN P_EN P_EN
Reset 0 0 0 0 0 0 0

6 TVDPLL_HP TVDPLL_HP_EN TVDPLL hopping control
r
_EN 0: Register control
5 VENCPLL_H VENCPLL_HP_EN
e f o 1: Hopping control
VENCPLL hopping control
2
s
P_EN 0: Register control
l e a P I - R 1: Hopping control
MSDCPLL_ MSDCPLL_HP_EN MSDCPLL hopping control
Re Pi B
HP_EN 0: Register control
1: Hopping control
3 MEMPLL_H MEMPLL_HP_EN MEMPLL hopping control
P_EN
a n a 0: Register control
1: Hopping control
2
1
_EN
Ba n
MMPLL_HP MMPLL_HP_EN
MAINPLL_H MAINPLL_HP_EN
MSDCPLL hopping control
0: Register control
1: Hopping control
MAINPLL hopping control
1: Hopping control
0 ARMPLL_H ARMPLL_HP_EN ARMPLL hopping control
1: Hopping control
PLL_TEST_CON
r
10209038 PLL Test Control Register 0 00C00000
o
0
Bit
Name
31 30 29 28 27
s e f 26
2
25 24 23 22 21 20
PLLGP_RESERVE
19 18 17 16
a R
Type RW
Reset
Bit 15 14 13 12
l e 11
P I
10
- 9 8
1
7
1
6 5
0 0
4
0 0
3 2
0
1
0
0
Re Pi B
PLLG PLLG PLLG PLLG PLLG
PLLDI PLLG
P_MO P_LVR PLLGP_TST_ P_TST P_A2 P_TST
Name V_TES PLLGP_TSTMUX P_TST
NREF OD_E SEL OD_E DCK_ CK_E
T _EN
a
_EN N N EN N
B a
MT7623N
f o r
Type
Reset
RW
0
RW
0
e a s e
RW
0
I - R0
2 RW
0 0 0
RW
0 0
RW
0
RW
0
RW
0
RW
0

23:16 PLLGP_RES PLLGP_RESERVE
l
a
ERVE
13 PLLDIV_TE PLLDIV_TEST
ST
n a n
Ba
12 PLLGP_MO PLLGP_MONREF_ FBK clock testing mode enable
NREF_EN EN
11 PLLGP_LVR PLLGP_LVROD_E Overdrive open drain LDO
OD_EN N
10:9 PLLGP_TST PLLGP_TST_SEL Test Mux Selection
_SEL
7:4 PLLGP_TST PLLGP_TSTMUX Test Mux Selection
MUX
3 PLLGP_TST PLLGP_TSTOD_E Enable open drain
OD_EN N
2 PLLGP_A2D PLLGP_A2DCK_E Enable frequency meter path
CK_EN N
r
1 PLLGP_TST PLLGP_TSTCK_EN PLL output clock testing mode enable
0
CK_EN
PLLGP_TST PLLGP_TST_EN
e f o Testing mode enable
2
s
_EN
l e a P I - R
10209100
Bit 31
HDMI_CON0
30 29 Re Pi B
28
27 26 25 24 23 22 21 20 19 18
0000000A
17 16
Name
Type
RG_HDMITX_EN_DRV
RW
a n a RG_HDMITX_EN_IMP
RW
RG_HDMITX_EN_PRED
RW
RG_HDMITX_EN_SLDO
RW
n
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Ba
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_H RG_H RG_H RG_H
DMITX DMITX DMITX DMITX RG_HDMITX
Name RG_HDMITX_EN_SER _EN_ _EN_S _EN_S _EN_S _SER_PASS_ RG_HDMITX_DRV_IBIAS
DIN_B ER_P ER_A ER_A SEL
IST EM BIST BEDG
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0

31:28 RG_HDMITX RG_HDMITX_EN_ enable TX DRV
_EN_DRV DRV 1'b0: disable
1'b1: enable
27:24 RG_HDMITX RG_HDMITX_EN_I enable TX IMP
_EN_IMP MP
f
1'b0: disable
o r
e
1'b1: enable
23:20 RG_HDMITX RG_HDMITX_EN_
_EN_PRED PRED
l e a s I - R 2
enable TX Predriver
1'b0: disable
P
1'b1: enable
Re Pi B
19:16 RG_HDMITX RG_HDMITX_EN_ enable TX SER2T1 LDO
_EN_SLDO SLDO 1'b0: disable
1'b1: enable
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
Description
l
15:12 RG_HDMITX RG_HDMITX_EN_ enable TX SER
11
_EN_SER SER
Re Pi B
RG_HDMITX RG_HDMITX_EN_ P 1'b0: disable
1'b1: enable
enable TX data bist gen to output random data
a
_EN_DIN_BI DIN_BIST 1'b0: disable
n
ST 1'b1: enable
10
n a
RG_HDMITX RG_HDMITX_EN_ enable TX SER Pre-ephasis path
Ba
_EN_SER_P SER_PEM 1'b0: disable
EM 1'b1: enable
9 RG_HDMITX RG_HDMITX_EN_ NC
_EN_SER_A SER_ABIST
BIST
8 RG_HDMITX RG_HDMITX_EN_ enable TX SER Abist edge detect
_EN_SER_A SER_ABEDG 1'b0: disable
BEDG 1'b1: enable
7:6 RG_HDMITX RG_HDMITX_SER select Predriver input from test_in
_SER_PASS _PASS_SEL [1]=1'b0: Predirver input from SER
_SEL [1]=1'b1: Predirver input from test_in
[0]=1'b0: test_in from PLL HR CLK
[0]=1'b1: test_in from mon_clk
5:0 RG_HDMITX RG_HDMITX_DRV
_DRV_IBIAS _IBIAS
f o r set TX DRV bias current

[5]: enable 0.5mA
e a s e I - R
[4]: enable 5mA
2
[3]: enable 8mA
[2]: enable 4mA
l
Re Pi B P
[1]: enable 2mA
[0]: enable 1mA
if IBIAS[5:0]=6'b111111, I=20.5mA
if IBIAS[5:0]=6'b001010, I=10mA
a n a
10209104
Bit 31
HDMI_CON1
30
Ba
29 n 28
27 26 25 24
RG_H RG_H RG_H
DMITX DMITX DMITX
23
RG_H
DMITX
22 21 20
RG_HDMITX
19 18
002C0000
17 16
Name RG_HDMITX_DRV_IMP _SER_ _SER_ _SER_ RG_HDMITX_PRED_IBIAS _CKLDO_LV

_PRE
BIST_ CLKDI DIN_S ROD
D_IMP
TOG G_INV EL
Reset 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_HDMITX
Name _SLDO_LVR RG_HDMITX_SER_DIN
OD
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0

f o r Description
31:26 RG_HDMITX RG_HDMITX_DRV
_DRV_IMP _IMP
e a s e I - R 2
set TX DRV impedance=4.2k/ ([4:0]+20x[5])
[5]: enable 4.2k/20
l
Re Pi B P
[4]: enable 4.2k/16
[3]: enable 4.2k/8
[2]: enable 4.2k/4
[1]: enable 4.2k/2
a
[0]: enable 4.2k/1
Ba
MT7623N
f o r
e a s e I - R 2
Description
if IMP[5:0]=6'b011100, DRV impedance=4.2k/28=150
25 RG_HDMITX RG_HDMITX_SER
_SER_BIST__BIST_TOG
TOG l
Re Pi B P set data toggle for ABIST
1'b0: disable
1'b1: enable
a
24 RG_HDMITX RG_HDMITX_SER set CLKDIG & CLKDIG_CTS same/invert phase to CK_ANAFF
_SER_CLKD _CLKDIG_INV
IG_INV
n a n 1'b0: same phase

1'b1: invert phase
Ba
23 RG_HDMITX RG_HDMITX_SER select SER data source
_SER_DIN_ _DIN_SEL 1'b0: from digital
SEL 1'b1: from RG_SER_DIN[9:0]
22 RG_HDMITX RG_HDMITX_PRE set Predriver impedance
_PRED_IMP D_IMP 1'b0: 200 ohm for <1.5Gbps
1'b1: 100 ohm for >1.5Gbps
***note for swing
(1)<1.5Gbps, set
PRED_IMP=1'b0
PRED_IBAS[3:0]=4'b1011
(1)>1.5Gbps, set
PRED_IMP=1'b1
r
21:18 RG_HDMITX RG_HDMITX_PRE set Predirver bias current
o
_PRED_IBIA D_IBIAS [3]: enable 0.5mA
S
s e f [2]: enable 4mA
2
[1]: enable 2mA
a R
[0]: enable 1mA
l e P I - if IBIAS[3:0]=4'b1011, current=3.5mA
***note for swing
Re Pi B
(1)<1.5Gbps, set
PRED_IMP=1'b0
a
(1)>1.5Gbps, set
n
PRED_IMP=1'b1
n a PRED_IBAS[3:0]=4'b1111
Ba
17:16 RG_HDMITX RG_HDMITX_CKL Clock LDO voltage boost
_CKLDO_LV DO_LVROD 2'b00: LDO=VCCK
ROD 2'b01: LDO=VCCK+50mV
2'b10: LDO=VCCK+50mV
15:14 RG_HDMITX RG_HDMITX_SLD SER2T1 LDO voltage boost
_SLDO_LVR O_LVROD 2'b00: LDO=VCCK
OD 2'b01: LDO=VCCK+50mV
13:4 RG_HDMITX RG_HDMITX_SER if RG_HDMITX_SER_DIN_SEL=1, SER 10 bit data comes from
_SER_DIN _DIN this register value
f o r
e
10209108 HDMI_CON2 HDMI control register 2 0007C000
Bit
Name
31 30 29 28
e a s
RG_HDMITX_SER_TEST_SEL
l
27
I - R 2
26 25 24 23 22 21 20 19
RG_HDMITX_DATA_CLKCH[9:2]
18 17 16
P
Type RW RW
Re Pi B
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_HDMITX RG_HDMITX RG_HDMITX RG_H RG_H RG_H RG_H RG_H RG_HDMITX RG_H RG_H RG_H
a
_DATA_CLK _MBIAS_LOI _MBIAS_LOX DMITX DMITX DMITX DMITX DMITX _TX_POSDIV DMITX DMITX DMITX
Ba
MT7623N
f o r
CH[1:0] BI
e a s e I
BI
- R 2 _EN_ _EN_ _MBIA _EN_ _TX_P

MBIA MBIA S_LPF MBIA OSDIV
_REF _EN_T _EN_T
EXT_S X_PO X_CK
l
S_LOI S_LO _EN S _SEL EL SDIV LDO
Type
Reset 1
RW
1 0
Re Pi B
RW
0
P
0
RW
0
RW
0
X
RW
0
RW
0
RW
0
RW
0 0
RW
0
RW
0
RW
0
RW
0
a n a Description
n
31:24 RG_HDMITX RG_HDMITX_SER
Ba
_SER_TEST _TEST_SEL
_SEL
23:14 RG_HDMITX RG_HDMITX_DATA PAD_CLK data from this register value
_DATA_CLK _CLKCH
CH
13:12 RG_HDMITX RG_HDMITX_MBIA set INTR local bias current
_MBIAS_LOIS_LOIBI 2'b00: 80uA
BI 2'b01: 100uA
2'b10: 100uA
2'b11: 133uA
11:10 RG_HDMITX RG_HDMITX_MBIA set EXTR local bias current
_MBIAS_LO S_LOXBI 2'b00: 80uA
XBI 2'b01: 100uA
r
2'b10: 100uA
9 RG_HDMITX RG_HDMITX_EN_
2'b11: 133uA
e f o 2
enable INTR current from local bias
s
_EN_MBIAS MBIAS_LOI 1'b0: disable
8
_LOI
RG_HDMITX RG_HDMITX_EN_
l e a P I - R 1'b1: enable
enable EXTR current from local bias
Re Pi B
_EN_MBIAS MBIAS_LOX 1'b0: disable
_LOX 1'b1: enable
7 RG_HDMITX RG_HDMITX_MBIA enable Mbias low-pass filter
_MBIAS_LP S_LPF_EN
F_EN
a n a
1'b0: disable
1'b1: enable
6
5
_EN_MBIAS MBIAS
Ba n
RG_HDMITX RG_HDMITX_EN_ enable Mbias current
1'b0: disable
1'b1: enable
RG_HDMITX RG_HDMITX_TX_P sel TX half-rate clock source
_TX_POSDI OSDIV_SEL 1'b0: from PLL/1
V_SEL 1'b1: from PLL/POSDDIV[1:0]
4:3 RG_HDMITX RG_HDMITX_TX_P TX half-rate post divider setting
_TX_POSDI OSDIV 2'b00: /1
V 2'b01: /2
2'b10: /4
2'b11: NC
2 RG_HDMITX RG_HDMITX_REF
_REFEXT_S EXT_SEL
r
EL
1
_EN_TX_PO X_POSDIV
e f o
RG_HDMITX RG_HDMITX_EN_T enable TX /5 circuit
1'b0: disable
2
s
SDIV 1'b1: enable
0
e a I - R
RG_HDMITX RG_HDMITX_EN_T enable TX half-rate clock LDO
_EN_TX_CK X_CKLDO
l P
Re Pi B
1'b0: disable
LDO 1'b1: enable
a n a
n
Ba
MT7623N
f o r
1020910C HDMI_CON3
e a s e R 2
I -
00000000
l
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RG_HDMITX RG_HDMITX
Name _TEST_DIV_ _TEST_SEL_
Re Pi B P
RG_HDMITX_TEST_EN
RG_H RG_H
DMITX DMITX
_SER_ _SER_
BIST_ EIN_S
RG_HDMITX_TEST_SEL
a
SEL TOP
TOG_ EL_C
Type
Reset 0
RW
0 0
n a
RW
n 0 0 0
RW
0 0
CKCH KCH
RW
0
RW
0 0 0 0
RW
0 0 0
Ba
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset

31:30 RG_HDMITX RG_HDMITX_TEST
_TEST_DIV_ _DIV_SEL
SEL
_TEST_SEL _SEL_TOP
_TOP
_TEST_EN _EN
f o r
e
_SER_BIST__BIST_TOG_CKCH
TOG_CKCH
l e a s I - R 2
P
Re Pi B
_SER_EIN_ _EIN_SEL_CKCH
SEL_CKCH
_TEST_SEL _SEL
a n a
10209110
Bit
Name
31
HDMI_CON4
30 Ba
29
n 28
27 26 25 24
RG_HDMITX_RESERVE[31:16]
23 22 21 20 19 18
00000000
17 16
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RG_HDMITX_RESERVE[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
r
31:0 RG_HDMITX RG_HDMITX_RES reserved
o
_RESERVE ERVE
s e f 2
10209114 HDMI_CON5
l e a P I - R
HDMI control register 5 00000000
Re Pi B
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RGS_
RGS_HDMITX_ABIST_51E RGS_HDMITX_ABIST_51L RGS_HDMITX_ABIST_21E
Name HDMI DG EV DG
a
TX_PL
Ba
MT7623N
f o r
UG_T
ST
e a s e I - R 2
l
Type RO RO RO RO
Reset
Bit
0
15 14
Name RGS_HDMITX_ABIST_21L
EV
13
Re Pi B
12
0
11
P 0
10
0
9
0
8
RGS_HDMITX_CAL_STATUS
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Type
Reset 0 0
RO
0
a n0
a 0 0 0 0
RO
0 0 0 0
Bit(s) Mnemonic
31
Ba
Name
n
RGS_HDMIT RGS_HDMITX_PL
X_PLUG_TS UG_TST
T
Description
Plug test result
0: RX disappear
1: RX plug in
27:24 RGS_HDMIT RGS_HDMITX_ABI ABIST 5T1SER edge test result
X_ABIST_51 ST_51EDG
EDG
23:20 RGS_HDMIT RGS_HDMITX_ABI ABIST 5T1SER level test result
X_ABIST_51 ST_51LEV
LEV
19:16 RGS_HDMIT RGS_HDMITX_ABI ABIST 2T1SER edge test result
X_ABIST_21 ST_21EDG
r
EDG
X_ABIST_21 ST_21LEV
e f o
15:12 RGS_HDMIT RGS_HDMITX_ABI ABIST 2T1SER level test result
2
s
LEV
11:4 RGS_HDMIT RGS_HDMITX_CA
X_CAL_STA L_STATUS
l e a P I - RCalibration status
0: fail
Re Pi B
TUS 1: success
10209118 HDMI_CON6
a n a HDMI control register 6 09040000

Bit 31
RG_H
Name TPLL_
EN
30
Ba
29
n 28 27
RG_HTPLL_FBKDIV
26 25 24
RG_H
23
TPLL_
DDSF
BK_E
RG_H
22 21 20 19
TPLL_ RG_HTPLL_ RG_HTPLL_ RG_HTPLL_

RLH_
EN
FBKSEL PREDIV POSDIV
18 17 16
N
Reset 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RG_HTPLL_ RG_HTPLL_
Name RG_HTPLL_IC RG_HTPLL_IR RG_HTPLL_BP
BC BR
Type RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 RG_HTPLL_ RG_HTPLL_EN
EN
f o r PLL Enable
1'b0: Disable
a s e - R
30:24 RG_HTPLL_ RG_HTPLL_FBKDI Feedback divide ratio
e I 2
1'b1: Enable
l
FBKDIV V
P
7'd0: /1
Re Pi B
7'd1: /2
7'd127: /128
23 RG_HTPLL_ RG_HTPLL_DDSF DDS Feedback Enable
DDSFBK_E BK_EN
a n a 1'b0: Disable
n
Ba
MT7623N
f o r
Bit(s) Mnemonic
N
Name
e a s e I - R 2
Description
1'b1: Enable
22
l
Re Pi B P
RG_HTPLL_ RG_HTPLL_RLH_E Feedback Relatch Enable
RLH_EN N 1'b0: Disable
1'b1: Enable
a
21:20 RG_HTPLL_ RG_HTPLL_FBKSE Feedback clock select
FBKSEL L
n a n
2'b00: VCO/1
2'b01: VCO/2
Ba
2'b1X: VCO/4
19:18 RG_HTPLL_ RG_HTPLL_PREDI Pre-divider ratio
PREDIV V 2'b00: /1
2'b01: /2
2'b1X: /4
17:16 RG_HTPLL_ RG_HTPLL_POSDI Post-divider ratio
POSDIV V 2'b00: /1
2'b01: /2
2'b10: /4
2'b11: Gating
15:12 RG_HTPLL_ RG_HTPLL_IC I-path current adjustment
IC MSB 5uA
5uA
r
2.5uA
11:8 RG_HTPLL_ RG_HTPLL_IR
e f o LSB 1.25uA
P-path current adjustment
2
s
IR MSB 40uA
l e a P I - R 20uA
10uA
Re Pi B
LSB 5uA
7:4 RG_HTPLL_ RG_HTPLL_BP P-path capacitance adjustment
BP MSB=1pF
a n a 0.5pF
0.25pF
LSB=125fF
3:2
BC
Ba n
RG_HTPLL_ RG_HTPLL_BC I-path capacitance adjustment
0:1pF
1:2pF
2:3pF
3:4pF
1:0 RG_HTPLL_ RG_HTPLL_BR P-path resistance adjustment
BR 2'b00:60kohm
2'b01:40kohm
2'b10:20kohm
2'b11:10kohm
1020911C
Bit 31
HDMI_CON7
30 29 28 27
f r
o26 25 24 23 22 21 20 19 18
8080000F
17 16
e
RG_H
s 2
RG_H
TPLL_
a R
RG_HTPLL_ RG_HTPLL_ TPLL_
-
Name AUTO RG_HTPLL_DIVEN AUTOK_KS AUTOK_KF AUTO RG_HTPLL_BAND
Type
Reset
Bit
K_LO
AD
RW
15
1 0
14
RW
0
13
0
12
0
11
RW
0
10
l
0
9
e
Re Pi B
RW
0
8
P
K_EN
RW
1
I 7
0
6 5
0 0
4
RW
0
3
0
2
0
1
0
0
a n a
Name RG_H RG_H RG_H RG_H RG_H RG_H RG_H RG_H RG_HTPLL_RESERVE
n
B a
MT7623N
f o r
a s e -
MONC MONV MONR VOD_ DET_ OSC_ BIAS_ BIAS_
e I 2
TPLL_ TPLL_ TPLL_ TPLL_ TPLL_ TPLL_ TPLL_ TPLL_
R
l
K_EN C_EN EF_E EN EN RST LPF_E EN
Type
Reset
RW
0
RW
0
N
RW
0
RW
0
Re Pi B
RW
0
RW
0
P N
RW
0
RW
0 0 0 0 0
RW
1 1 1 1
a n a Description
n
31 RG_HTPLL_ RG_HTPLL_AUTO Load Last-Time Auto K-Band Result
Ba
AUTOK_LO K_LOAD 1'b0: Load
AD 1'b1: Unload
30:28 RG_HTPLL_ RG_HTPLL_DIVEN Time domain cap multiplication ratio
DIVEN 3'd0: x1
3'd1: x2
3'd2: x4
...
3'd6: x64
27:26 RG_HTPLL_ RG_HTPLL_AUTO Auto K-Band Time Control
AUTOK_KS K_KS
25:24 RG_HTPLL_ RG_HTPLL_AUTO Auto K-Band Time Control
AUTOK_KF K_KF
23 RG_HTPLL_ RG_HTPLL_AUTO Auto K-Band Enable
AUTOK_EN K_EN
f o r 1'b0: Disable
1'b1: Enable
22:16 RG_HTPLL_ RG_HTPLL_BAND
BAND
e a s e I - R 2
Manual PLL Band Selection
6'b000001: Lowest Band
l
6'b111110: Highest Band
15
Re Pi B P
RG_HTPLL_ RG_HTPLL_MONC Monitor clock Enable
MONCK_EN K_EN 1'b0: Disable
1'b1: Enable
14
MONVC_EN C_EN
a n a
RG_HTPLL_ RG_HTPLL_MONV Monitor Vctrl Enable
1'b0: Disable
n
1'b1: Enable
Ba
13 RG_HTPLL_ RG_HTPLL_MONR Monitor reference Enable
MONREF_E EF_EN 1'b0: Disable
N 1'b1: Enable
12 RG_HTPLL_ RG_HTPLL_VOD_ CHP OverDrive Enable
VOD_EN EN (If AVDD12 > DVDD10 & use DVDD10 as LV reference TIE High,
else TIE Low)
1'b0: Disable
1'b1: Enable
11 RG_HTPLL_ RG_HTPLL_DET_E PLL WatchDog Enable
DET_EN N 1'b0: Disable
1'b1: Enable
10 RG_HTPLL_ RG_HTPLL_OSC_ Reset WatchDog Flag
OSC_RST RST
r
1'b0: Normal
o
1'b1: Reset
9 RG_HTPLL_ RG_HTPLL_BIAS_
BIAS_LPF_ LPF_EN
s e f Constant-Gm Bias LPF Enable
2
1'b0: Bypass LPF
a R
EN
-
1'b1: LPF Enable
8
7:0
RG_HTPLL_ RG_HTPLL_BIAS_
BIAS_EN EN
l e
Re Pi B
RG_HTPLL_ RG_HTPLL_RESE
P I Constant-Gm Bias Enable
1'b0:Disable
1'b1: Enable
Reserve
a n a
n
Ba
MT7623N
f o r
Bit(s) Mnemonic
RESERVE
Name
RVE
e a s e I - R 2
Description
l
Re Pi B P
a
10209120 HDMI_CON8 HDMI control register 8 00000000
Bit 31 30 29
n a n28 27 26 25 24 23
RGS_
22 21 20 19 18 17 16
Ba
HTPL
Name RGS_HTPLL_AUTOK_FAIL L_AU
TOK_
BAND
Type RO RO
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGS_
HTPL
Name L_AU
TOK_
PASS
Type RO
Reset 0

31:25 RGS_HTPLL RGS_HTPLL_AUT
f o r Description
ABIST 5T1SER level test result
23
_AUTOK_FA OK_FAIL
IL
RGS_HTPLL RGS_HTPLL_AUT
e a s e I - R 2
Plug test result
15
_AUTOK_B OK_BAND
AND
RGS_HTPLL RGS_HTPLL_AUT
l
Re Pi B P 0: RX disappear
1: RX plug in
ABIST 5T1SER edge test result
a
_AUTOK_PA OK_PASS
n
SS
n a
10209200
Bit
Name
Type
31 30 Ba
ARMPLL_CON0 ARMPLL Control Register 0
29 28 27 26 25 24 23 22 21 20 19 18
00000100
17 16
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARMP
ARMP
LL_SD
Name M_FR
LL_E
N
A_EN
Type RW RW
Reset 1 0
f o r Description
8
DM_FRA_E A_EN
N
e a e
0: Integer mode
I - 2
ARMPLL_S ARMPLL_SDM_FR Enables SDMPLL fractional mode
s R
l
1: Fractional mode
0 ARMPLL_E ARMPLL_EN
N
Re Pi B P Enables PLL
a n a
n
Ba
MT7623N
f o r
10209204
a s e R 2
ARMPLL_CON1 ARMPLL Control Register 1
e I -
800A8000
l
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARMP
LL_S
Name DM_P
CW_C
Re Pi B P ARMPLL_POSDIV ARMPLL_SDM_PCW[20:16]
Type
Reset
HG
RW
1
a n a 0
RW
0 0 0 1
RW
0 1 0
Bit
Name
Type
Reset
15
1
14
0
Ba
13
0
n 12
0
11
0
10
0
9 8
ARMPLL_SDM_PCW[15:0]
0 0
RW
0 0
7 6 5
0
4
0
3
0
2
0
1
0
0

31 ARMPLL_S ARMPLL_SDM_PC Feedback divide ratio update signal
DM_PCW_C W_CHG
HG
26:24 ARMPLL_P ARMPLL_POSDIV Post divide ratio
OSDIV 000: /1
001: /2
010: /4
r
011: /8
20:0
e f o 100: /16
ARMPLL_S ARMPLL_SDM_PC Feedback divide ratio
2
s
DM_PCW W
l e a P I - R
1020920C
ARMPLL_PWR_
CON0 Re Pi B
ARMPLL Power Control Register 0 00000002
Bit 31
ARMP
30 29
a n a
28 27 26 25 24 23 22 21 20 19 18 17 16
Type
Reset
LL_S
Name DM_P
WR_A
CK
RO
0
Ba n
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARMP
ARMP
LL_S
LL_SD
Name M_ISO
DM_P
WR_O
_EN
N
Type RW RW
Reset 1 0
r
31
f o
ARMPLL_S ARMPLL_SDM_PW ARMPLL power ack
DM_PWR_A R_ACK
e 2
s
CK
1 ARMPLL_S ARMPLL_SDM_IS
DM_ISO_EN O_EN
l e a P I - R Enables ARMPLL iso
Re Pi B
0 ARMPLL_S ARMPLL_SDM_PW ARMPLL power-on
DM_PWR_O R_ON
N
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
10209210
Bit 31 30 29 l
Re Pi B
28
MAIN MAIN MAIN MAIN
P
MAINPLL_CON0 MAINPLL Control Register 0
27 26 25 24
MAIN
23 22 21 20 19 18
78000110
17 16
Name
n a
PLL_D PLL_D PLL_D PLL_D
IV2_E IV3_E IV5_E IV7_E
a
PLL_D
IV_RS
n
N N N N TB
Ba
Type RW RW RW RW RW
Reset 1 1 1 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAIN
PLL_S MAIN
Name DM_F MAINPLL_POSDIV PLL_E
RA_E N
N
Type RW RW RW
Reset 1 0 0 1 0

30 MAINPLL_DIMAINPLL_DIV2_EN Enables MAINPLL DIV2
V2_EN
29
V3_EN
f o r
MAINPLL_DIMAINPLL_DIV3_EN Enables MAINPLL DIV3
28
V5_EN
e a e
MAINPLL_DIMAINPLL_DIV5_EN Enables MAINPLL DIV5
s I - R 2
l
27 MAINPLL_DIMAINPLL_DIV7_EN Enables MAINPLL DIV7
24
V7_EN
Re Pi B
MAINPLL_DIMAINPLL_DIV_RS
V_RSTB TB P PLL divider reset bar
0: Reset
a
1: Enable
8
DM_FRA_E A_EN
n a n
MAINPLL_S MAINPLL_SDM_FR Enables SDMPLL fractional mode
0: Integer mode
Ba
N 1: Fractional mode
6:4 MAINPLL_P MAINPLL_POSDIV Post divide ratio
OSDIV 000: /1
001: /2
010: /4
011: /8
100: /16
0 MAINPLL_E MAINPLL_EN Enables PLL
N
10209214 MAINPLL_CON1MAINPLL Control Register 1 80150000

Bit 31
MAIN
30 29 28 27
f o r 26 25 24 23 22 21 20 19 18 17 16
e
PLL_S
Name DM_P
CW_C
HG
l e a s I - R 2 MAINPLL_SDM_PCW[20:16]
Type
Reset
Bit
Name
RW
1
15 14 13
Re Pi B
12 P
11 10 9 8
MAINPLL_SDM_PCW[15:0]
7 6 5
1
4
0
3
RW
2
1 0
1 0
1
Type
a n a RW
n
Ba
MT7623N
f o r
Reset 0 0 0 0
e a s e 0
I - R 2
0 0 0 0 0 0 0 0 0 0 0
Bit(s) Mnemonic
31
Name
l
MAINPLL_S MAINPLL_SDM_PC Feedback divide ratio update signal
DM_PCW_C W_CHG
a
HG
20:0
DM_PCW W
n a n
MAINPLL_S MAINPLL_SDM_PC Feedback divide ratio
1020921C
_CON0
Ba
MAINPLL_PWR
MAINPLL Power Control Register 0 00000002
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAIN
PLL_S
Name DM_P
WR_A
CK
Type RO
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
f o r MAIN
PLL_S
MAIN
PLL_S
DM_P
e
DM_IS
s 2
WR_O
O_EN
a R
N
Type
Reset
l e P I - RW
1
RW
0

Re Pi B Description
31 MAINPLL_S MAINPLL_SDM_P
DM_PWR_A WR_ACK
CK
a n a MAINPLL power ack
0
DM_ISO_EN O_EN
Ba n
MAINPLL_S MAINPLL_SDM_IS
MAINPLL_S MAINPLL_SDM_P
DM_PWR_O WR_ON
Enables MAINPLL iso
MAINPLL power-on
10209220 UNIVPLL_CON0 UNIVPLL Control Register 0 FC000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UNIVP UNIVP
UNIVP UNIVP UNIVP UNIV4 USB4
LL_DI LL_DI
Name V2_E LL_DI LL_DI LL_DI 8M_E 8M_E V_RS
V3_EN V5_EN V7_EN N N
r
N TB
Type
Reset
Bit
RW
1
15
RW
1
14
RW
1
13
RW
1
RW
1
12
RW
1
e f
11
o 2
10 9
RW
0
8 7 6 5 4 3 2 1 0
Name
l e a s I - R
UNIVP
LL_SD
UNIVPLL_POSDIV
UNIVP
LL_E
P
M_FR
Re Pi B
N
A_EN
Type RW RW RW
Reset 0 0 0 0 0
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
Description
l
31 UNIVPLL_DI UNIVPLL_DIV2_EN Enables UNIVPLL DIV2
30
V2_EN
Re Pi B P
UNIVPLL_DI UNIVPLL_DIV3_EN Enables UNIVPLL DIV3
V3_EN
a
29 UNIVPLL_DI UNIVPLL_DIV5_EN Enables UNIVPLL DIV5
28
V5_EN
n a n
UNIVPLL_DI UNIVPLL_DIV7_EN Enables UNIVPLL DIV7
Ba
V7_EN
27 UNIV48M_E UNIV48M_EN Enables UNIV 48M clock
N
26 USB48M_ENUSB48M_EN Enables USB 48M clock
24 UNIVPLL_DI UNIVPLL_DIV_RST PLL divider reset bar
V_RSTB B 0: Reset
1: Enable
8 UNIVPLL_S UNIVPLL_SDM_FR Enables SDMPLL fractional mode
DM_FRA_E A_EN 0: Integer mode
6:4 UNIVPLL_P UNIVPLL_POSDIV Post divide ratio
OSDIV 000: /1
r
001: /2
e f o 010: /4
011: /8
2
100: /16
0 UNIVPLL_E UNIVPLL_EN
N
l e a s I - R Enables PLL
Re Pi B P
10209224
Bit 31 30 29
a a
UNIVPLL_CON1 UNIVPLL Control Register 1
n28 27 26 25 24 23 22 21 20 19 18
800C0000
17 16
Type
UNIVP
LL_S
Name DM_P
CW_C
HG
RW Ba n UNIVPLL_SDM_PCW[6:2]
RW
Reset 1 0 1 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNIVPLL_SD
Name M_PCW[1:0]
Type RW
Reset 0 0

31 UNIVPLL_S UNIVPLL_SDM_PC Feedback divide ratio update signal
DM_PCW_C W_CHG
HG
f o r
DM_PCW W
e a s e
20:14 UNIVPLL_S UNIVPLL_SDM_PC Feedback divide ratio
I - R 2
1020922C
UNIVPLL_PWR_
l
Re Pi B P
UNIVPLL Power Control Register 0 00000002
a
CON0
Ba
MT7623N
f o r
Bit 31
UNIVP
30 29 28
e a s e 27
I - R 2
26 25 24 23 22 21 20 19 18 17 16
l
LL_S
Name DM_P
Type
WR_A
CK
RO
Re Pi B P
a
Reset 0
Bit 15 14 13
n a n12 11 10 9 8 7 6 5 4 3 2 1
UNIVP
0
UNIVP
LL_S
Ba
LL_SD
Name DM_P
M_ISO
WR_O
_EN
N
Type RW RW
Reset 1 0

31 UNIVPLL_S UNIVPLL_SDM_P UNIVPLL power ack
DM_PWR_A WR_ACK
CK
1 UNIVPLL_S UNIVPLL_SDM_IS Enables UNIVPLL iso
DM_ISO_EN O_EN
r
0 UNIVPLL_S UNIVPLL_SDM_P UNIVPLL power-on
o
DM_PWR_O WR_ON
N
s e f 2
l e a P I - R
Re Pi B
10209230 MMPLL_CON0 MMPLL Control Register 0 00000120
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
a
Type
n
Reset
Bit 15 14 13
n a 12 11 10 9 8 7 6 5 4 3 2 1 0
Ba
MMPL
L_SD MMPL
Name M_FR
MMPLL_POSDIV
L_EN
A_EN
Type RW RW RW
Reset 1 0 1 0 0

8 MMPLL_SD MMPLL_SDM_FRA Enables SDMPLL fractional mode
M_FRA_EN _EN 0: Integer mode
1: Fractional mode
6:4 MMPLL_PO MMPLL_POSDIV Post divide ratio
SDIV 000: /1
r
001: /2
o
010: /4
s e f 011: /8
100: /16
2
a R
0 MMPLL_EN MMPLL_EN Enables PLL
l e P I -
10209234
Re Pi B
MMPLL_CON1 MMPLL Control Register 1 80134000
a n a
n
Ba
MT7623N
f o r
Bit 31
MMPL
30 29 28
e a s e27
I - R 2
26 25 24 23 22 21 20 19 18 17 16
l
L_SD
Name M_PC
Type
W_CH
G
RW
Re Pi B P MMPLL_SDM_PCW[20:16]
RW
a
Reset 1 1 0 0 1 1
Bit
Name
Type
15 14 13
n a n12 11 10 9 8
MMPLL_SDM_PCW[15:0]
7 6 5 4 3 2 1 0
Ba
RW
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 MMPLL_SD MMPLL_SDM_PC Feedback divide ratio update signal
M_PCW_CH W_CHG
G
20:0 MMPLL_SD MMPLL_SDM_PC Feedback divide ratio
M_PCW W
MMPLL_PWR_C
1020923C
Bit 31
ON0
30 29 28
f
27
o r
MMPLL Power Control Register 0
26 25 24 23 22 21 20 19 18
00000002
17 16
MMPL
L_SD
Name M_PW
e a s e I - R 2
Type
Reset
R_AC
K
RO
0
l
Re Pi B P
a
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
n
MMPL MMPL
a
L_SD L_SD
Name
n
M_ISO M_PW
Ba
_EN R_ON
Type RW RW
Reset 1 0

31 MMPLL_SD MMPLL_SDM_PW MMPLL power ack
M_PWR_AC R_ACK
K
1 MMPLL_SD MMPLL_SDM_ISO Enables MMPLL iso
M_ISO_EN _EN
0 MMPLL_SD MMPLL_SDM_PW MMPLL power-on
M_PWR_ON R_ON
f o r
10209240
MSDCPLL_CON
0
a s e R 2
MSDCPLL Control Register 0
e I -
00000120
Bit
Name
Type
Reset
31 30 29
l
Re Pi B
28
P
27 26 25 24 23 22 21 20 19 18 17 16
a
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Ba
MT7623N
f o r
e a s e I - R 2 MSDC
PLL_S MSDC
l
Name DM_F MSDCPLL_POSDIV PLL_E
Type
Reset
Re Pi B P RA_E
N
RW
1 0
RW
1 0
N
RW
0
a n a Description
8
6:4
EN
Ba n
MSDCPLL_ MSDCPLL_SDM_F Enables SDMPLL fractional mode
SDM_FRA_ RA_EN
MSDCPLL_ MSDCPLL_POSDI
0: Integer mode
1: Fractional mode
Post divide ratio
POSDIV V 000: /1
001: /2
010: /4
011: /8
100: /16
0 MSDCPLL_ MSDCPLL_EN Enables PLL
EN
10209244
MSDCPLL_CON
f o r
MSDCPLL Control Register 1 800F6276
e
1
Bit 31
MSDC
30 29
l
28
e a s 27
I - R 2
26 25 24 23 22 21 20 19 18 17 16
P
PLL_S
Re Pi B
Name DM_P MSDCPLL_SDM_PCW[20:16]
CW_C
HG
Type RW RW
Reset
Bit
1
15 14 13
a n a
12 11 10 9 8 7 6 5
0
4
1
3 2
1 1
1 0
1
n
Name MSDCPLL_SDM_PCW[15:0]
Ba
Type RW
Reset 0 1 1 0 0 0 1 0 0 1 1 1 0 1 1 0

31 MSDCPLL_ MSDCPLL_SDM_P Feedback divide ratio update signal
SDM_PCW_ CW_CHG
CHG
20:0 MSDCPLL_ MSDCPLL_SDM_P Feedback divide ratio
SDM_PCW CW
1020924C
MSDCPLL_PWR
_CON0
o r
MSDCPLL Power Control Register 0
f
00000002
Bit 31
MSDC
PLL_S
30 29 28
e a s e 27
I - R
26
2
25 24 23 22 21 20 19 18 17 16
l
Name DM_P
Type
Reset
WR_A
CK
RO
0
Re Pi B P
a n a
n
Ba
MT7623N
f o r
Bit 15 14 13 12
e a s e 11
I - R 2
10 9 8 7 6 5 4 3 2 1
MSDC
0
MSDC
l
PLL_S
P
PLL_S
Re Pi B
Name DM_P
DM_IS
WR_O
O_EN
N
Type RW RW
a
Reset 1 0
n a n Description
Ba
31 MSDCPLL_ MSDCPLL_SDM_P MSDCPLL power ack
SDM_PWR_ WR_ACK
ACK
1 MSDCPLL_ MSDCPLL_SDM_IS Enables MSDCPLL iso
SDM_ISO_E O_EN
N
0 MSDCPLL_ MSDCPLL_SDM_P MSDCPLL power-on
SDM_PWR_ WR_ON
ON
r
10209250 TVDPLL_CON0 TVDPLL Control Register 0 00000130
Bit
Name
31 30 29 28 27
e f o26
2
25 24 23 22 21 20 19 18 17 16
s
Type
Reset
Bit 15 14 13 12
l e a11
P I
10
- R 9 8 7 6 5 4 3 2 1 0
Re Pi B
TVDP
TVDP
LL_SD
Name M_FR
TVDPLL_POSDIV LL_E
N
A_EN
a
Type RW RW RW
Reset
n a n 1 0 1 1 0
Bit(s) Mnemonic
8
Name
B a
TVDPLL_SD TVDPLL_SDM_FR
M_FRA_EN A_EN
Description
Enables SDMPLL fractional mode
0: Integer mode
1: Fractional mode
6:4 TVDPLL_PO TVDPLL_POSDIV Post divide ratio
SDIV 000: /1
001: /2
010: /4
011: /8
100: /16
0 TVDPLL_EN TVDPLL_EN Enables PLL
f o r
e
10209254 TVDPLL_CON1 TVDPLL Control Register 1 800B6C4F
Bit
TVDP
31 30 29
l
28
e a s 27
I - R 2
26 25 24 23 22 21 20 19 18 17 16
P
LL_S
Re Pi B
Name DM_P TVDPLL_SDM_PCW[20:16]
CW_C
HG
Type RW RW
a n a
n
Ba
MT7623N
f o r
Reset
Bit
1
15 14 13 12
e a s e 11
I - R 2
10 9 8 7 6 5
0
4
1
3
0
2
1
1
1
0
l
Name TVDPLL_SDM_PCW[15:0]
Type
Reset 0 1 1
Re Pi B
0 1
P 1 0 0
RW
0 1 0 0 1 1 1 1
Bit(s) Mnemonic
31
Name
a
TVDPLL_SD TVDPLL_SDM_PC
n a Description
Feedback divide ratio update signal
20:0
M_PCW_CH W_CHG
G
Ba n
TVDPLL_SD TVDPLL_SDM_PC
M_PCW W
Feedback divide ratio
TVDPLL_PWR_
1020925C TVDPLL Power Control Register 0 00000002
CON0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TVDP
LL_S
Name DM_P
WR_A
Type
Reset
CK
RO
f o r
e
0
Bit 15 14 13
l
12
e a s
11
I - R 2
10 9 8 7 6 5 4 3 2 1
TVDP
0
TVDP
LL_S
P
LL_SD
Re Pi B
Name M_ISO
DM_P
WR_O
_EN
N
Type RW RW
a
Reset 1 0
n a n Description
Ba
31 TVDPLL_SD TVDPLL_SDM_PW TVDPLL power ack
M_PWR_AC R_ACK
K
1 TVDPLL_SD TVDPLL_SDM_ISO Enables TVDPLL iso
M_ISO_EN _EN
0 TVDPLL_SD TVDPLL_SDM_PW TVDPLL power-on
M_PWR_ON R_ON
TVDPLL_SSC_C
10209260 TVDPLL SSC Control Register 0 00020000
ON0
Bit 31 30 29 28 27
f o r 26 25 24 23 22 21 20 19 18 17 16
TVDP TVDP
e
LL_SD LL_S
Name
l e a s I - R 2 M_SS DM_S
C_PH SC_E
_INIT N
Re Pi B P
Type RW RW
Reset 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TVDPLL_SDM_SSC_PRD
a
Type RW
Ba
MT7623N
f o r
Reset 0 0 0 0
e a s e 0
I - R 2
0 0 0 0 0 0 0 0 0 0 0
Bit(s) Mnemonic
17
Name
l
Re Pi B
TVDPLL_SDM_SS
C_PH_INIT P Description
SDM SSC phase initial
1'b0: Upward
a
1'b1: Downward
16
a n
TVDPLL_SDM_SS
C_EN
n
SDM SSC enable
1'b0: Disable
Ba
1'b1: Enable
15:0 TVDPLL_SDM_SS SDM SSC period
C_PRD 16'd0: Min
16'd65536: Max
TVDPLL_SSC_C
10209264 TVDPLL SSC Control Register 1 00000000
ON1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TVDPLL_SDM_SSC_DELTA1
Type RW
Reset
r
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset 0 0 0 0
s e f
0
2
0
TVDPLL_SDM_SSC_DELTA
0 0
RW
0 0 0 0 0 0 0 0
l e a P I - R
Re Pi B
31:16 TVDPLL_SDM_SS SDM SSC amplitude 1
C_DELTA1 16'd0: Min
15:0
a n a
TVDPLL_SDM_SS
16'd65536: Max
SDM SSC amplitude
n
C_DELTA 16'd0: Min
Ba
16'd65536: Max
AUD1PLL_CON
10209270 AUD1PLL Control Register 0 00000140
0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUD1
PLL_S AUD1
Name
f o r DM_F
RA_E
N
AUD1PLL_POSDIV PLL_E
N
Type
Reset
e a s e I - R 2
RW
1 1
RW
0 0
RW
0
Bit(s) Mnemonic
8
Name
AUD1PLL_S AUD1PLL_SDM_F
DM_FRA_E RA_EN
l
0: Integer mode
N
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
Description
1: Fractional mode
6:4
l
Re Pi B P
AUD1PLL_P AUD1PLL_POSDIV Post divide ratio
OSDIV 000: /1
001: /2
010: /4
a n a
011: /8
100: /16
0
N
Ba n
AUD1PLL_E AUD1PLL_EN Enables PLL
AUD1PLL_CON
10209274 AUD1PLL Control Register 1 BC7EA932
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AUD1
PLL_S
Name DM_P AUD1PLL_SDM_PCW[30:16]
CW_C
HG
Type RW RW
r
Reset 1 0 1 1 1 1 0 0 0 1 1 1 1 1 1 0
Bit
Name
15 14 13 12
e f
11
o 10
2
9 8
AUD1PLL_SDM_PCW[15:0]
7 6 5 4 3 2 1 0
s
Type RW
a R
Reset 1 0 1 0 1 0 0 1 0 0 1 1 0 0 1 0
l e P I -
Re Pi B
31 AUD1PLL_S AUD1PLL_SDM_P Feedback divide ratio update signal
DM_PCW_C CW_CHG
30:0
HG
a
AUD1PLL_S AUD1PLL_SDM_P
n a Feedback divide ratio
DM_PCW CW
Ba
AUD1PLL_PWR
n
1020927C AUDPLL Power Control Register 0 00000002
_CON0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AUDP
LL_S
Name DM_P
WR_A
CK
Type RO
Reset 0
r
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
o
AUD1
f
AUD1
PLL_S
e
PLL_S
Name DM_P
s 2
DM_IS
WR_O
a R
O_EN
-
N
Type
Reset

l e
Re Pi B P I Description
RW
1
RW
0
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
Description
l
31 AUDPLL_SDAUDPLL_SDM_PW AUD1PLL power ack
1
M_PWR_AC R_ACK
K
Re Pi B P
AUD1PLL_S AUD1PLL_SDM_IS Enables AUD1PLL iso
DM_ISO_EN O_EN
0 AUD1PLL_S AUD1PLL_SDM_P
DM_PWR_O WR_ON
a n a AUD1PLL power-on
Ba n
10209280 TRGPLL_CON0 TRGPLL Control Register 0 00000110
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGP
TRGP
LL_SD
Name M_FR
TRGPLL_POSDIV LL_E
N
A_EN
r
Type RW RW RW
o
Reset 1 0 0 1 0
s e f 2
Description
8 TRGPLL_SD TRGPLL_SDM_FR
l e a P I - R Enables SDMPLL fractional mode
Re Pi B
M_FRA_EN A_EN 0: Integer mode
1: Fractional mode
6:4 TRGPLL_POTRGPLL_POSDIV Post divide ratio
a
SDIV 000: /1
n a n 001: /2
010: /4
011: /8
Ba
100: /16
0 TRGPLL_EN TRGPLL_EN Enables PLL
10209284 TRGPLL_CON1 TRGPLL Control Register 1 B7C4EC4F

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRGP
LL_S
Name DM_P TRGPLL_SDM_PCW[30:16]
CW_C
HG
Type RW RW
Reset
Bit
1
15
0
14
1
13
1
12
0
f
11
o r 1
10
1
9
1
8
1
7
1
6
0
5
0
4
0
3
1
2
0
1
0
0
e
Name TRGPLL_SDM_PCW[15:0]
Type
Reset 1 1 1
l
0
e a s 1
I - R 2
1 0 0
RW
0 1 0 0 1 1 1 1
Bit(s) Mnemonic
31
Name
TRGPLL_SD TRGPLL_SDM_PC Feedback divide ratio update signal
M_PCW_CH W_CHG
a n a
n
Ba
MT7623N
f o r
Bit(s) Mnemonic
G
Name
e a s e I - R 2
Description
30:0
l
Re Pi B P
TRGPLL_SD TRGPLL_SDM_PC Feedback divide ratio
M_PCW W
TRGPLL_PWR_
a n a
1020928C
Bit 31
TRGP
LL_S
CON0
30
Ba
29 n
TRGPLL Power Control Register 0
28 27 26 25 24 23 22 21 20 19 18
00000002
17 16
Name DM_P
WR_A
CK
Type RO
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGP
TRGP
LL_S
LL_SD
Name M_ISO
DM_P
WR_O
_EN
N
r
Type RW RW
Reset
e f o 2
1 0
Bit(s) Mnemonic
31
Name
l e a s I -
TRGPLL_SD TRGPLL_SDM_PW TRGPLL power ack
R
Description
1
M_PWR_AC R_ACK
K
Re Pi B P
TRGPLL_SD TRGPLL_SDM_ISO Enables TRGPLL iso
a
M_ISO_EN _EN
0
M_PWR_ON R_ON
n a n
TRGPLL_SD TRGPLL_SDM_PW TRGPLL power-on
10209290
Bit
Name
31 30
Ba
ETHPLL_CON0 ETHPLL Control Register 0
29 28 27 26 25 24 23 22 21 20 19 18
00000120
17 16
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETHP
ETHP
LL_SD
Name ETHPLL_POSDIV LL_E
M_FR
N
A_EN
Type RW RW RW
r
Reset 1 0 1 0 0
e f o 2
Description
8 ETHPLL_SD ETHPLL_SDM_FR
M_FRA_EN A_EN
l e a s I - R Enables SDMPLL fractional mode

0: Integer mode
6:4
Re Pi B
ETHPLL_PO ETHPLL_POSDIV
SDIV P 1: Fractional mode
Post divide ratio
000: /1
a n a 001: /2
n
Ba
MT7623N
f o r
e a s e I - R 2
Description
010: /4
0 ETHPLL_EN ETHPLL_EN l
Re Pi B P
011: /8
100: /16
Enables PLL
a n a
10209294
Bit 31
ETHP
LL_S
Name DM_P
30
Ba
29
n
ETHPLL_CON1 ETHPLL Control Register 1
28 27 26 25 24 23
ETHPLL_SDM_PCW[30:16]
22 21 20 19 18
CCEC4EC5
17 16
CW_C
HG
Type RW RW
Reset 1 1 0 0 1 1 0 0 1 1 1 0 1 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ETHPLL_SDM_PCW[15:0]
Type RW
Reset 0 1 0 0 1 1 1 0 1 1 0 0 0 1 0 1
Bit(s) Mnemonic
31
Name
ETHPLL_SD ETHPLL_SDM_PC
f o r Description
e
M_PCW_CH W_CHG
30:0
G
ETHPLL_SD ETHPLL_SDM_PC
l e a s I - R 2
Feedback divide ratio
P
M_PCW W
Re Pi B
1020929C
ETHPLL_PWR_
CON0
n a
ETHPLL Power Control Register 0
a
00000002
Bit 31
ETHP
LL_S
Name DM_P
WR_A
30
Ba
29
n 28 27 26 25 24 23 22 21 20 19 18 17 16
CK
Type RO
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETHP
ETHP
LL_S
LL_SD
Name DM_P
M_ISO
WR_O
_EN
N
Type RW RW
Reset 1 0
f o r
e
31
a s
ETHPLL_SD ETHPLL_SDM_PW PLL power ack
M_PWR_AC R_ACK
l e I - R 2
P
K
Re Pi B
1 ETHPLL_SD ETHPLL_SDM_ISO Enables PLL iso
M_ISO_EN _EN
a
0 ETHPLL_SD ETHPLL_SDM_PW PLL power-on
Ba
MT7623N
f o r
M_PWR_ON R_ON
e a s e I - R 2
Description
l
Re Pi B P
a
VDECPLL_CON
102092A0 VDECPLL Control Register 0 00000120
Bit 31
0
30 29
n a n28 27 26 25 24 23 22 21 20 19 18 17 16
Ba
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VDEC
PLL_S VDEC
Name DM_F VDECPLL_POSDIV PLL_E
RA_E N
N
Type RW RW RW
Reset 1 0 1 0 0

8 VDECPLL_S VDECPLL_SDM_F Enables SDMPLL fractional mode
DM_FRA_E RA_EN
N
f o r 0: Integer mode
1: Fractional mode
6:4
OSDIV
e a e
VDECPLL_P VDECPLL_POSDIV Post divide ratio
s
000: /1
001: /2
I - R 2
0 VDECPLL_E VDECPLL_EN
l
Re Pi B
010: /4
011: /8
100: /16 P Enables PLL
N
a n a
102092A4
1 Ba
VDECPLL_CON n
VDECPLL Control Register 1 B4000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VDEC
PLL_S
Name DM_P VDECPLL_SDM_PCW[30:16]
CW_C
HG
Type RW RW
Reset 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name VDECPLL_SDM_PCW[15:0]
Type
r
RW
o
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
s e f 2
Description
31 VDECPLL_S VDECPLL_SDM_P
DM_PCW_C CW_CHG
l e a P I - R Feedback divide ratio update signal
Re Pi B
HG
30:0 VDECPLL_S VDECPLL_SDM_P Feedback divide ratio
DM_PCW CW
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
102092AC
Bit 31
VDECPLL_PWR
_CON0
30 29
l
Re Pi B
28
P
VDECPLL Power Control Register 0
27 26 25 24 23 22 21 20 19 18
00000002
17 16
VDEC
PLL_S
a n a
n
Name DM_P
Ba
WR_A
CK
Type RO
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VDEC
VDEC
PLL_S
PLL_S
Name DM_P
DM_IS
WR_O
O_EN
N
Type RW RW
Reset 1 0

DM_PWR_A WR_ACK
CK
f o r PLL power ack
1
DM_ISO_EN O_EN
e a s e
VDECPLL_S VDECPLL_SDM_IS Enables PLL iso
I - R 2
DM_PWR_O WR_ON
N l
Re Pi B P
PLL power-on
a n a
102092B0
Bit
Name
Type
31
HADDS2PLL_C
ON0
30
Ba
29 n
28 27 26 25 24 23 22 21 20 19 18
00000120
17 16
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HADD
S2PLL HADD
HADDS2PLL_POSD
Name _SDM
IV
S2PLL
_FRA_ _EN
EN
Type RW RW RW
Reset 1 0 1 0 0
f o r Description
e
8 HADDS2PLLHADDS2PLL_SDM Enables SDMPLL fractional mode
_SDM_FRA_ _FRA_EN
EN
l e s
0: Integer mode
a I - R
1: Fractional mode
2
P
6:4 HADDS2PLLHADDS2PLL_POS Post divide ratio
Re Pi B
_POSDIV DIV 000: /1
001: /2
010: /4
a
011: /8
Ba
MT7623N
f o r
e a s e I - R 2
Description
100: /16
0 HADDS2PLLHADDS2PLL_EN
_EN
l
Re Pi B P Enables PLL
HADDS2PLL_C
a n a
102092B4
Bit 31
HADD
S2PLL
ON1
30
Ba
29 n
28 27 26 25 24 23 22 21 20 19 18
AD5EFEE6
17 16
Name _SDM HADDS2PLL_SDM_PCW[30:16]

_PCW
_CHG
Type RW RW
Reset 1 0 1 0 1 1 0 1 0 1 0 1 1 1 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name HADDS2PLL_SDM_PCW[15:0]
Type RW
Reset 1 1 1 1 1 1 1 0 1 1 1 0 0 1 1 0
Bit(s) Mnemonic
31
Name
f o r Description
HADDS2PLLHADDS2PLL_SDM Feedback divide ratio update signal
30:0
_SDM_PCW _PCW_CHG
_CHG
e a s e I - R 2
HADDS2PLLHADDS2PLL_SDM Feedback divide ratio
_SDM_PCW _PCW
l
Re Pi B P
102092BC
HADDS2PLL_P
WR_CON0
a n a
HADDS2PLL Power Control Register 0 00000002
Bit 31
HADD
S2PLL
Name _SDM
_PWR
30
Ba
29
n 28 27 26 25 24 23 22 21 20 19 18 17 16
_ACK
Type RO
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HADD HADD
S2PLL S2PLL
Name _SDM _SDM
_ISO_ _PWR
EN _ON
Type RW RW
r
Reset 1 0
e f o Description
2
31
_SDM_PWR _PWR_ACK
l e a s
HADDS2PLLHADDS2PLL_SDM PLL power ack
I - R
1
_ACK
Re Pi B P
HADDS2PLLHADDS2PLL_SDM Enables PLL iso
_SDM_ISO_ _ISO_EN
EN
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
Description
l
0 HADDS2PLLHADDS2PLL_SDM PLL power-on
_SDM_PWR _PWR_ON
_ON
Re Pi B P
AUD2PLL_CON
a n a
102092C0
Bit
Name
Type
Reset
31
0
30
Ba
29
n
AUD2PLL Control Register 0
28 27 26 25 24 23 22 21 20 19 18
00000120
17 16
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUD2
PLL_S AUD2
Name DM_F AUD2PLL_POSDIV PLL_E
RA_E N
N
Type RW RW RW
Reset 1 0 1 0 0
Bit(s) Mnemonic
8
Name
AUD2PLL_S AUD2PLL_SDM_F
f o r Description
e
DM_FRA_E RA_EN 0: Integer mode
6:4
N
e a s I - R
AUD2PLL_P AUD2PLL_POSDIV Post divide ratio
l 2
1: Fractional mode
OSDIV
Re Pi B
000: /1
001: /2
010: /4
011: /8
P
0 AUD2PLL_E AUD2PLL_EN
a n a
100: /16
Enables PLL
N
Ba
AUD2PLL_CON
n
102092C4 AUD2PLL Control Register 1 A9AF46FD
1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AUD2
PLL_S
Name DM_P AUD2PLL_SDM_PCW[30:16]
CW_C
HG
Type RW RW
Reset 1 0 1 0 1 0 0 1 1 0 1 0 1 1 1 1
r
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
o
Name AUD2PLL_SDM_PCW[15:0]
Type
Reset 0 1 0 0
s e f
0 1
2
1 0
RW
1 1 1 1 1 1 0 1
Re Pi B
31 AUD2PLL_S AUD2PLL_SDM_P Feedback divide ratio update signal
DM_PCW_C CW_CHG
HG
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
Description
l
30:0 AUD2PLL_S AUD2PLL_SDM_P Feedback divide ratio
DM_PCW CW
Re Pi B P
102092CC
AUD2PLL_PWR
_CON0
a n a
AUD2PLL Power Control Register 0 00000002
Bit 31
AUD2
PLL_S
Name DM_P
WR_A
30
Ba
29
n 28 27 26 25 24 23 22 21 20 19 18 17 16
CK
Type RO
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUD2
AUD2
PLL_S
PLL_S
Name DM_IS
DM_P
WR_O
O_EN
N
Type RW RW
r
Reset 1 0
e f o Description
2
31 AUD2PLL_S AUD2PLL_SDM_P
DM_PWR_A WR_ACK
l e a s I - R
AUD2PLL power ack
1
CK
Re Pi B P
AUD2PLL_S AUD2PLL_SDM_IS Enables AUD2PLL iso
DM_ISO_EN O_EN
a
0 AUD2PLL_S AUD2PLL_SDM_P AUD2PLL power-on
n
DM_PWR_O WR_ON
N
n a
102092D0
Bit
Name
31 30
Ba
TVD2PLL_CON0 TVD2PLL Control Register 0
29 28 27 26 25 24 23 22 21 20 19 18
00000120
17 16
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TVD2
PLL_S TVD2
Name DM_F TVD2PLL_POSDIV PLL_E
RA_E N
N
r
Type RW RW RW
o
Reset 1 0 1 0 0
s e f 2
Description
8
e a I - R
TVD2PLL_S TVD2PLL_SDM_FR Enables SDMPLL fractional mode
l P
Re Pi B
DM_FRA_E A_EN 0: Integer mode
6:4 TVD2PLL_P TVD2PLL_POSDIV Post divide ratio
a
OSDIV 000: /1
Ba
MT7623N
f o r
e a s e I - R 2
Description
001: /2
0 TVD2PLL_E TVD2PLL_EN
l
Re Pi B P
010: /4
011: /8
100: /16
Enables PLL
N
a n a
102092D4
Bit 31 30 Ba
29
n
TVD2PLL_CON1TVD2PLL Control Register 1
28 27 26 25 24 23 22 21 20 19 18
800B6C4F
17 16
TVD2
PLL_S
Name DM_P TVD2PLL_SDM_PCW[20:16]
CW_C
HG
Type RW RW
Reset 1 0 1 0 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TVD2PLL_SDM_PCW[15:0]
Type RW
Reset 0 1 1 0 1 1 0 0 0 1 0 0 1 1 1 1

f o r Description
31 TVD2PLL_S TVD2PLL_SDM_P
DM_PCW_C CW_CHG
e a s e I - R 2
l
HG
20:0
Re Pi B
TVD2PLL_S TVD2PLL_SDM_P
DM_PCW CW
P Feedback divide ratio
a n a
102092DC
Bit 31
TVD2
PLL_S
TVD2PLL_PWR
_CON0
30
Ba
29 n
TVD2PLL Power Control Register 0
28 27 26 25 24 23 22 21 20 19 18
00000002
17 16
Name DM_P
WR_A
CK
Type RO
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TVD2
TVD2
PLL_S
PLL_S
Name DM_IS
DM_P
WR_O
O_EN
r
N
o
Type RW RW
Reset
s e f 2
1 0
Bit(s) Mnemonic
31
Name
TVD2PLL_S TVD2PLL_SDM_P
TVD2PLL power ack
Re Pi B
DM_PWR_A WR_ACK
CK
1 TVD2PLL_S TVD2PLL_SDM_IS Enables TVD2PLL iso
a n a
n
Ba
MT7623N
f o r
DM_ISO_EN O_EN
e a s e I - R 2
Description
0 TVD2PLL_S TVD2PLL_SDM_P
DM_PWR_O WR_ON
N l
Re Pi B P TVD2PLL power-on
a n a
102092F0
Bit 31
CON0
30
Ba
TVD2PLL_SSC_
29
n
TVD2PLL SSC Control Register 0
28 27 26 25 24 23 22 21 20 19 18
00020000
17 16
TVD2 TVD2
PLL_S PLL_S
Name DM_S DM_S
SC_P SC_E
H_INIT N
Type RW RW
Reset 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TVD2PLL_SDM_SSC_PRD
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
f o r Description
17
C_PH_INIT
e a s e
TVD2PLL_SDM_SS SDM SSC phase initial
I - R
1'b0: Upward
2
1'b1: Downward
16
l
Re Pi B P
TVD2PLL_SDM_SS SDM SSC enable
C_EN 1'b0: Disable
1'b1: Enable
a
15:0 TVD2PLL_SDM_SS SDM SSC period
n
C_PRD 16'd0: Min
n a 16'd65536: Max
102092F4
CON1
Ba
TVD2PLL_SSC_
TVD2PLL SSC Control Register 1 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TVD2PLL_SDM_SSC_DELTA1
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TVD2PLL_SDM_SSC_DELTA
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
f o r Description
31:16
C_DELTA1
e a e
16'd0: Min
I - 2
TVD2PLL_SDM_SS SDM SSC amplitude 1
s R
16'd65536: Max
15:0
l
Re Pi B P
TVD2PLL_SDM_SS SDM SSC amplitude
C_DELTA 16'd0: Min
16'd65536: Max
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
10209400
Bit
Name
31
AP_AUXADC_C
ON0
30 29 l
Re Pi B
28
AUXADC_RSV
27P
AUXADC Control Register 0
26 25 24 23 22 21 20 19 18
00008800
17 16
Type
Reset
Bit
0
15
0
14
0
13
a n
0
12a
RW
0
11
0
10
0
9
0
8 7 6 5 4 3 2 1 0
Name
Type
AUXADC_DUALY
RW Ba n AUXADC_DUALX
RW
AUXA
DC_PI
RQ_R
ES
RW
AUXADC_CALI
RW
Reset 1 0 0 0 1 0 0 0 0 0 0 0 0

31:24 AUXADC_R AUXADC_RSV Reserved register
SV
15:12 AUXADC_D AUXADC_DUALY Reserved
UALY
11:8 AUXADC_D AUXADC_DUALX Reserved
r
UALX
4 AUXADC_PI AUXADC_PIRQ_R
RQ_RES ES
e f o PENIRQ pull-high resistance

0: 55K
2
3:0 AUXADC_C AUXADC_CALI
l e a s I - R
1: 90K
ADC core bias current calibration
P
ALI
Re Pi B
0000: 1X
0001: 1.25X
0010: 1.5X
0011: 1.75X
a n a 0100: 2X
1000: 1X
1001: 0.8X
Ba n 1010: 0.67X
1011: 0.57X
1100: 0.5X
AP_AUXADC_C
10209404 AUXADC Control Register 1 00000000
ON1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
AUXA
o
DC_R
Name
s e f 2
TP_DI
SABL
E
a R
Type
-
RW
e I
Reset
l
0
Bit(s) Mnemonic
0
Name
Re Pi B
AUXADC_R AUXADC_RTP_DIS Disables RTP
P Description
a n a
n
Ba
MT7623N
f o r
TP_DISABL ABLE
e a s e I - R 2
Description
l
Re Pi B P
1020940C
AP_AUXADC_C
ON2
a n a
AUXADC Control Register 2 00004000
Bit
Name
31 30
Ba
29
n 28 27 26 25 24 23 22 21 20 19
AUXA
18
DC_8
BDAC
AUXA
DC_H
DMIR
17
X_TES
16
AUXA
DC_B
UF_P
_TEST WDB
T
Type RW RW RW
Reset 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUXA
AUXA AUXA AUXA AUXA AUXA AUXA AUXA AUXA AUXA AUXA AUXA
DC_B AUXA
DC_V DC_G DC_G DC_G DC_G DC_G DC_G DC_G DC_G DC_G DC_G
Name UF_B AUXADC_CUR_SEL DC_F DAC_ PI9_E PI8_E PI7_E PI6_E PI5_E PI4_E PI3_E PI2_E PI1_E PI0_E
UFMO S
TEST N N N N N N N N N N
DE
Reset
r
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
e f o Description
2
18
TEST
l e a
AUXADC_8BDAC_
s I - R
17
16
Re Pi B
AUXADC_HDMIRX
_TEST
AUXADC_BUF_PW P
a
DB
15
FMODE
n a n
AUXADC_BUF_BU
Ba
14:12 AUXADC_CUR_SE
L
11 AUXADC_FS
10 AUXADC_VDAC_T
EST
9 AUXADC_GPI9_EN PAD_AUX_IN9 scan in function enable
1: enalbe
0: disable
1: enalbe
0: disable
f o r
1: enalbe
0: disable
e
l e a s1: enalbe
I -
0: disable
R 2
5
4 Re Pi B P
AUXADC_GPI5_EN PAD_AUX_IN5 scan in function enable
1: enalbe
0: disable
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
Description
1: enalbe
3
l
Re Pi B P
0: disable
1: enalbe
0: disable
2
n a
a 1: enalbe
Ba n 0: disable
1: enalbe
0: disable
1: enalbe
0: disable
10209600 TS_CON0 Thermal Sensor Control Register 0 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
r
Name BGR_RSV BGR_TCTRL
o
Type RW RW
Reset
Bit
0
15
0
14
0
13
0
12
0
11
s e f 0
10
2
0
9
0
8
0
7
0
6 5
0 0
4
0
3
BGR_
0
2
0
1
0
0
a R
BGR_ BGR_
-
BGR_ BGR_ UNCH
e I
Name BGR_CTRL BGR_RSEL TS2AUXADC FSET UNCH
l
UGB BUFIN OP_P
P
UP OP
Re Pi B
H
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
a n a Description
n
31:24 BGR_RSV BGR_RSV RG_BGR_RSV[7:1]: Reserved register
23:16 BGR_TCTR BGR_TCTRL

L
B a RG_BGR_RSV[0]: Enable VBGR output to PAD_TESTIIN
1: Enable
0: Disable
BGR_TCTRL[1:0]: BGR Replica VBE TSensor chopping control
00: Unchop, PH = 0
01: Unchop, PH = 1
10: Chop
11: Disable
The current for VBE TSensor is also as the reference of calibrating
VBE TSensor for 00/01/10 mode.
By setting RG_BGR_CTRL[3]=1 and RG_BGR_TCTRL[1:0]=11,the
current source of calibrating VBE can be applied externally (drawn
from PD_TESTIIN).
f o r BGR_TCTRL[3:2]: PAD_TSOUT output selection

00: Disable TSOUT
e
01: IPTAT_OUT (for VBE calibration)
l e a s I - R 2
10: VBE_MCU
11: VBE_ABB
Re Pi B P RG_BGR_TCTRL[7:4]: IPTAT VBE TSensor current selection

0000: 100000000 for 1I calibrating VBE
a n a 0011: 000100000 for 1I calibrating VBE
n
Ba
MT7623N
f o r
e a s e I - R 2
Description
l
Re Pi B P
a
n a n 1010: 000111000 for 3I calibrating VBE

Ba
15:12 BGR_CTRL BGR_CTRL RG_BGR_CTRL[2:0]: BGR resistor selection for denomerator
RG_BGR_CTRL[3]: Enable test current input
1: Enable test current. In this mode, PAD_TESTIIN is used for
applying calibrating VBE TSensor current. (see
RG_BGR_TCTRL[1:0].)
0: Disable test current
11:8 BGR_RSEL BGR_RSEL BGR resistor selection for numerator
7:6 TS2AUXAD TS2AUXADC Enables output buffer and selects TS output to AUXADC
C 00: Buffer on, TSMCU to AUXADC
01: Buffer on, TSABB to AUXADC
10: Buffer on, VBGR to AUXADC
11: Buffer off
r
4 BGR_UGB BGR_UGB BGR VBUFFER force unity gain mode
e f o 0: Disable
1: Enable
2
3 BGR_BUFIN BGR_BUFIN
l e a s I - R
BGR VBUFFER external input mode
0: Disable
P
1: Enable
Re Pi B
2 BGR_FSET BGR_FSETUP BGR fast setup control
UP 0: Disable resistor in low pass filter, speed up settling
1: Enable low pass filter
1
n a
BGR_UNCH BGR_UNCHOP_PH Selects BGR unchop mode phase
OP_PH
a
0
OP
Ba
BGR_UNCH BGR_UNCHOP
n BGR unchop mode

0: Chop
1: Unchop
10209604 TS_CON1 Thermal Sensor Control Register 1 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name VBE_SEL
Type
r
RW
o
Reset 0 0 0
s e f 2
Description
2:0 VBE_SEL VBE_SEL
l e a P I - R VBE selection
Re Pi B
a
1000F800 VENCPLL_CON VENCPLL Control Register 0 00000120
Ba
MT7623N
f o r
Bit 31
0
30 29
e
28
a s e 27
I - R 2
26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13
l
Re Pi B
12 P
11 10 9 8 7 6 5 4 3 2 1 0
a
VENC
VENC VENC VENC
n
PLL_S VENC
a
PLL_ PLL_ PLL_L
Name DM_F VENCPLL_POSDIV PLL_E
n
MONV MONC VROD
RA_E N
Ba
C_EN K_EN _EN
N
Reset 0 0 0 1 0 1 0 0

11 VENCPLL_ VENCPLL_MONVC
MONVC_EN _EN
10 VENCPLL_MONCK
_EN
9 VENCPLL_LVROD
_EN
8 VENCPLL_S VENCPLL_SDM_F Enables SDMPLL fractional mode
r
DM_FRA_E RA_EN 0: Integer mode
6:4
N
e f o
VENCPLL_P VENCPLL_POSDIV Post divide ratio
2
1: Fractional mode
OSDIV
l e s
000: /1
a
001: /2
I - R
P
010: /4
Re Pi B
011: /8
100: /16
0 VENCPLL_E VENCPLL_EN Enables PLL
N
a n a
1000F804
VENCPLL_CON
1
Ba n
VENCPLL Control Register 1 800B6000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VENC
PLL_
Name N_INF VENCPLL_N_INFO[20:16]
O_CH
G
Type RW RW
Reset 1 0 1 0 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name VENCPLL_N_INFO[15:0]
Type RW
Reset 0 1 1 0
f
0
o r 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Mnemonic
31
Name
a s e - R 2
Description
VENCPLL_N VENCPLL_N_INFO Feedback divide ratio update signal
e I
l
_INFO_CHG _CHG
20:0
Re Pi B P
VENCPLL_N VENCPLL_N_INFO Feedback divide ratio
_INFO
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
1000F80C
Bit 31
VENC
VENCPLL_PWR
_CON0
30 29 l
Re Pi B
28 P
VENCPLL Power Control Register 0
27 26 25 24 23 22 21 20 19 18
00000002
17 16
PLL_S
Name DM_P
WR_A
a n a
Type
Reset
Bit
CK
RO
0
15 14
Ba
13
n 12 11 10 9 8 7 6 5 4 3 2 1
VENC
0
VENC
PLL_S
PLL_S
Name DM_P
DM_IS
WR_O
O_EN
N
Type RW RW
Reset 1 0

31 VENCPLL_S VENCPLL_SDM_P VENCPLL power ack
r
DM_PWR_A WR_ACK
o
CK
1
DM_ISO_EN O_EN
s e f
VENCPLL_S VENCPLL_SDM_IS Enables VENCPLL iso
2
0 VENCPLL_S VENCPLL_SDM_P
DM_PWR_O WR_ON
l e a P I - R VENCPLL power-on
Re Pi B
N
a n a
Ba n
f o r
e a s e I - R 2
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
3 Top Reset Generate Unit
e a s e I - R 2
3.1 Introduction
l
Re Pi B P
a n a
The top reset generator unit (TOPRGU) generates reset signals and distributes to each system. A
3.2 Feature list Ba n

watchdog timer is also included in this module.
 Hardware reset signals for the whole chip

 Software controllable reset for each system (except for infrastructure and apmixedsys system)
 Watchdog timer
 Reset output signals for companion chips
3.3 Block Diagram
f o r
CHIP
e a s e - R 2
Top Reset Generation Unit
I
SYSRSTB l
Re Pi B P IRQ irq
a n a
Ba n
DEBUGSYS
SCPSYS Mixer grst_b
Thermal WATCHDOG
WDT
f o r PMIC
e a s e I - R 2
RESET_B
Figure 3-1: Block diagram of top reset generation unit

SYSRST_B
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
10007000 WDT_MODE
l
Re Pi B P
Module name: TOPRGU Base address: (+10007000h)
Address Name Width
32
Register function
Watchdog mode register (will not be reset)
10007004 WDT_LENGTH
a n a 32 Watchdog counter setting register
n
10007008 WDT_RESTART 32 Watchdog counter restart register
Ba
1000700C WDT_STA 32 Watchdog status register (will not be reset)
10007010 WDT_INTERVAL 32 Watchdog reset pulse width register
10007014 WDT_SWRST 32 Software watchdog reset register
10007018 WDT_SWSYSRST 32 System software reset register
10007030 WDT_REQ_MODE 32 Reset request mode register (will not be reset)
10007034 WDT_REQ_IRQ_EN 32 Reset request IRQ enable register (will not be reset)
10007040 WDT_DEBUG_CTL 32 Debug control register (will not be reset)
WDT_INTERCORE_
10007050 32 Register for intercore sync
SYNC
r
WDT_INTERCORE_
o
10007054 32 Set control of register for intercore sync
f
SYNC_SET
10007058
WDT_INTERCORE_
SYNC_CLR
e a s e I - R 2 32 Clear control of register for intercore sync
Address Name l
Re Pi B P
Module name: TOPRGU_2ND Base address: (+10000000h)
Width Register function
10000310
RESET_DEGLITCH_
KEY
a n a 32 Reset deglitch enable key register
10007000 WDT_MODE
Ba n Watchdog Mode Register (will not be reset) 2200004D
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name unlock_key
Type WO
Reset 0 0 1 0 0 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ddr_re
dual_ irq_lvl wdt_ir wdt_e
Name serve_ exten extpol
mode _en q n
mode
Reset 0 1 0 1 1 0 1
Bit(s) Name
f o r
Description
31:24
7
unlock_key
ddr_reserve_mode
e a s e I - R 2
Write 0x22 to unlock the write protection of this register
Enables ddr_reserve_mode
l
0: Disable
6 dual_mode
Re Pi B P
1: Enable
Enables dual_mode
Turn on watchdog timer and enable the correspondent irq_en and wdt_en if
a n a
n
Ba
MT7623N
f o r
Bit(s) Name
e a s e
Description
I - R 2
dual_mode is used.
5 irq_lvl_en
l
Re Pi B P
0: Disable
1: Enable
Selects IRQ type
a
0: Edge (32K)
3 wdt_irq
n a n 1: Level
Enables watchdog timer IRQ
Ba
0: Trigger reset
1: Trigger IRQ
2 exten Enables watchdog output reset signal
0: Disable
1: Enable
1 extpol Watchdog output reset signal polarity
0: Active low
1: Active high
0 wdt_en Enables watchdog timer
0: Disable
1: Enable
f o r
10007004
Bit
Name
31 30 29 28
e a s e
WDT_LENGTH Watchdog Counter Setting Register
27
I - R 2
26 25 24 23 22 21 20 19 18
0000FFE8
17 16
Type
Reset
Bit
Name
15 14 13 l
Re Pi B
12
P
11 10
wdt_length
9 8 7 6 5 4 3 2
unlock_key
1 0
a
Type RW WO
Reset 1 1 1
n a n 1 1 1 1 1 1 1 1 0 1 0 0 0
Ba
15:5 wdt_length Watchdog time-out counter setting
The counter is restarted with {wdt_length [10:0], 1_1111_1111b}, and
therefore the watchdog timer time-out period is multiple of 512*T32k=15.6ms.
4:0 unlock_key Write 0x8 to unlock the write protection of this register
10007008 WDT_RESTART Watchdog Counter Restart Register 00001971

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11
f o r
10 9 8 7 6 5 4 3 2 1 0
e
Name wdt_restart
Type
Reset 0 0 0 1
l e a1
s I
0
- R 2 0 1
WO
0 1 1 1 0 0 0 1
Bit(s)
15:0
Name
wdt_restart
Re Pi B P
Description
Write 0x1971 to reset the watchdog time-out counter
a n a
n
B a
MT7623N
f o r
e a s e I - R 2
1000700C
Bit 31
WDT_STA
30
Name hw_w sw_w irq_as
dt_rst dt_rst sert
29
l
Re Pi B
28
Watchdog Status Register (will not be reset)
27
P 26 25 24 23 22 21 20 19
debug
_rst
18
00000000
17 16
a
Type RO RO RO RO
n
Reset 0 0 0 0
Bit 15 14 13
n a 12 11 10 9 8 7 6 5 4 3 2 1
spm_
0
Ba
therm
Name wdt_r
al_rst
st
Type RO RO
Reset 0 0
B Name Description
i
t
(
s
)
3 hw_wdt_rst Indicates hardware watchdog generated reset is asserted
1
3
0
sw_wdt_rst
f o r Indicates software watchdog generated reset is asserted
2
9
irq_assert
e a s e I - R 2
Indicates IRQ is asserted instead of reset
1
0
9
debug_rst
spm_wdt_rst
thermal_rst
l
Re Pi B P
Indicates debug generated reset is asserted
Indicates scpsys time-out generated reset is asserted

Indicates thermal generated by scpsys reset is asserted
a n a
10007010
Bit
Name
31 30
Ba
29
n
WDT_INTERVAL Watchdog Reset Pulse Width Register
28 27 26 25 24 23 22 21 20 19 18
00000FFF
17 16
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name wdt_reset_interval
Type RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1

Resets pulse width generated by watchdog
r
11:0 wdt_reset_interval
Needs 2T 32K for TD modem. Unit: 1T=1x32kHz
e f o 2
10007014 WDT_SWRST
l e a s I - R
Software Watchdog Reset Register 00001209
Bit
Name
Type
Reset
31 30 29
Re Pi B
28 27
P 26 25 24 23 22 21 20 19 18 17 16
a n a
n
Ba
MT7623N
f o r
Bit
Name
15 14 13 12
e a s e 11
I - R 2
10 9 8
unlock_key
7 6 5 4 3 2 1 0
l
Type WO
Reset
Bit(s)
0
Name
0 0
Re Pi B
1
P0
Description
0 1 0 0 0 0 0 1 0 0 1
15:0 unlock_key
a n a Write 0x1209 to generate a software watchdog reset
10007018
WDT_SWSYSR
ST Ba n
System Software Reset Register 88000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name unlock_key
Type WO
Reset 1 0 0 0 1 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
bdp_d conn_ venc_i ethdm
hifsys apmix conn_ infra_ md_rs ddrph vdec_ mfg_r mm_r infra_r
Name isp_rs mcu_r
_rst ed_rst rst ao_rst t y_rst
mg_rs
rst
asys_r
st st st
t st t st
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
f o r
Description
31:24
13
unlock_key
bdp_disp_rst
e a s e I - 2
Write 0x88 to unlock the write protection of this register.
R
Write 1 to reset BDP_DISP
12
11
10
conn_mcu_rst
hifsys_rst
apmixed_rst
l
Re Pi B P
Write 1 to reset CONN_MCU.
Write 1 to reset hifsys
Write 1 to reset APMIXEDSYS.
9
8
conn_rst
infra_ao_rst
a n a Write 1 to reset CONNSYS

Write 1 to reset INFRA_AO
7
6
5
md_rst
ddrphy_rst
venc_img_rst Ba n Write 1 to reset the MODEM system.
Needs 2T 32K duration for TD modem.
Write 1 to reset DDRPHY and MEMPLL
Write 1 to reset VENC and IMG and its related pad macro (CAM, MIPI_RX)
4 vdec_rst Write 1 to reset VDEC
3 ethdma_rst Write 1 to reset ETHDMA
2 mfg_rst Write 1 to reset MFG
1 mm_rst Write 1 to reset MM and its related pad macro (SPI, DPI, MIPI_CFG,
MIPI_TX)
0 infra_rst Write 1 to reset INFRASYS and its related pad macro (NLI,EFUSE)
WDT_REQ_MO
f o r
10007030
Bit 31
DE
30 29
e
28
a s e
Reset Request Mode Register (will npt be reset)
I
27
- R 2
26 25 24 23 22 21 20 19 18
33080003
17 16
Name
Type
Reset 0 0 1
l
Re Pi B
unlock_key
1
WO
P0 0 1 1
debug
_en
RW
1
a
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Ba
MT7623N
f o r
Name
e a s e I - R 2 scpsy therm
s_en al_en
l
Type RW RW
Reset
Bit(s) Name
Re Pi B P
Description
1 1
31:24
19
unlock_key
debug_en
a n a Write 0x33 to unlock the write protection of this register

Enables debugsys reset
1 scpsys_en
Ba n 0: Disable
1: Enable
Enables scpsys reset
0: Disable
1: Enable
0 thermal_en Enables thermal reset
0: Disable
1: Enable
WDT_REQ_IRQ
10007034 Reset Request IRQ Enable Register (will not be reset) 44080003
r
_EN
Bit
Name
31 30 29 28
unlock_key
27
e f o26
2
25 24 23 22 21 20 19
debug
18 17 16
s
_irq
a R
Type WO RW
Reset 0 1 0 0
l e
0
P I
1
- 0 0 1
Re Pi B
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
scpsy therm
Name s_irq al_irq
Type RW RW
a
Reset 1 1
Bit(s) Name
n a nDescription
31:24
19
unlock_key
debug_irq
B a Write 0x44 to unlock the write protection of this register
Triggers IRQ instead of reset when debugsys reset is enabled
0: Trigger reset
1: Trigger IRQ
1 scpsys_irq Triggers IRQ instead of reset when scpsys reset is enabled
0: Trigger reset
1: Trigger irq
0 thermal_irq Triggers IRQ instead of reset when thermal reset is enabled
0: Trigger reset
1: Trigger IRQ
f o r
e
WDT_DEBUG_C
2
10007040 Debug Control Register (will not be reset) FFFE00F1
Bit 31
TL
30 29
l e
28
a s I
27
- R 26 25 24 23 22 21 20 19 18 17 16
Re Pi B P
ddr_re
ddr_sr
Name unlock_key
ef_sta
serve
_sta
Type WO RU RO
a
Reset 0 1 0 1 1 0 0 1 z 0
Ba
MT7623N
f o r
Bit 15 14 13 12
e a s e 11
I - R 2
10 9
rg_dra rg_dra rg_dra
8 7 6 5 4 3 2 1
rg_mc
0
rg_dd
l
r_prot
P
Name mc_co mc_is mc_sr rg_dramc_timeout u_lath
Re Pi B
ect_e
nf_iso o ef _en
n
Reset 0 0 0 1 1 1 1 0 1
Bit(s) Name
a n a Description
31:24
17
unlock_key
ddr_sref_sta
Ba n Write 0x59 to unlock the write protection of this register

Indicates the current DDR status
0: Currently not in self-refresh mode
1: Currently in self-refresh mode
16 ddr_reserve_sta Indicates ddr_reserve_mode is successful
0: Failed
1: Succeed
10 rg_dramc_conf_iso ddr_reserve_mode related register
9 rg_dramc_iso ddr_reserve_mode related register
8 rg_dramc_sref ddr_reserve_mode related register
7:4 rg_dramc_timeout ddr_reserve_mode related register
1
0
rg_mcu_lath_en
rg_ddr_protect_en
f o r
Enables ddr_protect_mode
e a s e
When ddr_reserve_mode is enabled, ddr_protect_en will be over-ridden
I -
0: Disable
R 2
automatically.
l
Re Pi B P
1: Enable
10007050
WDT_INTERCO
RE_SYNC
a n a Intercore Sync Register 00000000
Bit
Name
Type
Reset
Bit
31
0
15
30
0
14
Ba
29
0
13
n 28
0
12
27
0
11
26
0
10
25
0
9
0
24
8
0
23
rg_intercore_sync[31:16]
RW
7
0
22
6
21
0
5
20
0
4
19
0
3
18
0
2
17
0
1
16
0
0
Name rg_intercore_sync[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31:0 rg_intercore_sync Register for intercore sync usage
WDT_INTERCO
f o r
e
10007054 Set Control of Intercore Sync Register 00000000
2
RE_SYNC_SET
Bit
Name
31 30 29
l
28
e a s 27
I - R 26 25 24 23
rg_intercore_sync_set[31:16]
22 21 20 19 18 17 16
Type
Reset
Bit
Name
0
15
0
14
0
13
Re Pi B
0
12 P
0
11
0
10
0
9
0
Other
8
0 0
7
0
rg_intercore_sync_set[15:0]
6 5
0
4
0
3
0
2
0
1
0
0
a n a
n
Ba
MT7623N
f o r
Type
Reset 0 0 0
e
0
a s e 0
I - R 20 0 0
Other
0 0 0 0 0 0 0 0
Bit(s)
31:0
Name
l
Re Pi B P
Description
rg_intercore_sync_set Sets 1'b1 to the correspondent bit of rg_intercore_sync.
a n a
10007058
Bit
Name
31
Ba
WDT_INTERCO
RE_SYNC_CLR
30 29
n
Clear Control of Intercore Sync Register
28 27 26 25 24 23
rg_intercore_sync_clr[31:16]
22 21 20 19 18
00000000
17 16
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rg_intercore_sync_clr[15:0]
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
r
31:0 rg_intercore_sync_clr Set 1'b0 to the correspondent bit of rg_intercore_sync
e f o 2
10000310
RESET_DEGLIT
l e a s I - R
Reset Deglitch Enable Key Register FFFFFFFF
P
CH_KEY
Re Pi B
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name dgrst_en_key[31:16]
Type RW
a
Reset x x x x x x x x x x x x x x x x
Bit
Name
15 14 13
n a n 12 11 10 9 8
dgrst_en_key[15:0]
7 6 5 4 3 2 1 0
Ba
Type RW

31:0 dgrst_en_key Write 0x67D2_A357 to enable reset deglitch.
3.5 Programming Guide
3.5.1 TOPRGU Initial
r
Enable dual mode reset when TOPRGU is first initialized. Because WDT_MODE will not be reset and
only be reset by SYSRSTB.
e f o
the dual mode will be disabled if system reset is triggered through WDT_SWRST, these registers will
2
l e a s I - R
P
The following registers will not be reset by TOPRGU.
Re Pi B
 WDT_MODE
 WDT_STA
 WDT_NONRST_REG
a n a
n
Ba
MT7623N
f o r


WDT_NONRST_REG2
WDT_REQ_MODE
e a s e I - R 2


WDT_REQ_IRQ_EN
WDT_DEBUG_CTL l
Re Pi B P
3.5.2 Watchdog Timer
a n a



Ba n
Trigger WDT_RESTART right after WDT_LENGTH is updated.
WDT_SWRST can be triggered without wdt_en set to 1’b1.
It is recommended to trigger WDT_RESTART before setting wdt_en to 1’b1.
3.5.3 IRQ Mode

Dual mode reset is default on. Therefore, all reset requests are default with IRQ mode enabled. This
means the interrupt is triggered instead of triggering system reset immediately. If you would like to
trigger system reset instead of interrupt, change the corresponding configuration of each reset
request.
f o r
e a s e I - R 2
Each reset request can be configured as reset or IRQ separately.
3.5.4
l
Re Pi B
CONNSYS Watchdog Timeout
P
CONNSYS has its own watchdog timer. When the watchdog timers expire, it notify AP through
n a
interrupts. AP then asserts software reset to CONNSYS.

a
n
CONSYS
Ba
1. conn_rst = 1’b1
2. Wait for 2T 32kHz then set md_rst/conn_rst = 1’b0.
3.5.5 Dual Mode Reset

Dual mode reset is system reset after TOPRGU triggers interrupt. The watchdog timer needs to be
enabled to complete this function.
In this mode, the watchdog timer will be AUTO-RESTART after interrupt is triggered. AP needs to
clear WDT_STA after receiving interrupt from TOPRGU, or system reset will be triggered after
watchdog timer expires.
f o r
1. Set wdt_en = 1’b1.
2. Set dual_mode = 1’b1.
e a s e I - R 2
l
Re Pi B P
3. Set wdt_irq, thermal_irq, scpsys_irq or debug_irq to 1’b1.
a n a
n
Ba
MT7623N
f o r
3.5.6 DDR Protect
e a s e I - R 2
l P
DDR protect (rg_ddr_protect_en) is useless when DDR reserved mode is enabled.
Re Pi B
a
3.5.7 DDR Reserved Mode Reset
a n
DDR reserved mode keeps data in DDR during system reset. In order to complete this function,
n
Ba
DRAMC, DRMC_CONF, DDRPHY_CONF and EMI_CONF (optional) will not be reset.
1. Enable DDR reserved mode when initializing TOPRGU.

2. Wait for system reset to be triggered.
3. [Optional] Check DDR reserved mode status (ddr_reserve_sta).
4. After system reset, release DRAMC_CONF protect (set rg_dramc_conf_iso = 1’b0).
5. Ensure related clocks of EMI, DRAMC, DDRPHY are ready (including PLL).
6. Wait for dramc_sref_sta = 1’b1.
7. Release DRAMC protect (set rg_dramc_iso = 1’b0).
8. Release DRAMC self-refresh control (set rg_dramc_sref = 1’b0).
r
9. Wait for dramc_sref_sta = 1’b0.
e f o 2
l e a s I - R
Re Pi B P
a n a
Ba n
f o r
e a s e I - R 2
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
4 Peripheral Controller
e a s e I - R 2
4.1 Introduction
l
Re Pi B P
a n a
The peripheral controller is used to control the reset, clock and bus setting of peripheral sub-system.
(power-down control).
4.2 Feature list

n
Each module inside the peripheral sub-system has its own software reset and clock gated control
Ba
 Supports software reset control of each module inside peripheral sub-system
 Supports clock gated control of the modules insider peripheral sub-system by AP MCU
 Supports DCM control of peripheral sub-system
 Supports bus setting (bandwidth limit/way enable/…) of peripheral sub-system
4.3 Block Diagram
f o r
e a s e I - R 2
Pericfg controller
l
Re Pi B P SW Reset Control
a n a
Ba n DCM Control
Bus Setting
Figure 4-1: Block diagram of Pericfg Controller
f o r
e a s e I
Module name: PERICFG Base address: (+10003000h)
- R 2
Address
10003000
Name
PERI_GLOBAL
l
Re Pi B hP
Widt
32
Register Function
Peripheral Software Reset Register0
a n a
n
Ba
MT7623N
f o r
10003004
CON_RST0
PERI_GLOBAL
e a s e I
32
- R 2 Peripheral Software Reset Register1
10003008
CON_RST1
PERI_GLOBAL
CON_PDN0_S
ET
l
Re Pi B P32 Peripheral Power Down0 Register Set
1000300C
PERI_GLOBAL
CON_PDN1_SE
T
a n a 32 Peripheral Power Down1 Register Set
10003010
10003014
PERI_GLOBAL
CON_PDN0_C
LR
PERI_GLOBAL
CON_PDN1_C
Ba n 32
32
Peripheral Power Down0 Register Clear

LR
PERI_GLOBAL
10003018 CON_PDN0_S 32 Peripheral Power Down0 Register Status
TA
PERI_GLOBAL
1000301C CON_PDN1_ST 32 Peripheral Power Down1 Register Status
A
PERI_GLOBAL
10003020 CON_PDN_MD 32 Peripheral MD1 Power Down0 Register Set
r
1_SET
10003024
PERI_GLOBAL
CON_PDN_MD
2_SET
e f o
32
2
Peripheral MD2 Power Down0 Register Set
10003028
PERI_GLOBAL
CON_PDN_MD
l e a s I
32
- R Peripheral MD1 Power Down0 Register Clear
1000302C
1_CLR
PERI_GLOBAL
CON_PDN_MD
2_CLR
Re Pi B P32 Peripheral MD2 Power Down0 Register Clear
10003030
PERI_GLOBAL
CON_PDN_MD
a n a 32 Peripheral MD1 Power Down0 Register Status
n
1_STA
Ba
PERI_GLOBAL
10003034 CON_PDN_MD 32 Peripheral MD2 Power Down0 Register Status
2_STA
PERI_GLOBAL
10003038 CON_PDN_MD 32 Peripheral MD Power Down1 Register MASK
_MASK
10003050 PERI_GLOBAL 32 Peripheral DCM Control Register

CON_DCMCTL
PERI_GLOBAL
10003054 CON_DCMDBC 32 Peripheral DCM Debounce Counter
PERI_GLOBAL
10003058 CON_DCMFSE 32 Peripheral DCM Frequency Selection
L
r
PERI_GLOBAL
1000305C 32 Peripheral Clock Selection
o
CON_CKSEL
10003200
PERIAXI_BUS
_CTL1
s e f 32
2
Peripheral AXI Bus Control 1
10003204 PERIAXI_BUS
_CTL2
l e a P I
32
- R Peripheral AXI BUS Control 2
Re Pi B
PERIAXI_SI0_
10003208 CTL 32 Peripheral AXI SI0 Control
1000320C PERIAXI_SI1_ 32 Peripheral AXI SI1 Control
a
CTL
Ba
MT7623N
f o r
10003210 PERIAXI_MI_
STA
e a s e 32
I - R 2 Peripheral AXI MI Status
10003300
10003304
PERIAXI_AHB
_LMT_CON1
PERIAXI_AHB
_LMT_CON2
l
Re Pi B P32
32
Peripheral AHB Bus 0 Bandwidth Limiter
10003308
PERIAXI_AHB
_LMT_CON3
a n a 32 Peripheral AHB Bus 1 Bandwidth Limiter
1000330C
10003310
PERIAXI_AHB
_LMT_CON4
Ba
PERIAXI_AHB
_LMT_CON5
PERIAXI_AHB
n 32
32
10003314 _LMT_CON6 32 Peripheral AHB Bus 2 Bandwidth Limiter
10003318 PERIAXI_AHB 32 Peripheral AHB Bus 3 Bandwidth Limiter

_LMT_CON7
PERIAXI_AHB
1000331C _LMT_CON8 32 Peripheral AHB Bus 3 Bandwidth Limiter
10003320 PERIAXI_AXI 32 Peripheral AXI MST0 Bandwidth Limiter

_LMT_CON1
PERIAXI_AXI
10003324 _LMT_CON2 32 Peripheral AXI MST1 Bandwidth Limiter
10003328
PERIAXI_AXI
_LMT_CON3
f o
32
r Peripheral AXI MST2 Bandwidth Limiter
1000332C PERIAXI_AXI
_LMT_CON4
PERIAXI_AXI
e a s e 32
I - R 2 Peripheral AXI DMA Bandwidth Limiter
10003330
10003334
_LMT_CON5
PERIAXI_AXI
_LMT_CON6
PERIAXI_AXI
l
Re Pi B P
32
32
Peripheral AXI DMA Bandwidth Limiter
10003338 _LMT_CON7
PERIAXI_AXI
a n a 32 Peripheral AXI DMA Bandwidth Limiter
n
1000333C 32 Peripheral AXI DMA Bandwidth Limiter
_LMT_CON8
Ba
PERI_USB_W
10003400 AKEUP_DEC_ 32 Peripheral USB WAKEUP CONTROL0
CON0
PERI_UART_C
1000340C K_SOURCE_S 32 Peripheral UART CLOCK SOURCE SELECTION
EL
10003420 PERI_ETH_NI 32 Peripheral ETH_NIC CONTROL

C_CON
PERI_NFI_CK
10003424 _SOURCE_SEL 32 Peripheral NFI CLOCK SOURCE SELECTION
10003428 PERI_NFI_MA 32 Peripheral NFI MAC CONTROL

C_CTRL
f o r
1000300
0
PERI_GLOB
ALCON_RST
0
e a s e R 2
I -
00000000
Bit
Nam
e
31 30 29
ET
H_
SW
l
Re Pi B
28
US
B_
SW
P
27 26 25
I2C
3_
SW
24
I2C
2_
SW
23
I2C
1_S
W_
22
I2C
0_
SW
21 20
MS
DC
1_S
19
MS
DC
0_
18 17
MS
DC
2_
16
TH
ER
M_
a n a
n
Ba
MT7623N
f o r
_R
ST
_R
ST
e a s e I - R 2 _R
ST
_R
ST
RS
T
_R
ST
W_
RS
SW
_R
SW
_R
SW
_R
l
T ST ST ST
Type
Reset
Bit 15 14
RW
0
13
Re Pi B
RW
0
12 P
11 10
AU
RW
0
9
RW
0
8
RW
0
7
RW
0
6
GC
5
RW
0
4
RW
UA
0
3 2
UA
RW
0
1
UA
RW
0
0
UA
Nam
NL
I_S
W_
NFI
_S
W_
a n a DM
A_
SW
XA
DC
_S
PW
M_
SW
BTI
F_
SW
PU
_S
RT
3_S
RT
2_
RT
1_S
RT
0_
n
e RS RS _R W_ _R _R
W_ W_ SW W_ SW
Ba
RS RS _R RS _R
T T ST RS ST ST
T T ST T ST
T
Reset 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
ETH software reset
ETH_SW
29 ETH_SW_RST 0: Not reset ETH
_RST
1: Reset ETH
USB software reset
USB_SW
28 USB_SW_RST 0: Not reset USB
_RST
r
1: Reset USB
25
I2C3_SW
_RST
I2C3_SW_RST
e f o 2
I2C3 software reset
0: Not reset I2C3
s
1: Reset I2C3
24
I2C2_SW
l e
I2C2_SW_RST
a P I - R I2C2 software reset
0: Not reset I2C2
Re Pi B
_RST
1: Reset I2C2
I2C1 software reset
I2C1_SW
23 I2C1_SW_RST 0: Not reset I2C1
a
_RST
1: Reset I2C1
22
I2C0_S
n a n
I2C0_SW_RST
I2C0 software reset
0: Not reset I2C0
Ba
W_RST
1: Reset I2C0
MSDC1 software reset
MSDC1_
20 MSDC1_SW_RST 0: Not reset MSDC1
SW_RST
1: Reset MSDC1
MSDC0_ MSDC0_SW_RS
19 0: Not reset MSDC0
SW_RST T
1: Reset MSDC0
MSDC2_ MSDC2_SW_RS
17 0: Not reset MSDC2
SW_RST T
1: Reset MSDC2
THERM software reset
THERM_ THERM_SW_RS
16 0: Not reset THERM
r
SW_RST T
1: Reset THERM
15
NLI_SW
NLI_SW_RST
e f o 2
NLI software reset
0: Not reset NLI
_RST
l e a s I - R
1: Reset NLI
NFI software reset
14
11
NFI_SW
_RST
DMA_S
Re Pi B
NFI_SW_RST
DMA_SW_RST
P 0: Not reset NFI
1: Reset NFI
DMA software reset
W_RST
a n a 0: Not reset DMA
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
10
AUXADC
_SW_RS
T
l
Re Pi B
AUXADC_SW_R
ST P
1: Reset DMA
AUXADC software reset
0: Not reset AUXADC
1: Reset AUXADC
8
PWM_S
a n a
PWM_SW_RST
PWM software reset
0: Not reset PWM
n
W_RST
1: Reset PWM
5
BTIF_S
W_RST
GCPU_S
Ba
BTIF_SW_RST
GCPU_SW_RST
BTIF software reset
0: Not reset BTIF
1: Reset BTIF
GCPU software reset
0: Not reset GCPU
W_RST
1: Reset GCPU
UART3 software reset
UART3_
3 UART3_SW_RST 0: Not reset UART3
SW_RST
1: Reset UART3
UART2 software reset
UART2_
2 UART2_SW_RST 0: Not reset UART2
SW_RST
1: Reset UART2
1
UART1_S
UART1_SW_RST
f o r UART1 software reset

0: Not reset UART1
e
W_RST
2
1: Reset UART1
0
UART0_
l e
UART0_SW_RS
a s I - R UART0 software reset
0: Not reset UART0
SW_RST T
Re Pi B P 1: Reset UART0
1000300
PERI_GLOB
a n a
4
Bit
Nam
e
31
ALCON_RST
1
30
Ba
29 n 28
27 26 25 24 23 22 21 20 19 18
00000000
17 16
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI
0_
Nam SW
e _R
ST
Type RW
Reset 0
Bit(s Mnemon
Name
f o r Description
) ic
SPI0_S
e a s e I - R 2 SPI0 software reset
l
1 SPI0_SW_RST 0: Not reset SPI0
P
W_RST
Re Pi B
1: Reset SPI0
a n a
n
Ba
MT7623N
f o r
1000300
PERI_GLOB
ALCON_PD
e a s e I - R 2
Peripheral Power Down0 Register Set 00000000
8
Bit 31
US
N0_SET
30
US
29
US
l
Re Pi B
28 27
P 26
AU
25 24 23 22 21 20
UA
19
UA
18 17
UA
16
a
B_ B1_ B0 ET SPI I2C I2C I2C BTI UA
XA I2C RT RT RT NLI
n
Nam SL MC _M H_ 0_ 3_ 2_ 0_ F_ RT
DC 1_P 3_ 2_ 0_ _P
a
e V_ U_ CU PD PD PD PD PD PD 1_P
_P DN PD PD PD DN
n
PD PD _P N N N N N N DN
DN N N N
Ba
N N DN
Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MS MS MS
AP TH
DC DC DC US US PW PW PW PW PW PW PW PW
_D ER NFI
Nam 30 20 20
MA
B1_ B0 M_ M7 M6 M5 M4 M3 M2 M1
M_ _P
e _1_ _2 _1_
_P
PD _P PD _P _P _P _P _P _P _P
PD DN
PD _P PD N DN N DN DN DN DN DN DN DN
DN N
N DN N
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
r
) ic
31
USB_SL
V_PDN
USB_SLV_PDN
e f o 2
USB_SLV power down
0: keep original value
USB1_M
l e
USB1_MCU_PD
a s I - R
1: Power down USB_SLV
USB1_MCU power down
P
30 0: keep original value
Re Pi B
CU_PDN N
1: Power down USB1_MCU
USB0_MCU power down
USB0_M USB0_MCU_PD
CU_PDN N
a n a 1: Power down USB0_MCU

ETH power down
28
27
ETH_PD
N
SPI0_PD
N
n
ETH_PDN
Ba
SPI0_PDN
1: Power down ETH
SPI0 power down
1: Power down SPI0
AUXADC power down
AUXADC
26 AUXADC_PDN 0: keep original value
_PDN
1: Power down AUXADC
I2C3 power down
I2C3_PD
25 I2C3_PDN 0: keep original value
N
1: Power down I2C3
I2C2 power down
I2C2_PD
N
f o r 1: Power down I2C2

I2C1 power down
23
I2C1_PD
N
I2C1_PDN
e a s e I - R 2 0: keep original value

1: Power down I2C1
22
21
I2C0_PD
N
BTIF_PD BTIF_PDN
l
Re Pi B
I2C0_PDN
P
I2C0 power down
1: Power down I2C0
BTIF power down
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
20
N
UART3_
l
Re Pi B
UART3_PDN
P
1: Power down BTIF
UART3 power down
a
PDN
1: Power down UART3
19
UART2_
n a n
UART2_PDN
UART2 power down
Ba
PDN
1: Power down UART2
UART1 power down
UART1_
18 UART1_PDN 0: keep original value
PDN
1: Power down UART1
UART0 power down
UART0_
PDN
1: Power down UART0
NLI power down
NLI_PD
16 NLI_PDN 0: keep original value
N
1: Power down NLI
MSDC30_2 power down
MSDC30
15 MSDC30_2_PDN 0: keep original value
r
_1_PDN
1: Power down MSDC30_2
14
MSDC20
MSDC30_1_PDN
e f o 2
MSDC30_1 power down
_2_PDN
l e a s I - R
MSDC30_0 power down
13
MSDC20
_1_PDN
AP_DMA
MSDC30_0_PD
N
Re Pi B P 0: keep original value

AP_DMA power down
12
_PDN
a n a
AP_DMA_PDN 0: keep original value
1: Power down AP_DMA
11
10
USB1_P
DN
USB0_P Ba n
USB1_PDN
USB0_PDN
USB1 power down
1: Power down USB1
USB0 power down
DN
1: Power down USB0
PWM power down
PWM_P
9 PWM_PDN 0: keep original value
DN
1: Power down PWM7
PWM7 power down
PWM7_P
8 PWM7_PDN 0: keep original value
DN
1: Power down PWM7
PWM6 power down
PWM6_P
7
DN
PWM6_PDN
f o r 0: keep original value

1: Power down PWM6
6
PWM5_P
DN
PWM5_PDN
e a s e I - R 2
PWM5 power down
1: Power down PWM5
5
PWM4_P
DN l
Re Pi B
PWM4_PDN
P PWM4 power down
1: Power down PWM4
a
4 PWM3_P PWM3_PDN PWM3 power down
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
3
DN
PWM2_P
l
Re Pi B
PWM2_PDN
P
1: Power down PWM3
PWM2 power down
a
DN
1: Power down PWM2
2
PWM1_P
n a n
PWM1_PDN
PWM1 power down
Ba
DN
1: Power down PWM1
THERM power down
THERM_
1 THERM_PDN 0: keep original value
PDN
1: Power down THERM
AUXADC power down
NFI_PD
0 NFI_PDN_SET 0: keep original value
N
1: Power down NFI
PERI_GLOB
1000300
ALCON_PD Peripheral Power Down1 Register Set 00000000
r
C
N1_SET
Bit
Nam
31 30 29 28
e f
27
o 26
2
25 24 23 22 21 20 19 18 17 16
e
Type
l e a s I - R
P
Reset
Re Pi B
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NFI NFI
GC
PA _E
Nam PU
a
D_ CC
e _P
n
PD _P
DN
a
N DN
n
Type WO WO WO
Ba
Reset 0 0 0
Bit(s Mnemon
Name Description
) ic
NFIPAD power down
NFIPAD_
2 NFIPAD_PDN 0: keep original value
PDN
1: Power down NFIPAD
NFI_ECC power down
NFI_ECC
1 NFI_ECC_PDN 0: keep original value
_PDN
1: Power down NFI_ECC
GCPU power down
GCPU_P
0 GCPU_PDN 0: keep original value
DN
f o r 1: Power down GCPU
PERI_GLOB
e a s e I - R 2
10003010
Bit 31
ALCON_PD
N0_CLR
30 29
l
Re Pi B
28
P
27 26 25 24 23 22 21 20 19 18
00000000
17 16
a
Nam US US US ET SPI AU I2C I2C I2C I2C BTI UA UA UA UA NLI
Ba
MT7623N
f o r
e B_
SL
B1_
MC
B0
_M
H_
PD
e a s e
0_
PD
I -
XA
R
DC
2 3_
PD
2_
PD
1_P
DN
0_
PD
F_
PD
RT
3_
RT
2_
RT
1_P
RT
0_
_P
DN
l
V_ U_ CU N N _P N N N N PD PD DN PD
Type
PD
N
W1
C
PD
N
W1
C
_P
DN
W1
C
Re Pi B
W1
C
W1
C P DN
W1
C
W1
C
W1
C
W1
C
W1
C
W1
C
N
W1
C
N
W1
C
W1
C
N
W1
C
W1
C
a
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MS
DC
MS
DC
MS
DC
n aAP
US US PW PW PW PW PW PW PW PW
TH
Ba
_D ER NFI
Nam 30 20 20 B1_ B0 M_ M7 M6 M5 M4 M3 M2 M1
MA M_ _P
e _1_ _2 _1_ PD _P PD _P _P _P _P _P _P _P
_P PD DN
DN N
N DN N
W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1
Type C C C C C C C C C C C C C C C C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
USB_SLV clear power down
USB_SL
31 USB_SLV_PDN 0: keep original value
V_PDN
1: clear power down USB_SLV
30
USB1_M
CU_PDN
USB1_MCU_PD
N
f o r USB1_MCU clear power down

e
1: clear power down USB1_MCU
29
USB0_M
CU_PDN
USB0_MCU_PD
N
l e a s I - R 2 USB0_MCU clear power down

28
ETH_PD
N
Re Pi B
ETH_PDN P 1: clear power down USB0_MCU
ETH clear power down
1: clear power down ETH
27
SPI0_PD
a
SPI0_PDN
n a SPI0 clear power down
26
N
AUXADC
_PDN
Ba n
AUXADC_PDN
1: clear power down SPI0
AUXADC clear power down
1: clear power down AUXADC
I2C3 clear power down
I2C3_PD
N
1: clear power down I2C3
I2C2_PD
N
I2C1_PD
N
22
I2C0_PD
I2C0_PDN
f o r I2C0 clear power down
e
N
21
BTIF_PD
BTIF_PDN
l e a s I - R 2 1: clear power down I2C0

BTIF clear power down
P
Re Pi B
N
1: clear power down BTIF
UART3_ UART3 clear power down
20 UART3_PDN
PDN 0: keep original value
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
19
UART2_
PDN
l
Re Pi B
UART2_PDN P
1: clear power down UART3
UART2 clear power down
18
UART1_
a n
UART1_PDN
a UART1 clear power down
n
PDN
17
16
UART0_
PDN
NLI_PD
Ba
UART0_PDN
NLI_PDN
NLI clear power down
N
1: clear power down NLI
MSDC30_2 clear power down
MSDC30
_1_PDN
1: clear power down MSDC30_2
MSDC20
_2_PDN
13
MSDC20 MSDC30_0_PD
f o r MSDC30_0 clear power down

e
_1_PDN N
2
12
AP_DMA
l e
AP_DMA_PDN
a s I - R AP_DMA clear power down
11
_PDN
USB1_P
DN Re Pi B
USB1_PDN
P 1: clear power down AP_DMA
USB1 clear power down
USB0_P
a n a 1: clear power down USB1

10
9
DN
PWM_P
DN Ba n
USB0_PDN
PWM_PDN
1: clear power down USB0
PWM clear power down
1: clear power down PWM7
PWM7 clear power down
PWM7_P
DN
PWM6_P
DN
PWM5_P
DN
PWM4_P
f o r 1: clear power down PWM5
5
DN
PWM4_PDN
e a s e I - R 2
4
3
PWM3_P
DN
PWM2_P
l
Re Pi B
PWM3_PDN
PWM2_PDN
P 0: keep original value
a
DN 0: keep original value
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
2
PWM1_P
DN
l
Re Pi B
PWM1_PDN P
1
THERM_
a n
THERM_PDN
a THERM clear power down
n
PDN
1: clear power down THERM
0
NFI_PD
N
Ba
NFI_PDN_SET
NFI clear power down
1: clear power down NFI
PERI_GLOB
10003014 ALCON_PD Peripheral Power Down1 Register Clear 00000000
N1_CLR
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type
Reset
Bit 15 14 13 12
f
11
o r 10 9 8 7 6 5 4 3 2 1 0
Nam
e a s e I - R 2 NFI
PA
NFI
_E
GC
PU
l
D_ CC
e _P
Type
Re Pi B P PD
N
W1
C
_P
DN
W1
C
DN
W1
C
a
Reset 0 0 0
Bit(s Mnemon
n a n
Ba
Name Description
) ic
NFIPAD clear power down
NFIPAD_
PDN
1: clear power down NFIPAD
NFI_ECC clear power down
NFI_ECC
1 NFI_ECC_PDN 0: keep original value
_PDN
1: clear power down NFI_ECC
GCPU clear power down
GCPU_P
0 GCPU_PDN 0: keep original value
DN
1: clear power down GCPU
PERI_GLOB
f o r
10003018
Bit 31
ALCON_PD
N0_STA
30 29
e
28
a s ePeripheral Power Down0 Register Status
27
I - R 2
26 25 24 23 22 21 20 19 18
00000000
17 16
Nam
e
US
B_
SL
V_
US
B1_
MC
U_
US
B0
_M
CU
l
Re Pi B
ET
H_
PD
N
0_
PD
N
P
SPI
AU
XA
DC
_P
I2C
3_
PD
N
I2C
2_
PD
N
I2C
1_P
DN
I2C
0_
PD
N
BTI
F_
PD
N
UA
RT
3_
PD
UA
RT
2_
PD
UA
RT
1_P
DN
UA
RT
0_
PD
NLI
_P
DN
a
PD PD _P DN N N N
Ba
MT7623N
f o r
Type
N
RO
N
RO
DN
RO RO
e a s eRO
I - R 2
RO RO RO RO RO RO RO RO RO RO RO
l
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Nam
15
MS
DC
30
14
MS
DC
20
13
MS
DC
20
Re Pi B
12
AP
_D
MA
11
US
B1_
P 10
US
B0
PW
M_
9
PW
M7
8
PW
M6
7
PW
M5
6
PW
M4
5
PW
M3
4 3
PW
M2
2
PW
M1
1
TH
ER
M_
0
NFI
_P
e _1_
PD
N
_2
_P
DN
_1_
PD
N
a n
_P
DN
a PD
N
_P
DN
PD
N
_P
DN
_P
DN
_P
DN
_P
DN
_P
DN
_P
DN
_P
DN
PD
N
DN
Type
Reset
Bit(s
RO
0
Mnemon
RO
0
RO
Ba
0
Name
n RO
0
RO
0
RO
0
RO
0
Description
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
) ic
USB_SLV power down
USB_SL
V_PDN
USB1_MCU power down
USB1_M USB1_MCU_PD
CU_PDN N
USB0_MCU power down
USB0_M USB0_MCU_PD
CU_PDN N
f o r 1: Power down USB0_MCU

ETH power down
28
ETH_PD
N
ETH_PDN
e a s e I - R 2 0: keep original value

1: Power down ETH
27
SPI0_PD
N
SPI0_PDN
l
Re Pi B P
SPI0 power down
1: Power down SPI0
AUXADC power down
a
AUXADC
n
_PDN
n a I2C23 power down
Ba
I2C3_PD
N
1: Power down I2C3
I2C2 power down
I2C2_PD
N
1: Power down I2C2
I2C1 power down
I2C1_PD
N
1: Power down I2C1
I2C0 power down
I2C0_PD
N
1: Power down I2C0
BTIF power down
r
BTIF_PD
21 BTIF_PDN 0: keep original value
o
N
20
UART3_
UART3_PDN
s e f 2
1: Power down BTIF
UART3 power down
R
PDN
l e a P I - 1: Power down UART3
Re Pi B
UART2 power down
UART2_
PDN
1: Power down UART2
a
18 UART1_ UART1_PDN UART1 power down
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
17
PDN
UART0_
l
Re Pi B
UART0_PDN
P
1: Power down UART1
UART0 power down
a
PDN
1: Power down UART0
16
NLI_PD
n a
NLI_PDNn NLI power down
Ba
N
1: Power down NLI
MSDC30_2 power down
MSDC30
_1_PDN
MSDC30_1 power down
MSDC20
_2_PDN
MSDC30_0 power down
MSDC20 MSDC30_0_PD
_1_PDN N
AP_DMA power down
AP_DMA
12 AP_DMA_PDN 0: keep original value
r
_PDN
11
USB1_P
USB1_PDN
e f o 2
USB1 power down
DN
l e a s I - R
1: Power down USB1
USB0 power down
10
USB0_P
DN
PWM_P Re Pi B
USB0_PDN

1: Power down USB0
PWM power down
9
DN
PWM_PDN
a n a 0: keep original value

1: Power down PWM7
7
PWM7_P
DN
PWM6_P Ba n
PWM7_PDN
PWM6_PDN
PWM7 power down
1: Power down PWM7
PWM6 power down
DN
1: Power down PWM6
PWM5 power down
PWM5_P
DN
1: Power down PWM5
PWM4 power down
PWM4_P
DN
1: Power down PWM4
PWM3 power down
PWM3_P
4
DN
PWM3_PDN

1: Power down PWM3
3
PWM2_P
DN
PWM2_PDN
e a s e I - R 2
PWM2 power down
1: Power down PWM2
2
PWM1_P
DN l
Re Pi B
PWM1_PDN
P PWM1 power down
1: Power down PWM1
a
1 THERM_ THERM_PDN THERM power down
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
0
PDN
NFI_PD
l
Re Pi B
NFI_PDN_SET
P
1: Power down THERM
NFI power down
a
N
1: Power down NFI
n a n
1000301C
Bit 31
PERI_GLOB
ALCON_PD
N1_STA
30
Ba
29 28
Peripheral Power Down1 Register Status
27 26 25 24 23 22 21 20 19 18
00000000
17 16
Nam
e
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NFI NFI
GC
PA _E
Nam D_ CC
PU
e _P
r
PD _P
DN
o
N DN
Type
Reset
s e f 2
RO
0
RO
0
RO
0
Bit(s Mnemon
l e a P I - R
Re Pi B
Name Description
) ic
NFIPAD power down
NFIPAD_
PDN
NFI_ECC
a n a 1: Power down NFIPAD

NFI_ECC power down
1
0
_PDN
GCPU_P
DN B a
GCPU_PDN
n
NFI_ECC_PDN 0: keep original value
1: Power down NFI_ECC
GCPU power down
1: Power down GCPU
PERI_GLOB
10003020 ALCON_PD Peripheral MD1 Power Down0 Register Set 00000000
N_MD1_SET
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
US US US
r
AU UA UA UA
o
XA I2C RT RT RT NLI
Nam
f
SL MC _M H_ 0_ 3_ 2_ 0_ F_ RT
DC 1_P 3_ 2_ 0_ _P
e
_P DN PD PD PD DN
Type
Reset
N
WO
0
N
WO
0
DN
WO
0
WO
l0
e a s WO
0
I - R 2
DN
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
N
WO
0
N
WO
0
WO
0
N
WO
0
WO
0
Bit
Nam
e
15
MS
DC
30
14
MS
DC
20
13
MS
DC
20 Re Pi B
12
AP
_D
MA
US
P
11
B1_
PD
10
US
B0
_P
PW
M_
PD
9
PW
M7
_P
8
PW
M6
_P
7
PW
M5
_P
6
PW
M4
_P
5
PW
M3
_P
4 3
PW
M2
_P
2
PW
M1
_P
1
TH
ER
M_
0
NFI
_P
DN
a n a
n
Ba
MT7623N
f o r
_1_
PD
_2
_P
_1_
PD
_P
DN
e a s eN
I -
DN
R 2 N DN DN DN DN DN DN DN PD
N
l
N DN N
Type
Reset
WO
0
WO
0
WO
0
Re Pi B
WO
0
WO
0
P WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
Bit(s
)
Mnemon
ic
Name
a n a Description
n
USB_SLV power down
USB_SL
Ba
V_PDN
USB1_MCU power down
USB1_M USB1_MCU_PD
CU_PDN N
USB0_MCU power down
USB0_M USB0_MCU_PD
CU_PDN N
ETH power down
ETH_PD
28 ETH_PDN 0: keep original value
N
1: Power down ETH
SPI0 power down
SPI0_PD
r
27 SPI0_PDN 0: keep original value
N
AUXADC
e f o 2
1: Power down SPI0
AUXADC power down
26
_PDN
AUXADC_PDN
l e a s I - R
25
I2C3_PD
N
Re Pi B
I2C3_PDN
P I2C3 power down
1: Power down I2C3
I2C2 power down
24
I2C2_PD
N
I2C2_PDN

1: Power down I2C2
23
I2C1_PD
N
I2C0_PD
Ba n
I2C1_PDN
I2C1 power down
1: Power down I2C1
I2C0 power down
N
1: Power down I2C0
BTIF power down
BTIF_PD
N
1: Power down BTIF
UART3 power down
UART3_
PDN
1: Power down UART3
UART2 power down
19
UART2_
PDN
UART2_PDN

1: Power down UART2
18
UART1_
PDN
UART1_PDN
e a s e I - R 2 UART1 power down

l
1: Power down UART1
17
UART0_
PDN
Re Pi B
UART0_PDN
P UART0 power down
1: Power down UART0
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
16
NLI_PD
N
NLI_PDN
l
Re Pi B P NLI power down
1: Power down NLI
MSDC30_2 power down
15
MSDC30
_1_PDN
n a
MSDC30_2_PDN
a
14
MSDC20
_2_PDN
MSDC20
Ba n
MSDC30_1_PDN
MSDC30_0_PD
MSDC30_1 power down
MSDC30_0 power down
_1_PDN N
AP_DMA power down
AP_DMA
_PDN
USB1 power down
USB1_P
11 USB1_PDN 0: keep original value
DN
1: Power down USB1
USB0 power down
10
USB0_P
DN
USB0_PDN

1: Power down USB0
9
PWM_P
DN
PWM_PDN
e a s e I - R 2 PWM power down

l
1: Power down PWM7
8
PWM7_P
DN
Re Pi B
PWM7_PDN
P PWM7 power down
1: Power down PWM7
7
PWM6_P
DN
a n
PWM6_PDN
a PWM6 power down
6
PWM5_P
DN
Ba n
PWM5_PDN
1: Power down PWM6
PWM5 power down
1: Power down PWM5
PWM4 power down
PWM4_P
DN
1: Power down PWM4
PWM3 power down
PWM3_P
DN
1: Power down PWM3
PWM2 power down
PWM2_P
DN
1: Power down PWM2
2
PWM1_P
DN
PWM1_PDN
f o r PWM1 power down

1
THERM_
THERM_PDN
e a s e I - R 2
1: Power down PWM1
THERM power down
0
PDN
NFI_PD
N
l
Re Pi B
NFI_PDN_SET P 1: Power down THERM
NFI power down
a
1: Power down NFI
Ba
MT7623N
f o r
e a s e I - R 2
10003024
PERI_GLOB
ALCON_PD
N_MD2_SET
l
Re Pi B P
Peripheral MD2 Power Down0 Register Set 00000000
Bit 31
US
30
US
29
US
a n
28
a 27 26
AU
25 24 23 22 21 20
UA
19
UA
18 17
UA
16
Nam
e
Type
B_
SL
V_
PD
N
WO
B1_
MC
U_
PD
N
WO
B0
Ba
_M
CU
_P
DN
WO
n ET
H_
PD
N
WO
SPI
0_
PD
N
WO
XA
DC
_P
DN
WO
I2C
3_
PD
N
WO
I2C
2_
PD
N
WO
I2C
1_P
DN
WO
I2C
0_
PD
N
WO
BTI
F_
PD
N
WO
RT
3_
PD
N
WO
RT
2_
PD
N
WO
UA
RT
1_P
DN
WO
RT
0_
PD
N
WO
NLI
_P
DN
WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MS MS MS
AP TH
_D ER NFI
Nam 30 20 20 B1_ B0 M_ M7 M6 M5 M4 M3 M2 M1
MA M_ _P
e _1_ _2 _1_ PD _P PD _P _P _P _P _P _P _P
_P PD DN
DN N
N DN N
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name
f o r Description
)
31
ic
USB_SL
e
USB_SLV_PDN
a s e I - R 2 USB_SLV power down
l
P
V_PDN
Re Pi B
USB1_MCU power down
USB1_M USB1_MCU_PD
CU_PDN N
a
29
USB0_M
CU_PDN N
n a n
USB0_MCU_PD
USB0_MCU power down
Ba
ETH power down
ETH_PD
N
1: Power down ETH
SPI0 power down
SPI0_PD
N
1: Power down SPI0
AUXADC power down
AUXADC
_PDN
I2C3 power down
I2C3_PD
N
r
1: Power down I2C3
24
I2C2_PD
N
I2C2_PDN
e f o 2
I2C2 power down
I2C1_PD
l e a s I - R
1: Power down I2C2
I2C1 power down
P
Re Pi B
N
1: Power down I2C1
I2C0_PD I2C0 power down
22 I2C0_PDN
N 0: keep original value
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
21
BTIF_PD
N
l
Re Pi B
BTIF_PDN P
1: Power down I2C0
BTIF power down
1: Power down BTIF
20
UART3_
a n
UART3_PDN
a UART3 power down
n
PDN
1: Power down UART3
19
18
UART2_
PDN
UART1_
Ba
UART2_PDN
UART1_PDN
UART2 power down
1: Power down UART2
UART1 power down
PDN
1: Power down UART1
UART0 power down
UART0_
PDN
1: Power down UART0
NLI power down
NLI_PD
N
1: Power down NLI
15
MSDC30
MSDC30_2_PDN
f o r MSDC30_2 power down

e
_1_PDN
2
14
MSDC20
l e a
MSDC30_1_PDN s I - R MSDC30_1 power down
13
_2_PDN
MSDC20
_1_PDN Re Pi B
MSDC30_0_PD
N
P 1: Power down MSDC30_1
MSDC30_0 power down
AP_DMA
a n a 1: Power down MSDC30_0

AP_DMA power down
12
11
_PDN
USB1_P
DN Ba n
AP_DMA_PDN
USB1_PDN
USB1 power down
1: Power down USB1
USB0 power down
USB0_P
DN
1: Power down USB0
PWM power down
PWM_P
DN
1: Power down PWM7
PWM7 power down
PWM7_P
DN
PWM6_P
f o r 1: Power down PWM7
PWM6 power down
7
DN
PWM6_PDN
e a s e I - R 2
1: Power down PWM6
PWM5 power down
6
5
PWM5_P
DN
PWM4_P
l
Re Pi B
PWM5_PDN
PWM4_PDN
1: Power down PWM5
PWM4 power down
a
DN 0: keep original value
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
4
PWM3_P
DN
PWM3_PDNl
Re Pi B P
1: Power down PWM4
PWM3 power down
1: Power down PWM3
3
PWM2_P
a
PWM2_PDN
n a PWM2 power down
n
DN
1: Power down PWM2
1
PWM1_P
DN
THERM_
Ba
PWM1_PDN
THERM_PDN
PWM1 power down
1: Power down PWM1
THERM power down
PDN
1: Power down THERM
NFI power down
NFI_PD
N
1: Power down NFI
10003028
PERI_GLOB
ALCON_PD
f o r
Peripheral MD1 Power Down0 Register
00000000
e
Clear
Bit 31
US
N_MD1_CLR
30
US
29
US
28
l e a s 27
I - R 2
26 25 24 23 22 21 20 19 18 17 16
Nam
e
B_
SL
V_
PD
B1_
MC
U_
PD
B0
_M
CU
_P
Re Pi B
ET
H_
PD
N
SPI
0_
PD
N
P AU
XA
DC
_P
DN
I2C
3_
PD
N
I2C
2_
PD
N
I2C
1_P
DN
I2C
0_
PD
N
BTI
F_
PD
N
UA
RT
3_
PD
N
UA
RT
2_
PD
N
UA
RT
1_P
DN
UA
RT
0_
PD
N
NLI
_P
DN
Type
N
W1
C
N
W1
C
DN
W1
C
a n
W1
C
a W1
C
W1
C
W1
C
W1
C
W1
C
W1
C
W1
C
W1
C
W1
C
W1
C
W1
C
W1
C
Reset
Bit
Nam
DC
30
0
15
MS
0
14
MS
DC
20
0
Ba
13
MS
DC
20
n 0
12
AP
_D
MA
0
11
US
B1_
0
10
US
B0
0
PW
M_
9
0
PW
M7
8
0
PW
M6
7
0
PW
M5
6
0
PW
M4
5
0
PW
M3
4
0
3
PW
M2
0
2
PW
M1
0
1
TH
ER
M_
0
0
NFI
_P
e _1_ _2 _1_ PD _P PD _P _P _P _P _P _P _P
_P PD DN
DN N
N DN N
Type C C C C C C C C C C C C C C C C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
r
USB_SL
31
V_PDN
USB_SLV_PDN
e f o 2
s
USB1_MCU clear power down
R
USB1_M USB1_MCU_PD
30
CU_PDN N
l e a P I -
Re Pi B
USB0_M USB0_MCU_PD
CU_PDN N
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
28
ETH_PD
N
ETH_PDN
l
Re Pi B P ETH clear power down
SPI0 clear power down
27
SPI0_PD
N
n
SPI0_PDN
a a 0: keep original value

26
AUXADC
_PDN
I2C3_PD
Ba n
AUXADC_PDN
AUXADC clear power down
N
I2C2_PD
N
I2C1_PD
N
22
I2C0_PD
N
I2C0_PDN

21
BTIF_PD
N
BTIF_PDN
e a s e I - R 2 BTIF clear power down

l
20
UART3_
PDN
Re Pi B
UART3_PDN
P UART3 clear power down
19
UART2_
PDN
a n
UART2_PDN
a UART2 clear power down
18
UART1_
PDN
Ba n
UART1_PDN
UART0_
PDN
NLI_PD
N
MSDC30
_1_PDN
14
MSDC20
_2_PDN
MSDC30_1_PDN
f o r MSDC30_1 clear power down

13
MSDC20 MSDC30_0_PD
e a s e I - R 2
12
_1_PDN
AP_DMA
_PDN
N
l
Re Pi B
AP_DMA_PDN P 1: clear power down MSDC30_0
AP_DMA clear power down
a
1: clear power down AP_DMA
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
11
USB1_P
DN l
Re Pi B
USB1_PDN
P USB1 clear power down
10
USB0_P
DN
n
USB0_PDN

9
PWM_P
DN
PWM7_P
Ba n
PWM_PDN
PWM clear power down
DN
PWM6_P
DN
PWM5_P
DN
5
PWM4_P
DN
PWM4_PDN

4
PWM3_P
DN
PWM3_PDN
e a s e I - R 2 PWM3 clear power down

l
3
PWM2_P
DN
Re Pi B
PWM2_PDN
P PWM2 clear power down
2
PWM1_P
DN
a n
PWM1_PDN
a PWM1 clear power down
1
THERM_
PDN
Ba n
THERM_PDN
THERM clear power down
NFI clear power down
NFI_PD
N
PERI_GLOB
ALCON_PD Peripheral MD2 Power Down0 Register
1000302C 00000000
N_MD2_CL Clear
Bit 31
R
30 29 28 27
f o r
26 25 24 23 22 21 20 19 18 17 16
Nam
US
B_
SL
US
B1_
MC
US
B0
_M
ET
H_
e
SPI
a
0_
s e AU
XA
I
DC
- R 2 I2C
3_
I2C
2_
I2C
1_P
I2C
0_
BTI
F_
UA
RT
3_
UA
RT
2_
UA
RT
UA
RT
0_
NLI
_P
l
P
_P DN PD PD PD DN
Re Pi B
DN N N N
N N DN
Type
C C C C C C C C C C C C C C C C
Reset 0 0 0 0
a n a 0 0 0 0 0 0 0 0 0 0 0 0
n
B a
MT7623N
f o r
Bit 15
MS
14
MS
13
MS
12
AP
e a s e11
I - R 2
10 9 8 7 6 5 4 3 2 1
TH
0
l
P
_D ER NFI
Re Pi B
Nam 30 20 20 B1_ B0 M_ M7 M6 M5 M4 M3 M2 M1
MA M_ _P
e _1_ _2 _1_ PD _P PD _P _P _P _P _P _P _P
_P PD DN
DN N
N DN N
a
Type
n
C C C C C C C C C C C C C C C C
Reset 0 0 0
n a 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
31
Mnemon
ic
USB_SL
V_PDN
Ba
Name
USB_SLV_PDN
Description

USB1_M USB1_MCU_PD
CU_PDN N
USB0_M USB0_MCU_PD
CU_PDN N
r
ETH clear power down
ETH_PD
28
N
ETH_PDN
e f o 2
27
SPI0_PD
N
SPI0_PDN
l e a s I - R
SPI0 clear power down
26
AUXADC
_PDN
Re Pi B
AUXADC_PDN P AUXADC clear power down
25
I2C3_PD
N
a
I2C3_PDN
n a I2C3 clear power down
24
I2C2_PD
N
Ba n
I2C2_PDN
I2C1_PD
N
I2C0_PD
N
BTIF clear power down
BTIF_PD
N
20
UART3_
PDN
UART3_PDN
f o r UART3 clear power down

UART2_
e a s e I - R 2
l
P
PDN
Re Pi B
UART1_
PDN
a n a 1: clear power down UART1
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
17
UART0_
PDN l
Re Pi B
UART0_PDN
P UART0 clear power down
16
NLI_PD
N
NLI_PDN

15
MSDC30
_1_PDN
MSDC20
Ba n
MSDC30_2_PDN
_2_PDN
MSDC20 MSDC30_0_PD
_1_PDN N
AP_DMA clear power down
AP_DMA
_PDN
1: clear power down AP_DMA
11
USB1_P
DN
USB1_PDN

10
USB0_P
DN
USB0_PDN
e a s e I - R 2 USB0 clear power down

l
9
PWM_P
DN
Re Pi B
PWM_PDN
P PWM clear power down
8
PWM7_P
DN
a n
PWM7_PDN
a PWM7 clear power down
7
PWM6_P
DN
Ba n
PWM6_PDN
PWM5_P
DN
PWM4_P
DN
PWM3_P
DN
3
PWM2_P
DN
PWM2_PDN
f o r PWM2 clear power down

2
PWM1_P
PWM1_PDN
e a s e I - R 2
1
DN
THERM_
PDN
l
Re Pi B
THERM_PDN P 1: clear power down PWM1
THERM clear power down
a
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
0
NFI_PD
N l
Re Pi B
NFI_PDN_SET
P AUXADC clear power down
a n a
10003030
Bit 31
PERI_GLOB
ALCON_PD
N_MD1_STA
30 Ba
29
n 28
Status
27 26 25 24 23 22 21 20 19 18
00000000
17 16
US US US
AU UA UA UA
XA I2C RT RT RT NLI
Nam SL MC _M H_ 0_
DC
3_ 2_
1_P
0_ F_
3_ 2_
RT
0_ _P
e V_ U_ CU PD PD
_P
PD PD
DN
PD PD
PD PD
1_P
PD DN
DN N N N
N N DN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MS MS MS
AP TH
r
_D ER NFI
Nam 30 20 20 B1_ B0 M_ M7 M6 M5 M4 M3 M2 M1
e _1_
PD
_2
_P
_1_
PD
MA
_P
DN
PD
e
N
f o _P
DN
2
PD
N
_P
DN
_P
DN
_P
DN
_P
DN
_P
DN
_P
DN
_P
DN
M_
PD
N
_P
DN
s
N DN N
a R
Reset 0 0 0
l
0
e
0
P I - 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Name
Re Pi B Description
31
USB_SL
V_PDN
a n a
USB_SLV_PDN
USB_SLV power down
30
USB1_M
CU_PDN
Ba n
USB1_MCU_PD
N
USB1_MCU power down
USB0_MCU power down
USB0_M USB0_MCU_PD
CU_PDN N
ETH power down
ETH_PD
N
1: Power down ETH
SPI0 power down
SPI0_PD
N
1: Power down SPI0
26
AUXADC
_PDN
AUXADC_PDN
f o r AUXADC power down

e
25
I2C3_PD
N
I2C3_PDN
l e a s I - R 2 I2C3 power down

24
I2C2_PD
N
Re Pi B
I2C2_PDN P 1: Power down I2C3
I2C2 power down
1: Power down I2C2
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
23
I2C1_PD
N l
Re Pi B
I2C1_PDN
P I2C1 power down
1: Power down I2C1
I2C0 power down
22
I2C0_PD
N
n
I2C0_PDN

1: Power down I2C0
21
BTIF_PD
N
UART3_
Ba n
BTIF_PDN
BTIF power down
1: Power down BTIF
UART3 power down
PDN
1: Power down UART3
UART2 power down
UART2_
PDN
1: Power down UART2
UART1 power down
UART1_
PDN
1: Power down UART1
UART0 power down
17
UART0_
PDN
UART0_PDN

1: Power down UART0
16
NLI_PD
N
NLI_PDN
e a s e I - R 2 NLI power down

l
1: Power down NLI
15
MSDC30
_1_PDN
Re Pi B
MSDC30_2_PDN
P MSDC30_2 power down
14
MSDC20
_2_PDN
a n a
MSDC30_1_PDN
MSDC30_1 power down
13
MSDC20
_1_PDN
Ba n
MSDC30_0_PD
N
MSDC30_0 power down
AP_DMA power down
AP_DMA
_PDN
USB1 power down
USB1_P
DN
1: Power down USB1
USB0 power down
USB0_P
DN
1: Power down USB0
9
PWM_P
DN
PWM_PDN
f o r PWM power down

8
PWM7_P
PWM7_PDN
e a s e I - R 2
1: Power down PWM7
PWM7 power down
7
DN
PWM6_P
DN
l
Re Pi B
PWM6_PDN P 1: Power down PWM7
PWM6 power down
a
1: Power down PWM6
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
6
PWM5_P
DN
PWM5_PDN
l
Re Pi B P PWM5 power down
1: Power down PWM5
PWM4 power down
5
PWM4_P
DN
PWM4_PDN

1: Power down PWM4
4
PWM3_P
DN
PWM2_P
Ba n
PWM3_PDN
PWM3 power down
1: Power down PWM3
PWM2 power down
DN
1: Power down PWM2
PWM1 power down
PWM1_P
DN
1: Power down PWM1
THERM power down
THERM_
PDN
1: Power down THERM
NFI power down
0
NFI_PD
N
NFI_PDN_SET

1: Power down NFI
e a s e I - R 2
10003034
PERI_GLOB
ALCON_PD
N_MD2_STA
l
Re Pi B P
Status
00000000
Bit 31
US
30
US
29
US
a
28
n a 27 26
AU
25 24 23 22 21 20
UA
19
UA
18 17
UA
16
n
XA I2C RT RT RT NLI
Ba
Nam SL MC _M H_ 0_
DC
3_ 2_
1_P
0_ F_
3_ 2_
RT
0_ _P
e V_ U_ CU PD PD
_P
PD PD
DN
PD PD
PD PD
1_P
PD DN
DN N N N
N N DN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MS MS MS
AP TH
_D ER NFI
Nam 30 20 20 B1_ B0 M_ M7 M6 M5 M4 M3 M2 M1
MA M_ _P
e _1_ _2 _1_ PD _P PD _P _P _P _P _P _P _P
_P PD DN
DN N
N DN N
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name
f o r Description
e
) ic
31
USB_SL
V_PDN
e
USB_SLV_PDN
l a s I - R 2 USB_SLV power down

30
USB1_M
CU_PDN
Re Pi B
USB1_MCU_PD
N
P 1: Power down USB_SLV
USB1_MCU power down
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
29
USB0_M
CU_PDN N l
Re Pi B
USB0_MCU_PD
P USB0_MCU power down
ETH power down
28
ETH_PD
N
ETH_PDN

1: Power down ETH
27
SPI0_PD
N
AUXADC
Ba n
SPI0_PDN
SPI0 power down
1: Power down SPI0
AUXADC power down
_PDN
I2C3 power down
I2C3_PD
N
1: Power down I2C3
I2C2 power down
I2C2_PD
N
1: Power down I2C2
I2C1 power down
23
I2C1_PD
N
I2C1_PDN

1: Power down I2C1
22
I2C0_PD
N
I2C0_PDN
e a s e I - R 2 I2C0 power down

l
1: Power down I2C0
21
BTIF_PD
N
Re Pi B
BTIF_PDN
P BTIF power down
1: Power down BTIF
20
UART3_
PDN
a n
UART3_PDN
a UART3 power down
19
UART2_
PDN
Ba n
UART2_PDN
1: Power down UART3
UART2 power down
1: Power down UART2
UART1 power down
UART1_
PDN
1: Power down UART1
UART0 power down
UART0_
PDN
1: Power down UART0
NLI power down
NLI_PD
N
1: Power down NLI
15
MSDC30
_1_PDN
MSDC30_2_PDN
f o r MSDC30_2 power down

14
MSDC20
e a
MSDC30_1_PDN
s e I - R 2
MSDC30_1 power down
13
_2_PDN
MSDC20
_1_PDN
l
Re Pi B
MSDC30_0_PD
N
P 1: Power down MSDC30_1
MSDC30_0 power down
a
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
12
AP_DMA
_PDN l
Re Pi B
AP_DMA_PDN
P AP_DMA power down
USB1 power down
11
USB1_P
DN
n
USB1_PDN

1: Power down USB1
10
USB0_P
DN
PWM_P
Ba n
USB0_PDN
USB0 power down
1: Power down USB0
PWM power down
DN
1: Power down PWM7
PWM7 power down
PWM7_P
DN
1: Power down PWM7
PWM6 power down
PWM6_P
DN
1: Power down PWM6
PWM5 power down
6
PWM5_P
DN
PWM5_PDN

1: Power down PWM5
5
PWM4_P
DN
PWM4_PDN
e a s e I - R 2 PWM4 power down

l
1: Power down PWM4
4
PWM3_P
DN
Re Pi B
PWM3_PDN
P PWM3 power down
1: Power down PWM3
3
PWM2_P
DN
a n
PWM2_PDN
a PWM2 power down
2
PWM1_P
DN
Ba n
PWM1_PDN
1: Power down PWM2
PWM1 power down
1: Power down PWM1
THERM power down
THERM_
PDN
1: Power down THERM
NFI power down
NFI_PD
N
1: Power down NFI
10003038
PERI_GLOB
ALCON_PD
f o r
Peripheral MD Power Down1 Register
00000003
N_MD_MAS
K
e
MASK
a s e I - R 2
l
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type
Reset
Re Pi B P
a n a
n
B a
MT7623N
f o r
Bit 15 14 13 12
e a s e 11
I - R 2
10 9 8 7 6 5 4 3 2 1
MD
0
MD
l
Nam 2_ 1_
e
Type
Reset
Re Pi B P MA
SK
RW
1
MA
SK
RW
1
Bit(s Mnemon
a n a
n
Name Description
) ic
0
MD2_M
ASK
MD1_MA
Ba
MD2_MASK
MD1_MASK
MD2 power down mask
0: MD2 power down take effect
1: MD2 power down no effect
MD1 power down mask
0: MD1 power down take effect
SK
1: MD1 power down no effect
PERI_GLOB
10003050 ALCON_DC Peripheral DCM Control Register 000000F2
MCTL
Bit
Nam
31 30 29 28 27
f o r 26 25 24 23 22 21 20 19 18 17 16
e
Type
Reset
e a s e I - R 2
Bit 15 14 13
l12
Re Pi B P
11 10 9 8 7 6 5 4 3 2 1
AX
I_C
LO
CK
0
DC
M_
Nam
e
a n aDCM_IDLE_BYPASS_EN AHB_BUS_SLP_REQ _G
AT
EN
AB
n
ED LE
Ba
_E
N
Type RW RW RW RW
Reset 0 0 0 0 0 1 1 1 1 1 0
Bit(s Mnemon
Name Description
) ic
DCM idle bypass enable
DCM_ID bit 0: 1 ap_dma idle bypass enable
DCM_IDLE_BYP bit 1: 1 ap_hif idle bypass enable
12:8 LE_BYP
ASS_EN bit 2: 1 md_hif idle bypass enable
ASS_EN
bit 3: usb idle bypass enable
bist 4: msdc idle bypass
7:4
AHB_BU
S_SLP_R
AHB_BUS_SLP_
f o r AHB bus DCM control

bit 0: 1 AHB0_BUS_ON
EQ
REQ
e a s e I - R 2 bit 2: 1 AHB2_BUS_ON
0
AXI_CLO
CK_GAT
ED_EN
DCM_EN
TED_EN
l
Re Pi B
AXI_CLOCK_GA
DCM_ENABLE
P
AXI clock gated
0: Disable
1: Enable
DCM control setting
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
ABLE
l
Re Pi B P
0: Disable
1: Enable
PERI_GLOB
a n a
10003054
Bit
Nam
e
31
ALCON_DC
MDBC
30
Ba
29
n 28
Peripheral DCM Debounce Counter
27 26 25 24 23 22 21 20 19 18
000000FF
17 16
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DC
M_
DB
Nam C_ DCM_DBC_CNT
e EN
AB
LE
r
Type RW RW
Reset
e f o 2
1 1 1 1 1 1 1 1
Bit(s
)
Mnemon
ic
Name
7
DCM_DB
C_ENAB
LE
BLE
Re Pi B
DCM_DBC_ENA
P DCM debouncing control
0: Disable
1: Enable
a
DCM_DB
6:0 DCM_DBC_CNT DCM debouncing counter
C_CNT
n a n
10003058
PERI_GLOB
ALCON_DC
MFSEL
Ba Peripheral DCM Frequency Selection 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam DCM_FULL_FSEL
e
Type RW
Reset 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam DCM_QTR_FSE
DCM_HALF_FSEL
e L
Type RW RW
Reset
f
0
o r 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Name
20:16
11:8
DCM_FU
LL_FSEL
DCM_HA
LF_FSEL
L
l
DCM_FULL_FSE
Re Pi B
DCM_HALF_FS
EL
P DCM frequency selection for full speed clock
DCM frequency selection for half speed clock
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
2:0
DCM_QT
R_FSEL
l
Re Pi B
DCM_QTR_FSE
L
P DCM frequency selection for quarter speed clock
PERI_GLOB
a n a
1000305C
Bit
Nam
31
ALCON_CKS
EL
30
Ba
29
n 28
Peripheral Clock Selection
27 26 25 24 23 22 21 20 19 18
00000000
17 16
e
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PE
RI
BU
Nam S_
e CK
_S
EL
Type
Reset
f o r RW
0
Bit(s
)
Mnemon
ic
Name
0
PERIBUS
_CK_SE
l
Re Pi B
PERIBUS_CK_S
P PERIBUS clock
Suggest to set to "half clock" mode when eMMC4.5 HS200 mode is
enable. This can enhance the periaxi/periahb data transfer
bandwidth, thus the eMMC4.5 HS200 mode data bandwidth can be
L
EL
a n a improved.
0: peribus operates at quarter clock
Ba n 1: peribus operates at half clock
PERIAXI_B
10003200 Peripheral AXI Bus Control 1 00000000
US_CTL1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam AHB0_SHARE_EN AHB1_SHARE_EN
e
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type
Reset
f o r
Bit(s
)
Mnemon
ic
Name
31:28
AHB0_S
HARE_E
N
EN l
Re Pi B
AHB0_SHARE_
P AHB bus0 share enable
Bit 0: PWM share enable
Bit 1: SPM share enable
Bit 2: NFI share enable
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
27:24
AHB1_S
HARE_E
l
Re Pi B
AHB1_SHARE_E
N
P
Bit 3: USB0 share enable
AHB bus1 share enable
Bit 1: DBGAHB share enable
Bit 2: ETHERNET share enable
a
N
Bit 3: USB1 share enable
n a n
10003204
Bit
Nam
31
PERIAXI_B
US_CTL2
30
Ba
29 28
Peripheral AXI BUS Control 2
27 26 25 24 23 22 21 20 19 18
101FFFFF
17 16
AHB2_SHARE_EN AHB_SECURE_EN[6:2]
e
Type RW RW
Reset 0 0 0 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AHB_SEC
Nam URE_EN[ AHB_BUFFER_EN AHB_MERGE_EN
e 1:0]
Type RW RW RW
r
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s Mnemon
e f o 2
s
Name Description
) ic
l e a P I - R AHB bus2 share enable
Re Pi B
AHB2_S Bit 0: THERM share enable
AHB2_SHARE_E
31:28 HARE_E Bit 1: MSDC1 share enable
N
N Bit 2: SPI1 share enable
Bit 3: SPI0share enable
20:14
AHB_SE
CURE_E
EN
a n a
AHB_SECURE_
AHB2AXI secure enable
13:7
N
AHB_BU
FFER_E
N
AHB_ME
N
Ba n
AHB_BUFFER_E
AHB_MERGE_E
AHB2AXI buffer enable
6:0 AHB2AXI merge enable

RGE_EN N
PERIAXI_SI
10003208 Peripheral AXI SI0 Control 00000300
0_CTL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PE PE
PE PE
r
RI RI
PE PE RI RI
o
AX AX
f
PE RI RI AX AX
I_S I_S
RI AX AX I_S I_S
Nam
e
AX
I_C
G_
e a s e I - R 2
I_S
I0_
WR
I_S
I0_
RD
I0_
DF
SL
I0_
DF
SL
I0_
DF
SL
I0_
DF
SL
PERIAXI_SI0_
R_CHNL_SEL
l
V_ V_
P
DIS _O _O V_ V_
Re Pi B
SE SE
AB T_ T_ SE SE
T_ T_
LE BU BU T_ T_
RI BI
SY SY WI RI
D_ D_
RQ RQ
a
MI MI
Ba
MT7623N
f o r
Type RW
e a s e I - R 2 RO RO
SS
RO
SS
RO RO RO RO
l
Reset 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
Re Pi B
12
PE
RI
P
11 10 9 8 7 6 5 4 3 2 1 0
PE
RI
AX
a n
AX
a
I_S
I_S
I0_
OU
n
I0_ PERIAXI
Nam PERIAXI_SI0_ ST
Ba
CT _SI0_WA
e B_CHNL_SEL AN
RL Y_EN
DI
_B
NG
YP
_D
AS
ISA
S
BL
E
Type RO RW RW RW
Reset 0 0 0 0 1 1 0
Bit(s Mnemon
Name Description
) ic
PERIAXI PERIAXI CG disable control
PERIAXI_CG_DI
31 _CG_DIS 0: Enable CG
ABLE
PERIAXI
SABLE
f o r 1: Disable CG
e
PERIAXI control bypass
2
_SI0_W PERIAXI_SI0_W
24
R_OT_B
USY
R_OT_BUSY
l e a s I - R
0: Disable
1: Enable
23
PERIAXI
_SI0_RD
_OT_BU
SY Re Pi B
PERIAXI_SI0_R
D_OT_BUSY P PERIAXI control bypass
0: Disable
1: Enable
PERIAXI
_SI0_DF
a n a
PERIAXI_SI0_D PERIAXI control bypass
22 SLV_SET
_RID_MI
SS
PERIAXI
_SI0_DF
n
FSLV_SET_RID_
Ba
MISS
PERIAXI_SI0_D
0: Disable
1: Enable

21 SLV_SET FSLV_SET_BID_ 0: Disable
_BID_MI MISS 1: Enable
SS
PERIAXI PERIAXI control bypass
PERIAXI_SI0_D
_SI0_DF
20 FSLV_SET_WIR 0: Disable
SLV_SET
Q 1: Enable
_WIRQ
PERIAXI_SI0_D
_SI0_DF
19 FSLV_SET_RIR 0: Disable
r
SLV_SET
Q 1: Enable
_RIRQ
PERIAXI
e f o 2
s
_SI0_R_ PERIAXI_SI0_R
18:16
R
0: Disable
CHNL_S
EL
_CHNL_SEL
l e a P I - 1: Enable
Re Pi B
_SI0_B_ PERIAXI_SI0_B
15:13 0: Disable
CHNL_S _CHNL_SEL
EL 1: Enable
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
12
PERIAXI
_SI0_CT
RL_BYP
ASS
l
Re Pi B
PERIAXI_SI0_C
TRL_BYPASS P PERIAXI control bypass
0: Disable
1: Enable
9:8
PERIAXI
_SI0_W
AY_EN
a n a
PERIAXI_SI0_W
PERIAXI SI0 way enable
n
AY_EN
Ba
PERIAXI
_SI0_OU PERIAXI_SI0_O
0 STANDI USTANDING_DI PERIAXI SI0 oustanding disable
NG_DIS SABLE
ABLE
PERIAXI_SI
1000320C Peripheral AXI SI1 Control 00000700
1_CTL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PE PE
RI RI PE PE
f o r PE
RI
AX
PE
RI
AX
AX
I_S
I1_
AX
I_S
I1_
RI
AX
I_S
RI
AX
I_S
Nam
e
e a s e I - R 2
I_S
I1_
WR
I_S
I1_
RD
DF
SL
V_
DF
SL
V_
I1_
DF
SL
I1_
DF
SL
PERIAXI_SI1_R
_CHNL_SEL
l
Re Pi B P
_O
T_
BU
SY
_O
T_
BU
SY
SE
T_
RI
D_
MI
SE
T_
BI
D_
MI
V_
SE
T_
WI
RQ
V_
SE
T_
RI
RQ
Type
Reset
a n a RO
0
RO
0
SS
RO
0
SS
RO
0
RO
0
RO
0 0
RO
0 0
Bit 15 14 13
Ba n 12
PE
RI
AX
11 10 9 8 7 6 5 4 3 2 1 0
PE
RI
AX
I_S
I1_
I_S
OU
I1_
Nam PERIAXI_SI1_B PERIAXI_SI1_ ST
CT
e _CHNL_SEL WAY_EN AN
RL
DI
_B
NG
YP
_D
AS
ISA
S
BL
E
Type RO RW RW RW
r
Reset 0 0 0 0 1 1 1 0
Bit(s Mnemon
e f o 2
s
Name Description
) ic
PERIAXI
l e a P I - R PERIAXI control bypass
Re Pi B
_SI1_WR PERIAXI_SI1_W
24 0: Disable
_OT_BU R_OT_BUSY
SY 1: Enable
23 PERIAXI PERIAXI_SI1_R PERIAXI control bypass
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
_SI1_RD
_OT_BU
SY
PERIAXI
l
D_OT_BUSY
Re Pi B P
0: Disable
1: Enable
22
_SI1_DF
SLV_SET
_RID_MI a
PERIAXI_SI1_D
n
FSLV_SET_RID_
MISS
a
0: Disable
n
1: Enable
Ba
SS
PERIAXI
_SI1_DF PERIAXI_SI1_D PERIAXI control bypass
21 SLV_SET FSLV_SET_BID_ 0: Disable
_BID_MI MISS 1: Enable
SS
PERIAXI_SI1_D
_SI1_DF
20 FSLV_SET_WIR 0: Disable
SLV_SET
Q 1: Enable
_WIRQ
PERIAXI_SI1_D
_SI1_DF
19 FSLV_SET_RIR 0: Disable
SLV_SET
Q 1: Enable
_RIRQ
PERIAXI
_SI1_R_ PERIAXI_SI1_R
f o r PERIAXI control bypass
e
18:16 0: Disable
CHNL_S _CHNL_SEL
EL
PERIAXI
l e a s I - R 2 1: Enable

15:13
_SI1_B_
CHNL_S
EL
PERIAXI Re Pi B
PERIAXI_SI1_B
_CHNL_SEL
P 0: Disable
1: Enable
12
_SI1_CT
RL_BYP
a n a
PERIAXI_SI1_C
TRL_BYPASS
0: Disable
1: Enable
10:8
ASS
PERIAXI
_SI1_WA
Y_EN
PERIAXI
Ba n
PERIAXI_SI1_W
AY_EN
PERIAXI SI0 way enable
_SI1_OU PERIAXI_SI1_O
0 STANDI USTANDING_DI PERIAXI SI0 oustanding disable
NG_DIS SABLE
ABLE
PERIAXI_MI
10003210 Peripheral AXI MI Status 00000040
_STA
Bit
Nam
31 30 29 28 27
f o r 26 25 24 23 22 21 20 19 18 17 16
e
Type
Reset
e a s e I - R 2
Bit
Nam
e
15 14 13
l12
Re Pi B P
11 10 9 8
_W
_B
US
7
MI1
_R
_B
US
6
MI1
_E
RR
MI
5
MI1
_E
RR
MI
4
MI1
3
MI
0_
W_
BU
2
MI
0_
R_
BU
1
MI
0_
ER
RM
0
MI
0_
ER
RM
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2 Y Y D_
SE
D_
SE
SY SY ID
_S
ID
_S
l
T_ T_ ET ET
Type
Reset
Re Pi B P RO
0
RO
1
BI
RQ
RO
0
RI
RQ
RO
0
RO
0
RO
0
_BI
RQ
RO
0
_RI
RQ
RO
0
Bit(s Mnemon
a n a
n
Name Description
) ic
Ba
PERIAXI MI1 Write Busy
MI1_W_
7 MI1_W_BUSY 0: MI1 not write busy
BUSY
1: MI1 write busy
PERIAXI MI1 Read Busy
MI1_R_B
6 MI1_R_BUSY 0: MI1 not read busy
USY
1: MI1 read busy
MI1_ER PERIAXI MI1 Write Error
MI1_ERRMID_S
5 RMID_S 0: MI1 no wite error MID
ET_BIRQ
ET_BIRQ 1: MI1 write error MID
MI1_ER PERIAXI MI1 Read Error
RMID_S MI1_ERRMID_S
4 0: MI1 no read error MID
ET_RIR ET_RIRQ
1: MI1 read error MID
Q
MI0_W_
f o r PERIAXI MI0 Write Busy
e
3 MI0_W_BUSY 0: MI0 not write busy
2
BUSY
MI0_R_
l e a s I - R
1: MI0 write busy
PERIAXI MI0 Read Busy
2
1
BUSY
MI0_ER
RMID_S Re Pi B
MI0_R_BUSY
MI0_ERRMID_S
P 0: MI0 not read busy
1: MI0 read busy
PERIAXI MI0 Write Error
a
ET_BIRQ 0: MI0 no wite error MID
n
ET_BIRQ 1: MI0 write error MID
MI0_ER
n a PERIAXI MI0 Read Error
Ba
RMID_S MI0_ERRMID_S
0 0: MI0 no read error MID
ET_RIR ET_RIRQ
Q 1: MI0 read error MID
PERIAXI_A
10003300 HB_LMT_C Peripheral AHB Bus 0 Bandwidth Limiter 00000000
ON1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type
r
Reset
Bit 15 14 13 12
e
11
f o 10
MS
DC
2
BU
9 8 7 6 5 4 3 2 1 0
s
BU FIL
0_ FF FIL
a R
FF TE
Nam
e
l e P I - EM
I_
ER
_M
ER
_E
SOFT_LIMIT_EN R_
CK
FILTER_
LEN
TE
R_
Re Pi B
UL OD EN
N EN
TR E
A
Reset
a n a 0 0 0 0 0 0 0 0 0 0 0
n
Ba
MT7623N
f o r
Bit(s Mnemon
e a s e I - R 2
) ic
Name
l
Re Pi B P
Description
msdc0 AHB master read/write cmd/data ultra attribute to

EMI.
Suggest to enable when the eMMC4.5 HS200 mode is enable. After
10
MSDC0_
EMI_UL
LTRA
a n a
MSDC0_EMI_U enable it, every MSDC0 command will become ultra priority in the
view of EMI arbitration.
TRA
Ba n 0: disable msdc0 AHB master read/write cmd/data with ultra

attribute to EMI
1: enable msdc0 AHB master read/write cmd/data with ultra
attribute to EMI
The condition of early response of
per2conn_ahb_bridge_f2s depends on hprot[2] signal of
BUFFER AHB
9 BUFFER_MODE
_MODE
0: always
1: conditional
To enable early response ability of
BUFFER per2conn_ahb_bridge_f2s
8 BUFFER_EN
_EN 0: disable
1: enable early response
SOFT_LI SOFT_LIMIT_E
r
7:4 AHB bus 0 bandwidth limiter enable
MIT_EN N
3
FILTER_
CKEN
FILTER_CKEN
e f o 2
AHB bus 0 bandwidth limiter filter clock enable
FILTER_
l e a s I - R
AHB bus 0 bandwidth limiter filter length
00: Fliter length = 256
2:1
LEN
FILTER_ Re Pi B
FILTER_LEN
P 01: Filter length = 512

10: Filter length = 1024
0
EN
FILTER_EN
a n a AHB bus 0 bandwidth limiter filterenable
10003304
PERIAXI_A
HB_LMT_C Ba n Peripheral AHB Bus 0 Bandwidth Limiter 00000000
ON2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
USB0P_BUS_GNT_CNT Audio_BUS_GNT_CNT
e
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam MSDC0_BUS_GNT_CNT NFI_BUS_GNT_CNT
e
Type RW RW
Reset 0 0 0 0
f
0
o r 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Name
31:24
23:16
USB0P_
BUS_GN
T_CNT
Audio_B
T_CNT
l
USB0P_BUS_GN
Re Pi B
Audio_BUS_GNT
P USB 0P bus grant count
Audio bus grant count
a
US_GNT _CNT
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
15:8
_CNT
MSDC0_
BUS_GN
T_CNT
l
Re Pi B
MSDC0_BUS_G
NT_CNT P MSDC0 bus grant count
7:0
NFI_BUS
_GNT_C
CNT
a n a
NFI_BUS_GNT_
NFI bus grant count
NT
Ba n
PERIAXI_A
ON3
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIL
r
FIL
TE
o
Nam FILTER_ TE
f
SOFT_LIMIT_EN R_
e LEN R_
CK
e
EN
2
EN
Type
Reset
l e a s I - R 0 0
RW
0 0
RW
0 0
RW
0
RW
0
Bit(s
)
Mnemon
ic
Name
7:4
SOFT_LI
MIT_EN N
a a
SOFT_LIMIT_E
n
AHB bus 1 bandwidth limiter enable
2:1
FILTER_
CKEN
FILTER_ Ba n
FILTER_CKEN
FILTER_LEN

LEN
FILTER_
0 FILTER_EN AHB bus 1 bandwidth limiter filterenable
EN
PERIAXI_A
1000330C HB_LMT_C Peripheral AHB Bus 1 Bandwidth Limiter 00000000
ON4
f o r
e
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type
l e s
SPI0_BUS_GNT_CNT
a RW
I - R 2 MSDC2_BUS_GNT_CNT
RW
Reset
Bit
Nam
e
0
15
0
14
0
13
Re Pi B
0
12
MSDC1_BUS_GNT_CNT P
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
PWM_BUS_GNT_CNT
0
3
0
2
0
1
0
0
Type
a n a RW RW
n
Ba
MT7623N
f o r
Reset 0 0 0 0
e a s e 0
I - R 20 0 0 0 0 0 0 0 0 0 0
Bit(s
)
31:24
Mnemon
ic
SPI0_BU
S_GNT_
Name
l
Re Pi B
SPI0_BUS_GNT
P Description
SPI0 bus grant count

CNT
MSDC2_
_CNT
a n a
23:16
15:8
BUS_GN
T_CNT
MSDC1_
BUS_GN
T_CNT
Ba n
MSDC2_BUS_G
NT_CNT
MSDC1_BUS_G
NT_CNT
MSDC2 bus grant count
MSDC1 bus grant count
PWM_B
PWM_BUS_GNT
7:0 US_GNT PWM bus grant count
_CNT
_CNT
PERIAXI_A
Bit 31
ON5
30 29 28 27
f o r
26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type
e a s e I - R 2
Reset
Bit
Nam
15 14 13 12
l
Re Pi B
11
P 10 9 8 7 6
SOFT_LIMIT_EN
5 4 3
FIL
TE
R_
2
FILTER_
1 0
FIL
TE
a
e CK
LEN R_
n
EN
EN
Type
Reset
a n a 0 0
RW
0 0
RW
0 0
RW
0
RW
0
Bit(s
)
7:4
Mnemon
ic
SOFT_LI
B
Name
SOFT_LIMIT_E
Description
AHB bus 2 bandwidth limiter enable

MIT_EN N
FILTER_
3 FILTER_CKEN AHB bus 2 bandwidth limiter filter clock enable
CKEN
FILTER_ 00: Fliter length = 256
2:1 FILTER_LEN 01: Filter length = 512
LEN
0
FILTER_
EN
FILTER_EN
f o r AHB bus 2 bandwidth limiter filterenable
e a s e I - R 2
10003314
PERIAXI_A
HB_LMT_C
ON6
l
Re Pi B P
Peripheral AHB Bus 2 Bandwidth Limiter 00000000
a n a
n
Ba
MT7623N
f o r
Bit
Nam
31 30 29 28
e a s
PTP_BUS_GNT_CNT e 27
I - R 2
26 25 24 23 22 21 20
DEBUGTOP_BUS_GNT_CNT
19 18 17 16
l
e
Type
Reset
Bit
Nam
0
15
0
14
0
13
Re Pi B
0
12
RW
P
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
RW
0
3
0
2
0
1
0
0
a
FHCTL_SPM_BUS_GNT_CNT
e
Type
Reset 0 0 0
n a n 0
RW
0 0 0 0
Bit(s
)
31:24
Mnemon
ic
PTP_BU
S_GNT_
Ba
Name
PTP_BUS_GNT_
CNT
Description
PTP bus grant count

CNT
DEBUGT
OP_BUS DEBUGTOP_BU
23:16 DEBUGTOP bus grant count
_GNT_C S_GNT_CNT
NT
FHCTL_
SPM_BU FHCTL_SPM_B
15:8 FHCTL_SPM bus grant count
S_GNT_ US_GNT_CNT
CNT
f o r
PERIAXI_A
e a s e I - R 2
10003318
Bit 31
HB_LMT_C
ON7
30 29
l
Re Pi B
28
P
27 26 25 24 23 22 21 20 19 18
00000000
17 16
Nam
e
Type
a n a
Reset
Bit
Nam
e
15 14
Ba
13
n 12 11 10 9 8 7 6
SOFT_LIMIT_EN
5 4 3
FIL
TE
R_
2
FILTER_
LEN
1 0
FIL
TE
R_
CK
EN
EN
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
7:4 AHB bus 3 bandwidth limiter enable
MIT_EN N
3
FILTER_
CKEN
FILTER_CKEN
f o r AHB bus 3 bandwidth limiter filter clock enable
2:1
FILTER_
FILTER_LEN
e a s e I - R 2
l
LEN
P
Re Pi B
FILTER_
0 FILTER_EN AHB bus 3 bandwidth limiter filterenable
EN
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
1000331C
PERIAXI_A
HB_LMT_C
ON8
l
Re Pi B P
Peripheral AHB Bus 3 Bandwidth Limiter 00000000
Bit
Nam
31 30 29
a n a
28
USB1P_BUS_GNT_CNT
27 26 25 24 23 22 21 20
ETH_BUS_GNT_CNT
19 18 17 16
e
Type
Reset
Bit
Nam
0
15
0
14
Ba
0
13
n 0
12
RW
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
RW
0
3
0
2
0
1
0
0
e
Type
Reset
Bit(s Mnemon
Name Description
) ic
USB1P_B
USB1P_BUS_GN
31:24 US_GNT PTP bus grant count
T_CNT
_CNT
23:16
ETH_BU
S_GNT_
CNT
ETH_BUS_GNT
_CNT
f o r DEBUGTOP bus grant count
e a s e I - R 2
10003320
PERIAXI_A
XI_LMT_CO
N1
l
Re Pi B P
Peripheral AXI MST0 Bandwidth Limiter 00000000
Bit 31 30 29
a n a
28 27 26 25 24 23 22 21 20 19 18 17 16
SO
Nam
e
Type
Ba n FT
_LI
MI
T_
EN
RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BW
FIL
_FI
TE
Nam R_
LT FILTER_
AXI_MST0_BUS_GNT_CNT
e CK
ER LEN
_E
EN
N
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
f o r
e
Name Description
2
) ic
16
SOFT_LI
l e
SOFT_LIMIT_E
a s I - R AXI MST0 soft bandwidth limiter enable
0: Disable
11
MIT_EN
FILTER_
CKEN
N
Re Pi B
FILTER_CKEN P 1: Enable
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
10
BW_FIL
TER_EN l
Re Pi B
BW_FILTER_EN
P AXI MST0 bandwidth limiter enable
0: Disable
1: Enable
AXI MST0 bandwidth limiter filter length
9:8
FILTER_
LEN
a n a
FILTER_LEN
7:0
AXI_MS
T0_BUS
_GNT_C Ba n
AXI_MST0_BUS
_GNT_CNT
AXI MST0 bus grant count

NT
PERIAXI_A
10003324 XI_LMT_CO Peripheral AXI MST1 Bandwidth Limiter 00000000
N2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
f o r SO
FT
_LI
e
e a s e I - R 2
MI
T_
EN
l
Type RW
Reset
Bit 15 14 13
Re Pi B
12
P
11
FIL
10
BW
_FI
9 8 7 6 5 4 3 2 1 0
0
a
TE
Nam LT FILTER_
n
R_ AXI_MST1_BUS_GNT_CNT
e ER LEN
a
CK
_E
Type
Reset
Ba n EN
RW
0
N
RW
0 0
RW
0 0 0 0 0
RW
0 0 0 0
Bit(s Mnemon
Name Description
) ic
AXI MST1 soft bandwidth limiter enable
16 0: Disable
MIT_EN N
1: Enable
FILTER_
11 FILTER_CKEN AHB bus 1 bandwidth limiter filter clock enable
CKEN
AXI MST1 bandwidth limiter enable
BW_FIL
10 BW_FILTER_EN 0: Disable
r
TER_EN
1: Enable
e f o 2
s
a R
-
LEN
7:0
AXI_MS
T1_BUS_
GNT_CN
l e
Re Pi B
AXI_MST1_BUS
_GNT_CNT
P I 10: Filter length = 1024
AXI MST1 bus grant count
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
T
l
Re Pi B P
10003328
PERIAXI_A
XI_LMT_CO
a n a Peripheral AXI MST2 Bandwidth Limiter 00000000
Bit
Nam
31
N3
30
Ba
29
n 28 27 26 25 24 23 22 21 20 19 18 17 16
SO
FT
_LI
e MI
T_
EN
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BW
FIL
_FI
TE
Nam LT FILTER_
R_ AXI_MST2_BUS_GNT_CNT
e ER LEN
CK
r
_E
EN
o
N
Type
Reset
RW
0
s e f RW
0
2
0
RW
0 0 0 0 0
RW
0 0 0 0
Bit(s Mnemon
Name
l e a P I - R
Description
Re Pi B
) ic
16 0: Disable
MIT_EN N
11
FILTER_
FILTER_CKEN
a n a 1: Enable
10
CKEN
BW_FIL
TER_EN
B a n
BW_FILTER_EN
0: Disable
1: Enable
LEN
AXI_MS
T2_BUS_ AXI_MST2_BUS
7:0 AXI MST2 bus grant count
GNT_CN _GNT_CNT
T
f o r
1000332C
PERIAXI_A
XI_LMT_CO
e a s e R 2
I -
00000000
l
N4
Bit
Nam
e
31 30 29
Re Pi B
28
P
27 26 25 24 23 22 21 20 19 18 17 16
SO
FT
_LI
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2 MI
T_
l
EN
Type
Reset
Bit 15 14 13
Re Pi B
12 P
11
FIL
10
BW
9 8 7 6 5 4 3 2 1
RW
0
0
Nam
e
a n a TE
R_
_FI
LT
ER
FILTER_
LEN
AXI_DMA_BUS_GNT_CNT
n
CK
_E
Ba
EN
N
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
AXI DMA soft bandwidth limiter enable
16 0: Disable
MIT_EN N
1: Enable
FILTER_
11 FILTER_CKEN AXI DMA bandwidth limiter filter clock enable
CKEN
AXI DMA bandwidth limiter enable
BW_FIL
10
TER_EN
BW_FILTER_EN
f o r 0: Disable
1: Enable
9:8
FILTER_
LEN
FILTER_LEN
e a s e I - R 2
AXI DMA bandwidth limiter filter length
7:0
AXI_DM
A_BUS_
l
Re Pi B
AXI_DMA_BUS_
P
AXI DMA bus grant count

GNT_CN
T
GNT_CNT
a n a
10003330
PERIAXI_A
XI_LMT_COBa n Peripheral AXI DMA Bandwidth Limiter 00000000
N5
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SO
FT
Nam _LI
e MI
T_
EN
Type RW
Reset 0
Bit 15 14 13 12 11
f
FIL
o r 10
BW
9 8 7 6 5 4 3 2 1 0
e
_FI
TE
Nam
e
l e a s R_
CK
EN
I - R 2
LT
ER
_E
FILTER_
LEN
AXI_DMA_BUS_GNT_CNT
P
N
Re Pi B
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
16
SOFT_LI
MIT_EN
FILTER_
N l
Re Pi B
SOFT_LIMIT_E
P AXI MST3 soft bandwidth limiter enable
0: Disable
1: Enable
11
CKEN
a n a
FILTER_CKEN AHB bus 3 bandwidth limiter filter clock enable

10
BW_FIL
TER_EN
FILTER_ Ba n
BW_FILTER_EN 0: Disable
1: Enable
LEN
AXI_DM
A_BUS_ AXI_DMA_BUS_
GNT_CN GNT_CNT
T
10003334
PERIAXI_A
XI_LMT_CO
f o r
Peripheral AXI DMA Bandwidth Limiter 00000000
Bit 31
N6
30 29
e
28
a s e 27
I - R 2
26 25 24 23 22 21 20 19 18 17 16
Nam
e
l
Re Pi B P SO
FT
_LI
MI
T_
Type
a n a EN
RW
n
Reset 0
Ba
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BW
FIL
_FI
TE
Nam LT FILTER_
R_ AXI_DMA_BUS_GNT_CNT
e ER LEN
CK
_E
EN
N
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
16 0: Disable
r
MIT_EN N
1: Enable
11
FILTER_
CKEN
FILTER_CKEN
e f o 2
10
BW_FIL
l e a
BW_FILTER_EN s I - R AXI MST3 bandwidth limiter enable
0: Disable
P
TER_EN
Re Pi B
1: Enable
FILTER_
9:8 FILTER_LEN 00: Fliter length = 256
LEN
a n a 01: Filter length = 512
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
AXI_DM
A_BUS_
l
Re Pi B
AXI_DMA_BUS_
P
a
GNT_CN GNT_CNT
T
n a n
10003338
PERIAXI_A
XI_LMT_CO
N7
Ba Peripheral AXI DMA Bandwidth Limiter 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SO
FT
Nam _LI
e MI
T_
EN
Type RW
Reset 0
Bit 15 14 13 12 11
f
FIL
o r 10
BW
9 8 7 6 5 4 3 2 1 0
e
_FI
2
TE
s
Nam LT FILTER_
R
R_ AXI_DMA_BUS_GNT_CNT
e
l e a CK
EN
P I -
ER
_E
LEN
Re Pi B
N
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Name
a n a Description
16
11
SOFT_LI
MIT_EN
FILTER_ Ba
N n
SOFT_LIMIT_E
FILTER_CKEN
0: Disable
1: Enable

CKEN
BW_FIL
10 BW_FILTER_EN 0: Disable
TER_EN
1: Enable
LEN
7:0
AXI_DM
A_BUS_ AXI_DMA_BUS_
f o r AXI MST3 bus grant count
e
GNT_CN GNT_CNT
T
l e a s I - R 2
1000333C PERIAXI_A
XI_LMT_CO Re Pi B P
Peripheral AXI DMA Bandwidth Limiter 00000000
a n a
n
Ba
MT7623N
f o r
Bit 31
N8
30 29
e
28
a s e 27
I - R 2
26 25 24 23 22 21 20 19 18 17 16
Nam
e
l
Re Pi B P
SO
FT
_LI
MI
T_
Type
a n a EN
RW
n
Reset 0
Ba
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BW
FIL
_FI
TE
Nam R_
LT FILTER_
AXI_DMA_BUS_GNT_CNT
e CK
ER LEN
_E
EN
N
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
16 0: Disable
r
MIT_EN N
1: Enable
11
FILTER_
CKEN
FILTER_CKEN
e f o 2
10
BW_FIL
l e a
BW_FILTER_EN
s I - R AXI MST3 bandwidth limiter enable
0: Disable
P
TER_EN
Re Pi B
1: Enable
a
LEN
n a n 10: Filter length = 1024

Ba
AXI_DM
A_BUS_ AXI_DMA_BUS_
GNT_CN GNT_CNT
T
PERI_USB_
1000340
WAKEUP_D Peripheral USB WAKEUP CONTROL0 00000000
0
EC_CON0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type
Reset
Bit 15 14 13 12 11
f o r
10 9 8 7 6 5 4 3 2 1 0
Nam
e a s e I - R 2 USB0_CDDEBOUNCE
US
B0
_C
l
e
P
DE
Re Pi B
N
Type RW RW
Reset 0 0 0 0 0
a n a
n
B a
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
4:1
USB0_C
DDEBOU
NCE
l
Re Pi B
USB0_CDDEBO
UNCE
P USB0_CDDEBOUNCE
usb0 debounce clock number: (0~15)
0000: 0
0001: 1
a n a 0010: 2
1111: 15
0
USB0_C
DEN
Ba n
USB0_CDEN
USB0_CDEN
usb0 clock debounce enable
0: Disable
1: Enable
PERI_UART
1000340 Peripheral UART CLOCK SOURCE
_CK_SOURC 00000000
C SELECTION
E_SEL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type
Reset
Bit 15 14 13 12 11
f o r
10 9 8 7 6 5 4 3 2 1 0
e
Nam
2
UART_CK_SEL
e
Type
Reset
l e a s I - R 0 0
RW
0 0
Bit(s
)
Mnemon
ic
Name
UART_C
a n a UART_CK_SEL
Clock source selection for UART0 through UART3
n
3:0 UART_CK_SEL
K_SEL 0: 26MHz clock
B a 1: 52MHz clock
PERI_ETH_
10003420 Peripheral ETH_NIC CONTROL 00000000
NIC_CON
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
r
NIC_MII_MODE
e
Type
Reset
e f o 2
0 0
RW
0 0
Bit(s Mnemon
Name
l e a s I - R
Description
)
3:0
ic
NIC_MII
_MODE
Re Pi B
NIC_MII_MODE P NIC_MII_MODE
a n a
n
B a
MT7623N
f o r
e a s e I - R 2
10003424
Bit 31
PERI_NFI_C
K_SOURCE_
SEL
30 29
l
Re Pi B
28
P
Peripheral NFI CLOCK SOURCE
SELECTION
27 26 25 24 23 22 21 20 19 18
00000000
17 16
Nam
e
Type
a n a
Reset
Bit
Nam
e
15 14
Ba
13
n 12 11 10 9 8 7 6 5 4 3 2 1 0
NFI
_C
K_
SE
L
Type RW
Reset 0
Bit(s Mnemon
Name Description
) ic
NFI_CK_SEL
NFI_CK_ Clock source selection for NFI
r
0 NFI_CK_SEL
SEL 0: axi clock
e f o 2
1: nfi pad 1x clock
l e a s I - R
10003428
Bit 31
PERI_NFI_
MAC_CTRL
30 29
Re Pi B
28 P
Peripheral NFI MAC CONTROL
27 26 25 24 23 22 21 20 19 18
00000000
17 16
a
Nam
n
e
Type
Reset
n a
Ba
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam NFI_MAC_CTRL
e
Type RW
Reset 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
NFI_MA
4:0 NFI_MAC_CTRL NFI_MAC_CTRL
C_CTRL
f o r
e a s e I - R 2
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
5 External Interrupt Controller
e a s e I - R 2
5.1 Introduction
l
Re Pi B P
a n a
The external interrupt controller (EINTC) processes all off-chip interrupt sources and forwards
interrupt request signals MCU.
5.2 Feature list Ba n

EINTC supports external interrupt signals and performs the following processes to the interrupt
signals coming from external sources:
 Polarity inversion
 Edge/level trigger selection
f o r
 De-bounce with a configurable 32kHz clock (optional)
e a s e I - 2
According to the register configuration, the external interrupt source will be forwarded to the Cortex-
R
A7 built-in interrupt controller with different IRQ signals, eint_irq or eint_direct_irq. EINTC generates
l
Re Pi B
wake up events to SPM controller.
P
5.3 Block Diagram
a n a
Ba n
This is the block diagram of the external interrupt controller. Every function block is controlled by the
corresponding control register define in next section
Edge/
De- 169-bit Domain
Polarity Level
bounce mask Mask
eint_bus[134:0] (EINT_P Sensitive eint_irq[0]
(EINT_C (EINT_M (EINT_D*
OL) (EINT_SE
ON) ASK) EN)
NS)
APB Bus Register
f o r
e a e I - R 2
Figure 5-1: Block diagram of external interrupt controller
s
l
Re Pi B P
Normally the external interrupt source goes through the de-bounce unit which is driven by 32kHz
clock and triggers the corresponding CPU with eint_irq. Therefore the minimum latency from eint_bus
to eint_irq will be 30.52 µs. Since the latency introduced by the de-bounce module may be too long for
a n a
n
Ba
MT7623N
f o r
e a s e I - 2
some applications, EINTC provides an alternative path which bypasses the de-bounce module and
R
directly triggers the interrupt signals, eint_direct_irq[14:0], to AP MCU.
l
Re Pi B P
a n a
Address
1000B000
Name
EINT_STA0
n
Module name: ap_cirq_eint_reg Base address: (+1000B000h)
Ba Widt
h
32
Register Function
External interrupt status register
1000B004 EINT_STA1 32 External interrupt status register
1000B00C EINT_STA3 32 External interrupt status register
1000B040 EINT_ACK0 32 External interrupt acknowledge register
1000B044 EINT_ACK1 32 External interrupt acknowledge register
1000B048
1000B04C
EINT_ACK2
EINT_ACK3
f
32
o
32
r External interrupt acknowledge register
External interrupt acknowledge register
1000B050
1000B054
EINT_ACK4
EINT_ACK5
e a s e 32
32
I - R 2
1000B080
1000B084
1000B088
EINT_MASK0
EINT_MASK1
EINT_MASK2
l
Re Pi B P
32
32
32
External interrupt mask register
a
1000B08C EINT_MASK3 32 External interrupt mask register
1000B090
1000B094
EINT_MASK4
EINT_MASK5
n a n 32
32
Ba
1000B0C0 EINT_MASK_S 32 External interrupt mask set register
ET0
EINT_MASK_S
1000B0C4 ET1 32 External interrupt mask set register
EINT_MASK_S
1000B0C8 ET2 32 External interrupt mask set register
1000B0CC EINT_MASK_S 32 External interrupt mask set register

ET3
EINT_MASK_S
1000B0D0 ET4 32 External interrupt mask set register
1000B0D4 EINT_MASK_S 32 External interrupt mask set register

ET5
EINT_MASK_
1000B100 CLR0
EINT_MASK_
f
32
o r External interrupt mask set register
e
1000B104 32 External interrupt mask set register
CLR1
1000B108 EINT_MASK_
CLR2
l e a s 32
I - R 2 External interrupt mask set register
1000B10C
1000B110
EINT_MASK_
CLR3
EINT_MASK_
CLR4 Re Pi B P32
32
External interrupt mask set register
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
1000B114
1000B140
1000B144
EINT_MASK_
CLR5
EINT_SENS0
EINT_SENS1
l
Re Pi B P32
32
32
External interrupt sensitivity register

1000B148
1000B14C
EINT_SENS2
EINT_SENS3
a n a 32
32
1000B150
1000B154
1000B180
EINT_SENS4
EINT_SENS5
EINT_SENS_S
ET0 Ba n 32
32
32
External interrupt sensitivity set register
1000B184 EINT_SENS_S 32 External interrupt sensitivity set register

ET1
EINT_SENS_S
1000B188 ET2 32 External interrupt sensitivity set register
1000B18C EINT_SENS_S 32 External interrupt sensitivity set register

ET3
EINT_SENS_S
EINT_SENS_S
r
1000B1C0 EINT_SENS_C
LR0
e f o
32
2
External interrupt sensitivity clear register
1000B1C4
EINT_SENS_C
LR1
l e a s 32
I - R External interrupt sensitivity clear register
1000B1C8
1000B1CC
EINT_SENS_C
LR2
EINT_SENS_C
LR3 Re Pi B P32
32
1000B1D0 EINT_SENS_C
LR4
a n a 32 External interrupt sensitivity clear register
1000B1D4
1000B200
1000B204
EINT_SENS_C
LR5
EINT_SOFT0
EINT_SOFT1Ba n 32
32
32
Software interrupt register

1000B208 EINT_SOFT2 32 Software interrupt register
1000B20C EINT_SOFT3 32 Software interrupt register
1000B240 EINT_SOFT_S 32 Software interrupt set register

ET0
EINT_SOFT_S
1000B244 ET1 32 Software interrupt set register
1000B248 EINT_SOFT_S
ET2
f
32
o r Software interrupt set register
e
EINT_SOFT_S
1000B24C 32 Software interrupt set register
1000B250
ET3
EINT_SOFT_S
ET4
l e a s I
32
- R 2 Software interrupt set register
1000B254
1000B280
EINT_SOFT_S
ET5
EINT_SOFT_C
Re Pi B P32
32
Software interrupt set register
Software interrupt clear register
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
l
LR0
1000B284
1000B288
EINT_SOFT_C
LR1
EINT_SOFT_C
Re Pi B P32
32
a
LR2
1000B28C
EINT_SOFT_C
LR3
n a n 32 Software interrupt clear register
Ba
1000B290 EINT_SOFT_C 32 Software interrupt clear register
LR4
EINT_SOFT_C
1000B294 LR5 32 Software interrupt clear register
1000B300 EINT_POL0 32 External interrupt polarity register

1000B30C EINT_POL3 32 External interrupt polarity register
EINT_POL_SE
1000B340 T0 32 External interrupt polarity set register
1000B344 EINT_POL_SE
T1
f o
32
r External interrupt polarity set register
1000B348 EINT_POL_SE
T2
EINT_POL_SE
e a s e 32
I - R 2 External interrupt polarity set register
1000B34C
1000B350
T3
EINT_POL_SE
T4
EINT_POL_SE
l
Re Pi B P
32
32
External interrupt polarity set register
1000B354 T5
EINT_POL_CL
a n a 32 External interrupt polarity set register
n
1000B380 32 External interrupt polarity clear register
R0
Ba
EINT_POL_CL
1000B384 R1 32 External interrupt polarity clear register
EINT_POL_CL
1000B38C EINT_POL_CL 32 External interrupt polarity clear register

R3
EINT_POL_CL
1000B394 EINT_POL_CL 32 External interrupt polarity clear register

R5
1000B400 EINT_D0EN0 32 Domain 0 external interrupt enable control register
1000B408
1000B40C
EINT_D0EN2
EINT_D0EN3
f
32
o
32
r Domain 0 external interrupt enable control register
Domain 0 external interrupt enable control register
1000B410
1000B414
EINT_D0EN4
EINT_D0EN5
e a s e 32
32
I - R 2
1000B420
1000B424
1000B428
EINT_D1EN0
EINT_D1EN1
EINT_D1EN2
l
Re Pi B P
32
32
32
a
1000B42C EINT_D1EN3 32 Domain 1 external interrupt enable control register
Ba
MT7623N
f o r
e a s e I - R 2
1000B430
1000B434
1000B440
1000B444
EINT_D1EN4
EINT_D1EN5
EINT_D2EN0
EINT_D2EN1
l
Re Pi B P
32
32
32
32
1000B448 EINT_D2EN2
a n a 32 Domain 1 external interrupt enable control register
n
1000B44C EINT_D2EN3 32 Domain 1 external interrupt enable control register
Ba
1000B500 EINT_DBNC_3
~ _0[n] 32 External interrupt debounce control register
1000B50C (n=0~3)
1000B600 EINT_DBNC_S
~ ET_3_0[n] 32 External interrupt debounce control register
1000B60C (n=0~3)
1000B700 EINT_DBNC_C
~ LR_3_0[n] 32 External interrupt debounce control register
1000B70C (n=0~3)
1000B00
EINT_STA0
f o r External interrupt status register 00000000
0
Bit 31 30 29 28
e a s e 27
I - R 2
26 25 24 23 22 21 20 19 18 17 16
l
Mne EINT_PEND0[31:16]
Type
Reset
Bit
Mne
0
15
0
14
0
13
Re Pi B
0
12 P
0
11
0
10
0
9
0
RO
8
0
EINT_PEND0[15:0]
0
7 6
0
5
0
4
0
3
0
2
0
1
0
0
Type
Reset 0 0 0
a n a
0 0 0 0 0
RO
0 0 0 0 0 0 0 0
Bit(s
)
31:0
Mnemon
ic
Ba n Name
EINT_PEND0
Description
Each bit read as 1 indicates the corresponding external

interrupt is pending
1000B00
EINT_STA1 External interrupt status register 00000000
4
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RO
Reset
Bit
Mne
0
15
0
14
0
13
0
12
f
0
11
o r 0
10
0
9
0
8
0 0
7 6
0
5
0
4
0
3
0
2
0
1
0
0
e
EINT_PEND1[15:0]
Type
Reset 0 0 0
l
0
e a s 0
I - R 20 0 0
RO
0 0 0 0 0 0 0 0
Bit(s
)
31:0
Mnemon
ic
Re Pi B
Name
EINT_PEND1
P Description
a
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
Re Pi B P interrupt is pending
1000B00
8
EINT_STA2
a n a External interrupt status register 00000000
Bit
Mne
Type
Reset
Bit
31
0
15
30
0
14
Ba
29
0
13
n 28
0
12
27
0
11
26
0
10
25
0
9
0
24
EINT_PEND2[31:16]
RO
8
0 0
23
7
22
6
21
0
5
20
0
4
19
0
3
18
0
2
17
0
1
16
0
0
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0 EINT_PEND2
f o r
1000B00
C
EINT_STA3
e a s e I - R 2
External interrupt status register 00000000
Bit
Mne
Type
Reset
31
0
30
0
29
0
l
Re Pi B
28
0
P
27
0
26
0
25 24
EINT_PEND3[31:16]
0 0
RO
0 0
23 22 21
0
20
0
19
0
18
0
17
0
16
0
Bit
Mne
15 14 13
a n a
12 11 10 9 8
EINT_PEND3[15:0]
7 6 5 4 3 2 1 0
n
Type RO
Ba
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0 EINT_PEND3
1000B010 EINT_STA4 External interrupt status register 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type
Reset
Bit
0
15
0
14
0
13
0
12
0
11
f o r
0
10
0
9
0
RO
8
0 0
7 6
0
5
0
4
0
3
0
2
0
1
0
0
Mne
Type
e a s e I - R 2 EINT_PEND4[15:0]
RO
l
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Re Pi B
Name P Description
a n a
n
B a
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
31:0
l
Re Pi B
EINT_PEND4
P Each bit read as 1 indicates the corresponding external
1000B014 EINT_STA5
a n a External interrupt status register 00000000

Bit
Mne
Type
Reset
Bit
31
0
15
30
0
14
Ba
29
0
13
n 28
0
12
27
0
11
26
0
10
25
0
9
0
24
EINT_PEND5[31:16]
RO
8
0 0
23
7
22
6
21
0
5
20
0
4
19
0
3
18
0
2
17
0
1
16
0
0
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0 EINT_PEND5
f o r
1000B04
0
EINT_ACK0
e a s e I - R 2
External interrupt acknowledge register 00000000
Bit
Mne
Type
Reset
31
0
30
0
29
0
l
Re Pi B
28
0
P
27
0
26
0
25
0
24
EINT_ACK0[31:16]
0
WO
0 0
23 22 21
0
20
0
19
0
18
0
17
0
16
0
Bit
Mne
15 14 13
a n a
12 11 10 9 8
EINT_ACK0[15:0]
7 6 5 4 3 2 1 0
n
Type WO
Ba
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
Write 1 to specific bit acknowledges the corresponding
31:0 EINT_ACK0
external interrupt
1000B04
EINT_ACK1 External interrupt acknowledge register 00000000
4
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne
Type
f o r EINT_ACK1[31:16]
WO
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Mne
Type
15 14 13
l
12
e a s 11
I - R 2
10 9 8
EINT_ACK1[15:0]
WO
7 6 5 4 3 2 1 0
Reset 0 0 0
Re Pi B
0
P
0 0 0 0 0 0 0 0 0 0 0 0
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
31:0
l
Re Pi B
EINT_ACK1
P Write 1 to specific bit acknowledges the corresponding
external interrupt
1000B04
a n a
8
Bit
Mne
Type
31
EINT_ACK2
30
Ba
29 n 28 27
26 25 24
EINT_ACK2[31:16]
WO
23 22 21 20 19 18
00000000
17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne EINT_ACK2[15:0]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0 EINT_ACK2
f o r external interrupt
1000B04
e a s e I - R 2
C
Bit
Mne
Type
31
EINT_ACK3
30 29 l
Re Pi B
28
P
27
26 25 24
EINT_ACK3[31:16]
WO
23 22 21 20 19 18
00000000
17 16
Reset
Bit
0
15
0
14
0
13
a n a
0
12
0
11
0
10
0
9
0
8
0 0
7 6
0
5
0
4
0
3
0
2
0
1
0
0
Mne
Type
Reset 0 0
Ba
0 n 0 0 0 0
EINT_ACK3[15:0]
0
WO
0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0 EINT_ACK3
external interrupt
1000B05
EINT_ACK4 External interrupt acknowledge register 00000000
0
Bit
Mne
31 30 29 28 27
f o r 26 25 24
EINT_ACK4[31:16]
23 22 21 20 19 18 17 16
Type
Reset
Bit
0
15
0
14
0
13
0
12
e a s e 0
11
I - R 20
10
0
9
0
WO
8
0 0
7 6
0
5
0
4
0
3
0
2
0
1
0
0
Mne
Type
Reset 0 0 0 l
Re Pi B
0
P
0 0 0
EINT_ACK4[15:0]
0
WO
0 0 0 0 0 0 0 0
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
31:0
l
Re Pi B
EINT_ACK4
P Write 1 to specific bit acknowledges the corresponding
external interrupt
1000B05
a n a
4
Bit
Mne
Type
31
EINT_ACK5
30
Ba
29 n 28 27
26 25 24
EINT_ACK4[31:16]
WO
23 22 21 20 19 18
00000000
17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne EINT_ACK4[15:0]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0 EINT_ACK4
f o r external interrupt
1000B08 EINT_MASK
e a s e I - R 2
0
Bit
Mne
Type
31 30
0
29 l
Re Pi B
28
P
27
26 25 24
EINT_MASK0[31:16]
RO
23 22 21 20 19 18
FFFFFFFF
17 16
Reset
Bit
1
15
1
14
1
13
a n a
1
12
1
11
1
10
1
9
1
8
1 1
7 6
1
5
1
4
1
3
1
2
1
1
1
0
Mne
Type
Reset 1 1
Ba
1 n 1 1 1
EINT_MASK0[15:0]
1 1
RO
1 1 1 1 1 1 1 1
Bit(s Mnemon
Name Description
) ic
31:0 EINT_MASK0 External interrupt mask value
1000B08 EINT_MASK
External interrupt mask register FFFFFFFF
4 1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne
Type
f o r EINT_MASK1[31:16]
RO
Reset
Bit
Mne
1
15
1
14
1
13
1
12
e a s e 1
11
I - R 2
1
10
1
9
1
8
1
EINT_MASK1[15:0]
1
7 6
1
5
1
4
1
3
1
2
1
1
1
0
Type
Reset 1 1 1
l
Re Pi B
1
P
1 1 1 1
RO
1 1 1 1 1 1 1 1
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
31:0
l
Re Pi B
EINT_MASK1
P External interrupt mask value
1000B08
8
EINT_MASK
2
a n a External interrupt mask register FFFFFFFF
Bit
Mne
Type
Reset
31
1
30
1 Ba
29
1
n 28
1
27
1
26
1
25 24
EINT_MASK2[31:16]
1 1
RO
1 1
23 22 21
1
20
1
19
1
18
1
17
1
16
1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mne EINT_MASK2[15:0]
Type RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s Mnemon
Name Description
) ic
f o r
1000B08
C
EINT_MASK
3
e a s e I - R 2
Bit
Mne
Type
Reset
Bit
31
1
15
30
1
14
29
1
13
l28
Re Pi B
1
12
27
P
1
11
26
1
10
25
1
9
1
24
EINT_MASK3[31:16]
RO
8
1 1
23
7
22
6
21
1
5
20
1
4
19
1
3
18
1
2
17
1
1
16
1
0
Mne
Type
a n a EINT_MASK3[15:0]
RO
Reset
Bit(s
)
1
Mnemon
ic
1 1
Ba n 1
Name
1 1 1 1 1 1 1
Description
1 1 1 1 1
1000B09 EINT_MASK
0 4
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne EINT_MASK4[31:16]
Type
r
RO
o
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit
Mne
Type
15 14 13 12
s e f
11 10
2
9 8
EINT_MASK4[15:0]
RO
7 6 5 4 3 2 1 0
Reset 1 1 1
l
1
e a 1
P I - R 1 1 1 1 1 1 1 1 1 1 1
Bit(s
)
Mnemon
ic
Re Pi B
Name Description
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
31:0
l
Re Pi B
EINT_MASK4
P External interrupt mask value
1000B09
4
EINT_MASK
5
a n a External interrupt mask register 000001FF
Bit
Nam
e
Type
31 30
Ba
29
n 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
EINT_MASK5
e
Type RO
Reset 1 1 1 1 1 1 1 1 1
Bit(s Mnemon
Name Description
) ic
r
e f o 2
1000B0C EINT_MASK
l e a s I - R
External interrupt mask set register 00000000
0
Bit
Nam
e
31 30
_SET0
29
Re Pi B
28
P
27 26 25 24
EINT_MASK_SET0[31:16]
23 22 21 20 19 18 17 16
Type
Reset 0 0 0
a n a
0 0 0 0 0
WO
0 0 0 0 0 0 0 0
n
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Ba
Nam EINT_MASK_SET0[15:0]
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
EINT_MASK_SE Write 1 to specific bit sets the mask of corresponding
31:0
T0 external interrupt
1000B0C EINT_MASK
4
Bit 31 30
_SET1
29 28
f
27
o r External interrupt mask set register
26 25 24 23 22 21 20 19 18
00000000
17 16
Nam
e
Type
e a s e I - R 2 EINT_MASK_SET1[31:16]
WO
Reset
Bit
Nam
e
0
15
0
14
0
13
l
Re Pi B
0
12
P
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Type
a n a WO
n
Ba
MT7623N
f o r
1000B0C
4
EINT_MASK
_SET1
e a s e I - R 2
Reset
Bit(s
0
Mnemon
0 0
l
Re Pi B
0
P
0 0 0 0 0 0 0 0 0 0 0 0
) ic
a n a
Name
EINT_MASK_SE
Description
Write 1 to specific bit sets the mask of corresponding

31:0
Ba nT1 external interrupt
1000B0C EINT_MASK
8 _SET2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam EINT_MASK_SET2[31:16]
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type
Reset 0 0 0 0 0
f o r
0 0 0
WO
0 0 0 0 0 0 0 0
Bit(s Mnemon
Name
l
) ic
31:0
T2
Re Pi B
EINT_MASK_SE
P Write 1 to specific bit sets the mask of corresponding
external interrupt
a n a
1000B0C
C
Bit
Nam
e
31
EINT_MASK
30
_SET3
B
29
a n
28 27
26 25 24
23 22 21 20 19 18
00000000
17 16
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
)
31:0
ic
EINT_MASK_SE
f o r Write 1 to specific bit sets the mask of corresponding

T3
e a s e I - R 2
external interrupt
1000B0D
0
EINT_MASK
_SET4
l
Re Pi B P External interrupt mask set register 00000000
Bit 31 30 29
a n a
28 27 26 25 24 23 22 21 20 19 18 17 16
n
Ba
MT7623N
f o r
1000B0D
0
EINT_MASK
_SET4
e a s e I - R 2
Nam
e
Type
Reset 0 0 0
l
Re Pi B
0
P
0 0
0 0
WO
0 0 0 0 0 0 0 0
Bit
Nam
15 14 13
a n a
12 11 10 9 8
7 6 5 4 3 2 1 0
n
e
Ba
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
EINT_MASK_SE Write 1 to specific bit sets the mask of corresponding
31:0
1000B0D EINT_MASK
4 _SET5
Bit
Nam
e
31 30 29 28 27
f o r 26 25 24
23 22 21 20 19 18 17 16
Type
Reset 0 0 0 0
e a s e 0
I - R 20 0 0
WO
0 0 0 0 0 0 0 0
l
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type
Reset 0 0 0
Re Pi B
0
P
0 0
0 0
WO
0 0 0 0 0 0 0 0
Bit(s Mnemon
a n a
)
31:0
ic
Ba n Name
EINT_MASK_SE
T5
Description
Write 1 to specific bit sets the mask of corresponding

external interrupt
EINT_MASK
1000B100 External interrupt mask set register 00000000
_CLR0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam EINT_MASK_CLR0[31:16]
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Nam
e
15 14 13 12 11
f o r 10 9 8
EINT_MASK_CLR0[15:0]
7 6 5 4 3 2 1 0
Type
Reset 0 0 0 0
e a s e 0
I - R 20 0 0
WO
0 0 0 0 0 0 0 0
Bit(s
)
31:0
Mnemon
ic l
Re Pi B
Name
EINT_MASK_CL
P Description
Write 1 to specific bit clear the mask of corresponding
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l R0
Re Pi B P external interrupt
1000B104
EINT_MASK
_CLR1
a n a External interrupt mask set register 00000000
Bit
Nam
e
Type
Reset
31
0
30
0
Ba
29
0
n 28
0
27
0
26
0
25 24
0 0
WO
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
r
EINT_MASK_CL Write 1 to specific bit clear the mask of corresponding
31:0
o
R1 external interrupt
s e f 2
EINT_MASK
l e a P I - R
Re Pi B
_CLR2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
a
e
Type
Reset 0 0 0
n a n 0 0 0 0 0
WO
0 0 0 0 0 0 0 0
Ba
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0
1000B10C
EINT_MASK
_CLR3
o r
f
00000000
Bit
Nam
e
31 30 29 28
e
27
a s e 26
I - R 2
25 24
23 22 21 20 19 18 17 16
Type
Reset
Bit
Nam
0
15
0
14
0
13
0
12 l
Re Pi B
0
11
P 0
10
0
9
0
8
WO
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
a
e
B a
MT7623N
f o r
1000B10C
EINT_MASK
_CLR3
e a s e I - R 2
Type
Reset 0 0 0 l
Re Pi B
0
P
0 0 0 0
WO
0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
a n a
Name Description
31:0
Ba n
EINT_MASK_CL
R3
external interrupt
EINT_MASK
_CLR4
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam EINT_MASK_CLR4[31:16]
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type
f o r EINT_MASK_CLR4[15:0]
WO
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
l e a s I - R 2
P
Name Description
Re Pi B
) ic
31:0
a n a
1000B114
Bit
Nam
31
EINT_MASK
30
_CLR5
Ba
29
n 28 27
26 25 24 23 22 21 20 19 18
00000000
17 16
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Name
f o r Description
31:0
EINT_MASK_CL
R5
e a s e I - R 2
external interrupt
1000B140
EINT_SENS
0
l
Re Pi B P External interrupt sensitivity register FFFFFFFF
a n a
n
Ba
MT7623N
f o r
1000B140
EINT_SENS
0
e a s e I - R 2
External interrupt sensitivity register FFFFFFFF
Bit
Nam
e
Type
31 30 29
l
Re Pi B
28
P
27 26 25 24
EINT_SENS0[31:16]
RO
23 22 21 20 19 18 17 16
Reset
Bit
1
15
1
14
1
13
a n a
1
12
1
11
1
10
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
Nam
e
Type
Reset 1 1
Ba
1
n 1 1 1 1
EINT_SENS0[15:0]
1
RO
1 1 1 1 1 1 1 1
Bit(s Mnemon
Name Description
) ic
31:0 EINT_SENS0 External interrupt sensitivity value
1000B144 EINT_SENS1 External interrupt sensitivity register FFFFFFFF

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type
f o r EINT_SENS1[31:16]
RO
Reset
Bit
Nam
1
15
1
14
1
13
1
12
e a s e 1
11
I - R 2
1
10
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
e
Type
Reset 1 1 1 l
Re Pi B
1
P
1 1 1
EINT_SENS1[15:0]
1
RO
1 1 1 1 1 1 1 1
Bit(s
)
Mnemon
ic
a n a
Name Description
31:0
Ba nEINT_SENS1 External interrupt sensitivity value
1000B148 EINT_SENS2 External interrupt sensitivity register FFFFFFFF

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam EINT_SENS2[31:16]
e
Type RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
EINT_SENS2[15:0]
e
Type
r
RO
o
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s Mnemon
s e f 2
a R
Name Description
-
) ic
31:0
l e
EINT_SENS2
Re Pi B P I External interrupt sensitivity value
a n a
n
Ba
MT7623N
f o r
1000B14C EINT_SENS3
e a s e I R 2
-
FFFFFFFF
l
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type
Reset 1 1 1
Re Pi B
1
P
1 1
EINT_SENS3[31:16]
1 1
RO
1 1 1 1 1 1 1 1
Bit
Nam
15 14 13
a n a
12 11 10 9 8
EINT_SENS3[15:0]
7 6 5 4 3 2 1 0
n
e
Ba
Type RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s Mnemon
Name Description
) ic
31:0 EINT_SENS3 External interrupt sensitivity value
EINT_SENS
1000B150 External interrupt sensitivity register FFFFFFFF
4
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type
f o r EINT_SENS4[31:16]
RO
Reset
Bit
Nam
1
15
1
14
1
13
1
12
e a s e 1
11
I - R 2
1
10
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
e
Type
Reset 1 1 1 l
Re Pi B
1
P
1 1 1
EINT_SENS4[15:0]
1
RO
1 1 1 1 1 1 1 1
Bit(s
)
Mnemon
ic
a n a
Name Description
31:0
Ba nEINT_SENS4 External interrupt sensitivity value
1000B154 EINT_SENS5 External interrupt sensitivity register 000001FF

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
EINT_SENS5
e
Type
r
RO
o
Reset 1 1 1 1 1 1 1 1 1
Bit(s Mnemon
s e f 2
a R
Name Description
-
) ic
8:0
l e
EINT_SENS5
Re Pi B P I External interrupt sensitivity value
a n a
n
Ba
MT7623N
f o r
1000B180
EINT_SENS
_SET0
e a s e I - R 2
External interrupt sensitivity set register 00000000
Bit
Nam
e
Type
31 30 29
l
Re Pi B
28
P
27 26 25 24
EINT_SENS_SET0[31:16]
WO
23 22 21 20 19 18 17 16
Reset
Bit
0
15
0
14
0
13
a n a
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Nam
e
Type
Reset 0 0
Ba
0
n 0 0 0
0 0
WO
0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
EINT_SENS_SE Write 1 to specific bit sets the sensitivity of corresponding
31:0
EINT_SENS
1000B184 External interrupt sensitivity set register 00000000
Bit 31 30
_SET1
29 28 27
f o r
26 25 24 23 22 21 20 19 18 17 16
e
Nam
2
e
Type
Reset 0 0 0 0
l e a0
s I0
- R 0 0
WO
0 0 0 0 0 0 0 0
Bit
Nam
e
Type
15 14 13
Re Pi B
12 11
P 10 9 8
WO
7 6 5 4 3 2 1 0
Reset 0 0 0 0
a n a 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
31:0
Mnemon
ic
B a n
Name
EINT_SENS_SE
T1
Description
Write 1 to specific bit sets the sensitivity of corresponding

external interrupt
EINT_SENS
1000B188 External interrupt sensitivity set register 00000000
_SET2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type WO
Reset
Bit
Nam
0
15
0
14
0
13
0
12
f
0
11
o r 0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
e
Type
Reset 0 0 0
e
0
a s e 0
I - R 20
0 0
WO
0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
l
Re Pi B
Name P Description
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
31:0
T2
l
Re Pi B
EINT_SENS_SE
P Write 1 to specific bit sets the sensitivity of corresponding

external interrupt
EINT_SENS
a n a
1000B18C
Bit
Nam
e
31 30
_SET3
Ba
29 n 28 27
26 25 24
23 22 21 20 19 18
00000000
17 16
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0
EINT_SENS_SE
T3
f o r Write 1 to specific bit sets the sensitivity of corresponding

external interrupt
e a s e I - R 2
1000B190
Bit 31
EINT_SENS
30
_SET4
29
l
Re Pi B
28
P
27
26 25 24 23 22 21 20 19 18
00000000
17 16
Nam
e
a n a EINT_SENS_SET4[31:16]
n
Type WO
Ba
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0
1000B194
EINT_SENS
f o r
Bit 31 30
_SET5
29 28
e a s e 27
I - R 2
26 25 24 23 22 21 20 19 18 17 16
l
Nam
P
Re Pi B
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
a n a EINT_SENS_SET5[15:0]
n
Ba
MT7623N
f o r
1000B194
EINT_SENS
_SET5
e a s e I - R 2
e
Type
Reset 0 0 0
l
Re Pi B
0 P
0 0 0 0
WO
0 0 0 0 0 0 0 0
Bit(s Mnemon
a n a
Name Description
n
) ic
Ba
31:0
EINT_SENS
1000B1C0 External interrupt sensitivity clear register 00000000
_CLR0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
EINT_SENS_CLR0[31:16]
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
f o r EINT_SENS_CLR0[15:0]
e
Type WO
Reset 0 0 0
l
0
e a s 0
I - R 20 0 0 0 0 0 0 0 0 0 0
Bit(s
)
31:0
Mnemon
ic
Re Pi B
Name
EINT_SENS_CL P Description
Write 1 to specific bit clear the sensitivity of
a
R0 corresponding external interrupt
n a n
1000B1C4
Bit
Nam
e
31
EINT_SENS
30
_CLR1
Ba
29 28
27 26 25 24
23 22 21 20 19 18
00000000
17 16
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam EINT_SENS_CLR1[15:0]
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Name
f o r Description
31:0
EINT_SENS_CL
R1
e a s e I - R 2 Write 1 to specific bit clear the sensitivity of

corresponding external interrupt
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
1000B1C8
EINT_SENS
_CLR2
e a s e I - R 2
External interrupt sensitivity clear register 00000000
Bit
Nam
e
Type
31 30 29
l
Re Pi B
28
P
27 26 25 24
WO
23 22 21 20 19 18 17 16
Reset
Bit
0
15
0
14
0
13
a n a
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Nam
e
Type
Reset 0 0
Ba
0
n 0 0 0
0 0
WO
0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
EINT_SENS_CL Write 1 to specific bit clear the sensitivity of
31:0
R2 corresponding external interrupt
EINT_SENS
1000B1CC External interrupt sensitivity clear register 00000000
Bit 31 30
_CLR3
29 28 27
f o r
26 25 24 23 22 21 20 19 18 17 16
e
Nam
2
e
Type
Reset 0 0 0 0
l e a0
s I0
- R 0 0
WO
0 0 0 0 0 0 0 0
Bit
Nam
e
Type
15 14 13
Re Pi B
12 11
P 10 9 8
WO
7 6 5 4 3 2 1 0
Reset 0 0 0 0
a n a 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
31:0
Mnemon
ic
B a n
Name
EINT_SENS_CL
R3
Description

1000B1D EINT_SENS
External interrupt sensitivity clear register 00000000
0 _CLR4
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type WO
Reset
Bit
Nam
0
15
0
14
0
13
0
12
f
0
11
o r 0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
e
Type
Reset 0 0 0
e
0
a s e 0
I - R 20
0 0
WO
0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
l
Re Pi B
Name P Description
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
31:0
R4
l
Re Pi B
EINT_SENS_CL
P Write 1 to specific bit clear the sensitivity of

1000B1D EINT_SENS
a n a
4
Bit
Nam
e
31 30
_CLR5
Ba
29 n 28
27 26 25 24
23 22 21 20 19 18
00000000
17 16
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0
EINT_SENS_CL
R5
f o r Write 1 to specific bit clear the sensitivity of

e a s e I - R 2
1000B20
0
Bit 31
EINT_SOFT
30
0
29
l
Re Pi B
28
P
27 26
25 24 23 22 21 20 19 18
00000000
17 16
Nam
e
a n a EINT_SOFT0[31:16]
n
Type RO
Ba
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
EINT_SOFT0[15:0]
e
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0 EINT_SOFT0 Software interrupt value
1000B20
4
EINT_SOFT1
f o r Software interrupt register 00000000
Bit
Nam
e
31 30 29 28
e
27
a s e 26
I - R 2 25 24
EINT_SOFT1[31:16]
23 22 21 20 19 18 17 16
Type
Reset
Bit
Nam
0
15
0
14
0
13
0
12 l
Re Pi B
0
11 P 0
10
0
9
0
8
RO
EINT_SOFT1[15:0]
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
a n a
n
B a
MT7623N
f o r
1000B20
4
EINT_SOFT1
e a s e I - R 2 Software interrupt register 00000000
Type
Reset 0 0 0 l
Re Pi B
0
P
0 0 0 0
RO
0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
a n a
Name Description
31:0
Ba nEINT_SOFT1 Software interrupt value
1000B20
EINT_SOFT2 Software interrupt register 00000000
8
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam EINT_SOFT2[31:16]
e
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
EINT_SOFT2[15:0]
e
Type
Reset 0 0 0 0 0
f o r
0 0 0
RO
0 0 0 0 0 0 0 0
Bit(s Mnemon
Name
l
) ic
31:0
Re Pi B
EINT_SOFT2
P Software interrupt value
1000B20
EINT_SOFT3
a n a Software interrupt register 00000000
C
Bit
Nam
e
Type
31 30
B
29
a n
28 27 26 25 24
EINT_SOFT3[31:16]
RO
23 22 21 20 19 18 17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
e
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0 EINT_SOFT3
f o r Software interrupt value
e a s e I - R 2
1000B210
Bit
Nam
e
31
EINT_SOFT4
30 29
l
Re Pi B
28
P
27 26
25 24
EINT_SOFT4[31:16]
23 22 21 20 19 18
00000000
17 16
a
Type RO
Ba
MT7623N
f o r
1000B210 EINT_SOFT4
e a s e I - R 2 Software interrupt register 00000000
l
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Nam
e
Type
15 14 13
Re Pi B
12
P
11 10 9 8
EINT_SOFT4[15:0]
RO
7 6 5 4 3 2 1 0
Reset 0 0 0
a n a
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
31:0
Mnemon
ic
Ba n Name
EINT_SOFT4
Description
Software interrupt value
1000B214 EINT_SOFT5 Software interrupt register 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
e
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type
f o r EINT_SOFT5[15:0]
RO
Reset 0 0 0 0
e a s e 0
I - R 2
0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
31:0
Mnemon
ic
l
Re Pi B
Name
EINT_SOFT5 P Description
Software interrupt value
a n a
1000B24
0
Bit
Nam
31
EINT_SOFT
30
_SET0
Ba
29
n 28 27 26
25 24
EINT_SOFT_SET0[31:16]
23 22 21 20 19 18
00000000
17 16
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
) ic
Name
EINT_SOFT_SE
f o r Description
Write 1 to specific bit sets the corresponding software

31:0
T0
e a s e I - R 2 interrupt
1000B24
4
EINT_SOFT
_SET1
l
Re Pi B P Software interrupt set register 00000000
a n a
n
Ba
MT7623N
f o r
1000B24
4
EINT_SOFT
_SET1
e a s e I - R 2 Software interrupt set register 00000000
Bit
Nam
e
Type
31 30 29
l
Re Pi B
28
P
27 26 25 24
WO
23 22 21 20 19 18 17 16
Reset
Bit
0
15
0
14
0
13
a n a
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Nam
e
Type
Reset 0 0
Ba
0
n 0 0 0
0 0
WO
0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
EINT_SOFT_SE Write 1 to specific bit sets the corresponding software
31:0
T1 interrupt
1000B24 EINT_SOFT
Software interrupt set register 00000000
8
Bit 31 30
_SET2
29 28 27
f o r
26 25 24 23 22 21 20 19 18 17 16
e
Nam
2
e
Type
Reset 0 0 0 0
l e a0
s I0
- R 0 0
WO
0 0 0 0 0 0 0 0
Bit
Nam
e
Type
15 14 13
Re Pi B
12 11
P 10 9 8
WO
7 6 5 4 3 2 1 0
Reset 0 0 0 0
a n a 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
31:0
Mnemon
ic
B a n
Name
EINT_SOFT_SE
T2
Description
Write 1 to specific bit sets the corresponding software

interrupt
1000B24 EINT_SOFT
Software interrupt set register 00000000
C _SET3
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type WO
Reset
Bit
Nam
0
15
0
14
0
13
0
12
f
0
11
o r 0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
e
Type
Reset 0 0 0
e
0
a s e 0
I - R 20
0 0
WO
0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
l
Re Pi B
Name P Description
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
31:0
T3
l
Re Pi B
EINT_SOFT_SE
P Write 1 to specific bit sets the corresponding software

interrupt
1000B25 EINT_SOFT
a n a
0
Bit
Nam
e
31 30
_SET4
Ba
29 n 28 27 26
25 24
23 22 21 20 19 18
00000000
17 16
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0
EINT_SOFT_SE
T4
f o r Write 1 to specific bit sets the corresponding software

interrupt
e a s e I - R 2
1000B254
Bit 31
EINT_SOFT
30
_SET5
29
l
Re Pi B
28
P
27 26
25 24 23 22 21 20 19 18
00000000
17 16
Nam
e
a n a EINT_SOFT_SET5[31:16]
n
Type WO
Ba
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
EINT_SOFT_SE Write 1 to specific bit sets the corresponding software
31:0
T5 interrupt
1000B28 EINT_SOFT
f o r Software interrupt clear register 00000000

0
Bit 31 30
_CLR0
29 28
e a s e 27
I - R 2
26 25 24 23 22 21 20 19 18 17 16
l
Nam
P
EINT_SOFT_CLR0[31:16]
Re Pi B
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
a n a EINT_SOFT_CLR0[15:0]
n
Ba
MT7623N
f o r
1000B28
0
EINT_SOFT
_CLR0
e a s e I - R 2
Software interrupt clear register 00000000
e
Type
Reset 0 0 0
l
Re Pi B
0 P
0 0 0 0
WO
0 0 0 0 0 0 0 0
Bit(s Mnemon
a n a
Name Description
n
) ic
Ba
EINT_SOFT_CL Write 1 to specific bit clear the corresponding software
31:0
R0 interrupt
1000B28 EINT_SOFT
4 _CLR1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
f o r EINT_SOFT_CLR1[15:0]
e
Type WO
Reset 0 0 0
l
0
e a s 0
I - R 20 0 0 0 0 0 0 0 0 0 0
Bit(s
)
31:0
Mnemon
ic
Re Pi B
Name
EINT_SOFT_CL P Description
Write 1 to specific bit clear the corresponding software
a
R1 interrupt
n a n
1000B28
8
Bit
Nam
e
31
EINT_SOFT
30
_CLR2
Ba
29 28 27
26 25 24
23 22 21 20 19 18
00000000
17 16
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam EINT_SOFT_CLR2[15:0]
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Name
f o r Description
31:0
EINT_SOFT_CL
R2
e a s e I - R 2 Write 1 to specific bit clear the corresponding software

interrupt
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
1000B28
C
EINT_SOFT
_CLR3
e a s e I - R 2
Bit
Nam
e
Type
31 30 29
l
Re Pi B
28
P
27 26 25 24
WO
23 22 21 20 19 18 17 16
Reset
Bit
0
15
0
14
0
13
a n a
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Nam
e
Type
Reset 0 0
Ba
0
n 0 0 0
0 0
WO
0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
EINT_SOFT_CL Write 1 to specific bit clear the corresponding software
31:0
R3 interrupt
1000B29 EINT_SOFT
0
Bit 31 30
_CLR4
29 28 27
f o r
26 25 24 23 22 21 20 19 18 17 16
e
Nam
2
e
Type
Reset 0 0 0 0
l e a0
s I0
- R 0 0
WO
0 0 0 0 0 0 0 0
Bit
Nam
e
Type
15 14 13
Re Pi B
12 11
P 10 9 8
WO
7 6 5 4 3 2 1 0
Reset 0 0 0 0
a n a 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
31:0
Mnemon
ic
B a n
Name
EINT_SOFT_CL
R4
Description
Write 1 to specific bit clear the corresponding software

interrupt
EINT_SOFT
1000B294 Software interrupt clear register 00000000
_CLR5
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type WO
Reset
Bit
Nam
0
15
0
14
0
13
0
12
f
0
11
o r 0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
e
Type
Reset 0 0 0
e
0
a s e 0
I - R 20
0 0
WO
0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
l
Re Pi B
Name P Description
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
31:0
R5
l
Re Pi B
EINT_SOFT_CL
P Write 1 to specific bit clear the corresponding software

interrupt
1000B30
a n a
0
Bit
Nam
e
31
EINT_POL0
30
Ba
29 n 28 27
External interrupt polarity register
26 25 24
EINT_POL0[31:16]
23 22 21 20 19 18
00000000
17 16
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
EINT_POL0[15:0]
e
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0 EINT_POL0
f o r External interrupt polarity value
e a s e I - R 2
1000B30
4
Bit
Nam
31
EINT_POL1
30 29
l
Re Pi B
28 P
27
26 25 24 23 22 21 20 19 18
00000000
17 16
a
EINT_POL1[31:16]
e
Type
Reset 0 0 0
n a n 0 0 0 0 0
RO
0 0 0 0 0 0 0 0
Ba
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
EINT_POL1[15:0]
e
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0 EINT_POL1 External interrupt polarity value
1000B30
8
Bit 31
EINT_POL2
30 29 28
f
27
o r External interrupt polarity register
26 25 24 23 22 21 20 19 18
00000000
17 16
Nam
e
Type
e a s e I - R 2 EINT_POL2[31:16]
RO
Reset
Bit
Nam
e
0
15
0
14
0
13
l
Re Pi B
0
12
P
0
11
0
10
0
9
0
8
0
7
EINT_POL2[15:0]
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Type
a n a RO
n
Ba
MT7623N
f o r
1000B30
8
EINT_POL2
e a s e I - R 2
External interrupt polarity register 00000000
Reset
Bit(s
0
Mnemon
0 0
l
Re Pi B
0
P
0 0 0 0 0 0 0 0 0 0 0 0
)
31:0
ic
a n a
Name
EINT_POL2
Description
External interrupt polarity value
1000B30 Ba n
EINT_POL3 External interrupt polarity register 00000000
C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
EINT_POL3[31:16]
e
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam EINT_POL3[15:0]
e
Type RO
Reset 0 0 0 0
f
0
o r 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Name
31:0
l
EINT_POL3
Re Pi B P
External interrupt polarity value
1000B310
Bit 31
EINT_POL4
30 29
a n a
28 27
26 25 24 23 22 21 20 19 18
00000000
17 16
Nam
e
Type
Reset
Bit
0
15
0
14 Ba
0
13
n 0
12
0
11
0
10
0
9
EINT_POL4[31:16]
0
8
RO
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Nam EINT_POL4[15:0]
e
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0 EINT_POL4 External interrupt polarity value
f o r
1000B314
Bit 31
EINT_POL5
30 29 28
e a s e 27
I - R 2
26 25 24 23 22 21 20 19 18
00000000
17 16
Nam
e
Type
Reset
Bit
0
15
0
14
0
13
l
Re Pi B
0
12
P
0
11
0
10
0
9
EINT_POL5[31:16]
0
8
RO
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
a n a
n
Ba
MT7623N
f o r
1000B314 EINT_POL5
e a s e I - R 2
l
Nam
P
EINT_POL5[15:0]
Re Pi B
e
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
a n a
Name Description
31:0
Ba nEINT_POL5 External interrupt polarity value
1000B34 EINT_POL_
External interrupt polarity set register 00000000
0 SET0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam EINT_POL_SET0[31:16]
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
r
EINT_POL_SET0[15:0]
e
Type
Reset 0 0 0 0
e f0
o 2
0 0 0
WO
0 0 0 0 0 0 0 0
Bit(s Mnemon
l e
Name
a s I - R Description
)
31:0
ic
Re Pi B
EINT_POL_SET
0 P Write 1 to specific bit sets the polarity of corresponding
external interrupt
a n a
1000B344
Bit
Nam
31
EINT_POL_
30
SET1
Ba
29
n 28 27
26 25 24
EINT_POL_SET1[31:16]
23 22 21 20 19 18
00000000
17 16
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
EINT_POL_SET1[15:0]
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
r
Bit(s Mnemon
Name Description
o
) ic
31:0 EINT_POL_SET1
s e f 2
Write 1 to specific bit sets the polarity of corresponding
external interrupt
l e a P I - R
1000B34
8
EINT_POL_
SET2 Re Pi B External interrupt polarity set register 00000000
a n a
n
Ba
MT7623N
f o r
1000B34
8
EINT_POL_
SET2
e a s e I - R 2
Bit
Nam
e
Type
31 30 29
l
Re Pi B
28
P
27 26 25 24
WO
23 22 21 20 19 18 17 16
Reset
Bit
0
15
0
14
0
13
a n a
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Nam
e
Type
Reset 0 0
Ba
0
n 0 0 0
EINT_POL_SET2[15:0]
0 0
WO
0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
EINT_POL_SET Write 1 to specific bit sets the polarity of corresponding
31:0
2 external interrupt
1000B34 EINT_POL_
C
Bit 31 30
SET3
29 28 27
f o r
26 25 24 23 22 21 20 19 18 17 16
e
Nam
2
e
Type
Reset 0 0 0 0
l e a0
s I0
- R 0 0
WO
0 0 0 0 0 0 0 0
Bit
Nam
e
Type
15 14 13
Re Pi B
12 11
P 10 9 8
EINT_POL_SET3[15:0]
WO
7 6 5 4 3 2 1 0
Reset 0 0 0 0
a n a 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
31:0
Mnemon
ic
B a n
Name
EINT_POL_SET
3
Description

external interrupt
1000B35 EINT_POL_
0 SET4
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type WO
Reset
Bit
Nam
0
15
0
14
0
13
0
12
f
0
11
o r 0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
e
Type
Reset 0 0 0
e
0
a s e 0
I - R 20
EINT_POL_SET4[15:0]
0 0
WO
0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
l
Re Pi B
Name P Description
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
31:0
4
l
Re Pi B
EINT_POL_SET
P Write 1 to specific bit sets the polarity of corresponding

external interrupt
EINT_POL_
a n a
1000B354
Bit
Nam
e
31 30
SET5
Ba
29 n 28 27
26 25 24
23 22 21 20 19 18
00000000
17 16
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
EINT_POL_SET5[15:0]
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0 EINT_POL_SET5
f o r Write 1 to specific bit sets the polarity of corresponding

external interrupt
e a s e I - R 2
1000B38
0
Bit 31
EINT_POL_
30
CLR0
29
l
Re Pi B
28
P
27
External interrupt polarity clear register
26 25 24 23 22 21 20 19 18
00000000
17 16
Nam
e
a n a EINT_POL_CLR0[31:16]
n
Type WO
Ba
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
EINT_POL_CLR0[15:0]
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
EINT_POL_CLR Write 1 to specific bit clear the polarity of corresponding
31:0
1000B38 EINT_POL_
f o r
External interrupt polarity clear register 00000000
4
Bit 31 30
CLR1
29 28
e a s e 27
I - R 2
26 25 24 23 22 21 20 19 18 17 16
l
Nam
P
EINT_POL_CLR1[31:16]
Re Pi B
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
a n a EINT_POL_CLR1[15:0]
n
Ba
MT7623N
f o r
1000B38
4
EINT_POL_
CLR1
e a s e I - R 2
e
Type
Reset 0 0 0
l
Re Pi B
0 P
0 0 0 0
WO
0 0 0 0 0 0 0 0
Bit(s Mnemon
a n a
Name Description
n
) ic
Ba
31:0
1000B38 EINT_POL_
8 CLR2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
f o r EINT_POL_CLR2[15:0]
e
Type WO
Reset 0 0 0
l
0
e a s 0
I - R 20 0 0 0 0 0 0 0 0 0 0
Bit(s
)
31:0
Mnemon
ic
Re Pi B
Name
EINT_POL_CLR P Description
Write 1 to specific bit clear the polarity of corresponding
a
n a n
1000B38
C
Bit
Nam
e
31
EINT_POL_
30
CLR3
Ba
29 28 27
26 25 24
23 22 21 20 19 18
00000000
17 16
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam EINT_POL_CLR3[15:0]
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Name
f o r Description
31:0
EINT_POL_CLR
3
e a s e I - R 2 Write 1 to specific bit clear the polarity of corresponding

external interrupt
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
1000B39
0
EINT_POL_
CLR4
e a s e I - R 2
Bit
Nam
e
Type
31 30 29
l
Re Pi B
28
P
27 26 25 24
WO
23 22 21 20 19 18 17 16
Reset
Bit
0
15
0
14
0
13
a n a
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Nam
e
Type
Reset 0 0
Ba
0
n 0 0 0
EINT_POL_CLR4[15:0]
0 0
WO
0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0
EINT_POL_
1000B394 External interrupt polarity clear register 00000000
Bit 31 30
CLR5
29 28 27
f o r
26 25 24 23 22 21 20 19 18 17 16
e
Nam
2
e
Type
Reset 0 0 0 0
l e a0
s I0
- R 0 0
WO
0 0 0 0 0 0 0 0
Bit
Nam
e
Type
15 14 13
Re Pi B
12 11
P 10 9 8
EINT_POL_CLR5[15:0]
WO
7 6 5 4 3 2 1 0
Reset 0 0 0 0
a n a 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
31:0
Mnemon
ic
B a n
Name
EINT_POL_CLR
5
Description

external interrupt
1000B40 EINT_D0EN Domain 0 external interrupt enable control

00000000
0 0 register
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
EINT_D0EN0[31:16]
e
Type RW
Reset
Bit
Nam
0
15
0
14
0
13
0
12
f
0
11
o r 0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
e
Type
Reset 0 0 0
e
0
a s e 0
I - R 20
EINT_D0EN0[15:0]
0 0
RW
0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
l
Re Pi B
Name P Description
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
31:0
l
Re Pi B
EINT_D0EN0
P Write 1 to specific bit enables the corresponding software
external interrupt in domain 0
1000B40 EINT_D0EN
a n a Domain 0 external interrupt enable control

4
Bit
Nam
e
31 30
1
Ba
29 n 28 27 26
register
25 24
EINT_D0EN1[31:16]
23 22 21 20 19 18
00000000
17 16
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
EINT_D0EN1[15:0]
e
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0 EINT_D0EN1
f o r Write 1 to specific bit enables the corresponding software

e a s e I - R 2
1000B40
8
Bit 31
EINT_D0EN
30
2
29
l
Re Pi B
28
P
Domain 0 external interrupt enable control
27 26
register
25 24 23 22 21 20 19 18
00000000
17 16
Nam
e
a n a EINT_D0EN2[31:16]
n
Type RW
Ba
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
EINT_D0EN2[15:0]
e
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
Write 1 to specific bit enables the corresponding software
31:0 EINT_D0EN2
1000B40 EINT_D0EN
f o r
00000000
C
Bit 31 30
3
29 28
e a s e 27
I - R 2
26
register
25 24 23 22 21 20 19 18 17 16
l
Nam
P
EINT_D0EN3[31:16]
Re Pi B
e
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
n
Ba
MT7623N
f o r
1000B40
C
EINT_D0EN
3
e a s e R 2
I - register
00000000
e
Type
Reset 0 0 0
l
Re Pi B
0 P
0 0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s Mnemon
a n a
Name Description
n
) ic
Ba
31:0 EINT_D0EN3
EINT_D0EN Domain 0 external interrupt enable control

1000B410 00000000
4 register
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
EINT_D0EN4[31:16]
e
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
f o r EINT_D0EN4[15:0]
e
Type RW
Reset 0 0 0
l
0
e a s 0
I - R 20 0 0 0 0 0 0 0 0 0 0
Bit(s
)
31:0
Mnemon
ic
Re Pi B
Name
EINT_D0EN4
P Description
a
n a n
1000B414
Bit
Nam
e
31
EINT_D0EN
30
5
Ba
29 28
27 26
register
25 24
EINT_D0EN5[31:16]
23 22 21 20 19 18
00000000
17 16
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam EINT_D0EN5[15:0]
e
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Name
f o r Description
31:0 EINT_D0EN5
e a s e I - R 2 Write 1 to specific bit enables the corresponding software

l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
1000B42
0
EINT_D1EN
0
e a s e R 2
I - register
00000000
Bit
Nam
e
Type
31 30 29
l
Re Pi B
28
P
27 26 25 24
EINT_D1EN0[31:16]
RW
23 22 21 20 19 18 17 16
Reset
Bit
0
15
0
14
0
13
a n a
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Nam
e
Type
Reset 0 0
Ba
0
n 0 0 0 0
EINT_D1EN0[15:0]
0
RW
0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0 EINT_D1EN0
1000B42 Domain 1 external interrupt enable control

EINT_D1EN1 00000000
4
Bit 31 30 29 28 27
f o r
26
register
25 24 23 22 21 20 19 18 17 16
e
Nam
2
EINT_D1EN1[31:16]
e
Type
Reset 0 0 0 0
l e a0
s I0
- R 0 0
RW
0 0 0 0 0 0 0 0
Bit
Nam
e
Type
15 14 13
Re Pi B
12 11
P 10 9 8
EINT_D1EN1[15:0]
RW
7 6 5 4 3 2 1 0
Reset 0 0 0 0
a n a 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
31:0
Mnemon
ic
B a n
Name
EINT_D1EN1
Description


00000000
8 2 register
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
EINT_D1EN2[31:16]
e
Type RW
Reset
Bit
Nam
0
15
0
14
0
13
0
12
f
0
11
o r 0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
e
Type
Reset 0 0 0
e
0
a s e 0
I - R 20 0
EINT_D1EN2[15:0]
0
RW
0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
l
Re Pi B
Name P Description
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
31:0
l
Re Pi B
EINT_D1EN2
1000B42 EINT_D1EN

C
Bit
Nam
e
31 30
3
Ba
29 n 28 27 26
register
25 24
EINT_D1EN3[31:16]
23 22 21 20 19 18
00000000
17 16
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
EINT_D1EN3[15:0]
e
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0 EINT_D1EN3

e a s e I - R 2
1000B43
0
Bit 31
EINT_D1EN
30
4
29
l
Re Pi B
28
P
27 26
register
25 24 23 22 21 20 19 18
00000000
17 16
Nam
e
n
Type RW
Ba
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
EINT_D1EN4[15:0]
e
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0 EINT_D1EN4
1000B434 EINT_D1EN5
f o r
00000000
Bit 31 30 29 28
e a s e 27
I - R 2
26
register
25 24 23 22 21 20 19 18 17 16
l
Nam
P
EINT_D1EN5[31:16]
Re Pi B
e
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
n
Ba
MT7623N
f o r
1000B434 EINT_D1EN5
e a s e I - R 2
register
00000000
e
Type
Reset 0 0 0
l
Re Pi B
0 P
0 0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s Mnemon
a n a
Name Description
n
) ic
Ba
31:0 EINT_D1EN5

00000000
0 0 register
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
EINT_D2EN0[31:16]
e
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
f o r EINT_D2EN0[15:0]
e
Type RW
Reset 0 0 0
l
0
e a s 0
I - R 20 0 0 0 0 0 0 0 0 0 0
Bit(s
)
31:0
Mnemon
ic
Re Pi B
Name
EINT_D2EN0
P Description
a
n a n
1000B44
4
Bit
Nam
e
31
EINT_D2EN
30
1
Ba
29 28
27 26
register
25 24
EINT_D2EN1[31:16]
23 22 21 20 19 18
00000000
17 16
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam EINT_D2EN1[15:0]
e
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Name
f o r Description
31:0
a s
EINT_D2EN1
e e I - R 2 Write 1 to specific bit enables the corresponding software

l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
1000B44
8
EINT_D2EN
2
e a s e R 2
I - register
00000000
Bit
Nam
e
Type
31 30 29
l
Re Pi B
28
P
27 26 25 24
EINT_D2EN2[31:16]
RW
23 22 21 20 19 18 17 16
Reset
Bit
0
15
0
14
0
13
a n a
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Nam
e
Type
Reset 0 0
Ba
0
n 0 0 0 0
EINT_D2EN2[15:0]
0
RW
0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0 EINT_D2EN2

00000000
C
Bit 31 30
3
29 28 27
f o r
26
register
25 24 23 22 21 20 19 18 17 16
e
Nam
2
EINT_D2EN3[31:16]
e
Type
Reset 0 0 0 0
l e a0
s I0
- R 0 0
RW
0 0 0 0 0 0 0 0
Bit
Nam
e
Type
15 14 13
Re Pi B
12 11
P 10 9 8
EINT_D2EN3[15:0]
RW
7 6 5 4 3 2 1 0
Reset 0 0 0 0
a n a 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
31:0
Mnemon
ic
B a n
Name
EINT_D2EN3
Description


00000000
0 4 register
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
EINT_D2EN4[31:16]
e
Type RW
Reset
Bit
Nam
0
15
0
14
0
13
0
12
f
0
11
o r 0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
e
Type
Reset 0 0 0
e
0
a s e 0
I - R 20 0
EINT_D2EN4[15:0]
0
RW
0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
l
Re Pi B
Name P Description
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
31:0
l
Re Pi B
EINT_D2EN4
EINT_D2EN

1000B454
Bit
Nam
e
31 30
5
Ba
29 n 28 27 26
register
25 24
EINT_D2EN5[31:16]
23 22 21 20 19 18
00000000
17 16
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
EINT_D2EN5[15:0]
e
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0 EINT_D2EN5

e a s e I - R 2
1000B50
0~
1000B50
EINT_DBNC
_3_0[n]
(n=0~3)
l
Re Pi B P External interrupt debounce control
register
00000000
C
Bit 31 30 29
a n a
28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type
Reset
DBNC_SETTIN
0
G3
RO
0
Ba n 0
DB
NC
_R
ST3
RO
0
EN
3
RO
0
DBNC_SETTIN
0
G2
RO
0 0
DB
NC
_R
ST2
RO
0
EN
2
RO
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB
DB
NC
Nam DBNC_SETTIN NC EN DBNC_SETTIN
_R
EN
e G1 _R 1 G0
ST
0
ST1
0
Type RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Name
f o r Description
e a s e I - R 2
Debounce setting
000: 0.5ms
001: 1ms
30:28
3
l
DBNC_SETTING
Re Pi B P
010: 16ms
011: 32ms
100: 64ms
101: 128ms
a
110: 256ms
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
25
l
Re Pi B
DBNC_RST3 P 111: 512ms
Debounce counter reset
0: Negative
1: Positive
24
a n a
EN3
Enable debounce function
0: Disable
Ba n 1: Enable
Debounce setting
000: 0.5ms
001: 1ms
DBNC_SETTING 010: 16ms
22:20 011: 32ms
2
100: 64ms
101: 128ms
110: 256ms
111: 512ms
17 DBNC_RST2 0: Negative
1: Positive
r
16 EN2
e f o 2
0: Disable
1: Enable
s
Debounce setting
l e a P I - R 000: 0.5ms
001: 1ms
Re Pi B
14:12 011: 32ms
1
100: 64ms
101: 128ms
a n a 110: 256ms
111: 512ms
Ba n
DBNC_RST1
0: Negative
1: Positive
8 EN1 0: Disable
1: Enable
Debounce setting
000: 0.5ms
001: 1ms
6:4 011: 32ms
0
100: 64ms
101: 128ms
110: 256ms
f o r 111: 512ms
1 DBNC_RST0
e a s e I - R 2
0: Negative
1: Positive
l
0
Re Pi B
EN0
P 0: Disable
1: Enable
a n a
n
Ba
MT7623N
f o r
1000B60
0~
EINT_DBNC
_SET_3_0[n
e a s e I - R 2
External interrupt debounce control
1000B60
C
Bit 31 30
]
(n=0~3)
29
l
Re Pi B
28
P
27 26 25
register
24 23 22 21 20 19 18
00000000
17 16
a n a DB
NC
_R
EN
DB
NC
_R
EN
n
Nam DBNC_SETTIN
ST
_S DBNC_SETTIN
ST
_S
Ba
e G_SET3
_S
ET G_SET2
_S
ET
3 2
ET ET
3 2
Type WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB
DB
NC
NC EN
EN _R
Nam DBNC_SETTIN _R DBNC_SETTIN _S
_S ST
e G_SET1 ST G_SET0 ET
ET1 _S
_S 0
ET
ET1
0
Reset 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name
f o r Description
) ic
e a s e I - R 2 Debounce setting
30:28 l
Re Pi B
DBNC_SETTING
_SET3 P
000: 0.5ms
001: 1ms
010: 16ms
011: 32ms
100: 64ms
a n a 101: 128ms
110: 256ms
n
111: 512ms
Ba
DBNC_RST_SET
25 0: Negative
3
1: Positive
24 EN_SET3 0: Disable
1: Enable
Debounce setting
000: 0.5ms
001: 1ms
22:20 011: 32ms
_SET2
100: 64ms
101: 128ms
f o r 110: 256ms
111: 512ms
17
DBNC_RST_SET
2
e a s e I - R 2
0: Negative
1: Positive
16
l
Re Pi B
EN_SET2
P Enable debounce function
0: Disable
1: Enable
a
14:12 DBNC_SETTING Debounce setting
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
_SET1
Re Pi B P 000: 0.5ms
001: 1ms
010: 16ms
011: 32ms
a
100: 64ms
n a n 101: 128ms
110: 256ms
111: 512ms
Ba
DBNC_RST_SET
9 0: Negative
1
1: Positive
1: Enable
Debounce setting
000: 0.5ms
001: 1ms
6:4 011: 32ms
_SET0
100: 64ms
r
101: 128ms
o
110: 256ms
DBNC_RST_SET
s e f 2
111: 512ms
1
0
l e a P I - R 0: Negative
1: Positive
Re Pi B
1: Enable
a n a
1000B70
0~
1000B70
C
EINT_DBNC
_CLR_3_0[n
]
(n=0~3) Ba n External interrupt debounce control
register
00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB EN DB EN
Nam DBNC_SETTIN NC _C DBNC_SETTIN NC _C
e G_CLR_CLR3 _R LR G_CLR_CLR2 _R LR
ST3 3 ST2 2
Reset 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB
DB EN EN
NC
r
Nam DBNC_SETTIN NC _C DBNC_SETTIN _C
_R
e G_CLR_CLR1
e f o 2
_R
ST1
LR
1
G_CLR_CLR0
ST
0
LR
0
s
a R
Reset 0 0 0 0 0 0 0 0 0 0
l e P I -
Re Pi B
Bit(s Mnemon
Name Description
) ic
30:28 DBNC_SETTING Debounce setting
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
l
_CLR_CLR3
Re Pi B P 000: 0.5ms
001: 1ms
010: 16ms
011: 32ms
a
100: 64ms
n a n 101: 128ms
110: 256ms
111: 512ms
Ba
1: Positive
24 EN_CLR3 0: Disable
1: Enable
Debounce setting
000: 0.5ms
001: 1ms
22:20 011: 32ms
_CLR_CLR2
100: 64ms
r
101: 128ms
o
110: 256ms
s e f 2
111: 512ms
17 DBNC_RST2
l e a P I - R 0: Negative
1: Positive
Re Pi B
1: Enable
a n a Debounce setting
000: 0.5ms
n
001: 1ms
Ba
14:12 011: 32ms
_CLR_CLR1
100: 64ms
101: 128ms
110: 256ms
111: 512ms
1: Positive
1: Enable
Debounce setting
f o r 000: 0.5ms
001: 1ms
010: 16ms
6:4
DBNC_SETTING
_CLR_CLR0
e a s e I - R 2 011: 32ms
100: 64ms
l
101: 128ms
1
Re Pi B
DBNC_RST0
P 110: 256ms
111: 512ms
a
0: Negative
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
0
l
Re Pi B
EN_CLR0 P 1: Positive
0: Disable
1: Enable
a n a
Ba n
f o r
e a s e I - R 2
l
Re Pi B P
a n a
Ba n
f o r
e a s e I - R 2
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
6 System Interrupt Controller
e a s e I - R 2
6.1 Introduction
l
Re Pi B P
a n a
For CA7 processor which has embedded interrupt controllers (GIC), the part of the MCUSYS will
n
need to keep feeding clock and power to make the interrupt functional. However, due to
Ba
power/leakage overhead introduced by higher clock ratio and deep submicron processes, reserving
an always on (or frequently turned on) domain in MCUSYS has become power ineffective. The
system interrupt controller (SYS_CIRQ) is a low power interrupt controller is designed to work outside
MCUSYS as a second level interrupt controller. With SYS_CIRQ, MCUSYS can be completely turned
off to improve the system power consumption without losing interrupts.
6.2 Feature list

SYS_CIRQ supports interrupts which can configure the following attributes individually.
 Polarity inversion
f o r
 Edge/level trigger selection
e a s e I - R 2
l
Re Pi B P
The interrupts will feed through SYS_C and connect to GIC in MCUSYS. When SYS_CIRQ is
enabled, it will record the edge-sensitive interrupts and generate a pulse signal to CPU GIC when the
flush command is executed.
a n a
6.3 Block Diagram
Ba n
ext_int[168:0] MCUSYS (Vsoc)
arm_ck, fix_ck
ext_int[167:0] CORE CPUSYS_WRAP (Vcore)

SYS CPU I/F
...
...
CIRQ GIC
CPUSYS (Vcore) CKGEN
APB
D
FALCON CPU0 FALCON CPU1 B DBGAPB
G
Interrupt will be lost if

SYS ext_int[168:0]
ext_int[167:0] GIC SCU powered down during WFI
CIRQ
sys_cirq_irq
infra
f o r L2C
SPM
e a s e I - R 2 ASYNC Vcore
l
Infra_ao
Re Pi B P AXI0
ASYNC Vsoc
AXI0 ACP
mcucfgreg
APB
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
Figure 6-1: System level block diagram of System Interrupt Controller
l
Re Pi B P
The SYS_CIRQ controller is integrated in between MCUSYS and other interrupt sources as the
second level interrupt controller. All interrupts are fed through SYS_CIRQ controller then bypassed to
MCUSYS. In normal mode (where MCUSYS GIC is active), SYS_CIRQ is disabled and interrupts will
n a
directly issued to MCUSYS. When MCUSYS enters the sleep mode, where GIC is power downed.
a
SYS_CIRQ controller will be enabled and monitor all edge-trigger interrupts (only edge-triggered
Ba n
interrupt will be lost in this scenario). When an edge-trigger interrupt is triggered, it will be recorded in
the SYS_CIRQ_STA register and can be restored to GIC by SW context restore or the SYS_CIRQ
flush function.
SYS _CIRQ
APB _I/F SYS _ CIRQ _REG
y q
k s ti ri n
r
sa n ra c o
e _ c
o
m s lo s _
f
p ys
169
e a s e I - R 2 169
l
Re Pi B P
SYS _CIRQ _ CON
event _b
a n a
Figure 6-2: Block diagram of system interrupt controller
6.4 Ba n
Register Definition
Module name: sys_cirq_reg Base address: (+10204000h)
Address Name Widt Register Function

h
10204000 CIRQ_STA0 32 System CIRQ status register
1020400C
10204010
CIRQ_STA3
CIRQ_STA4
f o r
32
32
System CIRQ status register
10204014
10204040
CIRQ_STA5
CIRQ_ACK0
e a s e 32
32
I - R 2
System CIRQ acknowledge register
10204044
10204048
1020404C
CIRQ_ACK1
CIRQ_ACK2
CIRQ_ACK3
l
Re Pi B P
32
32
32
a
10204050 CIRQ_ACK4 32 System CIRQ acknowledge register
Ba
MT7623N
f o r
e a s e I - R 2
10204054
10204080
10204084
10204088
CIRQ_ACK5
CIRQ_MASK0
CIRQ_MASK1
CIRQ_MASK2
l
Re Pi B P
32
32
32
32
System CIRQ mask register
1020408C CIRQ_MASK3
a n a 32 System CIRQ mask register
n
10204090 CIRQ_MASK4 32 System CIRQ mask register
Ba
10204094 CIRQ_MASK5 32 System CIRQ mask register
CIRQ_MASK_
102040C0 SET0 32 System CIRQ mask set register
102040C4 CIRQ_MASK_ 32 System CIRQ mask set register

SET1
CIRQ_MASK_
102040C8 SET2 32 System CIRQ mask set register
102040CC CIRQ_MASK_ 32 System CIRQ mask set register

SET3
CIRQ_MASK_
102040D0 SET4 32 System CIRQ mask set register
CIRQ_MASK_
102040D4 SET5 32 System CIRQ mask set register
10204100 CIRQ_MASK_
CLR0
f o r
32 System CIRQ mask set register
10204104
CIRQ_MASK_
CLR1
e a s e 32
I - R 2 System CIRQ mask set register
l
CIRQ_MASK_
P
10204108 32 System CIRQ mask set register
Re Pi B
CLR2
CIRQ_MASK_
1020410C CLR3 32 System CIRQ mask set register
a
10204110 CIRQ_MASK_ 32 System CIRQ mask set register
n
CLR4
10204114 CIRQ_MASK_
CLR5
n a 32 System CIRQ mask set register
10204140
10204144
10204148
1020414C
Ba
CIRQ_SENS0
CIRQ_SENS1
CIRQ_SENS2
CIRQ_SENS3
32
32
32
32
System CIRQ sensitivity register
10204150 CIRQ_SENS4 32 System CIRQ sensitivity register
10204154 CIRQ_SENS5 32 System CIRQ sensitivity register
10204180 CIRQ_SENS_ 32 System CIRQ sensitivity set register

SET0
CIRQ_SENS_
10204184 SET1 32 System CIRQ sensitivity set register
10204188 CIRQ_SENS_ 32 System CIRQ sensitivity set register
1020418C
SET2
CIRQ_SENS_
f o r
32 System CIRQ sensitivity set register
e
SET3
10204190 CIRQ_SENS_
SET4
l e a s 32
I - R 2 System CIRQ sensitivity set register
10204194
102041C0
CIRQ_SENS_
SET5
CIRQ_SENS_
CLR0
Re Pi B P 32
32
System CIRQ sensitivity set register
System CIRQ sensitivity clear register
a n a
n
Ba
MT7623N
f o r
e a s e
I - R 2
102041C4
102041C8
CIRQ_SENS_
CLR1
CIRQ_SENS_
CLR2
l
Re Pi B P 32
32
102041CC
CIRQ_SENS_
CLR3
a n a 32 System CIRQ sensitivity clear register
n
102041D0 CIRQ_SENS_ 32 System CIRQ sensitivity clear register
Ba
CLR4
CIRQ_SENS_
102041D4 CLR5 32 System CIRQ sensitivity clear register
10204200 CIRQ_POL0 32 External interrupt polarity register

1020420C CIRQ_POL3 32 External interrupt polarity register
CIRQ_POL_S
10204240 ET0 32 External interrupt polarity set register
CIRQ_POL_S
r
10204244 ET1 32 External interrupt polarity set register
10204248 CIRQ_POL_S
ET2
e f o 32
2
1020424C
CIRQ_POL_S
ET3
l e a s I -
32
R External interrupt polarity set register
10204250
10204254
CIRQ_POL_S
ET4
CIRQ_POL_S
ET5 Re Pi B P 32
32
10204280 CIRQ_POL_C
LR0
a n a 32 External interrupt polarity clear register
10204284
10204288
CIRQ_POL_C
LR1
CIRQ_POL_C
LR2
Ba n 32
32
1020428C CIRQ_POL_C 32 External interrupt polarity clear register

LR3
CIRQ_POL_C
10204290 LR4 32 External interrupt polarity clear register
10204294 CIRQ_POL_C 32 External interrupt polarity clear register

LR5
10204300 CIRQ_CON 32 Sytem CIRQ control register
f o r
10204000
Bit 31
CIRQ_STA0
30 29 28
e a s e 27
I - R 226
25 24 23 22 21 20 19 18
00000000
17 16
l
Mne CIRQ_PEND0[31:16]
Type
Reset
Bit
Mne
15
0 0
14
0
13
Re Pi B
0
12 P
0
11
0
10
0
9
0
RO
8
0
CIRQ_PEND0[15:0]
0
7 6
0
5
0
4
0
3
0
2
0
1
0
0
a n a
n
Ba
MT7623N
f o r
10204000 CIRQ_STA0
e a s e I - R 2 System CIRQ status register 00000000
l
Type RO
Reset
Bit(s
0
Mnemon
0 0
Re Pi B
0
P
0 0 0 0 0 0 0 0 0 0 0 0
a
Name Description
) ic
31:0
n a n
CIRQ_PEND0
Each bit read as 1 indicates the corresponding system
CIRQ is pending
10204004
Bit 31
CIRQ_STA1
30
Ba
29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Name
f o r Description
31:0 CIRQ_PEND1
e a s e I - R 2 Each bit read as 1 indicates the corresponding system

CIRQ is pending
10204008 CIRQ_STA2
l
Re Pi B P System CIRQ status register 00000000
Bit
Mne
31 30 29
a n a
28 27 26 25 24
CIRQ_PEND2[31:16]
23 22 21 20 19 18 17 16
Type
Reset
Bit
Mne
Type
0
15
0
14
Ba
0
13 n 0
12
0
11
0
10
0
9
0
RO
8
0
CIRQ_PEND2[15:0]
RO
0
7 6
0
5
0
4
0
3
0
2
0
1
0
0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0 CIRQ_PEND2
CIRQ is pending
1020400
CIRQ_STA3
f o r System CIRQ status register 00000000
e
C
Bit
Mne
31 30 29 28
l e
27
a s 26
I - R 2 25 24
CIRQ_PEND3[31:16]
23 22 21 20 19 18 17 16
P
Type RO
Re Pi B
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
a
Type RO
B a
MT7623N
f o r
1020400
C
CIRQ_STA3
e a s e I - R 2 System CIRQ status register 00000000
Reset
Bit(s
0
Mnemon
0 0
l
Re Pi B
0
P
0 0 0 0 0 0 0 0 0 0 0 0
) ic
a n a
Name Description

31:0
n
CIRQ_PEND3
Ba
CIRQ is pending
10204010 CIRQ_STA4 System CIRQ status register 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name
f o r Description
e
) ic
31:0 CIRQ_PEND4
l e a s I - R 2 Each bit read as 1 indicates the corresponding system

CIRQ is pending
10204014 CIRQ_STA5 Re Pi B P System CIRQ status register 00000000

Bit
Nam
31 30 29
a n a
28 27 26 25 24 23 22 21 20 19 18 17 16
e
Type
Reset
Bit
Nam
15 14
Ba
13
n 12 11 10 9 8 7 6 5 4 3 2 1 0
CIRQ_STA5
e
Type RO
Reset 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
8:0 CIRQ_STA5
CIRQ is pending
f o r
10204040
Bit 31
CIRQ_ACK0
30 29 28
e a s e 27
I - R 2
26 25 24 23 22 21 20 19 18
00000000
17 16
Nam
e
Type
Reset
Bit
0
15
0
14
0
13
l
Re Pi B
0
12
P
0
11
0
10
0
9
CIRQ_ACK0[31:16]
0
8
WO
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
a n a
n
Ba
MT7623N
f o r
10204040 CIRQ_ACK0
e a s e I - R 2
System CIRQ acknowledge register 00000000
l
Nam
P
CIRQ_ACK0[15:0]
Re Pi B
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
a n a
Name Description
31:0
Ba nCIRQ_ACK0
system CIRQ
10204044 CIRQ_ACK1 System CIRQ acknowledge register 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
CIRQ_ACK1[31:16]
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam CIRQ_ACK1[15:0]
r
e
Type
Reset 0 0 0 0
e f0
o 2
0 0 0
WO
0 0 0 0 0 0 0 0
Bit(s Mnemon
l e
Name
a s I - R Description
P
) ic
31:0
Re Pi B
CIRQ_ACK1
system CIRQ
a n a
10204048
Bit
Nam
e
Type
31
CIRQ_ACK2
30
Ba
29 n 28 27
26 25 24
CIRQ_ACK2[31:16]
WO
23 22 21 20 19 18
00000000
17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam CIRQ_ACK2[15:0]
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0 CIRQ_ACK2
f o r Write 1 to specific bit acknowledges the corresponding

system CIRQ
e a s e I - R 2
1020404C
Bit
Nam
31
CIRQ_ACK3
30 29 l
Re Pi B
28 P
27
26 25 24
CIRQ_ACK3[31:16]
23 22 21 20 19 18
00000000
17 16
a n a
n
Ba
MT7623N
f o r
1020404C CIRQ_ACK3
e a s e I - R 2
System CIRQ acknowledge register 00000000
l
Type WO
Reset
Bit
Nam
e
0
15
0
14
0
13
Re Pi B
0
12
P
0
11
0
10
0
9
0
8
CIRQ_ACK3[15:0]
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Type
Reset 0 0 0
a n a
0 0 0 0 0
WO
0 0 0 0 0 0 0 0
Bit(s
)
31:0
Mnemon
ic
Ba n Name
CIRQ_ACK3
Description

system CIRQ
10204050 CIRQ_ACK4 System CIRQ acknowledge register 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
CIRQ_ACK4[31:16]
e
Type WO
Reset
Bit
Nam
0
15
0
14
0
13
0
12
0
11
f o r 0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
e
CIRQ_ACK4[15:0]
2
e
Type
Reset 0 0 0
l e
0
a s 0
I - R 0 0 0
WO
0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Re Pi B
Name P Description
31:0
n a
CIRQ_ACK4
a
system CIRQ
10204054 CIRQ_ACK5
Ba n System CIRQ acknowledge register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam CIRQ_ACK5
e
Type WO
Reset 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name
f o r Description
e
) ic
8:0
a
CIRQ_ACK5
l e s I - R 2 Write 1 to specific bit acknowledges the corresponding

system CIRQ
Re Pi B P
a n a
n
Ba
MT7623N
f o r
10204080
CIRQ_MASK
0
e a s e I - R 2 System CIRQ mask register FFFFFFFF
Bit
Nam
e
Type
31 30 29
l
Re Pi B
28
P
27 26 25 24
CIRQ_MASK0[31:16]
RO
23 22 21 20 19 18 17 16
Reset
Bit
1
15
1
14
1
13
a n a
1
12
1
11
1
10
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
Nam
e
Type
Reset 1 1
Ba
1
n 1 1 1
CIRQ_MASK0[15:0]
1 1
RO
1 1 1 1 1 1 1 1
Bit(s Mnemon
Name Description
) ic
31:0 CIRQ_MASK0 system CIRQ mask value
CIRQ_MASK
10204084 System CIRQ mask register FFFFFFFF
1
Bit
Nam
31 30 29 28 27
f o r 26 25 24
CIRQ_MASK1[31:16]
23 22 21 20 19 18 17 16
e
e
Type
Reset
Bit
1
15
1
14
1
13
l
1
e
12
a s 1
11
I - R 21
10
1
9
1
8
RO
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
Nam
e
Type
Reset 1 1 1
Re Pi B
1
P
1 1
CIRQ_MASK1[15:0]
1 1
RO
1 1 1 1 1 1 1 1
Bit(s Mnemon
a n a
)
31:0
ic
Ba n Name
CIRQ_MASK1
Description
system CIRQ mask value
CIRQ_MASK
2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam CIRQ_MASK2[31:16]
e
Type RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type
f o r CIRQ_MASK2[15:0]
RO
Reset 1 1 1 1
e a s e 1
I - R 2
1 1 1 1 1 1 1 1 1 1 1
Bit(s
)
31:0
Mnemon
ic
l
Re Pi B
Name
CIRQ_MASK2 P Description
system CIRQ mask value
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
1020408C
Bit
Nam
31
CIRQ_MASK
30
3
29 l
Re Pi B
28 P
27 26
25 24
CIRQ_MASK3[31:16]
23 22 21 20 19 18
FFFFFFFF
17 16
e
Type
Reset 1 1 1
a n a
1 1 1 1 1
RO
1 1 1 1 1 1 1 1
Bit
Nam
e
Type
Reset
15
1
14
1
13
Ba
1
n 12
1
11
1
10
1
9 8
CIRQ_MASK3[15:0]
1 1
RO
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
Bit(s Mnemon
Name Description
) ic
CIRQ_MASK
r
4
Bit
Nam
31 30 29 28
e f
27
o 26
2
25 24 23 22 21 20 19 18 17 16
s
CIRQ_MASK4[31:16]
e
Type
Reset 1 1 1
l e
1
a P
1
I - R 1 1 1
RO
1 1 1 1 1 1 1 1
Re Pi B
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
CIRQ_MASK4[15:0]
e
Type
a
RO
n
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
n a
Ba
Bit(s Mnemon
Name Description
) ic
CIRQ_MASK
10204094 System CIRQ mask register 000000FF
5
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type
Reset
Bit
Nam
15 14 13 12 11
f o r 10 9 8 7 6 5 4
CIRQ_MASK5
3 2 1 0
e
e
Type
Reset
l e a s I - R 2 0 1 1 1
RO
1 1 1 1 1
Bit(s
)
Mnemon
ic
Re Pi B
Name
P Description
a
Ba
MT7623N
f o r
e a s e I - R 2
102040C
0
Bit 31
CIRQ_MASK
30
_SET0
29
l
Re Pi B
28
P
27 26
System CIRQ mask set register
25 24 23 22 21 20 19 18
00000000
17 16
Nam
e
a n a CIRQ_MASK_SET0[31:16]
n
Type WO
Ba
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
CIRQ_MASK_SET0[15:0]
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
CIRQ_MASK_SE Write 1 to specific bit sets the mask of corresponding
31:0
T0 system CIRQ
102040C4
CIRQ_MASK
f o r System CIRQ mask set register 00000000
Bit 31 30
_SET1
29 28
e a s e 27
I - R 2
26 25 24 23 22 21 20 19 18 17 16
l
Nam
P
Re Pi B
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type
WO
Reset
Bit(s
)
0
Mnemon
ic
0
Ba
0
n 0
Name
0 0 0 0 0 0 0
Description
0 0 0 0 0

31:0
T1 system CIRQ
CIRQ_MASK
102040C8 System CIRQ mask set register 00000000
_SET2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type
f o r CIRQ_MASK_SET2[31:16]
WO
Reset
Bit
Nam
0
15
0
14
0
13
0
12
e a s e 0
11
I - R 2
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
e
Type
Reset 0 0 0 l
Re Pi B
0
P
0 0
0 0
WO
0 0 0 0 0 0 0 0
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
31:0
T2
l
Re Pi B
CIRQ_MASK_SE
P Write 1 to specific bit sets the mask of corresponding

system CIRQ
102040C CIRQ_MASK
a n a
C
Bit
Nam
e
31 30
_SET3
Ba
29 n 28 27 26
25 24
23 22 21 20 19 18
00000000
17 16
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0
CIRQ_MASK_SE
T3
f o r Write 1 to specific bit sets the mask of corresponding

system CIRQ
e a s e I - R 2
102040D
0
Bit 31
CIRQ_MASK
30
_SET4
29
l
Re Pi B
28
P
27 26
25 24 23 22 21 20 19 18
00000000
17 16
Nam
e
n
Type WO
Ba
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0
T4 system CIRQ
102040D CIRQ_MASK
f o r System CIRQ mask set register 00000000

4
Bit 31 30
_SET5
29 28
e a s e 27
I - R 2
26 25 24 23 22 21 20 19 18 17 16
l
Nam
e
Type
Reset
Bit 15 14 13
Re Pi B
12
P
11 10 9 8 7 6 5 4 3 2 1 0
Nam
a n a CIRQ_MASK_SET5
n
Ba
MT7623N
f o r
102040D
4
CIRQ_MASK
_SET5
e a s e I - R 2 System CIRQ mask set register 00000000
e
Type
Reset
l
Re Pi B P 0 0 0 0
WO
0 0 0 0 0
Bit(s Mnemon
a n a
Name Description
n
) ic
Ba
8:0
T5 system CIRQ
CIRQ_MASK
10204100 System CIRQ mask set register 00000000
_CLR0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
CIRQ_MASK_CLR0[31:16]
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
f o r CIRQ_MASK_CLR0[15:0]
e
Type WO
Reset 0 0 0
l
0
e a s 0
I - R 20 0 0 0 0 0 0 0 0 0 0
Bit(s
)
31:0
Mnemon
ic
Re Pi B
Name
CIRQ_MASK_CL P Description
a
R0 system CIRQ
n a n
10204104
Bit
Nam
e
31
CIRQ_MASK
30
_CLR1
Ba
29 28 27 26
25 24
23 22 21 20 19 18
00000000
17 16
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam CIRQ_MASK_CLR1[15:0]
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Name
f o r Description
31:0
CIRQ_MASK_CL
R1
e a s e I - R 2 Write 1 to specific bit clear the mask of corresponding

system CIRQ
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
10204108
CIRQ_MASK
_CLR2
e a s e I - R 2 System CIRQ mask set register 00000000
Bit
Nam
e
Type
31 30 29
l
Re Pi B
28
P
27 26 25 24
WO
23 22 21 20 19 18 17 16
Reset
Bit
0
15
0
14
0
13
a n a
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Nam
e
Type
Reset 0 0
Ba
0
n 0 0 0
0 0
WO
0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
CIRQ_MASK_CL Write 1 to specific bit clear the mask of corresponding
31:0
R2 system CIRQ
CIRQ_MASK
1020410C System CIRQ mask set register 00000000
Bit 31 30
_CLR3
29 28 27
f o r
26 25 24 23 22 21 20 19 18 17 16
e
Nam
2
e
Type
Reset 0 0 0 0
l e a0
s I0
- R 0 0
WO
0 0 0 0 0 0 0 0
Bit
Nam
e
Type
15 14 13
Re Pi B
12 11
P 10 9 8
WO
7 6 5 4 3 2 1 0
Reset 0 0 0 0
a n a 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
31:0
Mnemon
ic
B a n
Name
CIRQ_MASK_CL
R3
Description

system CIRQ
CIRQ_MASK
10204110 System CIRQ mask set register 00000000
_CLR4
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type WO
Reset
Bit
Nam
0
15
0
14
0
13
0
12
f
0
11
o r 0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
e
Type
Reset 0 0 0
e
0
a s e 0
I - R 20
0 0
WO
0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
l
Re Pi B
Name P Description
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
31:0
R4
l
Re Pi B
CIRQ_MASK_CL
P Write 1 to specific bit clear the mask of corresponding

system CIRQ
CIRQ_MASK
a n a
10204114
Bit
Nam
e
31 30
_CLR5
Ba
29 n 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
CIRQ_MASK_CLR5
e
Type WO
Reset 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
8:0
CIRQ_MASK_CL
R5
f o r Write 1 to specific bit clear the mask of corresponding

system CIRQ
e a s e I - R 2
10204140
Bit 31
CIRQ_SENS
30
0
29
l
Re Pi B
28
P
27
26 25 24 23 22 21 20 19 18
FFFFFFE3
17 16
Nam
e
a n a CIRQ_SENS0[31:16]
n
Type RO
Ba
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
CIRQ_SENS0[15:0]
e
Type RO
Reset 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1
Bit(s Mnemon
Name Description
) ic
31:0 CIRQ_SENS0 system CIRQ sensitivity value
10204144
Bit 31
CIRQ_SENS1
30 29 28 27
f o r
26 25 24 23 22 21 20 19 18
FEFC7FFF
17 16
Nam
e
Type
e a s e I - R 2 CIRQ_SENS1[31:16]
RO
Reset
Bit
Nam
e
1
15
1
14
1
13
1
12
l
Re Pi B
1
11
P
1
10
1
9
0
8
CIRQ_SENS1[15:0]
1
7
1
6
1
5
1
4
1
3
1
2
0
1
0
0
a
Type RO
B a
MT7623N
f o r
10204144 CIRQ_SENS1
e a s e I - R 2System CIRQ sensitivity register FEFC7FFF
l
Reset 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s
)
Mnemon
ic Re Pi B
Name P Description
31:0
n a
CIRQ_SENS1
a
system CIRQ sensitivity value
10204148
CIRQ_SENS
2 Ba n System CIRQ sensitivity register FFEFDFFF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
CIRQ_SENS2[31:16]
e
Type RO
Reset 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam CIRQ_SENS2[15:0]
e
Type RO
Reset 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s Mnemon
f o r
)
31:0
ic
Name
a s
CIRQ_SENS2
e e I - R 2
Description
CIRQ_SENS
l
Re Pi B P
1020414C
Bit 31 30
3
29
a n a
28 27
26 25 24 23 22 21 20 19 18
FFFFFFFF
17 16
Nam
e
Type
Reset
Bit
1
15
1
14 Ba
1
13
n 1
12
1
11
1
10
CIRQ_SENS3[31:16]
1
9
1
8
RO
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
Nam CIRQ_SENS3[15:0]
e
Type RO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s Mnemon
Name Description
) ic
f o r
10204150
CIRQ_SENS
4
e a s e I - R 2System CIRQ sensitivity register 0777FFFF
Bit
Nam
e
Type
31 30 29
l28
Re Pi B P
27 26 25 24
CIRQ_SENS4[31:16]
RO
23 22 21 20 19 18 17 16
a
Reset 0 0 0 0 0 1 1 1 0 1 1 1 0 1 1 1
Ba
MT7623N
f o r
10204150
CIRQ_SENS
4
e a s e I - R 2System CIRQ sensitivity register 0777FFFF
Bit
Nam
e
Type
15 14 13
l
Re Pi B
12
P
11 10 9 8
CIRQ_SENS4[15:0]
RO
7 6 5 4 3 2 1 0
Reset 1 1 1
a n a
1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s
)
31:0
Mnemon
ic
Ba n Name
CIRQ_SENS4
Description
CIRQ_SENS
10204154 System CIRQ sensitivity register 00000000
5
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type
Reset
Bit
Nam
15 14 13 12 11
f o r 10 9 8 7 6 5 4
CIRQ_SENS5
3 2 1 0
e
e
Type
Reset
l e a s I - R 2 0 0 0 0
RO
0 0 0 0 0
Bit(s
)
Mnemon
ic
Re Pi B
Name
P Description
a
n a n
10204180
Bit
Nam
e
31
CIRQ_SENS
30
_SET0
Ba
29 28 27
26 25 24
CIRQ_SENS_SET0[31:16]
23 22 21 20 19 18
00000000
17 16
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam CIRQ_SENS_SET0[15:0]
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Name
f o r Description
31:0
CIRQ_SENS_SE
T0
e a s e I - R 2 Write 1 to specific bit sets the sensitivity of corresponding

system CIRQ
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
10204184
CIRQ_SENS
_SET1
e a s e I - R 2
System CIRQ sensitivity set register 00000000
Bit
Nam
e
Type
31 30 29
l
Re Pi B
28
P
27 26 25 24
WO
23 22 21 20 19 18 17 16
Reset
Bit
0
15
0
14
0
13
a n a
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Nam
e
Type
Reset 0 0
Ba
0
n 0 0 0
0 0
WO
0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
CIRQ_SENS_SE Write 1 to specific bit sets the sensitivity of corresponding
31:0
T1 system CIRQ
CIRQ_SENS
10204188 System CIRQ sensitivity set register 00000000
Bit 31 30
_SET2
29 28 27
f o r
26 25 24 23 22 21 20 19 18 17 16
e
Nam
2
e
Type
Reset 0 0 0 0
l e a0
s I0
- R 0 0
WO
0 0 0 0 0 0 0 0
Bit
Nam
e
Type
15 14 13
Re Pi B
12 11
P 10 9 8
WO
7 6 5 4 3 2 1 0
Reset 0 0 0 0
a n a 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
31:0
Mnemon
ic
B a n
Name
CIRQ_SENS_SE
T2
Description
Write 1 to specific bit sets the sensitivity of corresponding

system CIRQ
CIRQ_SENS
1020418C System CIRQ sensitivity set register 00000000
_SET3
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type WO
Reset
Bit
Nam
0
15
0
14
0
13
0
12
f
0
11
o r 0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
e
Type
Reset 0 0 0
e
0
a s e 0
I - R 20
0 0
WO
0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
l
Re Pi B
Name P Description
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
31:0
T3
l
Re Pi B
CIRQ_SENS_SE
P Write 1 to specific bit sets the sensitivity of corresponding

system CIRQ
CIRQ_SENS
a n a
10204190
Bit
Nam
e
31 30
_SET4
Ba
29 n 28 27
26 25 24
23 22 21 20 19 18
00000000
17 16
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0
CIRQ_SENS_SE
T4
f o r Write 1 to specific bit sets the sensitivity of corresponding

system CIRQ
e a s e I - R 2
10204194
Bit 31
CIRQ_SENS
30
_SET5
29
l
Re Pi B
28
P
27
26 25 24 23 22 21 20 19 18
00000000
17 16
Nam
e
a n a
n
Type
Ba
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
CIRQ_SENS_SET5
e
Type WO
Reset 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
CIRQ_SENS_SE Write 1 to specific bit sets the sensitivity of corresponding
8:0
T5 system CIRQ
102041C0
CIRQ_SENS
f o rSystem CIRQ sensitivity clear register 00000000
Bit 31 30
_CLR0
29 28
e a s e 27
I - R 2
26 25 24 23 22 21 20 19 18 17 16
l
Nam
P
CIRQ_SENS_CLR0[31:16]
Re Pi B
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
a n a CIRQ_SENS_CLR0[15:0]
n
Ba
MT7623N
f o r
102041C0
CIRQ_SENS
_CLR0
e a s e I - R 2
System CIRQ sensitivity clear register 00000000
e
Type
Reset 0 0 0
l
Re Pi B
0 P
0 0 0 0
WO
0 0 0 0 0 0 0 0
Bit(s Mnemon
a n a
Name Description
n
) ic
Ba
CIRQ_SENS_CL Write 1 to specific bit clear the sensitivity of
31:0
R0 corresponding system CIRQ
CIRQ_SENS
102041C4 System CIRQ sensitivity clear register 00000000
_CLR1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
f o r CIRQ_SENS_CLR1[15:0]
e
Type WO
Reset 0 0 0
l
0
e a s 0
I - R 20 0 0 0 0 0 0 0 0 0 0
Bit(s
)
31:0
Mnemon
ic
Re Pi B
Name
CIRQ_SENS_CL P Description
a
n a n
102041C8
Bit
Nam
e
31
CIRQ_SENS
30
_CLR2
Ba
29 28 27
26 25 24
23 22 21 20 19 18
00000000
17 16
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam CIRQ_SENS_CLR2[15:0]
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Name
f o r Description
31:0
CIRQ_SENS_CL
R2
e a s e I - R 2 Write 1 to specific bit clear the sensitivity of

corresponding system CIRQ
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
102041CC
CIRQ_SENS
_CLR3
e a s e I - R 2
System CIRQ sensitivity clear register 00000000
Bit
Nam
e
Type
31 30 29
l
Re Pi B
28
P
27 26 25 24
WO
23 22 21 20 19 18 17 16
Reset
Bit
0
15
0
14
0
13
a n a
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Nam
e
Type
Reset 0 0
Ba
0
n 0 0 0
0 0
WO
0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
CIRQ_SENS_CL Write 1 to specific bit clear the sensitivity of
31:0
CIRQ_SENS
102041D0 System CIRQ sensitivity clear register 00000000
Bit 31 30
_CLR4
29 28 27
f o r
26 25 24 23 22 21 20 19 18 17 16
e
Nam
2
e
Type
Reset 0 0 0 0
l e a0
s I0
- R 0 0
WO
0 0 0 0 0 0 0 0
Bit
Nam
e
Type
15 14 13
Re Pi B
12 11
P 10 9 8
WO
7 6 5 4 3 2 1 0
Reset 0 0 0 0
a n a 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
31:0
Mnemon
ic
B a n
Name
CIRQ_SENS_CL
R4
Description

CIRQ_SENS
102041D4 System CIRQ sensitivity clear register 00000000
_CLR5
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type
Reset
Bit
Nam
15 14 13 12 11
f o r
10 9 8 7 6 5 4 3 2 1 0
e
Type
Reset
e a s e I - R 2 0 0 0
CIRQ_SENS_CLR5
0
WO
0 0 0 0 0
Bit(s
)
Mnemon
ic
Name
l
a n a
n
B a
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
8:0
R5
l
Re Pi B
CIRQ_SENS_CL
P Write 1 to specific bit clear the sensitivity of

10204200 CIRQ_POL0
a n a External interrupt polarity register 00000000

Bit
Nam
e
Type
Reset
31
0
30
0
Ba
29
0
n 28
0
27
0
26
0
25
0
24
CIRQ_POL0[31:16]
0
RO
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
CIRQ_POL0[15:0]
e
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
r
31:0 CIRQ_POL0 system CIRQ polarity value
e f o 2
10204204 CIRQ_POL1
l e a s I - R
Bit
Nam
e
Type
31 30 29 28
Re Pi B P
27 26 25 24
CIRQ_POL1[31:16]
RO
23 22 21 20 19 18 17 16
a
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bit
Nam
e
15 14 13
n a n12 11 10 9 8 7
CIRQ_POL1[15:0]
6 5 4 3 2 1 0
Ba
Type RO
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
10204208 CIRQ_POL2 External interrupt polarity register 00102001

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type
f o r CIRQ_POL2[31:16]
RO
e
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bit
Nam
e
15 14 13
l
12
e a s 11
I - R 2
10 9 8
CIRQ_POL2[15:0]
7 6 5 4 3 2 1 0
Type
Reset 0 0 1
Re Pi B
0
P
0 0 0 0
RO
0 0 0 0 0 0 0 1
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
31:0
l
Re Pi B
CIRQ_POL2
P system CIRQ polarity value
1020420C CIRQ_POL3
a n a External interrupt polarity register 00000001
n
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Ba
Nam CIRQ_POL3[31:16]
e
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
CIRQ_POL3[15:0]
e
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit(s Mnemon
Name Description
) ic
f o r
10204210
Bit 31
CIRQ_POL4
30 29
e
28
a s e 27
I - R 2
26 25 24 23 22 21 20 19 18
00000000
17 16
Nam
e
Type
Reset 0 0 0
l
Re Pi B
0
P
0 0 0
CIRQ_POL4[31:16]
0
RO
0 0 0 0 0 0 0 0
a
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type
n a n CIRQ_POL4[15:0]
RO
Ba
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
10204214 CIRQ_POL5 External interrupt polarity register 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type
Reset
f o r
e
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type
l e a s I - R 2 CIRQ_POL5
RO
Reset
Re Pi B P 0 0 0 0 0 0 0 0 0
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
8:0
l
Re Pi B
CIRQ_POL5
P system CIRQ polarity value
10204240
CIRQ_POL_
SET0
a n a External interrupt polarity set register 00000000
Bit
Nam
e
Type
31 30
Ba
29
n 28 27 26 25 24
CIRQ_POL_SET0[31:16]
WO
23 22 21 20 19 18 17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
CIRQ_POL_SET0[15:0]
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0
CIRQ_POL_SET
0
f o r Write 1 to specific bit sets the polarity of corresponding

system CIRQ
e a s e I - R 2
10204244
Bit
Nam
31
CIRQ_POL_
30
SET1
29
l
Re Pi B
28 P
27
26 25 24 23 22 21 20 19 18
00000000
17 16
a
e
Type
Reset 0 0 0
n a n 0 0 0 0 0
WO
0 0 0 0 0 0 0 0
Ba
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
CIRQ_POL_SET1[15:0]
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0 CIRQ_POL_SET1
system CIRQ
10204248
CIRQ_POL_
SET2
f o r
Bit
Nam
e
31 30 29 28
e
27
a s e 26
I - R 2 25 24
23 22 21 20 19 18 17 16
Type
Reset
Bit
Nam
0
15
0
14
0
13
0
12 l
Re Pi B
0
11 P 0
10
0
9
0
8
WO
CIRQ_POL_SET2[15:0]
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
a n a
n
B a
MT7623N
f o r
10204248
CIRQ_POL_
SET2
e a s e I - R 2
Type
Reset 0 0 0 l
Re Pi B
0
P
0 0 0 0
WO
0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
a n a
Name Description
31:0
Ba n
CIRQ_POL_SET
2
system CIRQ
CIRQ_POL_
1020424C External interrupt polarity set register 00000000
SET3
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam CIRQ_POL_SET3[31:16]
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type
f o r CIRQ_POL_SET3[15:0]
WO
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
l e a s I - R 2
P
Name Description
Re Pi B
) ic
CIRQ_POL_SET Write 1 to specific bit sets the polarity of corresponding
31:0
3 system CIRQ
a n a
10204250
Bit
Nam
31
CIRQ_POL_
30
SET4
Ba
29
n 28 27
26 25 24 23 22 21 20 19 18
00000000
17 16
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
CIRQ_POL_SET4[15:0]
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
Name
f o r Description
31:0
CIRQ_POL_SET
4
e a s e I - R 2
system CIRQ
10204254
CIRQ_POL_
SET5
l
Re Pi B P External interrupt polarity set register 00000000
a n a
n
Ba
MT7623N
f o r
10204254
CIRQ_POL_
SET5
e a s e I - R 2
Bit
Nam
e
Type
31 30 29
l
Re Pi B
28
P
27 26 25 24 23 22 21 20 19 18 17 16
Reset
Bit 15 14 13
a n a
12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
Type
Reset
Ba n 0 0 0
CIRQ_POL_SET5
0
WO
0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
CIRQ_POL_SET Write 1 to specific bit sets the polarity of corresponding
8:0
5 system CIRQ
CIRQ_POL_
10204280 External interrupt polarity clear register 00000000
Bit 31 30
CLR0
29 28 27
f o r
26 25 24 23 22 21 20 19 18 17 16
e
Nam
2
CIRQ_POL_CLR0[31:16]
e
Type
Reset 0 0 0 0
l e a0
s I0
- R 0 0
WO
0 0 0 0 0 0 0 0
Bit
Nam
e
Type
15 14 13
Re Pi B
12 11
P 10 9 8
CIRQ_POL_CLR0[15:0]
WO
7 6 5 4 3 2 1 0
Reset 0 0 0 0
a n a 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s
)
31:0
Mnemon
ic
B a n
Name
CIRQ_POL_CLR
0
Description

system CIRQ
CIRQ_POL_
CLR1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type WO
Reset
Bit
Nam
0
15
0
14
0
13
0
12
f
0
11
o r 0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
e
Type
Reset 0 0 0
e
0
a s e 0
I - R 20
CIRQ_POL_CLR1[15:0]
0 0
WO
0 0 0 0 0 0 0 0
Bit(s
)
Mnemon
ic
l
Re Pi B
Name P Description
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
31:0
1
l
Re Pi B
CIRQ_POL_CLR
P Write 1 to specific bit clear the polarity of corresponding

system CIRQ
CIRQ_POL_
a n a
10204288
Bit
Nam
e
31 30
CLR2
Ba
29 n 28 27
26 25 24
23 22 21 20 19 18
00000000
17 16
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
CIRQ_POL_CLR2[15:0]
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
31:0
CIRQ_POL_CLR
2
f o r Write 1 to specific bit clear the polarity of corresponding

system CIRQ
e a s e I - R 2
1020428C
Bit 31
CIRQ_POL_
30
CLR3
29
l
Re Pi B
28
P
27
26 25 24 23 22 21 20 19 18
00000000
17 16
Nam
e
a n a CIRQ_POL_CLR3[31:16]
n
Type WO
Ba
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
CIRQ_POL_CLR3[15:0]
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s Mnemon
Name Description
) ic
CIRQ_POL_CLR Write 1 to specific bit clear the polarity of corresponding
31:0
3 system CIRQ
10204290
CIRQ_POL_
f o r
Bit 31 30
CLR4
29 28
e a s e 27
I - R 2
26 25 24 23 22 21 20 19 18 17 16
l
Nam
P
Re Pi B
e
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
a n a CIRQ_POL_CLR4[15:0]
n
Ba
MT7623N
f o r
10204290
CIRQ_POL_
CLR4
e a s e I - R 2
e
Type
Reset 0 0 0
l
Re Pi B
0 P
0 0 0 0
WO
0 0 0 0 0 0 0 0
Bit(s Mnemon
a n a
Name Description
n
) ic
Ba
CIRQ_POL_CLR Write 1 to specific bit clear the polarity of corresponding
31:0
4 system CIRQ
CIRQ_POL_
CLR5
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Nam
e
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nam
e
f o r CIRQ_POL_CLR5
e
Type WO
Reset
l e a s I - R 2 0 0 0 0 0 0 0 0 0
Bit(s
)
8:0
Mnemon
ic
Re Pi B
Name
CIRQ_POL_CLR P Description
a
5 system CIRQ
n a n
10204300
Bit 31
CIR
Q_
CIRQ_CON
30
B
29 a28 27 26
Sytem CIRQ control register
25 24 23 22 21 20 19 18
80000000
17 16
Nam EV
e EN
T_
B
Type RO
Reset 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CIR
CIR Q_
Q_ ED CIR
r
Nam
FL GE Q_
e
e f o 2
US
H
_O
NL
EN
s
Y
a R
Type WO RW RW
Reset
l e P I - 0 0 0
Bit(s
)
Mnemon
ic
Re Pi B
Name Description
a n a
n
Ba
MT7623N
f o r
Bit(s
)
Mnemon
ic
Name
31
2
1
l
Re Pi B
CIRQ_EVENT_B
CIRQ_FLUSH
CIRQ_EDGE_O
P Indicate sys_cirq_irq_b is triggered
Flush pending interrupts
Set edge-only mode, only edge-triggered interrupt will be
a
NLY recorded
0
n a n
CIRQ_EN Enable bit of system CIRQ controller
6.5
Ba
Programming Guide
6.5.1 MCUSYS MTCMOS Sequence

CPU Power Down Mode MTCMOS CONTROL SRAM PWR ON
CPU_WFI
edge-signal will be missed
PWR_RST_B
PWR_ISO
f o r
e
PWR_ON
s 2
Power Settle Time < 1us
a R
PWR_ON_S
l e P I -
Re Pi B
CLK_DIS
PWR_ACK
a
PWR_ACK_S
Note:
n a n
1. MEM_CKISO should connect to PISO cell to isolate the CLOCK and CHIP SEL input ports of SRAM to LOW
Ba
2. All the MEM_PDN and MEM_SLEEP_B signals come from the SPM in always power on domain.
3. MEM_SLEEP_B should always keep HIGH when SRAM power down
4. All the signals are controled by CPU(Software) or SPM
Figure 6-3: MCUSYS MTCMOS Sequence
f o r
e a s e I - R 2
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
6.5.2 SW Flow
e a s e I - R 2
l
Re Pi B P Enter WFI Handler
a n a Set I/F-bit Restore GIC context
Ba n Apply CIRQ
Mask / Polarity / Flush SYS_CIRQ
Sensitivity Settings
Enable SYS_CIRQ Disable SYS_CIRQ
f o r Mask GIC interrupts

Save GIC context
Clear I/F-bit
e a s e I - R 2
l
Re Pi B P Disable MCI Snoop RFE
a n a
n
dsb()
Ba WFI
wakeup_event
Figure 6-4: Software flow of MCUSYS MTCMOS Sequnce
f o r
e a s e I - R 2
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
7 General-Purpose Timer
e a s e I - R 2
7.1 Introduction
l
Re Pi B P
a n a
The General-Purpose Timer (GPT) includes 8 32-bit timers, one 64-bit timer and one secure 32-bit
Ba n
timer. Each timer has 4 operation modes, which are ONE-SHOT, REPEAT, KEEP-GO and FREERUN,
and can operate on one of the 2 clock sources, RTC clock (32.768kHz) and system clock (13MHz).
7.2 Feature list

The 4 operation modes for GPT are ONE-SHOT, REPEAT, KEEP-GO and FREERUN. See table
below for the functions of each mode.
Table 7-1: Operation mode of GPT
r
When
Example: Compare is
Mode
Auto
Stop
Interrupt
e f o Increases when
EN=1 and …
2
COUNTn
equals
set to 2
*Bold means interrupt
s
COMPAREn
ONE-
Yes Yes
l e a I - R
Stops when COUNTn
P
EN is reset to 0 0,1,2,2,2,2,2,2,2,2,2,2,…
Re Pi B
SHOT equals to COMPAREn
Count is reset
REPEAT No Yes 0,1,2,0,1,2,0,1,2,0,1,2…
to 0
KEEP-GO No Yes
a n a Reset to 0 when
overflow
0,1,2,3,4,5,6,7,8,9,10,…
FREERUN No
Ba n No
Reset to 0 when
overflow
0,1,2,3,4,5,6,7,8,9,10,…
Each timer can be programmed to select the clock source, RTC clock (32.76kHz) or system clock
(13MHz). After the clock source is determined, the division ratio of the selected clock can be
programmed. The division ratio can be fine-granulated as 1, 2, 3, 4 to 13 and coarse-granulated as 16,
32 and 64.
f o r
e a s e I - R 2
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
7.3 Block Diagram
e a s e I - R 2
l
Re Pi B
32bit
64 bit
P
a n a APXGPT
Ba
32kHz
13MHz n GPT1
GPT2
Sleep
Control
GPT3
GPT4
IRQ
MCU
f o r GPT5
e a s e I - R 2 GPT6
psecur_b
l
Re Pi B P GPT7
secure_irq
a n a GPT8
Ba n GPT9
GPT10
Figure 7-1: Block diagram of GPT
f o r
e
Module name: APXGPT base address: (+10008000h)
Address Name
l e a s I - R 2Width Register function
P
GPT IRQ enabling
Re Pi B
10008000 GPT_IRQEN 32
Controls the enabling/disabling of GPT interrupt
10008004 GPT_IRQSTA 32 GPT IRQ status
a n a
n
Ba
MT7623N
f o r
Address Name
e a s e I - R 2
l
Shows the interrupt status of each GPT
10008008
Re Pi B
GPT_IRQACK
P 32
GPT IRQ acknowledgement
Acknowledges the GPT interrupt
a
GPT1 control
10008010 GPT1_CON 32
n a n The general control for GPT1

GPT1 clock setting
Ba
10008014 GPT1_CLK 32 Controls the clock source and division ratio of GPT
clock
GPT1 counter
10008018 GPT1_COUNT 32
The timer count of GPT1
GPT1 compare value
1000801C GPT1_COMPARE 32
The compare value for GPT1
GPT2 control
10008020 GPT2_CON 32
The general control for GPT2
GPT2 clock setting
r
clock
10008028 GPT2_COUNT
e f o 2
32
GPT2 counter
1000802C GPT2_COMPARE
l e a s I - R 32
GPT2 compare value
P
Re Pi B
GPT3 control
10008030 GPT3_CON 32
10008034
a
GPT3_CLK
n a 32
GPT3 clock setting
Controls the clock source and division ratio of GPT
10008038
Ba n
GPT3_COUNT 32
clock
GPT3 counter
GPT3 compare value
GPT4 control
10008040 GPT4_CON 32
GPT4 clock setting
clock
GPT4 counter
r
10008048 GPT4_COUNT 32
e f o 2
32
GPT4 compare value
s
10008050 GPT5_CON
l e a P I - R 32
GPT5 control
Re Pi B
GPT5 clock setting
10008054 GPT5_CLK 32
a n a
n
Ba
MT7623N
f o r
Address Name
e a s e I - R 2
l
clock
10008058
Re Pi B
GPT5_COUNT
P 32
GPT5 counter
a
GPT5 compare value
n a n The compare value for GPT5

GPT6 control
Ba
10008060 GPT6_CON 32
GPT6 clock setting
clock
GPT6 counter L
10008068 GPT6_COUNTL 32
The lower word timer count for GPT6
GPT6 compare value L
1000806C GPT6_COMPAREL 32
The lower word compare value for GPT6
GPT6 counter H
10008078 GPT6_COUNTH 32
The higher word timer count for GPT6
1000807C GPT6_COMPAREH
f o r 32
GPT6 compare value H
The higher word compare value for GPT6
1000808C GPT7_CON
e a s e I - R 2 32
GPT7(secure) control
10008090 GPT7_CLK
l
Re Pi B P 32
GPT7(secure) clock setting
Controls the clock source and division ratio of GPT7
clock
10008094 GPT7_COUNT
a n a 32
GPT7(secure) counter
10008098
1000809C Ba n
GPT7_COMPARE
GPT7_SECURE
32
32
GPT7(secure) compare value
GPT7(secure) secure control
The secure control for GPT7
GPT7_IRQEN_SEC GPT7(secure) IRQ enabling
100080a0 32
URE Controls the enabling/disabling of GPT7 interrupt
GPT7_IRQACK_SE GPT7(secure) IRQ acknowledgement
100080a4 32
CURE Acknowledges the GPT7 interrupt
GPT8 control
100080a8 GPT8_CON 32
r
GPT8 clock setting
100080ac GPT8_CLK
e f o 2
32 Controls the clock source and division ratio of GPT
clock
100080b0 GPT8_COUNTH
l e a s I - R 32
GPT8 counter
100080b4
100080b8 Re Pi B
GPT8_COMPAREH
GPT9_CON
P 32
32
GPT8 compare value
GPT9 control
a n a
n
Ba
MT7623N
f o r
Address Name
e a s e I - R 2Width Register function
l
100080bc
Re Pi B
GPT9_CLK P 32
GPT9 clock setting
clock
100080c0
a
GPT9_COUNT
n a 32
GPT9 counter
100080c4
100080c8 Ba n
GPT9_COMPARE
GPT10_CON
32
32
GPT9 compare value
GPT10 control
GPT10 clock setting
100080cc GPT10_CLK 32 Controls the clock source and division ratio of GPT
clock
GPT10 counter
100080d0 GPT10_COUNT 32
GPT10 compare value
100080d4 GPT10_COMPARE 32
r
e f o 2
10008000 GPT_IRQEN
l e a s I - R GPT IRQ Enabling 00000000

Bit
Name
Type
Reset
31 30 29
Re Pi B
28
P
27 26 25 24 23 22 21 20 19 18 17 16
Bit
Name
15 14 13
a n a
12 11 10 9
IRQEN
8 7 6 5 4 3
IRQEN
2 1 0
n
Type RW RW
Ba
Reset 0 0 0 0 0 0 0 0 0

Enables interrupt of each GPT
5:0
IRQEN IRQEN 0: Disable associated interrupt of GPT
10:8
1: Enable associated interrupt of GPT
10008004 GPT_IRQSTA GPT IRQ Status 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
r
Name
o
Type
Reset
Bit
Name
15 14 13 12
s e f
11 10
2
9
IRQSTA
8 7 6 5 4 3
IRQSTA
2 1 0
Type
Reset
l e a P I - R 0 0
RU
0 0 0 0 0
RU
0 0 0
Bit(s) Mnemonic
Re Pi B
Name Description
a
5:0 IRQSTA IRQSTA Interrupt status of each GPT
Ba
MT7623N
f o r
Bit(s)
10:7
Mnemonic Name
0: No associated interrupt is generated.
l
Re Pi B P 1: Associated interrupt is pending and waiting for service.
10008008 GPT_IRQACK
a n a GPT IRQ Acknowledgement 00000000
n
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Ba
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name IRQACK IRQACK
Type WO WO
Reset 0 0 0 0 0 0 0 0 0

Interrupt acknowledgement for each GPT
5:0 0: No effect
IRQACK IRQACK
10:8 1: Associated interrupt request is acknowledged and should be
relinquished.
f o r
10008010 GPT1_CON
e a s e I - R 2 GPT1 Control 00000000

Bit
Name
Type
Reset
31 30 29
l 28
Re Pi B P
27 26 25 24 23 22 21 20 19 18 17 16
a
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
n
Name MODE1 CLR1 EN1
a
Type RW WO RW
n
Reset 0 0 0 0
Bit(s) Mnemonic
Ba Name Description
Operation mode of GPT1
00: ONE-SHOT mode
5:4 MODE1 MODE1 01: REPEAT mode
10: KEEP-GO mode
11: FREERUN mode
Clears the counter of GPT1 to 0
1 CLR1 CLR1 0: No effect
1: Clear
Enables GPT1
0 EN1 EN1
f o r 0: Disable
1: Enable
e a s e I - R 2
10008014
Bit
Name
31 30
GPT1_CLK
29 l
Re Pi B
28
P
27 26 25
GPT1 Clock Setting
24 23 22 21 20 19 18
00000000
17 16
a
Type
Ba
MT7623N
f o r
10008014 GPT1_CLK
e a s e I - R 2 GPT1 Clock Setting 00000000
l
Reset
Bit
Name
Type
Reset
15 14 13
Re Pi B
12
P
11 10 9 8 7 6 5 4
CLK1
RW
0
3
0
2
0
RW
1
CLKDIV1
0
0
a n a
n
Ba
Sets up clock source of GPT1
4 CLK1 CLK1 0: System clock (13MHz)
1: RTC clock (32kHz)
Setting of GPT1 input clock frequency divider
0000: Clock source divided by 1
CLKDIV1
r
3:0 CLKDIV1 0111: Clock source divided by 8
o
s e f 2
l e a P I - R 1011: Clock source divided by 12

Re Pi B
a n a
10008018
Bit
Name
31 30
Ba
GPT1_COUNT
29
n 28 27 26 25 24
GPT1 Counter
COUNTER1[31:16]
23 22 21 20 19 18
00000000
17 16
Type RU
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name COUNTER1[15:0]
Type RU
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31:0 COUNTER1 COUNTER1 Timer counter of GPT1
f o r
e a s e I - R 2 GPT1 Compare Value 00000000
l
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit
0
15
0
14
0
13
Re Pi B0
12
P0
11
0
10
0
9
COMPARE1[31:16]
0
RW
8
0 0
7 6
0
5
0
4 3
0
2
0 0
1
0
0
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2 GPT1 Compare Value 00000000
l
Name COMPARE1[15:0]
Type
Reset 0 0 0
Re Pi B0
P 0 0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s)
31:0
Mnemonic
COMPARE1
a n a Name
COMPARE1
Description
Compare value of GPT1
10008020 Ba
GPT2_CON
n GPT2 Control 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MODE2 CLR2 EN2
Type RW WO RW
Reset 0 0 0 0
r
5:4 MODE2 MODE2
e f o 2
00: ONE-SHOT mode
l e a s I - R
01: REPEAT mode
10: KEEP-GO mode
1 CLR2
Re Pi B CLR2
P 11: FREERUN mode
0: No effect
0 EN2
a n a EN2
1: Clear
Enables GPT2
Ba n 0: Disable
1: Enable
10008024 GPT2_CLK GPT2 Clock Setting 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CLK2 CLKDIV2
Type RW RW
Reset 0 0 0 0 0
f o r
e
4 CLK2
l e a s
CLK2
I - R 2 Sets up clock source of GPT2

0: System clock (13MHz)
3:0 CLKDIV2
Re Pi B
CLKDIV2
P 1: RTC clock (32kHz)
a n a
n
Ba
MT7623N
f o r
Bit(s) Mnemonic
e a s
Name
e I - R 2 Description
l
Re Pi B P 0010: Clock source divided by 3
a
n a n 0110: Clock source divided by 7

Ba
10008028 GPT2_COUNT GPT2 Counter 00000000

Bit
Name
31 30 29 28
f o
27
r 26 25 24
COUNTER2[31:16]
23 22 21 20 19 18 17 16
e
Type RU
Reset
Bit
Name
0
15
0
14
0
13
l
0
12
e a s 0
11
I - R 20
10
0
9
0
8
0 0
7 6
0
5
0
4 3
0
2
0 0
1
0
0
P
COUNTER2[15:0]
Re Pi B
Type RU
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:0
Mnemonic
COUNTER2
a n a Name
COUNTER2
Description
Timer counter of GPT2
1000802C Ba n
GPT2_COMPARE GPT2 Compare Value 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name COMPARE2[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name COMPARE2[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:0
Mnemonic
COMPARE2
Name
COMPARE2
f o r Description
Compare value of GPT2
e a s e I - R 2
10008030
Bit
Name
31
GPT3_CON
30 29 l
Re Pi B
28
P
27 26 25 24
GPT3 Control
23 22 21 20 19 18
00000000
17 16
a
Type
Ba
MT7623N
f o r
10008030 GPT3_CON
l
Reset
Bit
Name
Type
Reset
15 14 13
Re Pi B
12
P
11 10 9 8 7 6 5
MODE3
0
RW
0
4 3 2 1
WO
0
RW
0
0
CLR3 EN3
a n a
n
Ba
5:4 MODE3 MODE3 Operation mode of GPT3
00: ONE-SHOT mode
01: REPEAT mode
10: KEEP-GO mode
11: FREERUN mode
1 CLR3 CLR3 Clears the counter of GPT3 to 0
0: No effect
1: Clear
0 EN3 EN3 Enables GPT3
0: Disable
1: Enable
f o r
10008034
Bit 31
GPT3_CLK
30 29
e
28
a s e 27
I - R 2
26 25
GPT3 Clock Setting
24 23 22 21 20 19 18
00000000
17 16
Name
Type
Reset
Bit 15 14 13
l
Re Pi B
12 P
11 10 9 8 7 6 5 4 3 2 1 0
a
Name CLK3 CLKDIV3
n
Type RW RW
Reset
n a 0 0 0 0 0
Bit(s)
4
Mnemonic
CLK3
Ba Name
CLK3
Description
3:0 CLKDIV3 CLKDIV3 Setting of GPT3 input clock frequency divider
f o r 0110: Clock source divided by 7

e a s e I - R 2
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
Bit(s) Mnemonic
e a s
Name
l
10008038 GPT3_COUNT
a n a GPT3 Counter 00000000
n
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Ba
Name COUNTER3[31:16]
Type RU
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name COUNTER3[15:0]
Type RU
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1000803C
Bit 31
GPT3_COMPARE
30 29 28
f o
27 r 26 25
GPT3 Compare Value
24 23 22 21 20 19 18
00000000
17 16
Name
Type
e a s e I - R 2 COMPARE3[31:16]
RW
l
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
Type
Reset
15
0
14
0
13
0
Re Pi B
12
0
P
11
0
10
0
9
0
8
COMPARE3[15:0]
0
RW
0 0
7 6 5
0
4
0
3
0
2
0
1
0
0
Bit(s) Mnemonic
a n a Name Description
31:0 COMPARE3
Ba n COMPARE3 Compare value of GPT3
10008040 GPT4_CON GPT4 Control 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MODE4 CLR4 EN4
Type RW WO RW
Reset 0 0 0 0
f o r Description
5:4 MODE4
e s
MODE4
a e I - R 2
00: ONE-SHOT mode
1 CLR4
l
Re Pi B CLR4
P
01: REPEAT mode
10: KEEP-GO mode
11: FREERUN mode
a n a
n
Ba
MT7623N
f o r
Bit(s) Mnemonic
e a s
Name
0: No effect
0 EN4 l
Re Pi B EN4
P 1: Clear
Enables GPT4
0: Disable
a n a 1: Enable
10008044
Bit
Name
31 30
Ba
29
n
GPT4_CLK
28 27 26 25
GPT4 Clock Setting
24 23 22 21 20 19 18
00000000
17 16
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CLK4 CLKDIV4
Type RW RW
Reset 0 0 0 0 0
r
4 CLK4 CLK4 Sets up clock source of GPT4
e f o 2
3:0 CLKDIV4 CLKDIV4
l e a s I - R

a

Ba
10008048
Bit 31
GPT4_COUNT
30 29 28 27
f o r
26 25 24
GPT4 Counter
23 22 21 20 19 18
00000000
17 16
Name
Type
Reset 0 0 0 0
e a s0
e I -
0
R 2 0
COUNTER4[31:16]
0
RU
0 0 0 0 0 0 0 0
Bit
Name
Type
Reset
15
0
14
0
13
0
12
0
l
Re Pi B
11
0 P
10
0
9
0
8
COUNTER4[15:0]
0
RU
0 0
7 6 5
0
4
0
3
0
2
0
1
0
0
a n a
n
B a
MT7623N
f o r
Bit(s) Mnemonic
e a s
Name
l
Re Pi B P
1000804C
Bit 31
GPT4_COMPARE
30 29
a n a
28 27 26 25
GPT4 Compare Value
24 23 22 21 20 19 18
00000000
17 16
n
Ba
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name COMPARE4[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31:0 COMPARE4 COMPARE4 Compare value of GPT4
r
10008050 GPT5_CON GPT5 Control 00000000
Bit
Name
31 30 29 28 27
e f o26
2
25 24 23 22 21 20 19 18 17 16
s
Type
a R
Reset
Bit 15 14 13 12
l e 11
P I
10
- 9 8 7 6 5 4 3 2 1 0
Re Pi B
Name MODE5 CLR5 EN5
Type RW WO RW
Reset 0 0 0 0
Bit(s) Mnemonic
n
Name
a a Description
n
B a 00: ONE-SHOT mode

01: REPEAT mode
10: KEEP-GO mode
11: FREERUN mode
0: No effect
1: Clear
0: Disable
1: Enable
10008054 GPT5_CLK
f o r GPT5 Clock Setting 00000000
Bit
Name
31 30 29 28
e a s
27
e 26
I - R 2 25 24 23 22 21 20 19 18 17 16
l
Type
Reset
Bit
Name
Type
15 14 13
Re Pi B
12 11
P 10 9 8 7 6 5 4
CLK5
RW
3 2 1
CLKDIV5
RW
0
a n a
n
B a
MT7623N
f o r
10008054 GPT5_CLK
l
Reset 0 0 0 0 0
Bit(s) Mnemonic
Re Pi B Name P Description
a
n a n 0: System clock (13MHz)

Ba

e a s e I - R 2
l
Re Pi B P
10008058
Bit 31
GPT5_COUNT
30 29
a n a
28 27 26 25 24
GPT5 Counter
23 22 21 20 19 18
00000000
17 16
Name
Type
Reset
Bit
Name
0
15
0
14
Ba
0
13
n 0
12
0
11
0
10
0
9
COUNTER5[31:16]
0
RU
8
0
COUNTER5[15:0]
0
7 6
0
5
0
4 3
0
2
0 0
1
0
0
Type RU
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

r
1000805C GPT5_COMPARE GPT5 Compare Value 00000000
Bit
Name
31 30 29 28 27
e f o 26
2
25 24
COMPARE5[31:16]
23 22 21 20 19 18 17 16
s
Type RW
Reset
Bit
0
15
0
14
0
13
0
12
l e a 0
11
P I -
0
10
R 0
9
0
8
0 0
7 6
0
5
0
4 3
0
2
0 0
1
0
0
Re Pi B
Name COMPARE5[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
a n a
n
B a
MT7623N
f o r
Bit(s) Mnemonic
e a s
Name
l
Re Pi B P
10008060
Bit 31
GPT6_CON
30 29
a n a
28 27 26 25 24
GPT6 Control
23 22 21 20 19 18
00000000
17 16
n
Name
Ba
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MODE6 CLR6 EN6
Type RW WO RW
Reset 0 0 0 0

00: ONE-SHOT mode
01: REPEAT mode
10: KEEP-GO mode
r
11: FREERUN mode
1 CLR6 CLR6
e f o 2
0: No effect
0 EN6
l e a sEN6
I - R
1: Clear
Enable the GPT6
Re Pi B P 0: Disable
1: Enable
a n a
n
10008064 GPT6_CLK GPT6 Clock Setting 00000000
Ba
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CLK6 CLKDIV6
Type RW RW
Reset 0 0 0 0 0

r
3:0 CLKDIV6 CLKDIV6
e f o 2
GPT6 input clock frequency divider setting
l e a s I - R

a
Ba
MT7623N
f o r
Bit(s) Mnemonic
e a s
Name
l
a

Ba
10008068 GPT6_COUNTL GPT6 Counter L 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name COUNTER6L[31:16]
Type RU
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name COUNTER6L[15:0]
Type RU
Reset 0 0 0 0
f
0
o r 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Mnemonic
e a s
Name
e I - R 2
Description
Lower word of timer count of GPT6
31:0 COUNTER6L
l
COUNTER6L
Re Pi B P
A read operation of GPT6_COUNTL will make GPT6_COUNTH
fixed until the next read operation of GPT6_COUNTL.
1000806C GPT6_COMPAREL
a n a GPT6 Compare Value L 00000000

Bit
Name
Type
Reset
Bit
31
0
15
30
0
14 Ba
29
0
13
n 28
0
12
27
0
11
26
0
10
25
0
9
0
24
COMPARE6L[31:16]
RW
8
0
23
0
7
22
6
21
0
5
20
0
4
19
3
0
18
2
0
17
0
1
16
0
0
Name COMPARE6L[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31:0 COMPARE6L COMPARE6L Higher word of timer count of GPT6
10008078 GPT6_COUNTH
f o r GPT6 Counter H 00000000

Bit
Name
Type
31 30 29 28
e a
27
s e I
26
- R 2
25 24
COUNTER6H[31:16]
RU
23 22 21 20 19 18 17 16
Reset
Bit
Name
Type
0
15
0
14
0
13
0
12
l
Re Pi B
0
11
P
0
10
0
9
0
8
0
COUNTER6H[15:0]
RU
0
7 6
0
5
0
4 3
0
2
0 0
1
0
0
a
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
B a
MT7623N
f o r
e a s e I - R 2
l
31:0 COUNTER6H
Re Pi B
COUNTER6H
P Lower word of compare value of GPT6
a n a
1000807C
Bit
Name
Type
Reset
31
0
30
0 Ba
29
0
n
GPT6_COMPAREH
28
0
27
0
26
0
25
0
GPT6 Compare Value H
24
COMPARE6H[31:16]
0
RW
0 0
23 22 21
0
20
0
19
0
18
0
00000000
17
0
16
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name COMPARE6H[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31:0 COMPARE6H COMPARE6H Higher word of compare of GPT6
f o r
e
1000808C GPT7_CON GPT7 Control 00000000
Bit
Name
31 30 29
l
28
e a s 27
I - R 2
26 25 24 23 22 21 20 19 18 17 16
Re Pi B P
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MODE7 CLR7 EN7
a
Type RW WO RW
Reset
n a n 0 0 0 0
Ba
00: ONE-SHOT mode
01: REPEAT mode
10: KEEP-GO mode
11: FREERUN mode
0: No effect
1: Clear
0: Disable
f o r 1: Enable
10008090
Bit 31
GPT7_CLK
30 29
e
28
a s e 27
I - R 2
26 25
GPT7 Clock Setting
24 23 22 21 20 19 18
00000000
17 16
Name
Type
Reset
Bit 15 14 13
l
Re Pi B
12 P
11 10 9 8 7 6 5 4 3 2 1 0
a
Name CLK7 CLKDIV7
Ba
MT7623N
f o r
10008090 GPT7_CLK
l
Type RW RW
Reset
Bit(s) Mnemonic
Re Pi B Name
P Description
0 0 0 0 0
4 CLK7
a n a CLK7 Sets up clock source of GPT7

3:0 CLKDIV7
Ba n CLKDIV7

e a s e I - R 2
l
a
10008094 GPT7_COUNT GPT7 Counter 00000000
Bit
Name
31 30 29
n a n 28 27 26 25 24
COUNTER7[31:16]
23 22 21 20 19 18 17 16
Ba
Type RU
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name COUNTER7[15:0]
Type RU
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

10008098 GPT7_COMPARE
f o r GPT7 Compare Value 00000000
e
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset 0 0 0
l e0
a s 0
I - R 20 0
COMPARE7[31:16]
0
RW
0 0 0 0 0 0 0 0
Bit
Name
Type
Reset
15
0
14
0
13
0
Re Pi B
12
0
P
11
0
10
0
9
0
8
COMPARE7[15:0]
0
RW
0 0
7 6 5
0
4
0
3
0
2
0
1
0
0
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
l
31:0 COMPARE7
Re Pi B
COMPARE7
P Compare value of GPT7
1000809C GPT7_SECURE
a n a GPT7 Secure control 00000000

Bit
Name
Type
Reset
Bit
31
15
30
14
29
13 Ba n28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0
Name Secure_on
Type RW
Reset 0

Secure control of GPT7
0 GPT7_SECURE SECURE_ON 0: normol mode
1: secure mode
f o r
100080a0 GPT7_IRQEN_SECURE
e a s e I - R 2 GPT7 IRQ_enabling 00000000

Bit
Name
Type
Reset
31 30 29 28
l
Re Pi B
27
P 26 25 24 23 22 21 20 19 18 17 16
Bit
Name
15 14 13 12
a n a 11 10 9 8 7 6 5 4 3 2 1 0
Irqen_secur
n
Type RW
Ba
Reset 0

Enable irq GPT7(secure)
0 GPT7_IRQEN_SECUR IRQEN_SECURE 0: Disable associated interrupt of GPT7
1: Enable associated interrupt of GPT7
100080a4 GPT7_IRQACK_SECURE GPT7 IRQ Acknowledgement 00000000

2
Bit 31 30 29 28 27 26 5 24 23 22 21 20 19 18 17 16
Name
Type
f o r
e
Reset
Bit
Name
Type
15 14 13 12
l e a s
11
I
10
- R 2 9 8 7 6 5 4 3 2 1 0
ack_secure
WO
Reset
Re Pi B P 0
a n a
n
Ba
MT7623N
f o r
Bit(s)
Mnemoni
c
e a s
Name
0
IRQACK_
SECURE l
Re Pi B
IRQACK_SECURE
P Interrupt acknowledgement for GPT7(secure)
0: No effect
1: Associated interrupt request is acknowledged and should
a
be relinquished.
n a n
100080a8
Bit
Name
Type
Reset
31 30
Ba
GPT8_CON
29 28 27 26 25 24
GPT8 Control
23 22 21 20 19 18
00000000
17 16
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MODE8 CLR8 EN8
Type RW WO RW
Reset 0 0 0 0

f o r 00: ONE-SHOT mode

01: REPEAT mode
e a s e I - R 2
10: KEEP-GO mode
11: FREERUN mode
1 CLR8
EN8
l
Re Pi B
CLR8
P
0: No effect
1: Clear
Enables GPT8
a
0 EN8
n
0: Disable
n a 1: Enable
100080ac
Bit
Name
31 30
Ba
GPT8_CLK
29 28 27 26 25
GPT8 Clock Setting
24 23 22 21 20 19 18
00000000
17 16
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CLK8 CLKDIV8
Type RW RW
Reset 0 0 0 0 0
Bit(s)
4
Mnemonic
CLK8
Name
CLK8
f o r Description
e a s e I - R 2
3:0 CLKDIV8
l CLKDIV8
Re Pi B P
a n a
n
Ba
MT7623N
f o r
Bit(s) Mnemonic
e a s
Name
l
a

Ba
100080b0 GPT8_COUNT GPT8 Counter 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type
Reset
Bit
0
15
0
14
0
13
0
12
0
11
f o r0
10
0
9
0
RU
8
0 0
7 6
0
5
0
4 3
0
2
0 0
1
0
0
Name
Type
Reset 0 0 0 0
e a s
0 e I -
0
R 2 0
COUNTER8[15:0]
0
RU
0 0 0 0 0 0 0 0
Bit(s)
31:0
Mnemonic
COUNTER8
l
Re Pi B
Name
COUNTER8
P Description
a n a
100080b4
Bit
Name
31 30
B
GPT8_COMPARE
29 a n
28 27 26 25
GPT8 Compare Value
24
COMPARE8[31:16]
23 22 21 20 19 18
00000000
17 16
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name COMPARE8[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

f o r
e
100080b8 GPT9_CON GPT9 Control 00000000
Bit
Name
31 30 29
l
28
e a s 27
I - R 2
26 25 24 23 22 21 20 19 18 17 16
P
Type
Re Pi B
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MODE9 CLR9 EN9
a
Type RW WO RW
Ba
MT7623N
f o r
100080b8 GPT9_CON
l
Reset 0 0 0 0
Bit(s) Mnemonic
Re Pi B Name P Description
a
n a n 00: ONE-SHOT mode

01: REPEAT mode
Ba
10: KEEP-GO mode
11: FREERUN mode
0: No effect
1: Clear
0: Disable
1: Enable
100080bc GPT9_CLK GPT9 Clock Setting 00000000

Bit
Name
31 30 29 28
f o
27
r 26 25 24 23 22 21 20 19 18 17 16
Type
Reset
Bit 15 14 13
e
12
a s e 11
I - R 2
10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset l
Re Pi B P
CLK9
RW
0 0
CLKDIV9
0
RW
0 0
Bit(s) Mnemonic
CLK9
a n a Name Description
n
4 CLK9
Ba

e a s e I - R 2
l

a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
100080c0
Bit
Name
Type
31
GPT9_COUNT
30 29
l
Re Pi B
28
P
27 26 25 24
GPT9 Counter
COUNTER9[31:16]
RU
23 22 21 20 19 18
00000000
17 16
a
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
Type
15 14 13
n a n 12 11 10 9 8
COUNTER9[15:0]
RU
7 6 5 4 3 2 1 0
Ba
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

100080c4 GPT9_COMPARE GPT9 Compare Value 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW
Reset
r
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset 0 0 0 0
s e f 0
2 0 0
COMPARE9[15:0]
0
RW
0 0 0 0 0 0 0 0
l e a P I - R
Re Pi B
a n a
100080c8
Bit
Name
Type
Reset
31
GPT10_CON
30
Ba
29
n 28 27 26 25 24
GPT10 Control
23 22 21 20 19 18
00000000
17 16
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MODE10 CLR10 EN10
Type RW WO RW
Reset 0 0 0 0

00: ONE-SHOT mode
f o r 01: REPEAT mode

10: KEEP-GO mode
e
11: FREERUN mode
1 CLR9
l e a s
CLR9
I - R 2 Clears the counter of GPT9 to 0

0: No effect
0 EN9
Re Pi B EN9
P 1: Clear
Enables GPT9
0: Disable
a n a
n
Ba
MT7623N
f o r
Bit(s) Mnemonic
e a s
Name
1: Enable
l
Re Pi B P
a
100080cc GPT10_CLK GPT10 Clock Setting 00000000
Bit 31 30 29
n a n 28 27 26 25 24 23 22 21 20 1
9
18 17 16
Ba
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CLK10 CLKDIV10
Type RW RW
Reset 0 0 0 0 0


e a s e I - R 2
l
Re Pi B P
a n a 1000: Clock source divided by 9

Ba n 1010: Clock source divided by 11

100080d0 GPT10_COUNT GPT10 Counter 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RU
Reset
Bit
0
15
0
14
0
13
0
12
f o
0
11
r 0
10
0
9
0
8
0 0
7 6
0
5
0
4 3
0
2
0 0
1
0
0
e
Type
Reset 0 0 0
l e
0
a s 0
I - R 2 0 0 0
RU
0 0 0 0 0 0 0 0
Bit(s)
31:0
Mnemonic
COUNTER10
Re Pi B
Name
COUNTER10 P Description
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
100080d4
Bit
Name
Type
31
GPT10_COMPARE
30 29
l
Re Pi B
28
P
27 26 25
GPT10 Compare Value
24
COMPARE10[31:16]
RW
23 22 21 20 19 18
00000000
17 16
a
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
Type
15 14 13
n a n 12 11 10 9 8
COMPARE10[15:0]
RW
7 6 5 4 3 2 1 0
Ba
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

f o r
e a s e I - R 2
l
Re Pi B P
a n a
Ba n
f o r
e a s e I - R 2
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
8 UART
e a s e I - R 2
8.1 Introduction
l
Re Pi B P
a n a
The UARTs provide full duplex serial communication channels between the baseband chipset and
external devices.
Ba n
UART has both M16C450 and M16550A modes of operation, which are compatible with a range of
standard software drivers. The extensions are designed to be broadly software compatible with
16550A variants, but certain areas offer no consensus.
In common with M16550A, the UART supports word lengths from 5 to 8 bits, an optional parity bit and
one or two stop bits and is fully programmable by an 8-bit CPU interface. A 16-bit programmable
baud rate generator and an 8-bit scratch register are included, together with separate transmit and
receive FIFOs. 2 modem control lines and a diagnostic loop-back mode are provided. UART also
includes two DMA handshake lines, indicating when the FIFOs is ready to transfer data to the CPU.
o r
Interrupts can be generated from any of the 10 sources.
f
e a s e I - 2
Note that UART is designed so that all internal operation is synchronized by the CLK signal. This
R
synchronization results in minor timing differences between the UART and industry standard 16550A
l
Re Pi B P
device, which means that the core is not clock for clock identical to the original device.
After hardware reset, UART will be in M16C450 mode. Its FIFOs can then be enabled and UART can
n a
enter M16550A mode. UART has further additional functions beyond the M16550A mode. Each of the
a
n
extended functions can be selected individually under software control.
Ba
UART provides more powerful enhancements than the industry-standard 16550:
Hardware flow control

This feature is very useful when the ISR latency is hard to predict and control in the embedded
applications. The MCU is relieved of having to fetch the received data within a fixed amount of time.
Note that in order to enable the enhancements, and the enhanced mode bit, EFR[4], must be set. If
EFR[4] is not set, IER[7:5], FCR[5:4], ISR[5:4] and MCR[7:6] cannot be written. The enhanced mode
bit ensures that UART is backward compatible with the software that has been written for 16C450 and
16550A devices.
f o r
8.2 Feature list
e a s e I - R 2



Provides 3 channels
l
Re Pi B
DMA, polling or interrupt operation P
Supports word lengths from 5 to 8 bits, with an optional parity bit and one or two stop bits
a n a
n
Ba
MT7623N
f o r


e a s e
UART0 for hardware automatic flow control
I - R 2
Supports baud rates from 110bps up to 961,200bps

l
Re Pi B
Baud rate auto detection function
P
8.3 Block Diagram
a n a
Ba n Baud Rate
Generator
baud divisor
clock
TX Machine uart_tx_data
TX FIFO
APB Bus APB

BUS RX FIFO
RX Machine uart_rx_data
I/F
r Modem Modem Outputs
e f o 2
Control
Modem Inputs
l e a s I - R
Figure 8-1: Block Diagram of UART
8.4 Register Definition Re Pi B P

a n aTable 8-1: UART Base Address Table
UART number
UART0
UART1 B a n Base address
0x11002000
0x11003000
Feature
Supports DMA, HW flow control
Supports DMA, HW flow control
UART2 0x11004000 Supports DMA, HW flow control
UART3 0x11005000 Supports DMA, HW flow control
There are 4 UART IPs in this SOC. Use of the registers below are the same except that the base
address needs to be changed to respective one.
Module name: UART base address: (+11002000h)

Address Name
f o rWidth Register function
e
11002000 UARTn_RBR 16 RX buffer register
11002000 UARTn_THR
l e a s I - R 2
16 TX holding register
P
11002000 UARTn_DLL 16 Divisor Latch (LS)
Re Pi B
Interrupt enable register
11002004 UARTn_IER 16 By storing 1 to a specific bit position, the interrupt
a
associated with that bit will be enabled. Otherwise, the
Ba
MT7623N
f o r
Address Name
e a s e I - R 2
l
interrupt will be disabled.
11002004 Re Pi B
UARTn_DLM
P 16
IER[3:0] are modified when LCR[7] = 0.
IER[7:4] are modified when LCR[7] = 0 & EFR[4] = 1.
Divisor Latch (MS)
UARTn_IIR
a n a Interrupt identification register
n
11002008 16 Identifies if there are pending interrupts. ID4 and ID3 are
Ba
presented only when EFR[4] = 1.
FIFO control register
FCR is used to control the trigger levels of the FIFOs or
flush the FIFOs
11002008 UARTn_FCR 16
FCR[7:6] is modified when LCR != BFh.
FCR[5:4] is modified when LCR != BFh & EFR[4] = 1.
FCR[4:0] is modified when LCR != BFh.
Enhanced feature register
11002008 UARTn_EFR 16
Note: Only when LCR=BF'h
Line control register
Determines characteristics of serial communication
r
1100200C UARTn_LCR 16
signals.
e f o 2
Modified when LCR[7] = 0.
s
Modem control register
11002010 UARTn_MCR
l e a P I - R16
Controls interface signals of the UART.
Re Pi B
MCR[5:0] are modified when LCR != 8'hBF.
MCR[7] are modified when LCR != 8'hBF & EFR[4] = 1.
XON1
11002010 UARTn_XON1
a n a 16 Note: XON1, XON2, XOFF1, XOFF2 are valid only

when LCR=BF'h.
11002014
11002014
Ba n
UARTn_LSR
UARTn_XON2
16
16
Line status register
Modified when LCR != BFh.
XON2
Modem status register
Note: After a reset, D4-D7 are inputs. A modem status
11002018 UARTn_MSR 16 interrupt can be cleared by writing 0 or set by writing 1
to this register. D0-D3 can be written to.
11002018 UARTn_XOFF1 16 XOFF1
Scratch register
A general purpose read/write register. After reset, its
1100201C UARTn_SCR 16
f o r value is un-defined.
Modified when LCR != BFh.
1100201C
11002020
UARTn_XOFF2
UARTn_AUTOBAU
e a s e I - R 2
16
16
XOFF2
AUTOBAUD_EN
11002024
D_EN
UARTn_HIGHSPE
ED l
Re Pi B P 16 HIGH SPEED UART
a n a
n
Ba
MT7623N
f o r
Address Name
e a s e I - R 2
l
SAMPLE_COUNT
11002028
COUNT
Re Pi B
UARTn_SAMPLE_
P 16
When HIGHSPEED = 3, sample_count will be the
threshold value for UART sample counter
(sample_num).
a n a Counts from 0 to sample_count.

SAMPLE_POINT
1100202C
Ba n
UARTn_SAMPLE_
POINT
16
When HIGHSPEED = 3, UART gets the input data when
sample_count=sample_num, e.g. system clock =
13MHz, 921600 = 13000000/14
sample_count = 13 and sample point = 6 (sample the
central point to decrease the inaccuracy)
SAMPLE_POINT is usually (SAMPLE_COUNT-1)/2
without the decimal.
UARTn_AUTOBAU
11002030 16 AUTOBAUD_REG
D_REG
1100203C UARTn_GUARD 16 Guard time added register
UARTn_ESCAPE_
11002040 16 Escape character register
DAT
11002044
UARTn_ESCAPE_
EN
f o r 16 Escape enable register
11002048
UARTn_SLEEP_E
N
e a s e I - R 2
16 Sleep enable register
1100204C
11002050 UARTn_RXTRI_AD l
Re Pi B
UARTn_DMA_EN
P 16
16
DMA enable register
Rx trigger address
a
UARTn_FRACDIV_
11002054 16 Fractional divider LSB address
n
L
11002058
n a
UARTn_FRACDIV_
16 Fractional divider MSB address
Ba
M
1100205C UARTn_FCR_RD 16 FIFO control register
11002060 DEBUG0 16
Debug register 0
11002064 DEBUG1 16
Debug register 1
11002090 RX_SEL 16
UART RX pin sel
f o r
11002000 UARTn_RBR
e a s e I - R 2
RX Buffer Register 0000
Bit
Name
Type
Reset
15 14 13
l
Re Pi B
12
P
11 10 9 8 7
0
6
0
5
0
4
0
RBR
RU
3
0
2
0
1
0
0
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
l
7:0 RBR
Re Pi B
RBR P RX buffer register
Read-only register. The received data can be read by accessing this
register.
a n a Modified when LCR[7] = 0.
11002000
Bit
Name
15
UARTn_THR
14
Ba
13
n 12
TX Holding Register
11 10 9 8 7 6 5 4
THR
3 2 1
0000
0
Type WO
Reset 0 0 0 0 0 0 0 0

TX holding register
Write-only register. The data to be transmitted are written to this
7:0 THR THR
register and sent to the PC via serial communication.
f o r
11002000 UARTn_DLL
e a s e R 2
Divisor Latch (LS)
I -
0001
Bit
Name
Type
Reset
15 14 13
l 12
Re Pi B
11
P
10 9 8 7
0
6
0
5
0
4
0
DLL
RW
3
0
2
0
1
0
0
Bit(s) Mnemonic
a
Name
n a Description
7:0 DLL
Ba n
DLL Modified when LCR[7] = 1.
11002004 UARTn_IER Interrupt Enable Register 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_A
Name CTSI RTSI XOFFI BOVE EDSSI ELSI ETBEI ERBFI
_TRIG
Reset 0 0 0 0 0 0 0 0
Overview: By storing 1 to a specific bit position, the interrupt associated with that bit will be enabled. Otherwise,
r
the interrupt will be disabled. IER[3:0] are modified when LCR[7] = 0. IER[7:4] are modified when LCR[7] = 0 &
EFR[4] = 1.
e f o 2
Bit(s) Mnemonic
7 CTSI
Name
CTSI
l e a s I - R
Description
Masks an interrupt that is generated when a rising edge is
Re Pi B P detected on the CTS modem control line

Note: This interrupt is only enabled when hardware flow control is
enabled.
a n a 0: Mask an interrupt that is generated when a rising edge is detected
n
Ba
MT7623N
f o r
e a s e I - R 2Description
on the CTS modem control line.
6 RTSI RTSI
l
Re Pi B P 1: Unmask an interrupt that is generated when a rising edge is
detected on the CTS modem control line.
Masks an interrupt that is generated when a rising edge is
a
detected on the RTS modem control line
n a n Note: This interrupt is only enabled when hardware flow control is

enabled.
Ba
0: Mask an interrupt that is generated when a rising edge is detected
on the RTS modem control line.
1: Unmask an interrupt that is generated when a rising edge is
detected on the RTS modem control line.
5 XOFFI XOFFI Masks an interrupt that is generated when an XOFF character is
received
Note: This interrupt is only enabled when software flow control is
enabled.
0: Mask an interrupt that is generated when an XOFF character is
received.
1: Unmask an interrupt that is generated when an XOFF character is
received.
4 RX_ABOVE_TR RX_ABOVE_TR Masks Rx above trigger interrupt when rx_dma is enabled
IG IG
f o r
0: Mask Rx above trigger interrupt when rx_dma is enabled.
1: Unmask Rx above trigger interrupt when rx_dma is enabled.
3 EDSSI EDSSI
e a s e I - R 2
When set to 1, an interrupt will be generated if DDCD, TERI,
DDSR or DCTS (MSR[4:1]) becomes set
l
0: No interrupt is generated if DDCD, TERI, DDSR or DCTS
Re Pi B P (MSR[4:1]) becomes set.

1: An interrupt is generated if DDCD, TERI, DDSR or DCTS
(MSR[4:1]) becomes set.
2 ELSI ELSI
a n a When set to 1, an interrupt will be generated if BI, FE, PE or OE

(LSR[4:1]) becomes set.
n
0: No interrupt is generated if BI, FE, PE or OE (LSR[4:1]) becomes
Ba
set.
1: An interrupt is generated if BI, FE, PE or OE (LSR[4:1]) becomes
set.
1 ETBEI ETBEI When set to 1, an interrupt will be generated if the TX holding
register is empty or the contents of the TX FIFO are reduced to
its trigger level
0: No interrupt is generated if the TX Holding Register is empty or
the contents of the TX FIFO are reduced to its trigger level.
1: An interrupt is generated if the TX Holding Register is empty or the
contents of the TX FIFO are reduced to its trigger level
0 ERBFI ERBFI When set to 1, an interrupt will be generated if the RX buffer
contains data
0: No interrupt is generated if the RX buffer contains data.
f o r 1: An interrupt is generated if the RX buffer contains data.
e a s e I - R 2
l
11002004 UARTn_DLM Divisor Latch (MS) 0000
Bit
Name
Type
15 14 13
Re Pi B
12
P
11 10 9 8 7 6 5 4
DLM
RW
3 2 1 0
a
Reset 0 0 0 0 0 0 0 0
Ba
MT7623N
f o r
e a s e I - R 2
l
7:0 DLM
Re Pi B
DLM
P Modified when LCR[7] = 1
11002008 UARTn_IIR
a n a Interrupt Identification Register 0001

Bit
Name
Type
Reset
15 14 13
Ba n 12 11 10 9 8 7 6 5
ID4
RU
0
4
ID3
RU
0
3
ID2
RU
0
2
ID1
RU
0
1
ID0
RU
0
0
NINT
RU
1
Overview: Identifies if there are pending interrupts. ID4 and ID3 are presented only when EFR[4] = 1.

5 ID4 ID4
4 ID3 ID3
3 ID2 ID2
2 ID1 ID1
1
0
ID0
NINT
ID0
NINT
f o r
e a s e I - R 2
11002008
Bit 15
UARTn_FCR
14 13 l
Re Pi B
12 P
FIFO Control Register
11 10 9 8 7 6
RFTL1_RFTL TFTL1_TFTL
5 4 3 2 1
0000
0
a
Name 0 0
FIFOE
Type
Reset
n a n 0
WO
0 0
WO
0
WO
0
Bit(s) Mnemonic
Ba
Overview: FCR is used to control the trigger levels of the FIFOs or flush the FIFOs. FCR[7:6] is modified when
LCR != BFh. FCR[5:4] is modified when LCR != BFh & EFR[4] = 1. FCR[4:0] is modified when LCR != BFh.
Name Description
7:6 RFTL1_RFTL0 RFTL1_RFTL0 RX FIFO trigger threshold
RX FIFO contains total 24 bytes.
0: 1
1: 6
2: 12
3: RXTRIG
5:4 TFTL1_TFTL0 TFTL1_TFTL0
f o r TX FIFO trigger threshold

TX FIFO contains total 16 bytes.
e
0: 1
l e a s I - R 21: 4
2: 8
0 FIFOE
Re Pi B
FIFOE
P 3: 14 (FIFOSIZE - 2)
Enables FIFO
This bit must be set to 1 for any of the other bits in the registers to
a
have any effect.
Ba
MT7623N
f o r
0: Disable both RX and TX FIFOs
l
Re Pi B P 1: Enable both RX and TX FIFOs.
11002008 UARTn_EFR
a n a Enhanced Feature Register 0000
n
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Ba
AUTO AUTO
Name SW_FLOW_CONT
_CTS _RTS
Type RW RW RW
Reset 0 0 0 0 0 0
Overview: Only when LCR = BF'h

7 AUTO_CTS AUTO_CTS Enables hardware transmission flow control
0: Disable
1: Enable
6 AUTO_RTS AUTO_RTS Enables hardware reception flow control
f o r 0: Disable
1: Enable.
3:0
NT NT
a s e - 2
SW_FLOW_CO SW_FLOW_CO Software flow control bits
R
00xx: No TX flow control
e I
l
Re Pi B P
10xx: Transmit XON1/XOFF1 as flow control bytes
01xx: Transmit XON2/XOFF2 as flow control bytes
11xx: Transmit XON1 & XON2 and XOFF1 & XOFF2 as flow control
words
a n a
xx00: No RX flow control
xx10: Receive XON1/XOFF1 as flow control bytes
Ba n xx01: Receive XON2/XOFF2 as flow control bytes

xx11: Receive XON1 & XON2 and XOFF1 & XOFF2 as flow control
words
1100200C UARTn_LCR Line Control Register 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DLAB SB SP EPS PEN STB WLS1_WLS0
Reset 0 0 0 0 0 0 0 0
Overview: Determines characteristics of serial communication signals. Modified when LCR[7] = 0.
f o r Description
7 DLAB DLAB
e a s e I - R 2Divisor latch access bit

0: The RX and TX registers are read/written at Address 0 and the
6 SB SB
l
Re Pi B P
IER register is read/written at Address 4.
1: The Divisor Latch LS is read/written at Address 0 and the Divisor
Latch MS is read/written at Address 4.
Sets up break
a n a
n
Ba
MT7623N
f o r
0: No effect
5 SP SP l
Re Pi B P 1: SOUT signal is forced into the "0" state.
Stick parity
0: No effect.
a n a 1: The parity bit is forced into a defined state, depending on the

states of EPS and PEN: If EPS = 1 & PEN = 1, the parity bit is set
n
and checked = 0. If EPS = 0 & PEN = 1, the parity bit is set and
Ba
checked = 1.
4 EPS EPS Selects even parity
0: When EPS = 0, an odd number of ones is sent and checked.
1: When EPS = 1, an even number of ones is sent and checked.
3 PEN PEN Enables parity
0: The parity is neither transmitted nor checked.
1: The parity is transmitted and checked.
2 STB STB Number of STOP bits
0: One STOP bit is always added.
1: Two STOP bits are added after each character is sent; unless the
character length is 5 when 1 STOP bit is added.
1:0 WLS1_WLS0 WLS1_WLS0 Selects word length
f o r 0: 5 bits
1: 6 bits
e a s e I - R 2
2: 7 bits
3: 8 bits
11002010 UARTn_MCR
l
Re Pi B P
Modem Control Register 0000
Bit 15 14 13
a n a
12 11 10 9 8
XOFF
7 6 5 4 3 2 1 0
n
Name _STAT Loop OUT2 OUT1 RTS DTR
Ba
US
Type RU RW RW RW RW RW
Reset 0 0 0 0 0 0
Overview: Control interface signals of the UART. MCR[5:0] are modified when LCR != 8'hBF, MCR[7] are
modified when LCR != 8'hBF & EFR[4] = 1.

7 XOFF_STATUS XOFF_STATUS A read-only bit
0: When an XON character is received
1: When an XOFF character is received
4 Loop Loop Loop-back control bit.
r
0: No loop-back is enabled.
3 OUT2 OUT2
e f o 2
1: Loop-back mode is enabled.
Controls the state of the output NOUT2, even in loop mode.
s
0: NOUT2 = 1
2 OUT1 OUT1
l e a P I - R 1: NOUT2 = 0
Controls the state of the output NOUT1, even in loop mode.
Re Pi B
0: NOUT1 = 1
1: NOUT1 = 0
1 RTS RTS Controls the state of the output NRTS, even in loop mode.
a n a
n
Ba
MT7623N
f o r
0: NRTS = 1
0 DTR DTR
l
Re Pi B P
1: NRTS = 0
Controls the state of the output NDTR, even in loop mode.
0: NDTR = 1
1: NDTR = 0
a n a
11002010
Bit
Name
15 14
Ba
UARTn_XON1
13
n 12
XON1
11 10 9 8 7 6 5 4
XON1
3 2 1
0000
0
Type RW
Reset 0 0 0 0 0 0 0 0
Overview: XON1, XON2, XOFF1, XOFF2 are valid only when LCR=BF'h.

7:0 XON1 XON1 Auto-baud enabling signal
f o r
e
11002014 UARTn_LSR Line Status Register 0060
Bit
Name
15 14 13
l
12
e a s 11
I - R 2
10 9 8 7
FIFOE
6
TEMT THRE
5 4
BI
3
FE
2
PE
1
OE
0
DR
Re Pi B P
RR
Type RU RU RU RU RU RU RU RU
Reset 0 1 1 0 0 0 0 0
a n a
Overview: Modified when LCR != BFh.
Bit(s) Mnemonic
7 FIFOERR
Ba n
Name
FIFOERR
Description
RX FIFO error indicator
0: No PE, FE, BI set in the RX FIFO.
1: Set to 1 when there is at least one PE, FE or BI in the RX FIFO.
6 TEMT TEMT TX holding register (or TX FIFO) and the TX shiftrRegister are
empty
0: Empty conditions below are not met.
1: If FIFOs are enabled, the bit is set whenever the TX FIFO and the
TX shift register are empty. If FIFOs are disabled, the bit is set
whenever TX holding register and TX shift register are empty.
5 THRE THRE Indicates if there is room for TX holding register or TX FIFO is
reduced to its trigger level
f o r 0: Reset whenever the contents of the TX FIFO are more than its
trigger level (FIFOs are enabled), or whenever TX holding register
e
is not empty (FIFOs are disabled).
l e a s I - R 21: Set whenever the contents of the TX FIFO are reduced to its
trigger level (FIFOs are enabled), or whenever TX holding register
is empty and ready to accept new data (FIFOs are disabled).
4 BI
Re Pi B
BI
P Break interrupt
0: Reset by the CPU reading this register
1: If FIFOs are disabled, this bit is set whenever the SIN is held in
a n a
n
Ba
MT7623N
f o r
the 0 state for more than one transmission time (START bit +
l
Re Pi B P DATA bits + PARITY + STOP bits). If the FIFOs are enabled, this
error is associated with a corresponding character in FIFO and is
flagged when this byte is at the top of FIFO. When a break occurs,
only one zero character is loaded into FIFO: the next character
a n a transfer is enabled when SIN enters the marking state and

receives the next valid start bit.
3 FE
Ba n
FE Framing error
1: If FIFOs are disabled, this bit will be set if the received data do not
have a valid STOP bit. If FIFOs are enabled, the state of this bit
will be revealed when the byte it refers to is the next to be read.
2 PE PE Parity error
1: If FIFOs are disabled, this bit will be set if the received data do not
have a valid parity bit. If FIFOs are enabled, the state of this bit is
revealed when the referred byte is the next to be read.
1 OE OE Overrun error
0: Reset by the CPU reading this register.
1: If FIFOs are disabled, this bit will be set if the RX buffer is not read
f o r by the CPU before the new data from the RX shift register
overwrites the previous contents. If FIFOs are enabled, an overrun
error occurs when RX FIFO is full and the RX shift register
e a s e I - R 2
becomes full. OE is set as soon as this happens. The character in
the shift register is then overwritten, but not transferred to FIFO.
0 DR DR
l
Re Pi B P
Data ready
0: Cleared by the CPU reading the RX buffer or by reading all the
FIFO bytes.
1: Set by the RX buffer becoming full or by a byte being transferred
a n a into the FIFO.
11002014
Bit
Name
15 14
Ba
UARTn_XON2
13
n 12
XON2
11 10 9 8 7 6 5 4
XON2
3 2 1
0000
0
Type RW
Reset 0 0 0 0 0 0 0 0

7:0 XON2 XON2
11002018
Bit 15
UARTn_MSR
14 13 12 11
f o r
Modem Status Register
10 9 8 7 6 5 4 3 2 1
0000
0
Name
Type
Reset
e a s e I - R 2
CTS
RO
0
DCTS
RW
0
l
Re Pi B P
Overview: After a reset, D4-D7 are inputs. A modem status interrupt can be cleared by writing 0 or set by writing
1 to this register. D0-D3 can be written to. Modified when LCR[7] = 0.
a n a
n
B a
MT7623N
f o r
l
4 CTS CTS Clear to send
Re Pi B P When Loop = 0, this value is the complement of the NCTS input

signal.
When Loop = 1, this value is equal to the RTS bit in the modem
a
control register.
0 DCTS DCTS
n a n Delta clear to send

0: Cleared if the state of CTS has not changed since this register
Ba
was last read.
1: Set if the state of CTS has changed since this register was last
read.
11002018 UARTn_XOFF1 XOFF1 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name XOFF1
Type RW
Reset 0 0 0 0 0 0 0 0
r
7:0 XOFF1 XOFF1
e f o 2
l e a s I - R
1100201C
Bit
Name
Type
15
UARTn_SCR
14 13
Re Pi B
12
P
Scratch Register
11 10 9 8 7 6 5 4
SCR
3 2 1
0000
0
a
RW
n
Reset 0 0 0 0 0 0 0 0
n a
Overview: A general-purpose read/write register. After reset, its value will be un-defined. Modified when LCR !=
Ba
BFh.

7:0 SCR SCR
UARTn_XOFF2 XOFF2 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name XOFF2
Type RW
r
Reset 0 0 0 0 0 0 0 0
e f o 2
Description
7:0 XOFF2 XOFF2
l e a s I - R
11002020
Re Pi B
UARTn_AUTOBAUD_EN
P AUTOBAUD_EN 0000
a n a
n
Ba
MT7623N
f o r
Bit 15 14 13 12
e a s e 11
I - R 2
10 9 8 7 6 5 4 3 2 1
AUTO
0
AUTO
l
Name BAUD
P
_EN
Re Pi B
_SEL
Type RW RW
Reset 0 0
a n a Description
n
1 AUTOBAUD_S AUTOBAUD_SE Selects auto-baud
Ba
EL L 0: No effect
1: Does not fix baud rate at standard value
0 AUTO_EN AUTOBAUD_EN Auto-baud enabling signal
0: Disable auto-baud function
1: Enable auto-baud function (UARTn+0024h SPEED should be set
0.)
11002024 UARTn_HIGHSPEED HIGH SPEED UART 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SPEED
Type
Reset
f o r 0
RW
0
l
Re Pi B P
UART sample counter base
0: Based on 16*baud_pulse, baud_rate = system clock
frequency/16/{DLH, DLL}
1:0 SPEED SPEED
a n a frequency/8/{DLH, DLL}
n
frequency/4/{DLH, DLL}
Ba
3: Based on sampe_count * baud_pulse, baud_rate = system clock
frequency/sampe_count/{DLM, DLL}
11002028 UARTn_SAMPLE_COUNT SAMPLE_COUNT 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SAMPLECOUNT
Type RW
Reset 0 0 0 0 0 0 0 0
Overview: When HIGHSPEED = 3, sample_count will be the threshold value for UART sample counter
r
(sample_num). Counts from 0 to sample_count.
e f o 2
Description
7:0
SAMPLECOUN SAMPLECOUN
T T
l e a s I - R
Re Pi B P
a
1100202C UARTn_SAMPLE_POINT SAMPLE_POINT 00FF
Ba
MT7623N
f o r
Bit
Name
15 14 13 12
e a s e 11
I - R 2
10 9 8 7 6 5 4
SAMPLEPOINT
3 2 1 0
l
Type RW
Reset
Re Pi B P 1 1
Overview: When HIGHSPEED = 3, UART gets the input data when sample_count=sample_num, e.g. system
1 1 1 1 1 1
a n a
clock = 13MHz, 921600 = 13000000/14. sample_count = 13 and sample point = 6 (sample the central point to
decrease the inaccuracy). SAMPLE_POINT is usually (SAMPLE_COUNT-1)/2 without the decimal.
Bit(s) Mnemonic
7:0
Ba n
Name
SAMPLEPOINT SAMPLEPOINT
Description
11002030 UARTn_AUTOBAUD_REG AUTOBAUD_REG 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BAUD_STAT BAUD_RATE
Type RO RO
Reset 0 0 0 0 0 0 0 0
r
7:4 BAUD_STAT BAUD_STAT
e f o 2
Autobaud format
0: Autobaud is detecting.
l e a s I - R
1: AT_7N1
2: AT_7O1
Re Pi B P 3: AT_7E1
4: AT_8N1
5: AT_8O1
a n a 6: AT_8E1
7: at_7N1
n
8: at_7E1
Ba
9: at_7O1
10: at_8N1
11: at_8E1
12: at_8O1
13: Autobaud detection fails.
3:0 BAUD_RATE BAUD_RATE Autobaud baud rate
0: 115,200
1: 57,600
2: 38,400
3: 19,200
4: 9,600
5: 4,800
f o r 6: 2,400
7: 1,200
e a s e I - R 28: 300
9: 110
1100203C
Bit 15
UARTn_GUARD
14 13
l
Re Pi B
12
P
Guard time added register
11 10 9 8 7 6 5 4 3 2 1
000F
0
a n a
n
Ba
MT7623N
f o r
Name
e a s e I - R 2 GUAR
D_EN
GUARD_CNT
l
Type RW RW
Reset
Bit(s) Mnemonic
Re Pi B
Name
P Description
0 1 1 1 1
4 GUARD_EN
n a
GUARD_EN
a
Guard interval added enabling signal
0: No guard interval added
3:0 GUARD_CNT
Ba n
GUARD_CNT
1: Add guard interval after stop bit
Guard interval count value
Guard interval = [1/(system clock/div_step/div)]*GUARD_CNT
11002040 UARTn_ESCAPE_DAT Escape character register 00FF

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ESCAPE_DAT
Type RW
Reset 1 1 1 1 1 1 1 1
r
e f o 2
Escapes character added before software flow control data and
escape character
s
7:0 ESCAPE_DAT ESCAPE_DAT
For example, if Tx data are xon (31h), with esc_en =1, UART
l e a P I - R transmits data as esc + CEh (~xon).
11002044 Re Pi B
UARTn_ESCAPE_EN Escape enable register 0000
Bit 15 14 13
a n a
12 11 10 9 8 7 6 5 4 3 2 1 0
ESC_
n
Name
EN
Ba
Type RW
Reset 0

Adds escape character in transmitter and removes escape
character in receiver by UART
0 ESC_EN ESC_EN 0: Does not deal with the escape character
1: Add escape character in transmitter and remove escape character
in receiver.
11002048
Bit 15
UARTn_SLEEP_EN
14 13 12 11
f o r
Sleep enable register
10 9 8 7 6 5 4 3 2 1
0000
0
Name
Type
e a s e I - R 2
SLEE
P_EN
RW
Reset

l
0
a n a
n
B a
MT7623N
f o r
l
For sleep mode issue
0 SLEEP_EN
Re Pi B
SLEEP_EN P 0: Does not deal with sleep mode indication signal
1: Activate hardware flow control or software control according to
software initial settings when the chip enters the sleep mode.
a
Release the hardware flow when the chip wakes up. However, for
n
software control, UART sends XON when being awaken and when
n a FIFO does not reach the threshold level.
1100204C
Bit 15 14
Ba
UARTn_DMA_EN
13 12 11
DMA enable register
10 9 8 7 6 5 4 3
TO_C
2 1
0000
0
TX_D RX_D
NT_A
Name UTOR
MA_E MA_E
N N
ST
Type RW RW RW
Reset 0 0 0

2
RST RST
f o r
TO_CNT_AUTO TO_CNT_AUTO Time-out counter auto reset register
0: After RX time-out happens, SW shall reset the interrupt by reading
e
UART 0x4C.
l e s I - 2
1: The time-out counter will be auto reset. Set this register when
a R
Rain's new DMA is used.
1 TX_DMA_EN
Re Pi B
TX_DMA_EN
P TX_DMA mechanism enabling signal

0: Does not use DMA in TX
1: Use DMA in TX. When this register is enabled, the flow control is
based on the DMA threshold and generates a time-out interrupt for
0 RX_DMA_EN
a n a
RX_DMA_EN
DMA.
RX_DMA mechanism enabling signal
Ba n 0: Does not use DMA in RX

1: Use DMA in RX. When this register is enabled, the flow control is
based on the DMA threshold and generates a time-out interrupt
11002050 UARTn_RXTRI_AD Rx Trigger Address 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RXTRIG
Type RW
Reset 0 0 0 0
r
3:0 RXTRIG RXTRIG
e f o 2
When {rtm,rtl}=2'b11, Rx FIFO threshold will be Rxtrig.
The value is suggested to be smaller than half the RX FIFO size,
l e a s I - R
which is 24 bytes.
11002054
Re Pi B
UARTn_FRACDIV_L P Fractional Divider LSB Address 0000
a
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Ba
MT7623N
f o r
Name
Type
e a s e I - R 2 FRACDIV_L
RW
l
Reset 0 0 0 0 0 0 0 0
Bit(s) Mnemonic
Re Pi B
Name P Description
a
Adds sampling count (+1) from state data7 to data0 to contribute to
7:0 FRACDIV_L FRACDIV_L
n
fractional divisor
n a
11002058
Bit
Name
Type
15 14 Ba
UARTn_FRACDIV_M
13 12 11
Fractional Divider MSB Address
10 9 8 7 6 5 4 3 2 1
0000
0
FRACDIV_M
RW
Reset 0 0

Adds sampling count when in state stop to parity to contribute to
1:0 FRACDIV_M FRACDIV_M
fractional divisor
f o r
e
1100205C UARTn_FCR_RD FIFO Control Register 0000
Bit
Name
15 14 13
l
12
e a s 11
I - R 2
10 9 8 7 6 5
RFTL1_RFTL TFTL1_TFTL
4 3 2 1 0
FIFOE
P
0 0
Re Pi B
Type RO RO RO
Reset 0 0 0 0 0
Bit(s) Mnemonic
7:6
Name
a n
RFTL1_RFTL0 RFTL1_RFTL0
a Description
RX FIFO trigger threshold
Ba n RX FIFO contains total 24 bytes.

0: 1
1: 6
2: 12
3: RXTRIG
5:4 TFTL1_TFTL0 TFTL1_TFTL0 TX FIFO trigger threshold
TX FIFO contains total 16 bytes.
0: 1
1: 4
2: 8
3: 14 (FIFOSIZE - 2)
0 FIFOE FIFOE Enables FIFO
f o r This bit must be set to 1 for any of the other bits in the registers to
have any effect.
e a s e I - R 2
0: Disable both RX and TX FIFOs
1: Enable both RX and TX FIFOs
11002060 DEBUG0
l
Re Pi B P
Debug Register 0 0000
Bit 15 14 13
a n a
12 11 10 9 8 7 6 5 4 3 2 1 0
n
Ba
MT7623N
f o r
Name
Type
e a s e I - R 2 DEBUG0
RU
l
Reset 0 0 0 0 0

a
4:0 DEBUG0 DEBUG0 TX state machine
n a n
11002064
Bit
Name
Type
Reset
15
DEBUG1
14
Ba
13 12
Debug Register 1
11 10 9 8 7 6 5 4 3
0
2
DEBUG1
0
RU
0
1
0000
0

3:0 DEBUG1 DEBUG1 RX state machine
11002090 RX_SEL UART RX Pin Sel 0000

Bit
Name
15 14 13 12
f
11
o r 10 9 8 7 6 5 4 3 2 1 0
RX_S
e
EL
s 2
Type RW
a R
Reset 0
l e P I -
Re Pi B
Selects RX pin
a
0 RX_SEL RX_SEL Note: Only UART 0 can choose USB pin.
n
0: Choose UART RX pin
n a 1: Choose USB pin
Ba
f o r
e a s e I - R 2
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
9 I2C
e a s e I - R 2
9.1 Introduction
l
Re Pi B P
a n a
I2C (Inter-IC)/SCCB (Serial Camera Control Bus) is a two-wire serial interface. The two signals are
Ba n
SCL and SDA. SCL is a clock signal that is driven by the master. SDA is a bi-directional data signal
that can be driven by either the master or the slave. This generic controller supports the master role
and conforms to the I2C specification.
9.2 Feature list
 I2C compliant master mode operation

 Adjustable clock speed for LS/FS mode operation
 Supports 7-bit/10-bit addressing


Supports high-speed mode
Supports slave clock extension
f o r

 Manual transfer mode
e a s
START/STOP/REPEATED START condition
e I - R 2



Multi-write per transfer
Multi-read per transfer
l
Re Pi B
Multi-transfer per transaction P


a n a
Combined format transfer with length change capability.-
Active drive/wired-and I/O configuration
9.2.1
Ba n
Manual Transfer Mode
The controller offers manual mode
When the manual mode is selected, in addition to the slave address register, the controller has a built-
in 8byte deep FIFO which allows MCU to prepare up to 8 bytes of data for a write transfer, or read up
to 8 bytes of data for a read transfer.
f o r
e a s e I - R 2
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
9.3 Block Diagram
e a s e I - R 2
l
Re Pi B P Timing
Control
Multi-
Master
Control
Transactio
n Status
a n a I2C Bus
n
Fifo Condition
Ba
TX/RX I2C Master
APB Interface Apb regs Fifo
Acces Detection +
s Master Transaction FSM I/O Mode
I2C Bus
8bytes deep
select
I2C Master
Figure 9-1: Block Diagram of I2C

Module name: I2C Base address: (+11007000h)
f o r
Address Name
e a s e I - R 2
l
11007000 DATA_PORT 16 Data port register
11007004 SLAVE_ADDR
Re Pi B P 16 Slave address register

Interrupt mask register
a
This register provides masks for the corresponding
n
interrupt sources as indicated in intr_stat register.
11007008 INTR_MASK
n a 16
1 = Allow interrupt
Ba
0 = Disable interrupt
Note: While disabled, the corresponding interrupt will
not be asserted, however the intr_stat will still be
updated with the status, i.e. mask does not affect
intr_stat register values.
Interrupt status register
When an interrupt is issued by I2C controller, this
1100700C INTR_STAT 16 register will need to be read by MCU to determine the
cause for the interrupt. After this status has been read
and appropriate actions are taken, the corresponding
interrupt source will need to be written 1 to clear.
11007010 CONTROL 16 Control register
11007014 TRANSFER_LEN
f o r 16 Transfer length register (number of bytes per transfer)

Transaction length register (number of transfers per
e
11007018 TRANSAC_LEN 16
s 2
transaction)
1100701C DELAY_LEN
l e a P I - R16 Inter delay length register
Re Pi B
Timing controlregister
11007020 TIMING 16 LS/FS only. This register is used to control the output
waveform timing. Each half pulse width, i.e. each high
a
or low pulse, is equal to
Ba
MT7623N
f o r
Address Name
e a s e I - R 2
l
step_cnt_div+1*(sample_cnt_div+1)*1/4*BASE_CLO
11007024
11007028 Re Pi B
START
EXT_CONF
P 16
16
CK_PERIOD
Start register
Extension configuration register
11007030 FIFO_STAT
a n a 16 FIFO status register
11007034
Ba n
FIFO_THRESH 16
FIFO thresh register
(For debugging only) By default, these values do not
need to be adjusted.
Note: For RX, no time-out mechanism is
implemented. Therefore, RX_trig_thresh must be left
at 0, or there would be data left in FIFO that is not
fetched by the DMA controller.
11007038 FIFO_ADDR_CLR 16 FIFO address clear register
IO config register
11007040 IO_CONFIG 16 This register is used to configure the I/O for the SDA
and SCL lines to select between normal I/O mode, or
open-drain mode to support wired-and bus.
11007044 MULTIMAS
f o r 16
Multiple I2C masters
This registers contains options for supporting multi-
e a s e I - R 2
master features.
High speed mode register
11007048 HS
l
Re Pi B P 16
This register contains options for supporting high
speed operation features.
Each HS half pulse width, i.e. each high or low pulse,
is equal to
11007050 SOFTRESET
a n a 16
step_cnt_div*(sample_cnt_div*1/16.25MHz)
Soft reset register
11007054
11007064
11007068 Ba n
HW_DCM_EN
DEBUGSTAT
DEBUGCTRL
16
16
16
HW DCM enable
Debug status register
Debug control register
11007000 DATA_PORT Data Port Register 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DATA_PORT
Type RW
Reset 0 0 0 0 0 0 0 0
f o r Description
e
FIFO access port
DATA_PO
l e a s I - R 2 During master write sequences (slave_addr[0] = 0), this port can be

written by APB, and during master read sequences (slave_addr[0] =
P
7:0 DATA_PORT 1), this port can be read by APB.
Re Pi B
RT
Note: Slave_addr must be set correctly before accessing FIFO.
For debugging only: If the fifo_apb_debug bit is set, FIFO can be
read and written by the APB.
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
11007004
Bit
Name
15
SLAVE_ADDR
14 13 l
Re Pi B
12 P
Slave Address Register
11 10 9 8 7 6 5 4
SLAVE_ADDR
3 2 1
00BF
0
Type
Reset
a n a 1 0 1 1
RW
1 1 1 1
Bit(s) Mnemonic
SLAVE_A
Ba
Name
n Description
Specifies the slave address of the device to be accessed
Bit 0 is defined by the I2C protocol as a bit that indicates the
7:0 SLAVE_ADDR direction of transfer.
DDR
0: Master write
1: Master read
11007008 INTR_MASK Interrupt Mask Register 00FF

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
MAS MAS
MAS MAS
o
K_HS K_TR
f
K_AR K_AC
Name SPARE
B_LO
_NAC
KER
ANS
e
KER AC_C
s 2
ST R
R OMP
Type
Reset
l e a P I - R 1 1
RW
1 1
RW
1
RW
1
RW
1
RW
1
Re Pi B
Overview: This register provides masks for the corresponding interrupt sources as indicated in intr_stat register.
1 = allow interrupt; 0 = disable interrupt. Note that while disabled, the corresponding interrupt will not be asserted.
a n a
However, intr_stat will still be updated with the status, i.e. mask does not affect intr_stat register values.
Bit(s)
7:4
3
Mnemonic
SPARE
MASK_AR
B_LOST Ba
Name
n
SPARE
MASK_ARB_LOS
T
Description
Reserved
Setting this value to 0 will mask ARB_LOST interrupt signal.
2 MASK_HS MASK_HS_NAC Setting this value to 0 will mask HS_NACKERR interrupt signal.
_NACKER KERR
R
1 MASK_AC MASK_ACKERR Setting this value to 0 will mask ACK_ERR interrupt signal.
KERR
0 MASK_TR MASK_TRANSA Setting this value to 0 will mask TRANSAC_COMP interrupt signal.
ANSAC_C C_COMP
OMP
f o r
1100700C
Bit 15
INTR_STAT
14 13
e
12
a s e 11
I - R 2
Interrupt Status Register
10 9 8 7 6 5 4 3 2 1
0000
0
Name
l
Re Pi B P ARB_
LOST
HS_N
ACKE
RR
TRAN
ACK SAC_
ERR COM
P
a
Type W1 W1 W1 W1
Ba
MT7623N
f o r
1100700C INTR_STAT
e a s e R 2
Interrupt Status Register
I -
0000
l
C C C C
Reset
Re Pi B P
Overview: When an interrupt is issued by the I2C controller, this register will need to be read by MCU to
0 0 0 0
a n a
determine the cause for the interrupt. After this status has been read and appropriate actions are taken, the
corresponding interrupt source will need to be written 1 to clear.
Bit(s)
3
Mnemonic
ARB_LOS
T Ba
Name
n
ARB_LOST
Description
This status is asserted if the I2C controller loses arbitration.
2 HS_NACK HS_NACKERR This status is asserted ifHS master code NACK error detection is
ERR enabled. If enabled, HS master code NACK err will cause
transaction to end, and stop will be issued.
1 ACKERR ACKERR This status is asserted if ACK error detection is enabled. If enabled,
ACKERR will cause transaction to end, and stop will be issued.
0 TRANSAC TRANSAC_COM This status is asserted when a transaction is completed
_COMP P successfully.
11007010 CONTROL
f o r
Control Register 0000
Bit 15 14 13 12
e a s e 11
I - R 2
10 9 8 7 6
TRAN
5 4 3 2 1 0
l
ACK
SFER DIR_ CLK_
Re Pi B P
ERR_ DMA_ RS_S
Name _LEN CHA EXT_
DET_ EN TOP
_CHA NGE EN
EN
NGE
Reset
a n a 0 0 0 0 0 0
Bit(s)
6
Mnemonic
TRANSFE
R_LEN_C
HANGE
Name
Ba n
TRANSFER_LEN
_CHANGE
Description
Specifies whether or not to change the transfer length after the
fist transfer is completed
If enabled, the transfers after the first transfer will use the
transfer_len_aux parameter.
5 ACKERR_ ACKERR_DET_E Enables slave ACK error detection
DET_EN N When enabled, if slave ACK error is detected, the master shall
terminate the transaction by issuing a STOP condition and then
asserts the ACKERR interrupt. MCU handles this case
appropriately and then resets the FIFO address before reissuing
transaction again. If this option is disabled, the controller will ignore
slave ACK error and keep on scheduled transaction.
0: Disable
r
1: Enable
4 DIR_CHA
NGE
DIR_CHANGE
e f o 2
Combined transfer format, where the direction of transfer is to
be changed from write to read after the FIRST RS condition
l e a s I - R
Note: When set to 1, the transfers after the direction change will be
based on the transfer_len_aux parameter.
P
0: Disable
Re Pi B
1: Enable
3 CLK_EXT CLK_EXT_EN I2C spec allows slaves to hold the SCL line low if it is not yet
_EN ready for further processing.
a n a
n
Ba
MT7623N
f o r
Therefore, if this bit is set to 1, the master controller will enter a high
2 DMA_EN DMA_EN
l
Re Pi B P wait state until the slave releases the SCL line.
By default, this is disabled, and the FIFO data shall be
manually prepared by MCU.
a
This default setting should be used for transfer sizes of smaller than
n
8 data bytes and no multiple transfer is configured. When enabled,
n a DMA requests are turned on, and the FIFO data should be prepared
in memory.
Ba
1 RS_STOP RS_STOP In LS/FS mode, this bit affects multi-transfer transaction only.
It controls whether or not the REPEATED-START condition is used
between transfers. The last ending transfer always ends with a
STOP.
In HS mode, this bit must be set to 1.
0: Use STOP
1: Use REPEATED-START
TRANSFER_L Transfer Length Register (Number of Bytes per

11007014 0101
EN Transfer)
Bit
Name
15 14 13 12 11
f o r 10
TRANSFER_LEN_AUX
9 8 7 6 5 4
TRANSFER_LEN
3 2 1 0
e
Type RW RW
Reset
l
0
e a s
0
I
0
- R 2
0 1 0 0 0 0 0 0 0 1
Bit(s)
12:8
Mnemonic
TRANSFE
R_LEN_A
Re Pi B
Name
TRANSFER_LEN
_AUX P Description
This field is valid only when dir_change is set to 1.
Indicates the number of data bytes to be transferred in 1 transfer
a
UX unit (excluding slave address byte) for the transfers following the
n a n direction change. That is, if dir_change =1, then the first write
transfer length will depend on transfer_len, while the second read
Ba
transfer length depend on transfer_len_aux. Dir change is always
after the first transfer.
Note: The value must be set to be bigger than 1; otherwise no
transfer will take place.
7:0 TRANSFE TRANSFER_LEN Indicates the number of data bytes to be transferred in 1
R_LEN transfer unit (excluding slave address byte)
TRANSAC_LE Transaction Length Register (Number of Transfers

11007018 0001
N per Transaction)
Bit
Name
15 14 13 12 11
f o r 10 9 8 7 6 5 4
TRANSAC_LEN
3 2 1 0
e
Type RW
Reset
l e a s I - R 2 0 0 0 0 0 0 0 1
Bit(s)
7:0
Mnemonic
TRANSAC
_LEN Re Pi B
Name
TRANSAC_LEN
P Description
Indicates the number of transfers to be transferred in 1
transaction
a n a Note: The value must be set to be bigger than 1; otherwise no
n
Ba
MT7623N
f o r
l
Re Pi B P
a
1100701C DELAY_LEN Inter Delay Length Register 0002
Bit
Name
15 14 13
n a n12 11 10 9 8 7 6 5 4
DELAY_LEN
3 2 1 0
Ba
Type RW
Reset 0 0 0 0 0 0 1 0

Sets up wait delay between consecutive transfers when
DELAY_L RS_STOP bit is set to 0
7:0 DELAY_LEN
EN
Unit: Half the pulse width
11007020 TIMING Timing Control Register 1303

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
DATA
_REA
D_AD
DATA_READ_TIME
f o r
SAMPLE_CNT_DIV STEP_CNT_DIV
Type
Reset
J
RW
0 0
RW
0 1
e a s e I
0
- R 2 RW
1 1 0 0 0
RW
0 1 1
l
Re Pi B P
Overview: LS/FS only. This register is used to control the output waveform timing. Each half pulse width, i.e.
each high or low pulse, is equal to step_cnt_div+1*(sample_cnt_div+1)*1/4*BASE_CLOCK_PERIOD.
a n a Description
15 DATA_RE
AD_ADJ J
B n
DATA_READ_AD
a
When set to 1, data latch in sampling time during master reads are
adjusted according to the DATA_READ_TIME value. Otherwise, by
default, the data are latched in at half of the high pulse width point.
This value must be set to be smaller than or equal to half the high
pulse width.
14:12 DATA_RE DATA_READ_TI This value is valid only when DATA_READ_ADJ is set to 1. This
AD_TIME ME can be used to adjust so that the data are latched in at earlier
sampling points (assuming data are settled by then)
10:8 SAMPLE_ SAMPLE_CNT_D Used for LS/FS only. This adjusts the width of each sample.
CNT_DIV IV (sample width = sample_cnt_div*1/4 BASE_CLOCK_PERIOD)
5:0 STEP_CN STEP_CNT_DIV Specifies the number of samples per half pulse width, i.e. each high
T_DIV or low pulse
f o r
e
11007024 START Start Register 0000
Bit
Name
15 14 13
l
12
e a s 11
I - R 2
10 9 8 7 6 5 4 3 2 1 0
STAR
P
T
Re Pi B
Type RW
Reset 0
a n a
n
Ba
MT7623N
f o r
l
Starts the transaction on the bus
P
0 START START
Re Pi B
It is auto de-asserted at the end of the transaction.
11007028 EXT_CONF
a n a Extension Configuration Register 1800

Bit
Name
Type
Reset
15
0
14
0
13
Ba
0
n 12
EXT_TIME
1
RW
11
1
10
0
9
0
8
0
7 6 5 4 3 2 1 0
EXT
_EN
RW
0

15:8 EXT_TIME EXT_TIME Configurable extension time of start condition
Time unit: 1/4 BASE_CLOCK_PERIOD
Note: The max. value is {0xFF - SAMPLE_CNT_DIV}.
0 EXT_EN EXT_EN Used for standard mode only (baud rate is up to 100kHz)
This option decides to perform the extension of start /stop condition.
If enabled, perform the extension; otherwise not.
f o r 0: Disable
1: Enable
e a s e I - R 2
11007030
Bit
Name
15
FIFO_STAT
14
RD_ADDR
13 l
Re Pi B
12
P
FIFO Status Register
11 10
WR_ADDR
9 8 7 6
FIFO_OFFSET
5 4 3 2 1
0001
0
WR_ RD_E
a
FULL MPTY
n
Type RU RU RU RU RU
a
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit(s)
15:12
Mnemonic
RD_ADDR
Ba
Name
n
RD_ADDR
Description
Current RD address pointer
Only bit [2:0] has physical meaning.
11:8 WR_ADD WR_ADDR Current WR address pointer
R Only bit [2:0] has physical meaning.
7:4 FIFO_OFF FIFO_OFFSET wr_addr[3:0] - rd_addr[3:0]
SET
1 WR_FULL WR_FULL Indicates FIFO is full
0 RD_EMPT RD_EMPTY Indicates FIFO is empty
Y
f o r
11007034
FIFO_THRES
H
e a s e I - R 2
FIFO Thresh Register 0700
Bit
Name
Type
Reset
15 14 13
l12
Re Pi B P
11 10 9
TX_TRIG_THRESH
1
RW
1 1
8 7 6 5 4 3 2
0
1
RW
0 0
0
RX_TRIG_THRESH
a n a
n
Ba
MT7623N
f o r
a s e - 2
Overview: For debugging only. By default, these values do not need to be adjusted. Note that for RX, no time-out
R
mechanism is implemented. Therefore, RX_trig_thresh must be left at 0, or there will be data left in FIFO that is
e I
l
Re Pi B
not fetched by the DMA controller.
P Description
10:8 TX_TRIG_
THRESH SH
a n a
TX_TRIG_THRE When Tx FIFO level is below this value, Tx DMA request is
asserted.
2:0 RX_TRIG_
THRESH
Ba
SH
n
RX_TRIG_THRE When Rx FIFO level is above this value, Rx DMA request is
asserted.
FIFO_ADDR_
11007038 FIFO Address Clear Register 0000
CLR
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFO
_ADD
Name
R_CL
R
Type WO
Reset 0
f o r Description
0
FIFO_AD
DR_CLR
FIFO_ADDR_CL
R
e a s e I - R 2 When written with 1'b1, a 1 pulse fifo_addr_clr is generated to clear

the FIFO address to back to 0.
11007040 IO_CONFIG
l
Re Pi B P
IO Config Register 0003
Bit 15 14 13
a n a
12 11 10 9 8 7 6 5 4 3 2 1
SDA_ SCL_
0
n
IDLE IO_S
IO_C IO_C
Ba
Name _OE_ YNC_
ONFI ONFI
EN EN
G G
Type RW RW RW RW
Reset 0 0 1 1
Overview: This register is used to configure the I/O for the SDA and SCL lines to select between normal I/O
mode, or open-drain mode to support wired-and bus.

3 IDLE_OE_ IDLE_OE_EN 0: Does not drive bus in idle state
EN 1: Drive bus in idle state
2 IO_SYNC_ IO_SYNC_EN For debugging only
r
EN When set to 1, SCL and SDA inputs will be first dual synced by
1 SDA_IO_ SDA_IO_CONFI
e f o 2
bclk_ck. This should not be needed. Only reserved for debugging.
0: Normal tristate I/O mode
0
CONFIG
SCL_IO_C
G
l e a
SCL_IO_CONFIG
s I - R
1: Open-drain mode
0: Normal tristate I/O mode
ONFIG
Re Pi B P 1: Open-drain mode
a n a
n
Ba
MT7623N
f o r
11007044 MULTIMAS
e a s e R 2
Multiple I2C Masters
I -
0000
l
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Re Pi B P BUS_ CLK_
DET_ SYNC
EN
RW
_EN
RW
ARB_
EN
RW
Reset
a n a 0 0 0
Bit(s)
2
Mnemonic
BUS_DET Ba
Name
n
Overview: This registers contains options for supporting multi-master features.
BUS_DET_EN
Description
When enabled, the bus status is monitored, and if the bus is
_EN currently busy, no new transaction can proceed.
1 CLK_SYN CLK_SYNC_EN When enabled, clk synchronization will be performed.
C_EN
0 ARB_EN ARB_EN When enabled, multi-master arbitration will be performed.
11007048 HS High Speed Mode Register 0102

Bit 15 14 13 12 11
f o r 10 9 8 7 6 5 4 3 2 1
HS_N
0
e
ACK
2
HS_SAMPLE_CNT_ HS_E
s
Name DIV
HS_STEP_CNT_DIV MASTER_CODE ERR_
N
a R
DET_
Type
l e P I - EN
Re Pi B
RW RW RW RW RW
Reset 0 0 0 0 0 1 0 0 0 1 0
Overview: This register contains options for supporting high speed operation features. Each HS half-pulse width,
n a
i.e. each high or low pulse, is equal to step_cnt_div*(sample_cnt_div*1/16.25MHz).
a
Bit(s)
14:12
Mnemonic
HS_SAMP
LE_CNT_
DIV Ba
Name
n
HS_SAMPLE_CN
T_DIV
Description
When the high-speed mode is entered after the master code
transfer is completed, the sample width will become dependent on
this parameter.
10:8 HS_STEP HS_STEP_CNT_ When the high-speed mode is entered after the master code
_CNT_DIV DIV transfer is completed, the number of samples per half pulse width
will become dependent on this value.
6:4 MASTER_ MASTER_CODE This is the 3-bit programmable value for the master code to be
CODE transmitted.
1 HS_NACK HS_NACKERR_ Enables NACKERR detection during the master code
ERR_DET DET_EN transmission
_EN When enabled, if NACK is not received after the master code is
r
transmitted, the transaction will be terminated with a STOP
o
condition.
0 HS_EN HS_EN
s e f 2
Enables high-speed transaction
Note: rs_stop must be set to 1.
l e a P I - R
11007050 SOFTRESET
Re Pi B Soft Reset Register 0000
a
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Ba
MT7623N
f o r
11007050 SOFTRESET
e a s e R 2
Soft Reset Register
I -
0000
l
SOFT
Name
Type
Reset
Re Pi B P _RES
ET
WO
0
a n a Description
0
SOFT_RE
SET
Ba n
SOFT_RESET
When written with 1'b1, a 1 pulse soft reset is used as synchronous
reset to reset the I2C internal hardware circuits.
11007054 HW_DCM_EN HW DCM Enable 0001

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCM
Name _EN
Type RW
Reset 1
r
0 DCM_EN DCM_EN
e f o 2
Enables HW DCM function
Default is enable.
l e a s I - R
0: Disable
1: Enable
11007064 DEBUGSTAT Re Pi B P
Debug Status Register 0020
Bit 15 14 13
a n a
12 11 10 9 8 7
MAS MAS
6 5 4 3 2 1 0
Name
Type
Reset Ba n BUS_ TER_ TER_
BUSY WRIT REA
RU
0
E
RU
0
D
RU
1 0
MASTER_STATE
0
RU
0 0 0

7 BUS_BUS BUS_BUSY For debugging only
Y Valid when bus_detect_en is 1. bus_busy = 1 indicates a start
transaction has been detected and no stop condition has been
detected yet.
6 MASTER_ MASTER_WRITE For debugging only
WRITE 1: Current transfer is in the master write dir
5 MASTER_
READ
MASTER_READ
f o r For debugging only

1: Current transfer is in the master read dir
4:0 MASTER_
STATE
MASTER_STATE
e a s e I - R 2
For debugging only. Reads back the current master_state.
0: Idle state
l
Re Pi B P
1: I2C master is preparing sending out the start bit, SCL=1, SDA=1.
2: I2C master is sending out the start bit, SCL=1, SDA=0.
3: I2C master/slave is preparing transmitting data bit, SCL=0,
DA=data bit (data bit can be changed when SCL=0).
a n a 4: I2C master/slave is transmitting data bit, SCL=1, SDA=data bit
n
Ba
MT7623N
f o r
(data bit is stable when SCL=1).
l
Re Pi B P 5: I2C master/slave is preparing transmitting the ACK bit, SCL=0,
SDA=ack (The ACK bit can be changed when SCL=0)
6: I2C master/slave is transmitting the ACK bit, SCL=1, SDA=0 (ack
bit is stable when SCL=1)
a n a 7: I2C master is preparing sending out stop bit or repeated-start bit,

SCL=0, SDA=0/1 (0: Stop bit; 1: Repeated-start bit).
Ba n 8: I2C master is sending out stop bit or repeated-start bit, SCL=1,

SDA=1/0 (1: Stop bit; 0: Repeated-start bit).
9: I2C master is in delay start between two transfers, SCL=1,
SDA=1.
10: I2C master is in FIFO wait state; For writing transaction, it
means FIFO is empty and I2Cc master is waiting for DMA
controller writing data into FIFO; For reading transaction, it
means FIFOo is full and I2C master is waiting for DMA controller
reading data from FIFO, SCL=0, SDA=don't care.
12: I2C master is preparing sending out data bit of master code.
This state is used only in high-speed transaction, SCL=0,
SDA=data bit of master code (data bit of master code can be
changed when SCL=0).
13: I2C master is sending out data bit of master code. This state is
f o r used only in high-speed transaction, SCL=1, SDA=data bit of

master code (data bit of master code is stable when SCL=1)
e
14: I2C master/slave is preparing transmitting the NACK bit,
l e a s I - R 2 SCL=0, SDA=nack bit (The NACK bit can be changed when

SCL=0). This state is used only in high-speed transaction.
P
15: I2C master/slave is transmitting the NACK bit, SCL=1, SDA=1;
Re Pi B
This state is used only in high-speed transaction
11007068 DEBUGCTRL
a n a Debug Control Register 0000

Bit
Name
15 14
Ba
13
n 12 11 10 9 8 7 6 5 4 3 2 1 0
APB_ FIFO
DEB _APB
UG_R _DEB
D UG
Type WO RW
Reset 0 0

1 APB_DEB APB_DEBUG_R Only valid when fifo_apb_debug is set to 1
UG_RD D Writing to this register will generate a 1 pulsed FIFO APB RD signal
for reading the FIFO data.
0 FIFO_APB FIFO_APB_DEB Used for trace 32 debugging purposes
r
_DEBUG UG When using trace 32, and the memory map is shown, turning this
e f o 2
bit on will block the normal APB read access. The APB read access
to the FIFO is then enabled by writing to apb_debug_rd.
l e a s I - R
0: Disable
1: Enable
Address
Re Pi B
Name
P
Module name: I2C_SCCB_Controller base address : (+11007000h)
a n a
n
Ba
MT7623N
f o r
Address Name
l
11007000 DATA_PORT 16 Data port register
11007004 SLAVE_ADDR
Re Pi B P 16 Slave address register

Interrupt mask register
a
This register provides masks for the corresponding
n a n interrupt sources as indicated in the intr_stat

register.
Ba
11007008 INTR_MASK 16 1 = Allow interrupt
0 = Disable interrupt
Note: While disabled, the corresponding interrupt
will not be asserted. However the intr_stat will still
be updated with the status, i.e. mask does not affect
intr_stat register values.
Interrupt status register
When an interrupt is issued by I2C controller, this
register will need to be read by MCU to determine
1100700C INTR_STAT 16 the cause for the interrupt. After this status has been
read and appropriate actions are taken, the
corresponding interrupt source will need to be
r
written 1 to clear.
11007010 CONTROL
e f o 2
16 Control register
Transfer length register (number of bytes per
11007014 TRANSFER_LEN
l e a s I - R
16
transfer)
P
Transaction length register (number of transfers per
Re Pi B
11007018 TRANSAC_LEN 16
transaction)
1100701C DELAY_LEN 16 Inter delay length register
a
Timing control register
11007020 TIMING
n a n 16
LS/FS only. This register is used to control the
output waveform timing. Each half pulse width, i.e.
Ba
each high or low pulse, is equal to
(step_cnt_div+1)*(sample_cnt_div+1)*1/4*BASE_C
LOCK_PERIOD
11007024 START 16 Start register
11007028 EXT_CONF 16 Extension configuration register
11007030 FIFO_STAT 16 FIFO status register
FIFO thresh register
For debugging only. By default, these values do not
need to be adjusted.
11007034 FIFO_THRESH 16 Note: For RX, no time-out mechanism is
implemented. Therefore, RX_trig_thresh must be
f o r left at 0, or there will be data left in the FIFO that is

not fetched by the DMA controller.
11007038 FIFO_ADDR_CLR
e a s e I - R 2
16 FIFO address clear register
IO config register
11007040 IO_CONFIG
l
Re Pi B P 16 This register is used to configure the I/O for the SDA
and SCL lines to select between normal I/O mode,
or open-drain mode to support wired-and bus.
a
11007044 MULTIMAS 16 Multiple I2C masters
Ba
MT7623N
f o r
Address Name
l
This registers contains options for supporting multi-
Re Pi B P master features.
High speed mode register
This register contains options for supporting high
11007048 HS
a n a 16 speed operation features. Each HS half pulse width,

i.e. each high or low pulse, is equal to
11007050
11007054 Ba
SOFTRESET
HW_DCM_EN
n 16
16
(hs_step_cnt_div+1)*(hs_sample_cnt_div+1)*1/4*B
ASE_CLOCK_PERIOD
Soft reset register
HW DCM enable
11007064 DEBUGSTAT 16 Debug status register
11007068 DEBUGCTRL 16 Debug control register
11007000 DATA_PORT Data Port Register 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
Name DATA_PORT
o
Type RW
Reset
s e f 2
0 0 0 0 0 0 0 0
l e a P I - R
Description
Re Pi B
FIFO access port
During master write sequences (slave_addr[0] = 0), this port can be
written by APB, and during master read sequences (slave_addr[0] =
DATA_PO
7:0 DATA_PORT 1), this port can be read by APB.
a
RT
n
Note: Slave_addr must be set correctly before accessing FIFO.
a
For debugging only: If the fifo_apb_debug bit is set, FIFO can be
n
read and written by the APB.
11007004
B
SLAVE_ADDR
a Slave Address Register 00BF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SLAVE_ADDR
Type RW
Reset 1 0 1 1 1 1 1 1

Specifies the slave address of the device to be accessed
Bit 0 is defined by the I2C protocol as a bit that indicates the
7:0
SLAVE_A
DDR
SLAVE_ADDR
f o r direction of transfer.
0: Master writer
e a s e I - R 2
1: Master read
11007008
Bit 15
INTR_MASK
14 13
l
Re Pi B
12
P
Interrupt Mask Register
11 10 9 8 7 6 5 4 3 2 1
00FF
0
Name
a n a SPARE MAS MAS MAS MAS
n
Ba
MT7623N
f o r
11007008 INTR_MASK
e a s e R 2
Interrupt Mask Register
I -
00FF
l
K_AR K_HS K_AC K_TR
Type
Re Pi B P RW
B_LO _NAC KER ANS
ST
RW
KER
R
RW
R
RW
AC_C
OMP
RW
Reset
a n a 1 1 1 1 1 1 1 1
n
Overview: This register provides masks for the corresponding interrupt sources as indicated in intr_stat register.
Ba
1 = allow interrupt; 0 = disable interrupt Note that while disabled, the corresponding interrupt will not be asserted.
However, intr_stat will still be updated with the status, i.e. mask does not affect intr_stat register values.

7:4 SPARE SPARE Reserved
3 MASK_AR MASK_ARB_LOS Setting this value to 0 will mask ARB_LOST interrupt signal.
B_LOST T
2 MASK_HS MASK_HS_NAC Setting this value to 0 will mask HS_NACKERR interrupt signal.
_NACKER KERR
R
1 MASK_AC MASK_ACKERR Setting this value to 0 will mask ACK_ERR interrupt signal.
r
KERR
0 MASK_TR
ANSAC_C
MASK_TRANSA
C_COMP
e f o 2
Setting this value to 0 will mask TRANSAC_COMP interrupt signal.
OMP
l e a s I - R
1100700C INTR_STAT
Re Pi B P
Interrupt Status Register 0000
a
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
n
TRAN
HS_N
a
ARB_ ACK SAC_
Name
n
ACKE
LOST ERR COM
Ba
RR
P
Type W1C W1C W1C W1C
Reset 0 0 0 0
Overview: When an interrupt is issued by the I2C controller, this register will need to be read by MCU to
determine the cause for the interrupt. After this status has been read and appropriate actions are taken, the
corresponding interrupt source will need to be written 1 to clear.

3 ARB_LOS ARB_LOST This status is asserted if the I2C controller loses arbitration.
T
2 HS_NACK HS_NACKERR This status is asserted if HS master code NACK error detection is
ERR
f o r enabled. If enabled, HS master code NACK err will cause

transaction to end and stop will be issued.
1 ACKERR ACKERR
e a s e I - R 2
This status is asserted if ACK error detection is enabled. If enabled,
ACKERR will cause transaction to end and stop will be issued.
l
0 TRANSAC TRANSAC_COM This status is asserted when a transaction is completed
_COMP P
Re Pi B P successfully.
a n a
n
Ba
MT7623N
f o r
11007010 CONTROL
e a s e R 2
Control Register
I -
0000
l
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Re Pi B P TRAN
SFER
_LEN
_CHA
ACK
ERR_
DET_
DIR_ CLK_
CHA EXT_
NGE EN
DMA_ RS_S
EN TOP
a
EN
NGE
Type
Reset
n a n RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit(s)
6
Mnemonic
TRANSFE
R_LEN_C
HANGE
Ba
Name
TRANSFER_LEN
_CHANGE
Description
Specifies whether or not to change the transfer length after the
fist transfer is completed
If enabled, the transfers after the first transfer will use the
transfer_len_aux parameter.
5 ACKERR_ ACKERR_DET_E Enables slave ACK error detection
DET_EN N When enabled, if slave ACK error is detected, the master shall
terminate the transaction by issuing a STOP condition and then
asserts the ACKERR interrupt. MCU handles this case
appropriately and then resets the FIFO address before reissuing
transaction. If this option is disabled, the controller will ignore slave
r
ACK error and keep on scheduled transaction.
o
0: Disable
4 DIR_CHA DIR_CHANGE
s e f 2
1: Enable
Combined transfer format, where the direction of transfer is to
NGE
l e a P I - R be changed from write to read after the FIRST RS condition

Note: When set to 1, the transfers after the direction change will be
Re Pi B
based on the transfer_len_aux parameter.
0: Disable
1: Enable
3 CLK_EXT
_EN
a
CLK_EXT_EN
a n
I2C spec allows slaves to hold the SCL line low if it is not yet
ready for further processing.
n
Therefore, if this bit is set to 1, the master controller will enter a high
Ba
wait state until the slave releases the SCL line.
2 DMA_EN DMA_EN By default, this is disabled, and the FIFO data shall be
manually prepared by MCU.
This default setting should be used for transfer sizes of smaller than
8 data bytes and no multiple transfer is configured. When enabled,
DMA requests are turned on, and the FIFO data should be prepared
in memory.
1 RS_STOP RS_STOP In LS/FS mode, this bit affects multi-transfer transaction only.
It controls whether or not the REPEATED-START condition is used
between transfers. The last ending transfer always ends with a
STOP.
In HS mode, this bit must be set to 1.
0: Use STOP
f o r 1: Use REPEATED-START
e a s e I - R 2
l
TRANSFER_L Transfer Length Register (Number of Bytes per
P
11007014 0101
Re Pi B
EN Transfer)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TRANSFER_LEN_AUX TRANSFER_LEN
a
Type RW RW
Ba
MT7623N
f o r
11007014
TRANSFER_L
e a s e R 2
Transfer Length Register (Number of Bytes per
I - 0101
l
EN Transfer)
Reset
Bit(s) Mnemonic Re Pi B
Name
0
P
0 0 0
Description
1 0 0 0 0 0 0 0 1
12:8 TRANSFE
R_LEN_A
n a
TRANSFER_LEN
_AUX
a
This field is valid only when dir_change is set to 1.
n
Indicates the number of data bytes to be transferred in 1 transfer
Ba
UX unit (excluding slave address byte) for the transfers following the
direction change. That is, if dir_change =1, then the first write
transfer length will depend on transfer_len, while the second read
transfer length depends on transfer_len_aux. Dir change is always
after the first transfer.
7:0 TRANSFE TRANSFER_LEN Indicates the number of data bytes to be transferred in 1
R_LEN transfer unit (excluding slave address byte)
11007018
TRANSAC_LE
f o r
Transaction Length Register (Number of Transfers
0001
e
N per Transaction)
Bit
Name
15 14 13
l
12
e a s 11
I - R 2
10 9 8 7 6 5 4
TRANSAC_LEN
3 2 1 0
P
Type
Re Pi B
RW
Reset 0 0 0 0 0 0 0 1
a
7:0
TRANSAC
n a n
TRANSAC_LEN
Indicates the number of transfers to be transferred in 1
transaction
Ba
_LEN Note: The value must be set to be bigger than 1; otherwise no
1100701C DELAY_LEN Inter Delay Length Register 0002

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DELAY_LEN
Type RW
Reset 0 0 0 0 0 0 1 0
7:0
DELAY_L
EN
DELAY_LEN
f o r Sets up wait delay between consecutive transfers when

RS_STOP bit is set to 0
e
Unit: Half the pulse width)
l e a s I - R 2
11007020
Bit 15
TIMING
14 13
Re Pi B
12 P
Timing Control Register
11 10 9 8 7 6 5 4 3 2 1
1303
0
a
Name DATA DATA_READ_TIME SAMPLE_CNT_DIV STEP_CNT_DIV
Ba
MT7623N
f o r
11007020 TIMING
e a s e R 2
Timing Control Register
I -
1303
l
_REA
Type
Reset
D_AD
J
RW
0 0
RW
0
Re Pi B
1
P 0
RW
1 1 0 0 0
RW
0 1 1
a n a
Overview: LS/FS only. This register is used to control the output waveform timing. Each half pulse width, i.e.
Bit(s)
15
Mnemonic
DATA_RE Ba
Name
n
each high or low pulse, is equal to (step_cnt_div+1)*(sample_cnt_div+1)*1/4*BASE_CLOCK_PERIOD.
DATA_READ_AD
Description
When set to 1, data latch in sampling time during master reads are
AD_ADJ J adjusted according to the DATA_READ_TIME value. Otherwise, by
default, the data are latched in at half of the high pulse width point.
This value must be set to be smaller than or equal to half the high
pulse width.
14:12 DATA_RE DATA_READ_TI This value is valid only when DATA_READ_ADJ is set to 1. This
AD_TIME ME can be used to adjust so that the data are latched in at earlier
sampling points (assuming data are settled by then)
10:8 SAMPLE_ SAMPLE_CNT_D Used for LS/FS only. This adjusts the width of each sample.
CNT_DIV IV (sample width = sample_cnt_div*1/4 BASE_CLOCK_PERIOD)
5:0 STEP_CN
T_DIV
STEP_CNT_DIV
f o r Specifies the number of samples per half pulse width, i.e. each high
or low pulse
e a s e I - R 2
11007024
Bit 15
START
14 13 l
Re Pi B
12 P
Start Register
11 10 9 8 7 6 5 4 3 2 1
0000
0
STA
a
Name
RT
Type
Reset
n a n RW
0
Bit(s)
0
Mnemonic
START Ba
Name
START
Description
Starts the transaction on the bus
It is auto de-asserted at the end of the transaction.
11007028 EXT_CONF Extension Configuration Register 1800

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXT
Name EXT_TIME
_EN
Type RW RW
r
Reset 0 0 0 1 1 0 0 0 0
e f o 2
Description
15:8 EXT_TIME EXT_TIME
l e a s I - R Configurable extension time of start condition

Time unit: 1/4 BASE_CLOCK_PERIOD
0 EXT_EN
Re Pi B
EXT_EN P Note: The max. value is {0xFF - SAMPLE_CNT_DIV}.
Used for standard mode only (baud rate is up to 100kHz)
This option decides to perform the extension of start /stop condition.
a n a
n
Ba
MT7623N
f o r
If enabled, perform the extension; otherwise not.
l
Re Pi B P 0: Disable
1: Enable
11007030 FIFO_STAT
a n a FIFO Status Register 0001

Bit
Name
Type
Reset
15
0
14
RD_ADDR
0
RU
Ba
13
0
n 12
0
11
0
10
WR_ADDR
0
RU
9
0
8
0
7
0
6
FIFO_OFFSET
0
RU
5
0
4
0
3 2 1
ULL MPTY
RU
0
RU
1
0
WR_F RD_E

15:12 RD_ADDR RD_ADDR Current RD address pointer
Only bit [2:0] has physical meaning.
11:8 WR_ADD WR_ADDR Current WR address pointer
R Only bit [2:0] has physical meaning.
7:4 FIFO_OFF FIFO_OFFSET wr_addr[3:0] - rd_addr[3:0]
1
SET
WR_FULL WR_FULL
f o r Indicates FIFO is full

0 RD_EMPT
Y
RD_EMPTY
e a s e I - R 2
Indicates FIFO is empty
11007034
FIFO_THRES
l
Re Pi B P
FIFO Thresh Register 0700
Bit 15
H
14 13
a n a
12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset
Ba n TX_TRIG_THRESH
1
RW
1 1
Overview: For debugging only. By default, these values do not need to be adjusted. Note that for RX, no time-
RX_TRIG_THRESH
0
RW
0 0
out mechanism is implemented. Therefore, RX_trig_thresh must be left at 0, or there will be data left in FIFO that
is not fetched by the DMA controller.

10:8 TX_TRIG_ TX_TRIG_THRE When Tx FIFO level is below this value, Tx DMA request is
THRESH SH asserted.
2:0 RX_TRIG_ RX_TRIG_THRE When Rx FIFO level is above this value, Rx DMA request is
THRESH SH asserted.
f o r
11007038
FIFO_ADDR_
e a s e I - R 2
FIFO Address Clear Register 0000
l
CLR
Bit
Name
15 14 13
Re Pi B
12
P
11 10 9 8 7 6 5 4 3 2 1 0
FIFO_
ADDR
a
_CLR
Ba
MT7623N
f o r
11007038
FIFO_ADDR_
e a s e I - R 2
FIFO Address Clear Register 0000
l
CLR
Type
Reset
Re Pi B P WO
0
Bit(s) Mnemonic
FIFO_AD
Name
a n a
FIFO_ADDR_CL
Description
When written with 1'b1, a 1 pulse fifo_addr_clr is generated to clear
n
0
DR_CLR R the FIFO address to back to 0.
11007040
Bit 15
IO_CONFIG
14
Ba
13 12
IO Config Register
11 10 9 8 7 6 5 4 3 2 1
0003
0
IDLE_ IO_SY SDA_I SCL_I
Name OE_E NC_E O_CO O_CO
N N NFIG NFIG
Type RW RW RW RW
Reset 0 0 1 1
Overview: This register is used to configure the I/O for the SDA and SCL lines to select between normal I/O
r
mode, or open-drain mode to support wired-and bus.
e f o 2
Description
3 IDLE_OE_
EN
IDLE_OE_EN
l e a s I - R 0: Does not drive bus in idle state

1: Drive bus in idle state
2 IO_SYNC_
EN
Re Pi B
IO_SYNC_EN
P For debugging only

When set to 1, SCL and SDA inputs will be first dual synced by
bclk_ck. This should not be needed. Only reserved for debugging.
1 SDA_IO_
CONFIG G
a n a
SDA_IO_CONFI 0: Normal tristate I/O mode
1: Open-drain mode
0 SCL_IO_C
ONFIG
Ba n
SCL_IO_CONFIG 0: Normal tristate I/O mode
1: Open-drain mode
11007044 MULTIMAS Multiple I2C Masters 0000

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUS_ CLK_
ARB_
Name DET_ SYNC
EN
EN _EN
Type RW RW RW
Reset 0 0 0
Overview: This registers contains options for supporting multi-master features.
f o r
e
2 BUS_DET
_EN
BUS_DET_EN
l e a s I - R 2 When enabled, bus status is monitored and if bus is currently busy,

no new transaction can proceed.
1
0
CLK_SYN
C_EN
ARB_EN
Re Pi B
CLK_SYNC_EN
ARB_EN P When enabled, clk synchronization will be performed.
When enabled, multi-master arbitration will be performed.
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
11007048
Bit 15
HS
14 13
HS_SAMPLE_CNT_
l
Re Pi B
12
High Speed Mode Register
P
11 10 9 8 7 6 5 4 3 2 1
HS_N
ACKE
0102
0
HS_E
a
Name DIV
HS_STEP_CNT_DIV MASTER_CODE RR_D
N
n
ET_E
a
N
n
Type RW RW RW RW RW
Ba
Reset 0 0 0 0 0 1 0 0 0 1 0
Overview: This register contains options for supporting high speed operation features Each HS half pulse width,
i.e. each high or low pulse, is equal to step_cnt_div*(sample_cnt_div*1/16.25MHz)

14:12 HS_SAMP HS_SAMPLE_CN When the high-speed mode is entered after the master code
LE_CNT_ T_DIV transfer is completed, the sample width will become dependent on
DIV this parameter.
10:8 HS_STEP HS_STEP_CNT_ When the high-speed mode is entered after the master code
_CNT_DIV DIV transfer is completed, the number of samples per half pulse width
will become dependent on this value.
6:4 MASTER_
CODE
MASTER_CODE
f o r This is the 3-bit programmable value for the master code to be

transmitted.
1 HS_NACK
ERR_DET
HS_NACKERR_
DET_EN
e a s e I - R 2
Enables NACKERR detection during the master code
transmission
l
_EN When enabled, if NACK is not received after master code is
0 HS_EN
Re Pi B
HS_EN P transmitted, the transaction will be terminated with a STOP
condition.
Enables high-speed transaction
a n a Note: rs_stop must be set to 1.
11007050
Bit 15
SOFTRESET
14
Ba
13
n 12
Soft Reset Register
11 10 9 8 7 6 5 4 3 2 1
0000
0
SOFT
Name _RES
ET
Type WO
Reset 0

SOFT_RE When written with 1'b1, a 1 pulse soft reset is used as synchronous
0 SOFT_RESET
SET reset to reset the I2C internal hardware circuits.
f o r
11007054
Bit 15
HW_DCM_EN
14 13
e
12
a s e 11
I - R 2
HW DCM Enable
10 9 8 7 6 5 4 3 2 1
0001
0
Name
Type
Reset
l
Re Pi B P
DCM_
EN
RW
1
a n a
n
Ba
MT7623N
f o r
l
Enables HW DCM function
0 DCM_EN
Re Pi B
DCM_EN
P Default is enable.
0: Disable
1: Enable
a n a
11007064
Bit
Name
15
DEBUGSTAT
14
Ba
13 n 12
Debug Status Register
11 10 9 8 7
BUS_
BUSY
6
MAST MAST
ER_W ER_R
5 4 3 2
MASTER_STATE
1
0020
0
RITE EAD
Type RU RU RU RU
Reset 0 0 1 0 0 0 0 0

7 BUS_BUS BUS_BUSY For debugging only
Y Valid when bus_detect_en is 1. bus_busy = 1 indicates a start
transaction has been detected and no stop condition has been
detected yet.
6 MASTER_
WRITE
MASTER_WRITE
f o r For debugging only

1: Current transfer is in the master write dir.
5 MASTER_
READ
MASTER_READ
e a s e I - R 2 For debugging only

1: Current transfer is in the master read dir.
4:0 MASTER_
STATE
l
Re Pi B
MASTER_STATE
P For debugging only: Reads back the current master_state.

0: Idle state
1: I2C master is preparing sending out the start bit, SCL=1, SDA=1.
a
2: I2C master is sending out the start bit, SCL=1, SDA=0.
n a n 3: I2C master/slave is preparing transmitting data bit, SCL=0,

SDA=data bit (data bit can be changed when SCL=0).
Ba
4: I2C master/slave is transmitting data bit, SCL=1, SDA=data bit
(data bit is stable when SCL=1).
5: I2C master/slave is preparing transmitting the ACK bit, SCL=0,
SDA=ack (The ACK bit can be changed when SCL=0).
6: I2C master/slave is transmitting the ACK bit, SCL=1, SDA=0 (ack
bit is stable when SCL=1).
7: I2C master is preparing sending out stop bit or repeated-start bit,
SCL=0, SDA=0/1 (0: Stop bit; 1: Repeated-start bit).
8: I2C master is sending out stop bit or repeated-start bit, SCL=1,
SDA=1/0 (1: Stop bit; 0: Repeated-start bit).
9: I2C master is in delay start between two transfers, SCL=1,
SDA=1.
10: I2C master is in FIFO wait state; For writing transaction, it
f o r means FIFO is empty and I2C master is waiting for DMA

controller writing data into FIFO; For reading transaction, it
means FIFO is full and I2C master is waiting for DMA controller
e a s e I - R 2
reading data from FIFO, SCL=0, SDA=don’t care.
12: I2C master is preparing sending out data bit of master code.
l
This state is used only in high-speed transaction, SCL=0,
Re Pi B P SDA=data bit of master code (data bit of master code can be

changed when SCL=0).
13: I2C master is sending out data bit of master code. This state is
a
used only in high-speed transaction, SCL=1, SDA=data bit of
Ba
MT7623N
f o r
master code (data bit of master code is stable when SCL=1).
l
Re Pi B P 14: I2C master/slave is preparing transmitting the NACK bit,
SCL=0, SDA=nack bit (The NACK bit can be changed when
SCL=0); This state is used only in high-speed transaction.
15: I2C master/slave is transmitting the NACK bit, SCL=1, SDA=1;
a n a This state is used only in high-speed transaction.
11007068
Bit 15
DEBUGCTRL
14 Ba
13
n 12
Debug Control Register
11 10 9 8 7 6 5 4 3 2 1
0000
0
FIFO_
APB_
APB_
Name DEBU
DEBU
G_RD
G
Type WO RW
Reset 0 0

1 APB_DEB APB_DEBUG_R Only valid when fifo_apb_debug is set to 1
r
UG_RD D Writing to this register will generate a 1 pulsed FIFO APB RD signal
0 FIFO_APB FIFO_APB_DEB
e f o 2
for reading the FIFO data.
Used for trace 32 debug purposes
_DEBUG UG
l e a s I - R
When using trace 32, and the memory map is shown, turning this
bit on will block the normal APB read access. The APB read access
P
to the FIFO will then be enabled by writing to apb_debug_rd.
Re Pi B
0: Disable
1: Enable
a n a
Ba n
f o r
e a s e I - R 2
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
10
e
Pulse-Width Modulator (PWM)
a s e I - R 2
10.1 Introduction
l
Re Pi B P
a n a
Seven generic pulse-width modulators are implemented to generate pulse sequences with
Ba n
programmable frequency and duration for LCD backlight, charging or other purposes. Before enabling
PWM, the pulse sequences must be prepared in the memory or registers. Then PWM will read the
pulse sequences to generate random waveform to meet all kinds of applications
DATA
......
PWM
32-bit
f o r
e
Figure 10-1: Generation procedure of PWM
10.2 Feature list

l e a s I - R 2

Re Pi B P
Total 5 channel PWM can output to external pins

 Sequential output mode
a n a
Periodical memory and random mode
10.3 Ba
Block Diagram
n
f o r
e a s e I - R 2
l
Re Pi B P
Figure 10-2: Block Diagram of PWM
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
10.4
Address
Register Definition
l
Re Pi B
Name
P Width Register function
11006000 PWM_ENABLE
a n a 32 PWM enable register
n
11006004 PWM4_DELAY 32 PWM4 delay duration register
Ba
11006008 PWM5_DELAY 32 PWM5 delay duration register
1100600C PWM6_DELAY 32 PWM6 delay duration register
11006010 PWM1_CON 32 PWM1 control register
11006014 PWM1_HDURATION 32 PWM1 high duration register
11006018 PWM1_LDURATION 32 PWM1 low duration register
1100601C PWM1_GDRUATION 32 PWM1 guard duration register
PWM1_BUF0_BASE_
11006020 32 PWM1 buffer 0 base address register
ADDR
11006024 PWM1_BUF0_SIZE 32 PWM1 buffer 0 size register
PWM1_BUF1_BASE_
11006028
ADDR
f o r 32 PWM1 buffer 1 base address register
e
1100602C PWM1_BUF1_SIZE 32 PWM1 buffer1 size register
11006030
11006034
PWM1_SEND_DATA0
PWM1_SEND_DATA1
l e a s I - R 2 32
32
PWM1 send data 0 register
PWM1 send data1 register
11006038
1100603C
Re Pi B
PWM1_WAVE_NUM
PWM1_DATA_WIDTH P 32
32
PWM1 wave number register
PWM1 data width register
11006040 PWM1_THRESH
a
PWM1_SEND_WAVEN
n a 32 PWM1 thresh register
n
11006044 32 PWM1 send wave number register
UM
11006048
11006050
11006054
11006058
PWM2_CON
Ba
PWM1_VALID
PWM2_HDURATION
PWM2_LDURATION
32
32
32
32
PWM1 valid register
PWM2 control register
PWM2 high duration register
PWM2 low duration register
1100605C PWM2_GDRUATION 32 PWM2 guard duration register
PWM2_BUF0_BASE_
ADDR
11006064 PWM2_BUF0_SIZE 32 PWM2 buffer 0 size register
PWM2_BUF1_BASE_
r
ADDR
1100606C PWM2_BUF1_SIZE
e f o 2
32 PWM2 buffer 1 size register
s
11006070 PWM2_SEND_DATA0 32 PWM2 send data 0 register
11006074 PWM2_SEND_DATA1
l e a P I - R 32 PWM2 send data 1 register
Re Pi B
11006078 PWM2_WAVE_NUM 32 PWM2 wave number register
1100607C PWM2_DATA_WIDTH 32 PWM2 data width register
11006080 PWM2_THRESH 32 PWM2 thresh register
a n a
n
Ba
MT7623N
f o r
Address Name
e a s e I - R 2 Width Register function
l
PWM2_SEND_WAVEN
11006084
11006088
UM
PWM2_VALID
Re Pi B P 32
32
PWM2 send wave number register
PWM2 valid register
a
11006090 PWM3_CON 32 PWM3 control register
11006094
11006098
PWM3_HDURATION
n a
PWM3_LDURATION n 32
32
1100609C
110060A0
110060A4
ADDR Ba
PWM3_GDRUATION
PWM3_BUF0_BASE_
PWM3_BUF0_SIZE
32
32
32
PWM3 guard duration register
PWM3 buffer 0 base address register
PWM3 buffer 0 size register

PWM3_BUF1_BASE_
110060A8 32 PWM3 buffer 1 base address register
ADDR
110060AC PWM3_BUF1_SIZE 32 PWM3 buffer 1 size register
110060B0 PWM3_SEND_DATA0 32 PWM3 send data 0 register
110060B4 PWM3_SEND_DATA1 32 PWM3 send data 1 register
r
110060B8 PWM3_WAVE_NUM 32 PWM3 wave number register
110060BC
110060C0
PWM3_DATA_WIDTH
PWM3_THRESH
e f o 2
32
32
PWM3 thresh register
110060C4
PWM3_SEND_WAVEN
l e a s I - R 32 PWM3 send wave number register
P
UM
Re Pi B
110060C8 PWM3_VALID 32 PWM3 valid register
110060D0 PWM4_CON 32 PWM4 control register
110060D4
110060D8
PWM4_HDURATION
a
PWM4_LDURATION
n a 32
32
110060DC
110060E0
Ba n
PWM4_GDRUATION
PWM4_BUF0_BASE_
ADDR
32
32
110060E4 PWM4_BUF0_SIZE 32 PWM4 buffer 0 size register

PWM4_BUF1_BASE_
110060E8 32 PWM4 buffer 1 base sddress register
ADDR
110060EC PWM4_BUF1_SIZE 32 PWM4 buffer1 size register
110060F0 PWM4_SEND_DATA0 32 PWM4 send data 0 register
110060F4 PWM4_SEND_DATA1 32 PWM4 send data 1 register
110060F8 PWM4_WAVE_NUM 32 PWM4 wave number register
110060FC
PWM4_SEND_WAVEN
UM
f o r 32 PWM4 send wave number register
11006100
11006104
PWM4_DATA_WIDTH
PWM4_THRESH
e a s e I - R 2 32
32
PWM4 thresh register
11006108
11006110
11006114
PWM4_VALID
PWM5_CON
PWM5_HDURATION
l
Re Pi B P 32
32
32
PWM4 valid register
PWM5 control register
a n a
n
Ba
MT7623N
f o r
Address Name
e a s e I - R 2 Width Register function
l
11006118 PWM5_LDURATION 32 PWM5 low duration register
1100611C
11006120
Re Pi B
PWM5_GDRUATION
PWM5_BUF0_BASE_ P 32
32
a
ADDR
11006124 PWM5_BUF0_SIZE
n
PWM5_BUF1_BASE_
a n 32 PWM5 buffer 0 size register
Ba
ADDR
1100612C PWM5_BUF1_SIZE 32 PWM5 buffer 1 size register
11006138 PWM5_WAVE_NUM 32 PWM5 wave number register
PWM5_SEND_WAVEN
1100613C 32 PWM5 send wave number register
UM
11006140 PWM5_DATA_WIDTH 32 PWM5 data width register
11006144 PWM5_THRESH 32 PWM5 thresh register

11006148 PWM5_VALID
f o r 32 PWM5 valid register
110061CC
PWM_LOOP_BACK_T
EST
e a s e I - R 2 32 PWM loop back test
l
110061D0 PWM_3DLCM 32 PWM support for 3D LCM
11006200 Re Pi B
PWM_INT_ENABLE
P 32
base pwm2 , select pwm3 , pwm4 ,pwm5 same
as pwm2 or inversion of pwm2
PWM interrupt enable register
11006204 PWM_INT_STATUS
a n a 32 PWM interrupt status register

11006208
1100620C
PWM_INT_ACK
Ba
PWM_EN_STATUS
n 32
32
PWM interrupt acknowledge register
PWM enable status register
PWM_ENABL
11006000 PWM Enable Register 00000000
E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PWM PWM
_TES _SEQ
Name T_SE _MO
L DE
Type RW RW
Reset 0 0
Bit
Name
15 14 13 12 11
f o r 10 9 8 7 6 5 4 3
PWM PWM PWM PWM PWM
2 1 0
e
5_EN 4_EN 3_EN 2_EN 1_EN
Type
Reset
l e a s I - R 2 RW
0
RW
0
RW
0
RW
0
RW
0
Bit(s)
17
Name
PWM_TEST_SEL
Re Pi B P
Description
Set to 1 to enable the switch of the PWM output signal between PWM
a
unit 1, PWM unit 5
Ba
MT7623N
f o r
Bit(s) Name
e a s e I - R 2
Description
The default (0) setting is to select the output of PWM unit 5. If set to 1, the
16 PWM_SEQ_MODE
l
Re Pi B P
output of PWM unit1 will be selected instead of PWM unit 5.
Set to 1 to enable PWM3, PWM4, PWM5 sequential delay mode
In this mode, PWM3 starts first, and after PWM4_DELAY_TIME, PWM4
a
will start. After PWM4 starts, PWM5 will start after PWM5_DELAY_TIME.
n a n Note: The output of PWM_SEQ_MODE is started after PWM3 is enabled.

PWM_SEQ_MODE should be set before PWM4, PWM5 are enabled or at
Ba
the same time. This mode does not work when PWM3 is set at
OLD_PWM_MODE and CLKSEL = 1.
4 PWM5_EN Set to 1 to enable PWM5
11006004 PWM4_DELAY PWM4 Delay Duration Register 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
f o r DELA
Y_CL
e
KSEL
Type
Reset
Bit 15 14 13
l e
12
a s 11
I - R 210 9 8 7 6 5 4 3 2 1
RW
0
0
Name
Type
Reset 0 0 0
Re Pi B0 P0 0
PWM4_DELAY_DURATION
0 0
RW
0 0 0 0 0 0 0 0
Bit(s) Name
a n a Description
16
15:0
DELAY_CLKSEL
PWM4_DELAY_DU
RATION
Ba n Clock unit of PWM4_DELAY_DURATION
0: CLK = CLKSRC
1: CLK = CLKSRC/1,625
Time difference between PWM3 and PWM4
11006008 PWM5_DELAY PWM5 Delay Duration Register 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DELA
Name Y_CL
KSEL
r
Type RW
o
Reset 0
Bit
Name
Type
15 14 13 12 11
s e f 10
2
9 8
PWM5_DELAY_DURATION
RW
7 6 5 4 3 2 1 0
Reset 0 0 0 0
l e a 0
P I -
0
R 0 0 0 0 0 0 0 0 0 0
Bit(s)
16
Name
DELAY_CLKSEL
Re Pi B Description
Clock unit of PWM5_DELAY_DURATION
a n a
n
B a
MT7623N
f o r
Bit(s) Name
e a s e I - R 2
Description
0: CLK = CLKSRC
15:0 PWM5_DELAY_DU
RATION
l
Re Pi B P1: CLK = CLKSRC/1,625
a n a
1100600C
Bit
Name
31 30
Ba
PWM6_DELAY
29 n 28
PWM6 Delay Duration Register
27 26 25 24 23 22 21 20 19 18
00000000
17 16
DELA
Y_CL
KSEL
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PWM6_DELAY_DURATION
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

16 DELAY_CLKSEL
f o r
Clock unit of PWM6_DELAY_DURATION
0: CLK = CLKSRC
15:0 PWM6_DELAY_DU
e a s e I - R 2
l
RATION
Re Pi B P
11006010
Bit 31
PWM1_CON
30 29
a n a
28
PWM1 Control Register
27 26 25 24 23 22 21 20 19 18
00007E00
17 16
Name
Type
Reset
Bit 15
OLD_
PWM
14
Ba
13
n 12 11 10 9 8
GUA IDLE
7
MOD SRCS
6 5 4 3
CLKS
2 1 0
Name _MO
STOP_BITPOS RD_V _VAL
E EL EL
CLKDIV
ALUE UE
DE
Reset 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0

15 OLD_P Uses old PWM mode
M_MODE Note: Using old PWM mode also means using periodical mode. Therefore,
r
SRCSEL and MODE are ignored in this situation. Only old PWM mode with
e f o
32kHz clock source(however ,cannot work in sleep mode).
0: New PWM mode
2
14:9 STOP_BITPOS
l e a s 1: Old PWM mode
I - R
Stop bit position for source data in periodical mode
Re Pi B P
In FIFO mode, it is used to indicate the stop bit position in the total 64
bits(1 ~63;62 is not supported).
In the period memory mode, it is for the stop bit position in the last 32 bits
(1 ~31;30 is not supported).
a n a
n
Ba
MT7623N
f o r
Bit(s) Name
e a s e 2
Description
I - R
l
8 GUARD_VALUE PWM1 output value when in guard time
7
6
IDLE_VALUE
MODE
Re Pi B P
PWM1 output value when in idle state
Selects random generator mode
0: Periodical PWM mode
5 SRCSEL
a n a 1: Random PWM mode

Selects PWM1 data source
3 CLKSEL
Ba n 0: FIFO mode
1: Memory mode
Selects PWM1 clock
0: CLK = CLKSRC
2:0 CLKDIV Selects PWM1 clock scale
000b: CLK Hz
001b: CLK/2Hz
010b: CLK/4Hz
011b: CLK/8Hz
100b: CLK/16Hz
101b: CLK/32Hz
f o r
110b: CLK/64Hz
111b: CLK/128Hz
e a s e I - R 2
11006014
Bit
Name
31
PWM1_HDURATION
30 29 l
Re Pi B
28
P
27 26
PWM1 High Duration Register
25 24 23 22 21 20 19 18
00000001
17 16
a
Type
n
Reset
Bit
Name
15 14 13
n a 12 11 10 9 8
HDURATION
7 6 5 4 3 2 1 0
Ba
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

PWM1 pulse duration based on the current clock when PWM output is
high
15:0 HDURATION
If duration = N, program N-1 in this register.
Note: The duration of PWM must not be 0.
11006018 PWM1_LDURATION PWM1 Low Duration Register 00000001

Bit
Name
31 30 29 28 27
f o r
26 25 24 23 22 21 20 19 18 17 16
Type
Reset
Bit 15 14 13 12
e a s
11 e I -
10
R 2 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset 0 0 0 0 l
Re Pi B 0
P 0 0
LDURATION
0
RW
0 0 0 0 0 0 0 1
a n a
n
B a
MT7623N
f o r
Bit(s) Name
e a s e 2
Description
I - R
l
15:0 LDURATION
Re Pi B P
low
a n a
1100601C
Bit
Name
Type
31 30
Ba
29 n
PWM1_GDRUATION
28 27
PWM1 Guard Duration Register
26 25 24 23 22 21 20 19 18
00000000
17 16
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GUARD_DURATION
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Guarding interval between individual waveforms in fifo mode and period
memory mode; output is decided by GUARD_VALUE
15:0
GUARD_DURATIO
N
o r
If it equals N, program N-1 in this register.
f
Note: If this duration is 0, it means there is no guarding interval. The guard
e a s e I - R 2
duration of old mode should be set 0.
11006020
PWM1_BUF0_
BASE_ADDR
l
Re Pi B P
PWM1 Buffer 0 Base Address Register 00000000
Bit
Name
31 30 29
a n a
28 27 26 25 24 23
BUF0_BS_ADDR[31:16]
22 21 20 19 18 17 16
n
Type RW
Ba
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BUF0_BS_ADDR[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31:0 BUF0_BS_ADDR Base address of memory buffer 0 for PWM1's waveform data
11006024 PWM1_BUF0_SIZE PWM1 Buffer 0 Size Register 00000000

Bit
Name
Type
31 30 29 28
f
27
o r 26 25 24 23 22 21 20 19 18 17 16
Reset
Bit
Name
15 14 13 12
e a s e 11
I - R 210 9 8 7 6 5 4 3 2 1 0
l
BUF0_SIZE
Re Pi B P
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
a
Ba
MT7623N
f o r
Bit(s) Name
e a s e 2
Description
I - R
l
Length of the waveform data in memory buffer 0 that PWM1 should
15:0 BUF0_SIZE
Re Pi B P
generate
Note: The size is in unit of 32-bit data.
a n a
11006028
Bit
Name
31
BASE_ADDR
30
Ba
PWM1_BUF1_
29
n 28
PWM1 Buffer 1 Base Address Register
27 26 25 24 23
BUF1_BS_ADDR[31:16]
22 21 20 19 18
00000000
17 16
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Base address of memory buffer 1 for PWM1's waveform data
31:0 BUF1_BS_ADDR
o r
Note: Memory buffer 1 is useless in periodical mode.
f
e a s e I - R 2
1100602C
Bit
Name
Type
31
PWM1_BUF1_SIZE
30 29
l
Re Pi B
28
P
27
PWM1 Buffer 1 Size Register
26 25 24 23 22 21 20 19 18
00000000
17 16
a
Reset
Bit
Name
15 14 13
n a n 12 11 10 9 8
BUF1_SIZE
7 6 5 4 3 2 1 0
Ba
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15:0 BUF1_SIZE generate
11006030 PWM1_SEND_DATA0 PWM1 Send Data 0 Register 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset 0 0 0 0 0
f o r
0 0
SEND_DATA0[31:16]
0
RW
0 0 0 0 0 0 0 0
Bit
Name
Type
15 14 13 12
e a
11
s e 10
I - R 2
9 8
SEND_DATA0[15:0]
RW
7 6 5 4 3 2 1 0
Reset
Bit(s)
0
Name
0 0 0
l
Re Pi B
0
P
0
Description
0 0 0 0 0 0 0 0 0 0
a n a
n
B a
MT7623N
f o r
Bit(s) Name
e a s e 2
Description
I - R
l
PWM1 local buffer 0 of pulse sequence data to be generated
31:0 SEND_DATA0
Re Pi B P
Note: This value should be written only in periodical FIFO mode. In other
modes, this buffer is for internal memory access.
a n a
n
Ba
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SEND_DATA1[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31:0 SEND_DATA1 Note: This value should be written only in periodical FIFO mode. In other
f o r
11006038 PWM1_WAVE_NUM
e a s e I - R 2PWM1 Wave Number Register 00000000

Bit
Name
Type
Reset
31 30 29
l 28
Re Pi B P
27 26 25 24 23 22 21 20 19 18 17 16
a
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
n
Name WAVE_NUM
a
Type RW
n
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
15:0
Name
WAVE_NUM
Ba Description
The number by which PWM1 will generate from the pulse data
repeatedly
Note: If WAVE_NUM = 0, the waveform generation will not stop until it is
disabled.
1100603C PWM1_DATA_WIDTH PWM1 Data Width Register 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
r
Name
o
Type
Reset
Bit
Name
15 14 13 12
s e f11 10
2
9 8 7 6
DATA_WIDTH
5 4 3 2 1 0
Type
Reset
l e0
a P
0
I - R 0 0 0 0
RW
0 0 0 0 0 0 0
Bit(s) Name
Re Pi B Description
a
12:0 DATA_WIDTH PWM1 pulse data width in old PWM mode
Ba
MT7623N
f o r
e a s e I - R 2
11006040
Bit
Name
31
PWM1_THRESH
30 29 l
Re Pi B
28 P
27
PWM1 Thresh Register
26 25 24 23 22 21 20 19 18
00000000
17 16
Type
Reset
a n a
n
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Ba
Name THRESH
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

12:0 THRESH PWM1 pulse data high/low switching threshold in old PWM mode
PWM1_SEND_
11006044 PWM1 Send Wave Number Register 00000000
WAVENUM
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
f o r
Bit
Name
15 14 13 12
e a s e 11
I - R 210 9 8
SEND_WAVENUM
7 6 5 4 3 2 1 0
l
Type RO
Reset
Bit(s)
0
Name
0 0
Re Pi B
0
P0
Description
0 0 0 0 0 0 0 0 0 0 0
15:0 SEND_WAVENUM
a n a The number by which PWM1 has already generated from the specified
data source in the periodical mode
11006048 Ba
PWM1_VALID
n PWM1 Valid Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUF1 BUF0
BUF1 BUF0
_VALI _VALI
Name D_W
_VALI
D_W
_VALI
D D
EN EN
Type WO RW WO RW
Reset
r
0 0 0 0
Bit(s) Name
e f o
Description
2
3
2
BUF1_VALID_WEN
BUF1_VALID
l e a s I - R
This bit must be set to modify BUF1_VALID.
The valid status is used to indicate pulse data when memory buffer 1 is
1
0
BUF0_VALID_WEN
BUF0_VALID
Re Pi B P
ready.
a n a
n
Ba
MT7623N
f o r
Bit(s) Name
e a s e I - R
ready.
2
Description
l
Re Pi B P
a
11006050 PWM2_CON PWM2 Control Register 00007E00
Bit
Name
31 30 29
n a n 28 27 26 25 24 23 22 21 20 19 18 17 16
Ba
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OLD_
GUA IDLE
PWM MOD SRCS CLKS
Name _MO
E EL EL
CLKDIV
ALUE UE
DE
Reset 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0

15 OLD_PWM_MODE Uses old PWM mode
Note: Using old PWM mode also means using periodical mode. Therefore,
r
o
32kHz clock source (however ,cannot work in sleep mode).
s e f 0: New PWM mode
2
1: Old PWM mode
14:9 STOP_BITPOS
l e a P I - R
In FIFO mode, it is used to indicate the stop bit position in the total 64 bits
Re Pi B
(1 ~63; 62 is not supported). In the period memory mode, it is for the stop
bit position in the last 32 bits (1 ~ 31; 30 is not supported).
7
6
IDLE_VALUE
MODE
a n a PWM2 output value when in idle state

5 SRCSEL
Ba n 0: Periodical PWM mode
1: Random PWM mode
Selects PWM2 data source
0: FIFO mode
1: Memory mode
3 CLKSEL Selects PWM1 clock
0: CLK = CLKSRC
000b: CLK Hz
001b: CLK/2Hz
010b: CLK/4Hz
f o r
011b: CLK/8Hz
100b: CLK/16Hz
e a s e - 2
101b: CLK/32Hz
R
110b: CLK/64Hz
I
l
Re Pi B P
111b: CLK/128Hz
a n a
n
Ba
MT7623N
f o r
11006054 PWM2_HDURATION
e a s e I - R 2 PWM2 High Duration Register 00000001
l
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 Re Pi B
12
P
11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
a n a HDURATION
RW
n
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit(s)
15:0
Name
HDURATION
Ba Description
high

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
r
Name
o
Type
Reset
Bit
Name
15 14 13 12
s e f
11 10
2
9 8 7 6 5 4 3 2 1 0
R
LDURATION
Type
Reset 0 0 0
l e
0
a P
0
I - 0 0 0
RW
0 0 0 0 0 0 0 1
Bit(s) Name
Re Pi B Description
a
15:0 LDURATION
n a n low
Ba
1100605C PWM2_GDRUATION PWM2 Guard Duration Register 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GUARD_DURATION
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
f o r
Description
GUARD_DURATIO
e a s e 2
Guarding interval between individual waveforms in fifo mode and
R
period memory mode; output is decided by GUARD_VALUE
I -
l
15:0 If it equals to N, program N-1 in this register.
P
N
Re Pi B
duration of old mode should be set 0
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
11006060
Bit
Name
31
PWM2_BUF0_
BASE_ADDR
30 29 l
Re Pi B
28 P
27 26 25 24 23
BUF0_BS_ADDR[31:16]
22 21 20 19 18
00000000
17 16
Type
Reset
Bit
0
15 14
0 0
13
a n a0
12
0
11
0
10
0
9
0
RW
8
0 0
7 6
0
5
0
4 3
0
2
0 0
1
0
0
Name
Type
Reset 0 0
Ba
0 n 0 0 0
BUF0_BS_ADDR[15:0]
0 0
RW
0 0 0 0 0 0 0 0

11006064 PWM2_BUF0_SIZE PWM2 Buffer 0 Size Register 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
r
Type
o
Reset
Bit
Name
15 14 13 12 11
s e f 10
2
9 8
BUF0_SIZE
7 6 5 4 3 2 1 0
R
Type
a
RW
Reset 0 0 0 0
l e
0
P I -
0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
Re Pi B Description
15:0 BUF0_SIZE
a n a generate
If it equals to N, program N-1 in this register.
11006068
BASE_ADDR
B
PWM2_BUF1_ a n PWM2 Buffer 1 Base Address Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
o r
Description
f
e
Base address of memory buffer 1 for PWM2's waveform data.
2
31:0 BUF1_BS_ADDR
l e a s Note: Memory buffer 1 is useless in periodical mode.
I - R
1100606C
Re Pi B
PWM2_BUF1_SIZE P PWM2 Buffer 1 Size Register 00000000
a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Ba
MT7623N
f o r
1100606C PWM2_BUF1_SIZE
e a s e I - R 2PWM2 Buffer 1 Size Register 00000000
l
Name
Type
Reset
Bit
Name
15 14 13
Re Pi B
12 P
11 10 9 8
BUF1_SIZE
7 6 5 4 3 2 1 0
Type
Reset 0 0 0
a n a0 0 0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s)
15:0
Name
BUF1_SIZE Ba n Description
generate
If it equals to N, program N-1 in this register.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
15 14 13 12
f
11
o r 10 9 8
SEND_DATA0[15:0]
7 6 5 4 3 2 1 0
e
Type RW
Reset 0 0 0
l e
0
a s
0
I - R 20 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:0
Name
SEND_DATA0
Re Pi B P
Description
a
n a n
11006074
Bit
Name
Type
Reset
31
0
30
0
Ba
PWM2_SEND_DATA1
29
0
28
0
27
0
26
0
PWM2 Send Data1 Register
25
0
24 23
SEND_DATA1[31:16]
0
RW
0 0
22 21
0
20
0
19
0
18
0
00000000
17
0
16
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
r
o
31:0 SEND_DATA1 Note: This value should be written only in periodical FIFO mode. In other
s e f
2
l e a P I - R
Re Pi B
11006078 PWM2_WAVE_NUM PWM2 Wave Number Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
a n a
n
Ba
MT7623N
f o r
11006078 PWM2_WAVE_NUM
e a s e I - R 2PWM2 Wave Number Register 00000000
l
Reset
Bit
Name
Type
Reset
15
0
14
0
13
0
Re Pi B
12
0
P
11
0
10
0
9
0
8
WAVE_NUM
0
RW
0
7 6
0
5
0
4
0
3
0
2
0
1
0
0
a n a
n
Ba
repeatedly
15:0 WAVE_NUM
disabled.
1100607C PWM2_DATA_WIDTH PWM2 Data Width Register 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
f o r DATA_WIDTH
RW
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
l e a s I - R 2
Description
12:0 DATA_WIDTH
Re Pi B P
PWM2 pulse data width in old PWM mode
a n a PWM2 Thresh Register 00000000

Bit
Name
Type
Reset
Bit
31
15
30
14 Ba
29
13
n 28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0
Name THRESH
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

11006084
PWM2_SEND_
f o r
PWM2 Send Wave Number Register 00000000
e
WAVENUM
Bit
Name
31 30 29 28
l e a s
27
I
26
- R 2 25 24 23 22 21 20 19 18 17 16
P
Type
Re Pi B
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SEND_WAVENUM
a
Type RO
B a
MT7623N
f o r
11006084
PWM2_SEND_
e a s e I - R 2
l
WAVENUM
Reset
Bit(s)
0
Name
0 0
Re Pi B
0
P 0 0
Description
0 0 0 0 0 0 0 0 0 0
15:0 SEND_WAVENUM
a n a The number by which PWM2 has already generated from the specified
11006088 Ba
PWM2_VALID
n PWM2 Valid Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUF1 BUF0
BUF1 BUF0
_VAL _VAL
Name _VAL _VAL
ID_W ID_W
ID ID
EN EN
Type WO RW WO RW
r
Reset 0 0 0 0
Bit(s) Name
e f o 2
Description
3 BUF1_VALID_WEN
l e a s - R
I
P
2 BUF1_VALID The valid status is used to indicate pulse data when memory buffer 1 is
Re Pi B
ready.
1 BUF0_VALID_WEN This bit must be set to modify BUF0_VALID.
a
0 BUF0_VALID The valid status is used to indicate pulse data when memory buffer0 is
n
ready.
n a
11006090
Bit
Name
Type
31
PWM3_CON
30 Ba
29 28
PWM3 Control Register
27 26 25 24 23 22 21 20 19 18
00007E00
17 16
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OLD GUA
IDLE
_PW RD_V MOD SRC CLKS
Name M_M
STOP_BITPOS
ALU
_VAL
E SEL EL
CLKDIV
UE
ODE E
Reset 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Bit(s) Name
f o r
Description
15 OLD_PWM_MODE
e a s e - R 2
Uses old PWM mode
I
l
Re Pi B P32kHz clock source (however ,cannot work in sleep mode).

0: New PWM mode
1: Old PWM mode
a n a
n
Ba
MT7623N
f o r
Bit(s) Name
e a s e 2
Description
I - R
l
14:9 STOP_BITPOS Stop bit position for source data in periodical mode
Re Pi B P In FIFO mode, it is used to indicate the stop bit position in the total 64
8 GUARD_VALUE
a n a (1 ~31;30 is not supported).

PWM3 output value when in guard time
7
6
IDLE_VALUE
MODE
Ba n PWM3 output value when in idle state

1: Random PWM mode
5 SRCSEL Selects PWM3 data source
0: FIFO mode
1: Memory mode
0: CLK = CLKSRC
000b: CLK Hz
o r
001b: CLK/2Hz
f
010b: CLK/4Hz
e a s e - 2
011b: CLK/8Hz
R
100b: CLK/16Hz
I
l
101b: CLK/32Hz
Re Pi B P
110b: CLK/64Hz
111b: CLK/128Hz
a n a
11006094
Bit
Name
Type
Reset
31 30
Ba
29
n
PWM3_HDURATION
28 27 26
25 24 23 22 21 20 19 18
00000001
17 16
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name HDURATION
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

high
15:0 HDURATION
r
e f o
2
l e a s I - R
P
Bit
Name
Type
31 30 29
Re Pi B
28 27 26 25 24 23 22 21 20 19 18 17 16
a n a
n
Ba
MT7623N
f o r
11006098 PWM3_LDURATION
e a s e I - R 2 PWM3 Low Duration Register 00000001
l
Reset
Bit
Name
Type
Reset
15
0
14
0
13
0
Re Pi B
12
0
P
11
0
10
0
9
0
8
LDURATION
0
RW
0
7 6
0
5
0
4
0
3
0
2
0
1
0
0
a n a
n
Ba
low
15:0 LDURATION

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
r
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
o
Name GUARD_DURATION
Type
Reset 0 0 0 0
s e f 0
2
0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s) Name
l e a I - R
Description
P
Re Pi B
GUARD_DURATIO
15:0 If it equals N, program N-1 in this register.
a
N
n a n duration of old mode should be set 0
110060A0
Bit 31
BASE_ADDR
30
Ba
PWM3_BUF0_
29 28
27 26 25 24 23 22 21 20 19 18
00000000
17 16
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
o r
Description
f
e
l e a s I - R 2
110060A4
Bit 31 30 29
Re Pi B
PWM3_BUF0_SIZE
28 P
27
26 25 24 23 22 21 20 19 18
00000000
17 16
a
Name
Ba
MT7623N
f o r
110060A4 PWM3_BUF0_SIZE
e a s e I - R 2PWM3 Buffer 0 Size Register 00000000
l
Type
Reset
Bit
Name
Type
15 14 13
Re Pi B
12
P
11 10 9 8
BUF0_SIZE
RW
7 6 5 4 3 2 1 0
Reset 0 0 0
a n a0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
15:0
Name
BUF0_SIZE
Ba n Description
generate
PWM3_BUF1_
110060A8 PWM3 Buffer 1 Base Address Register 00000000
BASE_ADDR
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
15 14 13 12
f o
11
r 10 9 8
BUF1_BS_ADDR[15:0]
7 6 5 4 3 2 1 0
e
Type RW
Reset 0 0 0
l e
0
a s 0
I - R 2 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:0
Name
BUF1_BS_ADDR
Re Pi B P
Description
a n a
110060AC
Bit
Name
Type
31 30
Ba
29 n
PWM3_BUF1_SIZE
28 27
26 25 24 23 22 21 20 19 18
00000000
17 16
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BUF1_SIZE
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

r
e f o
2
l e a s I - R
P
110060B0 PWM3_SEND_DATA0 PWM3 Send Data 0 Register 00000000
Re Pi B
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW
Reset 0 0 0
a n a0 0 0 0 0 0 0 0 0 0 0 0 0
n
Ba
MT7623N
f o r
110060B0 PWM3_SEND_DATA0
e a s e I - R 2 PWM3 Send Data 0 Register 00000000
l
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset 0 0 0
Re Pi B0 P0 0 0
SEND_DATA0[15:0]
0
RW
0 0 0 0 0 0 0 0
Bit(s) Name
a n a Description
31:0 SEND_DATA0
Ba n PWM3 local buffer 0 of pulse sequence data to be generated

110060B4 PWM3_SEND_DATA1 PWM3 Send Data 1 Register 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type RW
Reset 0 0 0 0
f o
0
r 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e a s e I - R 2
Description
31:0 SEND_DATA1
l
Re Pi B P
110060B8 PWM3_WAVE_NUM
a n a PWM3 Wave Number Register 00000000

Bit
Name
Type
Reset
Bit
31
15
30
14 Ba
29
13
n 28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0
Name WAVE_NUM
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

repeatedly
15:0 WAVE_NUM
r
disabled.
e f o 2
110060BC PWM3_DATA_WIDTH
l e a s I - R PWM3 Data Width Register 00000000

Bit
Name
Type
Reset
31 30 29
Re Pi B
28
P
27 26 25 24 23 22 21 20 19 18 17 16
Bit 15 14 13
a n a
12 11 10 9 8 7 6 5 4 3 2 1 0
n
Ba
MT7623N
f o r
110060BC PWM3_DATA_WIDTH
e a s e I - R 2 PWM3 Data Width Register 00000000
l
Name DATA_WIDTH
Type
Reset
Re Pi B0
P0 0 0 0 0
RW
0 0 0 0 0 0 0
Bit(s)
12:0
Name
DATA_WIDTH
a n a Description
110060C0 Ba
PWM3_THRESH
n PWM3 Thresh Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name THRESH
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
r
12:0 THRESH
e f o
PWM3 pulse data high/low switching threshold in old PWM mode
2
l e a s I - R
110060C4
Bit 31
PWM3_SEND_
WAVENUM
30 29
Re Pi B
28 P
PWM3 Send Wave Number Register
27 26 25 24 23 22 21 20 19 18
00000000
17 16
a
Name
Type
Reset
Bit 15 14 13
n a n 12 11 10 9 8 7 6 5 4 3 2 1 0
Ba
Name SEND_WAVENUM
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

The number by which PWM3 has already generated from the specified
15:0 SEND_WAVENUM
110060C8 PWM3_VALID PWM3 Valid Register 00000000
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
o
Name
Type
Reset
Bit 15 14 13 12
s e f11
210 9 8 7 6 5 4 3 2 1 0
l e a P I - R BUF1
_VALI
BUF1
BUF0
_VALI
BUF0
Re Pi B
Name D_W
_VALI
D_W
_VALI
D D
EN EN
Type WO RW WO RW
Reset 0 0 0 0
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
l
3
2
BUF1_VALID_WEN
BUF1_VALID
Re Pi B PThis bit must be set to modify BUF1_VALID.
The valid status is used to indicate pulse data when memory buffer1 is
ready.
1
0
BUF0_VALID_WEN
BUF0_VALID
a n a This bit must be set to modify BUF0_VALID.

Ba n ready.
110060D0 PWM4_CON PWM4 Control Register 00007E00

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OLD_
GUA IDLE
PWM MOD SRCS CLKS
Name _MO
E EL EL
CLKDIV
ALUE UE
DE
r
Reset 0 1 1 1
e f o1
2
1 1 0 0 0 0 0 0 0 0
Bit(s)
15
Name
OLD_P
l e a s I - R
Description
Uses old PWM mode
M_MODE
Re Pi B PNote: Using old PWM mode also means using periodical mode. Therefore,
a
0: New PWM mode
14:9 STOP_BITPOS
n a n 1: Old PWM mode

Ba
In FIFO mode, it is used to indicate the stop bit position in the total 64
7 IDLE_VALUE PWM4 output value when in idle state
6 MODE Selects random generator mode
1: Random PWM mode
0: FIFO mode
3 CLKSEL
f r
1: Memory mode
o
Selects PWM1 clock
e a s e 2
0: CLK = CLKSRC
R
I -
l
Re Pi B P000b: CLK Hz
001b: CLK/2Hz
010b: CLK/4Hz
a n a
n
Ba
MT7623N
f o r
Bit(s) Name
e a s e I - R 2
Description
011b: CLK/8Hz
l
Re Pi B P
100b: CLK/16Hz
101b: CLK/32Hz
110b: CLK/64Hz
a
111b: CLK/128Hz
n a n
110060D4
Bit
Name
Type
Reset
31 30
Ba
PWM4_HDURATION
29 28 27 26
25 24 23 22 21 20 19 18
00000001
17 16
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name HDURATION
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

15:0 HDURATION
f o
high
r
e a s e I - R 2
110060D8
Bit 31
PWM4_LDURATION
30 29
l
Re Pi B
28
P
27
PWM4 Low Duration Register
26 25 24 23 22 21 20 19 18
00000001
17 16
Name
Type
a n a
n
Reset
Ba
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name LDURATION
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

low
15:0 LDURATION
110060DC PWM4_GDRUATION
f o r PWM4 Guard Duration Register 00000000
e
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
l e a s I - R 2
Bit
Name
Type
Reset
15
0
14
0
13
0
Re Pi B
12
0
11
0
P 10
0
9
0
8
GUARD_DURATION
0
RW
0 0
7 6 5
0
4
0
3
0
2
0
1
0
0
a n a
n
B a
MT7623N
f o r
e a s e I - R 2
l
15:0
GUARD_DURATIO
N Re Pi B P
a n a Note: If this duration is 0, it means there is no guarding interval. The guard

110060E0
BASE_ADDRBa
PWM4_BUF0_
n PWM4 Buffer 0 Base Address Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:0
Name
BUF0_BS_ADDR
o r
Description
f
e a s e I - R 2
110060E4
Bit
Name
31
PWM4_BUF0_SIZE
30 29 l
Re Pi B
28 P
27
26 25 24 23 22 21 20 19 18
00000000
17 16
Type
Reset
a n a
n
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Ba
Name BUF0_SIZE
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM4_BUF1_
110060E8 PWM4 Buffer 1 Base Address Register 00000000
r
BASE_ADDR
Bit
Name
31 30 29 28 27
e f o 26
2
25 24 23
BUF1_BS_ADDR[31:16]
22 21 20 19 18 17 16
s
Type RW
Reset
Bit
0
15 14
0 0
13
0
12
l e a 0
11
P I -
0
10
R 0
9
0
8
0 0
7 6
0
5
0
4 3
0
2
0 0
1
0
0
Re Pi B
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
a n a
n
B a
MT7623N
f o r
Bit(s) Name
e a s e 2
Description
I - R
l
P
31:0 BUF1_BS_ADDR
Re Pi B
110060EC PWM4_BUF1_SIZE
a n a PWM4 Buffer 1 Size Register 00000000

Bit
Name
Type
Reset
Bit
31
15
30
14
29
Ba
13
n 28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0
Name BUF1_SIZE
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

f o r
110060F0
Bit 31
PWM4_SEND_DATA0
30 29 28
e a s e 27
I - R 2
26
PWM4 Send Data 0 Register
25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
Reset
Bit
0
15 14
0 0
13
l
Re Pi B0
12 P
0
11
0
10
0
9
SEND_DATA0[31:16]
0
RW
8
0 0
7 6
0
5 4
0 0
3
0
2
0
1
0
0
a
n
Type RW
a
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:0
Name
SEND_DATA0 Ba n Description
110060F4 PWM4_SEND_DATA1 PWM4 Send Data 1 Register 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
15 14 13 12
f o
11
r 10 9 8
SEND_DATA1[15:0]
7 6 5 4 3 2 1 0
e
Type RW
Reset 0 0 0
l e
0
a s 0
I - R 20 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:0
Name
SEND_DATA1
Re Pi B P
Description
PWM4 local buffe r0 of pulse sequence data to be generated.
a n a
n
Ba
MT7623N
f o r
Bit(s) Name
e a s e I - R 2
Description
l
Re Pi B P
a
110060F8 PWM4_WAVE_NUM PWM4 Wave Number Register 00000000
Bit
Name
31 30 29
n a n 28 27 26 25 24 23 22 21 20 19 18 17 16
Ba
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name WAVE_NUM
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

repeatedly
15:0 WAVE_NUM
disabled.
f o r
110060FC
PWM4_SEND_
WAVENUM
e a s e I - R 2
l
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
12
P
11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
a n a SEND_WAVENUM
RO
n
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
15:0
Name
SEND_WAVENUM Ba Description
11006100 PWM4_DATA_WIDTH PWM4 Data Width Register 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit
Name
Type
15 14 13 12
f
11
o r 10 9 8 7 6
DATA_WIDTH
RW
5 4 3 2 1 0
Reset
e
0
a s e 0
I - R 2
0 0 0 0 0 0 0 0 0 0 0
Bit(s)
12:0
Name
DATA_WIDTH
l
Re Pi B P
Description
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
PWM4 Thresh Register 00000000
l
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
12
P11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
a n a THRESH
RW
n
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
12:0
Name
THRESH Ba Description
PWM4 pulse data high/low switching threshold in old PWM mode
11006108 PWM4_VALID PWM4 Valid Register 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
f o r BUF1
_VALI
D_WE
BUF1
_VALI
BUF0
_VALI
D_WE
BUF0
_VALI
e
D D
2
N N
Type
Reset
l e a s I - R
WO
0
RW
0
WO
0
RW
0
Bit(s)
3
Name
BUF1_VALID_WEN
Re Pi B PDescription
2 BUF1_VALID
a n a The valid status is used to indicate pulse data when memory buffer1 is
ready.
1
0
BUF0_VALID_WEN
BUF0_VALID
Ba n This bit must be set to modify BUF0_VALID.

ready.
11006110 PWM5_CON PWM5 Control Register 00007E00

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OLD_
GUAR IDLE_
Name PWM
r
MOD SRCS CLKS
STOP_BITPOS D_VA VALU CLKDIV
o
_MOD E EL EL
f
LUE E
E
e
Reset 0 1 1
l e
1
a s 1
I - R 21 1 0 0 0 0 0 0 0 0
Bit(s)
15
Name
OLD_P
M_MODE
Re Pi B PDescription
Uses old PWM mode
a n a SRCSEL and MODE are ignored in this situation. Only old PWM mode with
n
Ba
MT7623N
f o r
Bit(s) Name
e a s e I - R 2
Description
14:9 STOP_BITPOS
l
Re Pi B P
0: New PWM mode
1: Old PWM mode
a n a In FIFO mode, it is used to indicate the stop bit position in the total 64
n
Ba
7 IDLE_VALUE PWM5 output value when in idle state
6 MODE Selects random generator mode
1: Random PWM mode
0: FIFO mode
1: Memory mode
0: CLK = CLKSRC
2:0 CLKDIV
f r
o
Selects PWM5 clock scale
e a s e - 2
000b: CLK Hz
R
001b: CLK/2Hz
I
l
010b: CLK/4Hz
Re Pi B P
011b: CLK/8Hz
100b: CLK/16Hz
101b: CLK/32Hz
a n a 110b: CLK/64Hz
111b: CLK/128Hz
11006114 Ba n
PWM5_HDURATION PWM5 High Duration Register 00000001
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name HDURATION
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
r
e f o
high
2
s
15:0 HDURATION
l e a I - R
P
11006118 Re Pi B
PWM5_LDURATION PWM5 Low Duration Register 00000001
a n a
n
Ba
MT7623N
f o r
11006118 PWM5_LDURATION
e a s e I - R 2PWM5 Low Duration Register 00000001
l
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
12
P
11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
a n a LDURATION
RW
n
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit(s)
15:0
Name
LDURATION
Ba Description
low

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
r
Name
o
Type
Reset
Bit
Name
15 14 13 12
s e f11
2
10 9 8 7 6 5 4 3 2 1 0
R
GUARD_DURATION
Type
Reset 0 0 0
l e0
a P
0
I - 0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s) Name
Re Pi B Description
a
15:0
GUARD_DURATIO
N
n a n period memory mode; output is decided by GUARD_VALUE

Ba
PWM5_BUF0_
11006120 PWM5 Buffer 0 Base Address Register 00000000
BASE_ADDR
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type
Reset 0 0 0 0 0
f o r0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s) Name
e a s e
Description
I - R 2
l
Re Pi B P
a n a
n
B a
MT7623N
f o r
11006124 PWM5_BUF0_SIZE
e a s e I - R 2
PWM5 Buffer 0 Size Register 00000000
l
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
12
P
11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
a n a BUF0_SIZE
RW
n
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
15:0
Name
BUF0_SIZE
Ba Description
generate
PWM5_BUF1_
11006128 PWM5 Buffer 1 Base Address Register 00000000
BASE_ADDR
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
r
o
Type RW
Reset
Bit
Name
0
15 14
0 0
13
0
12
0
11
s e f 0
10
2
0
9
0
8
0 0
BUF1_BS_ADDR[15:0]
7 6
0
5
0
4 3
0
2
0 0
1
0
0
Type
Reset 0 0 0 0
l e a 0
P I -
0
R 0 0
RW
0 0 0 0 0 0 0 0
Bit(s) Name
Re Pi B Description
a
n
31:0 BUF1_BS_ADDR
a n a
1100612C
Bit
Name
31 30
B
PWM5_BUF1_SIZE
29 28 27
26 25 24 23 22 21 20 19 18
00000000
17 16
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BUF1_SIZE
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15:0 BUF1_SIZE
f o r
generate
e a s e I - R 2
11006130
Bit 31
PWM5_SEND_DATA0
30 29
l
Re Pi B
28
P
27 26
PWM5 Send Data 0 Register
25 24 23 22 21 20 19 18
00000000
17 16
a n a
n
Ba
MT7623N
f o r
11006130 PWM5_SEND_DATA0
e a s e I - R 2 PWM5 Send Data 0 Register 00000000
l
Type
Reset
Bit
Name
0
15 14
0 0
13
Re Pi B0
12 P0
11
0
10 9
0 0
RW
8
0 0
SEND_DATA0[15:0]
7 6
0
5
0
4
0
3
0
2 1
0 0
0
Type
Reset 0 0 0
a n a0 0 0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s)
31:0
Name
SEND_DATA0 Ba n Description

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
15 14 13 12
f
11
o r 10 9 8
SEND_DATA1[15:0]
7 6 5 4 3 2 1 0
e
Type RW
Reset 0 0 0
l e
0
a s
0
I - R 20 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:0
Name
SEND_DATA1
Re Pi B P
Description
a
moded, this buffer is for internal memory access.
n a n
11006138
Bit
Name
Type
Reset
31 30
Ba
PWM5_WAVE_NUM
29 28 27 26
PWM5 Wave Number Register
25 24 23 22 21 20 19 18
00000000
17 16
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name WAVE_NUM
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
r
o
repeatedly
f
15:0 WAVE_NUM
e a s e disabled.
I - R 2
1100613C
PWM5_SEND_
WAVENUM
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
1100613C
PWM5_SEND_
e a s e I - R 2
l
WAVENUM
Bit
Name
Type
31 30 29
Re Pi B
28
P
27 26 25 24 23 22 21 20 19 18 17 16
a
Reset
n
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
a
Name SEND_WAVENUM
Type
Reset
Bit(s)
0
Name
0
Ba
0
n 0 0
Description
0 0 0
RO
0 0 0 0 0 0 0 0
15:0 SEND_WAVENUM
11006140 PWM5_DATA_WIDTH PWM5 Data Width Register 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11
f o r
10 9 8 7 6 5 4 3 2 1 0
e
Name DATA_WIDTH
Type
Reset 0
l e a s
0
I
0
- R 2 0 0 0
RW
0 0 0 0 0 0 0
Bit(s)
12:0
Name
DATA_WIDTH
Re Pi B P
Description
a n a
11006144
Bit
Name
Type
31
PWM5_THRESH
30
B
29
a n
28 27
PWM5 Thresh Register
26 25 24 23 22 21 20 19 18
00000000
17 16
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name THRESH
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

f o r
11006148
Bit 31
PWM5_VALID
30 29 28
e a s e 27
I - R 2
PWM5 Valid Register
26 25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
Reset
Bit 15 14 13
l
Re Pi B
12 P
11 10 9 8 7 6 5 4 3 2 1 0
a
Name BUF1 BUF1 BUF0 BUF0
Ba
MT7623N
f o r
11006148 PWM5_VALID
e a s e R 2
PWM5 Valid Register
I -
00000000
l
_VAL _VAL _VAL _VAL
Type
Reset
Re Pi B P ID_W
EN
WO
0
ID ID_W ID
RW
0
EN
WO
0
RW
0
Bit(s) Name
a n a Description
3
2
1
BUF1_VALID_WEN
BUF1_VALID
BUF0_VALID_WEN
Ba n This bit must be set to modify BUF1_VALID.
ready.
0 BUF0_VALID The valid status is used to indicate pulse data when memory buffer 0 is
ready.
PWM_LOOP_ 0000000
110061CC PWM Loop Back Test
BACK_TEST 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
f o r
e
Reset
Bit
Name
15 14 13
l
12
e a s 11
I - R 2
10 9 8 7 6 5 4 3
PWM PWM PWM PWM PWM
2
5_ST 4_ST 3_ST 2_ST 1_ST

1 0
Type
Reset
Re Pi B P ATUS ATUS ATUS ATUS ATUS
RU
0
RU
0
RU
0
RU
0
RU
0
Bit(s) Name
a n a Description
4
3
2
1
PWM5_STATUS
PWM4_STATUS
PWM3_STATUS
PWM2_STATUS Ba n PWM5 current status (for loop back test)
PWM4 current status (for loop back test)
0 PWM1_STATUS PWM1 current status (for loop back test)
110061D0 PWM_3DLCM PWM Support for 3D LCM 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
r
Reset
o
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
s e f 2
PWM
_3DL
CM_2
PWM
_3DL
CM_1
PWM
_3DL
CM_0
PWM
_3DL
CM_E
Type
l e a P I - R _INV
RW
_INV
RW
_INV
RW
N
RW
Re Pi B
Reset 0 0 0 0
a n a
n
Ba
MT7623N
f o r
Bit(s) Name
e a s e
Description
I - R 2
l
PWM_3DLCM_2_IN Set to 1 to make PWM5 inversion of PWM2
4 V
PWM_3DLCM_1_IN
Re Pi B P
0: PWM5 is the same as PWM2.
1: PWM5 is inversion of PWM2.
Set to 1 to make PWM4 inversion of PWM2
a
3 V 0: PWM4 is the same as PWM2.
PWM_3DLCM_0_IN
n a n 1: PWM4 is inversion of PWM2.

Set to 1 to make PWM3 inversion of PWM2
Ba
2 V 0: PWM3 is the same as PWM2.
1: PWM3 is inversion of PWM2.
0 PWM_3DLCM_EN Set to 1 to enable PWM for 3D LCM
PWM_INT_EN
11006200 PWM Interrupt Enable Register 00000000
ABLE
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
r
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
o
PWM PWM PWM PWM PWM
Name
s e f 2
5_IN
T_UN
DER
PWM
5_IN
T_FI
4_IN
T_UN
DER
PWM
4_IN
T_FI
3_IN
T_UN
DER
PWM
3_IN
T_FI
2_IN
T_UN
DER
PWM
2_IN
T_FI
1_IN
T_UN
DER
PWM
1_IN
T_FI
l e a P I - R FLO
W_E
NISH
_EN
FLO
W_E
NISH
_EN
FLO
W_E
NISH
_EN
FLO
W_E
NISH
_EN
FLO
W_E
NISH
_EN
Re Pi B
N N N N N
Type RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
a n a Description
n
9 PWM5_INT_UNDER Set to 1 to enable PWM5 underflow interrupt
7
FLOW_EN
PWM5_INT_FINISH
_EN
PWM4_INT_UNDER
B a Set to 1 to enable PWM5 finish interrupt
Set to 1 to enable PWM4 underflow interrupt

FLOW_EN
6 PWM4_INT_FINISH Set to 1 to enable PWM4 finish interrupt
_EN
FLOW_EN
4 PWM3_INT_FINISH Set to 1 to enable PWM3 finish interrupt
_EN
2
FLOW_EN
PWM2_INT_FINISH
f o r
Set to 1 to enable PWM2 finish interrupt
1
_EN
PWM1_INT_UNDER
e a s e - R 2
Set to 1 to enable PWM1 underflow interrupt
I
l
FLOW_EN
0 PWM1_INT_FINISH
_EN
Re Pi B P
Set to 1 to enable PWM1 finish interrupt
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
11006204
Bit
Name
31
PWM_INT_ST
ATUS
30 29 l
Re Pi B
28 P
PWM Interrupt Status Register
27 26 25 24 23 22 21 20 19 18
00000000
17 16
Type
Reset
Bit 15 14 13
a n a
12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Ba n PWM
5_IN
T_UN
DER
FLO
PWM
5_IN
T_FI
NISH
PWM
4_IN
T_UN
DER
FLO
PWM
4_IN
T_FI
NISH
PWM
3_IN
T_UN
DER
FLO
PWM
3_IN
T_FI
NISH
PWM
2_IN
T_UN
DER
FLO
PWM
2_IN
T_FI
NISH
PWM
1_IN
T_UN
DER
FLO
PWM
1_IN
T_FI
NISH
W_S _ST W_S _ST W_S _ST W_S _ST W_S _ST
T T T T T
Type RU RU RU RU RU RU RU RU RU RU
Reset 0 0 0 0 0 0 0 0 0 0

9 PWM5_INT_UNDER PWM5 underflow status
FLOW_ST
8 PWM5_INT_FINISH PWM5 finish status
7
_ST
PWM4_INT_UNDER
f o r
PWM4 underflow status
6
FLOW_ST
PWM4_INT_FINISH
e a s e - R 2
PWM4 finish status
I
l
_ST
5
4
PWM3_INT_UNDER
FLOW_ST
PWM3_INT_FINISH
Re Pi B P
PWM3 finish status
3
_ST
PWM2_INT_UNDER
a n a PWM2 underflow status
1
FLOW_ST
_ST
PWM1_INT_UNDERBa
PWM2_INT_FINISH
n PWM2 finish status

FLOW_ST
0 PWM1_INT_FINISH PWM1 finish status
_ST
11006208 PWM_INT_ACK PWM Interrupt Acknowledge Register 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
f o r
e
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
l e a s I - R 2 PWM
5_IN
T_UN
PWM
5_IN
PWM
4_IN
T_UN
PWM
4_IN
PWM
3_IN
T_UN
PWM
3_IN
PWM
2_IN
T_UN
PWM
2_IN
PWM
1_IN
T_UN
PWM
1_IN
P
T_FI T_FI T_FI T_FI T_FI
Re Pi B
Name DER DER DER DER DER
NISH NISH NISH NISH NISH
FLO FLO FLO FLO FLO
_AC _AC _AC _AC _AC
W_A W_A W_A W_A W_A
K K K K K
CK CK CK CK CK
a
Type WO WO WO WO WO WO WO WO WO WO
Ba
MT7623N
f o r
11006208 PWM_INT_ACK
e a s e R 2
PWM Interrupt Acknowledge Register
I -
00000000
l
Reset 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
Re Pi B P
Description
a
9 PWM5_INT_UNDER Set to 1 to clear PWM5 underflow interrupt
n
FLOW_ACK
8 PWM5_INT_FINISH
n a Set to 1 to clear PWM5 finish interrupt
Ba
_ACK
FLOW_ACK
6 PWM4_INT_FINISH Set to 1 to clear PWM4 finish interrupt
_ACK
FLOW_ACK
_ACK
FLOW_ACK
1
_ACK
PWM1_INT_UNDER
f o r
Set to 1 to clear PWM1 underflow interrupt
e
FLOW_ACK
0 PWM1_INT_FINISH
_ACK
l e a s R 2
Set to 1 to clear PWM1 finish interrupt
I -
Re Pi B P
a
PWM_EN_STA
1100620C PWM Enable Status Register 00000000
Bit 31
TUS
30 29
n a n 28 27 26 25 24 23 22 21 20 19 18 17 16
Ba
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWM PWM PWM PWM PWM
Name 5_EN 4_EN 3_EN 2_EN 1_EN
_ST _ST _ST _ST _ST
Type RO RO RO RO RO
Reset 0 0 0 0 0

4 PWM5_EN_ST PWM5 enabling status
3 PWM4_EN_ST PWM4 enabling status
2
1
PWM3_EN_ST
PWM2_EN_ST
o r
PWM3 enabling status
f
0 PWM1_EN_ST
e a s e 2
I - R
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
11 SPI Interface Controller
e a s e I - R 2
11.1 Introduction
l
Re Pi B P
a n a
The SPI interface is a bit-serial, four-pin transmission protocol.
Ba n
The SPI interface controller is a master responsible of the data transmission with the slave.
CS_N CS_N
SCK SCK
MASTER SLAVE
MOSI MOSI
MISO MISO
Figure 11-1: Pin connection between SPI master and SPI slave
11.2 Feature list

f o r
e a s e I - R 2
l
There are total 3 channel SPI controllers:
Re Pi B P
 Configurable CS_N setup time, hold time and idle time
 Programmable SCK high time and low time
 Configurable transmitting and receiving bit order
n a
 Two configurable modes for the source of the data to be transmitted.
a
n
1) In TX DMA mode, the SPI controller automatically fetches the transmitted data (to be put on
Ba
the MOSI line) from memory;
2) In TX FIFO mode, the data to be transmitted on the MOSI line are written to FIFO before the
start of the transaction.
 Two configurable modes for destination of the data to be received.
1) In RX DMA mode, the SPI controller automatically stores the received data (from MISO line)
to memory;
2) In RX FIFO mode, the received data keep being in RX FIFO of the SPI controller. The
processor must read back the data by itself.
 Adjustable endian order from/to memory system
 Programmable byte length for transmission
 Unlimited length for transmission.
f o r
 Configurable option to control CS_N de-assert between byte transfers.
e a s e I - R 2
11.3 Block Diagram
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
l
Re Pi B P
a n a
Ba n
f o r
Figure 11-2: Block Diagram of SPI Controller
e a s e I - R 2
11.4
l
Register Definition
Re Pi B P
Module name: SPI0 base address: (+1100A000h)
n a
Module name: SPI1 base address: (+11016000h)
a
n
Address Name Width Register function
Ba
00000000 SPI_CFG0 32 SPI configuration 0 register
00000004 SPI_CFG1 32 SPI configuration 1 register
00000008 SPI_TX_SRC 32 SPI TX source address register
0000000C SPI_RX_DST 32 SPI RX destination address register
00000010 SPI_TX_DATA 32 SPI TX data FIFO
00000014 SPI_RX_DATA 32 SPI RX data FIFO
00000018 SPI_CMD 32 SPI command register
0000001C SPI_STATUS0 32 SPI status 0 register
00000020 SPI_STATUS1 32 SPI status 1 register
f o r
00000000 SPI_CFG0
e a s e R 2
SPI Configuration 0 Register
I -
00000000
l
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mne
Type
Reset
Bit
0
15
0
14
0
13
Re Pi B
CS_SETUP_COUNT
0
RW
12
0 0 P
11 10
0
9
0
8
0
7
0
6
0
5
CS_HOLD_COUNT
0
RW
4
0 0
3 2
0
1
0
0
Mne
a n a
SCK_LOW_COUNT SCK_HIGH_COUNT
n
Ba
MT7623N
f o r
00000000 SPI_CFG0
e a s e R 2
SPI Configuration 0 Register
I -
00000000
l
Type RW RW
Reset
Bit(s)
0 0
Mnemonic
0
Re Pi B
Name
0
P0 0 0
Description
0 0 0 0 0 0 0 0 0
31:24
CS_SETUP_
n a
CS_SETUP_
a
Chip selection setup time =
(CS_SETUP_COUNT+1)*CLK_PERIOD, where CLK_PERIOD
n
COUNT COUNT
is the cycle time of the clock the SPI engine adopts.
Ba
CS_HOLD_C CS_HOLD_C Chip selection hold time =
23:16
OUNT OUNT (CS_HOLD_COUNT+1)*CLK_PERIOD
SCK_LOW_C SCK_LOW_C
15:8 SCK clock low time = (SCK_LOW_COUNT+1)*CLK_PERIOD.
OUNT OUNT
SCK_HIGH_ SCK_HIGH_C
7:0 SCK clock high time = (SCK_HIGH_COUNT+1)*CLK_PERIOD
COUNT OUNT
00000004 SPI_CFG1 SPI Configuration 1 Register 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
r
GET_ GET_
o
TICK TICK
Name
f
PACKET_LENGTH
_DLY _DLY
e
2 1
Type
Reset
Bit
RW
0
15
RW
0
14 13
l e
12
a s I
11
- R 2
10
0
9
0
8
0
7
0
6
0
5
RW
0
4
0
3
0
2
0
1
0
0
Name
Type
Reset 0 0 0
Re Pi B
PACKET_LOOP_CNT
0
RW
0 0 P 0 0 0 0 0
CS_IDLE_COUNT
0
RW
0 0 0 0
Bit(s) Mnemonic
n
Name
a a Description
n
GET_TICK_D GET_TICK_D
Ba
31
LY2 LY2
If the speed of SPI is not fast enough, these two bits can
help tolerate get_tick timing
The timing range between get_tick and get_tick_dly1 is one
GET_TICK_D GET_TICK_D cycle depending on the SPI system clock. The timing range
30
LY1 LY1 between get_tick_dly1 and get_tick_dly2 is also one cycle
depending on the SPI system clock. One cycle of SPI system
clock is around 7.519 ns.us. Get_tick_dly1 can tolerate 8.138ns,
and get_tick_dly2 can tolerate 15.038ns.
PACKET_LE PACKET_LEN
25:16
NGTH GTH
The transmission on the SPI bus consists of units of bytes.
Hence, PACKET_LENGTH[9:0] defines the number of bytes in
15:8
PACKET_LO PACKET_LO
f o r one packet, and PACKET_LOOP_CNT[7:0] defines the number

of packets within one transaction. The number of bytes in one
e
OP_CNT OP_CNT packet = PACKET_LENGTH + 1. The number of packets in one
l e a s I - R 2 transaction = PACKET_LOOP_CNT + 1. The total bytes of one

transaction = (PACKET_LENGTH + 1)*(PACKET_LOOP_CNT +
1).
7:0
CS_IDLE_CO
UNT
Re Pi B
CS_IDLE_CO
UNT
P The chip selection idle time between consecutive transaction =
(CS_HOLD_COUNT+1)*CLK_PERIOD.
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
00000008
Bit
Name
Type
31
SPI_TX_SRC
30 29
l
Re Pi B
28
SPI TX Source Address Register
P
27 26 25 24 23
SPI_TX_SRC[31:16]
RW
22 21 20 19 18
00000000
17 16
a
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
Type
15 14 13
n a n 12 11 10 9 8
SPI_TX_SRC[15:0]
RW
7 6 5 4 3 2 1 0
Ba
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

If TX_DMA_EN is set, the data to be put on the MOSI line are
kept in memory in advance, and the SPI controller will
31:0 SPI_TX_SRC SPI_TX_SRC automatically read the data from memory. SPI_TX_SRC defines
the memory address from which the SPI controller starts to read
data.
0000000C SPI_RX_DST SPI RX Destination Address Register 00000000

Bit
Name
31 30 29 28
f o
27
r 26 25 24 23
SPI_RX_DST[31:16]
22 21 20 19 18 17 16
Type
Reset
Bit
0
15
0
14
0
13
e
0
12
a s e 0
11
I - R 20
10
0
9
0
RW
8
0 0
7 6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
Reset 0 0 0 l
Re Pi B0
P0 0 0
SPI_RX_DST[15:0]
0
RW
0 0 0 0 0 0 0 0
Bit(s) Mnemonic
n
Name
a a Description
If RX_DMA_EN is set, the received data from the MISO line will
31:0 SPI_RX_DST
Ba n SPI_RX_DST
be moved to memory automatically by the SPI controller.
SPI_RX_DST defines the memory address to which the SPI
controller starts to store the data.
00000010 SPI_TX_DATA SPI TX Data FIFO 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SPI_TX_DATA[31:16]
Type WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SPI_TX_DATA[15:0]
Type WO
Reset 0 0 0 0
f o
0
r 0 0 0 0 0 0 0 0 0 0 0
The depth of the TX FIFO is 32 bytes. Writing to this register will
l
SPI_TX_DAT SPI_TX_DAT
P
31:0 write 4 bytes to TX FIFO. The TX FIFO pointer will automatically
Re Pi B
A A
move towards the next four bytes.
a n a
n
Ba
MT7623N
f o r
00000014 SPI_RX_DATA
e a s e R 2
SPI RX Data FIFO
I -
00000000
l
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit
0
15
0
14
0
13 Re Pi B0
12
P0
11
0
10
SPI_RX_DATA[31:16]
0
9
0
RO
8
0 0
7 6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
a n a SPI_RX_DATA[15:0]
RO
n
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:0
Mnemonic
SPI_RX_DAT
A
Ba Name
SPI_RX_DAT
A
Description
The depth of the RX FIFO is 32 bytes. Reading from this register
will read 4 bytes from RX FIFO. The RX FIFO pointer will
automatically move towards the next four bytes.
00000018 SPI_CMD SPI Command Register 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PAUS FINIS
Name E_IE H_IE
Type
Reset
Bit 15 14 13 12
f o
11 r 10 9 8 7 6 5 4 3 2
RW
1
0
RW
0
0
TX_E RX_E
Name NDIA NDIA SBF
RXM TXM
e
SBF
a s eTX_D RX_D
I -
MA_ MA_
R 2
CPO
L
CPH
A
CS_D
EASS PAUS
ERT_ E_EN
RST
RES CMD
UME _ACT
l
N N EN EN
P
EN
Re Pi B
Type RW RW RW RW RW RW RW RW RW RW RW WO WO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
17
Mnemonic
PAUSE_IE
a n a
Name
PAUSE_IE
Description
Interrupt enabling bit of pause flag in SPI status register
16
15
FINISH_IE
TX_ENDIAN Ba n FINISH_IE
TX_ENDIAN
Interrupt enabling bit of finish flag in SPI status register
Defines whether to reverse the endian order of the data
DMA from memory
The default setting (0) is not to be reversed. Only supports DMA
mode.
Defines whether to reverse the endian order of the data
14 RX_ENDIAN RX_ENDIAN DMA to memory
The default setting (0) is not to be reversed.
Indicates the data received from MISO line is MSB first or
13 RXMSBF RXMSBF not
Set RXMSBF to 1 for MSB first; otherwise set it to 0.
Indicates the data sent on MOSI line is MSB first or not
r
12 TXMSBF TXMSBF
Set TXMSBF to 1 for MSB first; otherwise set it to 0.
11 TX_DMA_EN TX_DMA_EN
e f o 2
DMA mode enabling bit of the data to be transmitted
s
The default setting (0) is not to be enabled.
10 RX_DMA_EN
e a
RX_DMA_EN
l P I - R DMA mode enabling bit of the data received

The default setting (0) is not to be enable.
Re Pi B
Control bit of the SCK polarity
9 CPOL CPOL 0: CPOL = 0
1: CPOL = 1
a n a
n
Ba
MT7623N
f o r
l
Defines the SPI Clock Format 0 or SPI Clock Format 1
8 CPHA
Re Pi B
CPHA
P during transmission
0: CPHA = 0
1: CPHA = 1
5
CS_DEASSE
RT_EN
a
CS_DEASSE
n
RT_EN
a
Enabling bit of the chip selection de-assertion mode
Set to 1 to enable this mode.
2
PAUSE_EN
RST Ba n PAUSE_EN
RST
Enabling bit of the pause mode
Set to 1 to enable this mode.
Software reset bit
When this bit is 1, software reset will be active high.
Default value: 0
Used when controller is in PAUSE IDLE state
1 RESUME RESUME Writing 1 to this bit will trigger the SPI controller to resume
transfer from PAUSE IDLE state.
Command activate bit
0 CMD_ACT CMD_ACT Writing 1 to this bit will trigger the SPI controller to start the
transaction.
0000001C SPI_STATUS0
f o r
SPI Status 0 Register 00000000
Bit
Name
31 30 29 28
e a s e 27
I - R 226 25 24 23 22 21 20 19 18 17 16
Type
Reset
Bit
Name
15 14 13 l
Re Pi B
12
P
11 10 9 8 7 6 5 4 3 2 1 0
PAUS FINIS
E H
Type
Reset
a n a RC
0
RC
0
Bit(s)
1
Mnemonic
PAUSE Ba n Name
PAUSE
Description
Interrupt status bit in pause mode
It will be set by the SPI controller when it completes the
transaction, entering the PAUSE IDLE state.
Interrupt status bit in non-pause mode
0 FINISH FINISH It will be set by the SPI controller when it completes the
transaction, entering the IDLE state.
00000020 SPI_STATUS1 SPI Status 1 Register 00000001

Bit
Name
Type
31 30 29 28
f
27
o r 26 25 24 23 22 21 20 19 18 17 16
Reset
Bit 15 14 13 12
e a s e 11
I - R 210 9 8 7 6 5 4 3 2 1 0
l
Name IDLE
Type
Reset
Re Pi B P RU
1
a
Ba
MT7623N
f o r
l
This status flag reflects the SPI controller is idle or not.
0 IDLE
Re Pi B
IDLE
P This bit is low active, i.e. 0 represents the SPI controller is busy
now.
a n a
11.5
1.
Programming Guide
Ba n
Follow the steps below to perform SPI transmission:
Prepare the data in the memory with its start address to be the “source address”.
2. Set up the timing and protocol for the SPI transmission (see figure below for detailed setup
parameters).
3. Fill the “destination address”, which is the start address that you would like to place the received
data, and “source address”, which is the start address to place the data to be transmitted, into
register SPI_RX_DST and SPI_TX_SRC, respectively.
4. Set up the CMD_ACT (bit0 of SPI_CMD) to start the transfer
5. Get the data received from the buffer prepared starting from “destination address”.
f o r CS_N
e
idle time
2
Data Transmission
CS_N
l e a s I - R
P
CS_N setup time CS_N hold time
Re Pi B
SCK
(CPOL=0)
SCK Edge
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SCK
(CPOL=1)
a n a
SAMPLE MOSI/MISO
(CPHA=0)
SAMPLE MOSI/MISO
(CPHA=1)
B a n
Figure 11-3: SPI transmission formats
Figure shows the waveform during the SPI transmission. The low active CS_N determines the start
point and end point of one transaction. The CS_N setup time, hold time and idle time are also
depicted.
r
CPOL defines the clock polarity in the transmission. Two types of polarity can be adopted, i.e. polarity
f o
0 and polarity 1. It shows both of the clock polarity (CPOL) as examples.
e 2
l e a s I - R
CPHA defines the legal timing to sample MOSI and MISO. Two different methods can be adopted.
Re Pi B P
a n a
n
Ba
MT7623N
f o r
12 USB2.0
e a s e I - R 2
12.1 Introduction
l
Re Pi B P
a n a
The USB controller is configured for supporting 8 endpoints to receive packets and 8 endpoints to
n
send packets except for endpoint 0. These endpoints can be individually configured in the software to
Ba
handle either Bulk transfers, Interrupt transfers or Isochronous transfers. There are 8 DMA channels
and the embedded RAM size is configurable size up to 8K bytes. The embedded RAM can be
dynamically configured to each endpoint. As the host for point-to-point communications, the controller
maintains a frame counter and automatically schedules SOF, Isochronous, Interrupt and Bulk
transfers.
12.2 Feature list
 USB2.0 with OTG



8 Tx and 8 Rx end point (exclude EP0)
4 Tx and 4 Rx USBQ
f o r
 Battery Charge Configuration

a s e - R 2
support BC1.1 host mode for SDP/CDP detection
e I

l
Re Pi B P
support BC1.1 device mode for SDP/CDP/DCP detection with PMIC
a n a Table 12-1: USB20 Feature List
n
Feature list Description
Ba
USB specifications USB2.0 OTG
Generic Host QMU
Enhanced feature
Generic Dev QMU
8 Tx
Endpoint 8 Rx
EP0
DMA channel 8
Embedded RAM Up to 8KB
UTMI+ interface UTMI+ 16b
CPU slave interface AHB asynchronous design
DMA master interface
f o rAHB Busy Free Asynchronous Design
e
Base Address 32’h11200000
l e a s I - R 2
Re Pi B P
a n a
n
Ba
MT7623N
f o r
12.3 Block Diagram
e a s e I - R 2
l
Re Pi B P
a n a
Ba n
f o r
e a s e R 2
Figure 12-1: Block Diagram of USB2.0
I -
l
Re Pi B P
a n a
Ba n
Figure 12-2: Block Diagram of USB2.0 QMU
12.4 USB MAC Register Definition
f o r
e a s e
Registers accessed using byte manipulation are marked in blue columns. Byte accessing registers
R 2
can be accessed using word manipulation. Word accessing registers cannot be accessed using the
I -
byte manipulation.
Register
l
Re Pi B
Register name
P Manipulat
Acronym
a
address ion
Ba
MT7623N
f o r
e a s e I - R 2 (Byte/Wo
rd)
Common Registers
USB + 0000h
USB + 0001h
l
Re Pi B P
Function address register
Power management register
Byte
Byte
FADDR
POWER
USB + 0002h
n a
Tx interrupt status register
a
Byte INTRTX
USB + 0004h
USB + 0006h
USB + 0008h
USB + 000Ah
Ba n
Rx interrupt status register
Tx interrupt enable register
Rx interrupt enable register
Common USB interrupts register
Byte
Byte
Byte
Byte
INTRRX
INTRTXE
INTRRXE
INTRUSB
USB + 000Bh Common USB interrupts enable register Byte INTRUSBE
USB + 000Ch Frame number register Byte FRAME
USB + 000Eh Endpoint selecting index register Byte INDEX
Indexed EndPoint CSR Region
n stands for endpoint number.
For example, endpoint 1’s n = 1. Valid n = 1 ~ MaxEndPoint.
r
MaxEndPoint is hardware configured and the maximum is 15.
USB + 0010h
e f o
It maps to CSR EP0 ~ EPx depending on the Byte
INDEX register. For example, if INDEX is n,
2
s
~ Indexed CSR
R
address 0010h ~ 001Fh are mapped to
USB + 001Fh
l e a I -
0x(100+10*n)h ~ 0x(100+10*n+F)h.
P
Re Pi B
USB + 0020h USB endpoint 0 FIFO register Byte FIFO0
USB + 0020h Byte
USB endpoint n FIFO register FIFOn
+(n)*4 h
n a
OTG, Dynamic FIFO, Version Registers
a
USB + 0060h
USB + 0061h
USB + 0062h
USB + 0063h
Ba n
OTG device control register
Power up counter register
Tx FIFO size register
Rx FIFO size register
Byte
Byte
Byte
Byte
DEVCTL
PWRUPCNT
TXFIFOSZ
RXFIFOSZ
USB + 0064h Tx FIFO address register Byte TXFIFOADD
USB + 0066h Rx FIFO address register Byte RXFIFOADD
Hardware Configuration, Special Setting Registers
Time buffer available on HS transactions Byte
USB + 007Ch HS_EOF1
register
Time buffer available on FS transactions Byte
USB + 007Dh FS_EOF1
r
register
USB + 007Eh
USB + 007Fh Reset information register
e f o
Time buffer available on LS transactions register Byte
2
Byte
LS_EOF1
RST_INFO
USB + 0080h
a s -
Rx data toggle set/status register
l e I R Word RXTOG
USB + 0082h
USB + 0084h
USB + 0086h Re Pi B P
Rx data toggle enable register
Tx data toggle set/status register
Tx data toggle enable register
Word
Word
Word
RXTOGEN
TXTOG
TXTOGEN
a n a
n
B a
MT7623N
f o r
e a s e
Level1 interrupt Control/Status registers
I - R 2
l
USB + 00A0h USB Level 1 interrupt status register Byte USB_L1INTS
USB + 00A4h
USB + 00A8h
Re Pi B P
USB Level 1 interrupt unmask register
USB Level 1 interrupt polarity register
Byte
Byte
USB_L1INTM
USB_L1INTP
USB + 00ACh
a n
Non-indexed EndPoint CSR Region
a
USB Level 1 interrupt control register Byte USB_L1INTC
Ba n
n stands for endpoint number.
For example, endpoint 1’s n = 1. Valid n = 1 ~ MaxEndPoint.
USB + 0102h EP0 control status register Byte CSR0
USB + 0108h EP0 received bytes register Byte COUNT0
USB + 010Bh NAK limit register Byte NAKLIMT0
USB + 010Fh Core configuration register Byte CONFIGDATA
USB + 0100h Byte
TXMAP register TXMAP(n)
+(n)*10h
USB + 0102h Byte
Tx CSR register TXCSR(n)
+(n)*10h
USB + 0104h
f o r Byte
e
RXMAP register RXMAP(n)
2
+(n)*10h
USB + 0106h
Rx CSR register
l e a s I - R Byte
RXCSR(n)
P
+(n)*10h
USB + 0108h
+(n)*10h
Re Pi B
Rx Count register
Byte
RXCOUNT(n)
USB + 010Ah
+(n)*10h
TxType register
a n a Byte
TXTYPE(n)
USB + 010Bh
+(n)*10h
USB + 010Ch
B a n
TxInterval register
RxType register
Byte
Byte
TXINTERVAL(n)
RXTYPE(n)
+(n)*10h
USB + 010Dh Byte
RxInterval register RXINTERVAL(n)
+(n)*10h
USB + 010Fh Byte
Configured FIFO size register FIFOSIZE(n)
+(n)*10h
DMA Channels Control Registers
M stands for DMA channel number.
r
For example, DMA channel 1’s M = 1. Valid M = 1 ~ MaxDMAChannel.
USB + 0200h
f o
MaxDMAChannel is hardware configured and the maximum is 8.
e
DMA interrupt status register (word access only) Word
2
DMA_INTR
USB + 0210h
a s - R
DMA limiter register (word access only)
l e I
Word DMA_LIMITER
P
USB + 0220h DMA configuration register (word access only) Word DMA_CONFIG
USB + 0204h
+(M-1)*10h only)
Re Pi B
DMA channel M control register (word access Word
DMA_CNTL_M
a n a
n
Ba
MT7623N
f o r
USB + 0208h
+(M-1)*10h only)
e a s e I - 2
DMA channel M address register (word access Word
R DMA_ADDR_M
USB + 020Ch
+(M-1)*10h l
Re Pi B P
DMA channel M byte count register (word Word
access only)
EndPoint RX Packet Count Register
DMA_COUNT_M
n a
n stands for endpoint number. For example, endpoint 1’s n = 1. Valid n = 1 ~ MaxEndPoint.
a
n
Ba
USB + 0300h Word
EPn RxPktCount register EPnRXPKTCOUNT
+(n)*4h
Host/Hub Control Registers (Host mode only registers)
n stands for endpoint number. For example, endpoint 1’s n = 1. Valid n = 1 ~ MaxEndPoint.
MaxEndPoint is hardware configured and maximum is 15.
USB + 0480h Word
Transmit endpoint n function address TXFUNCADDR
+8*n h
USB + 0482h Word
Transmit endpoint n hub/port address TXHUBADDR
+8*n h
USB + 0484h Word
r
Receive endpoint n function address RXFUNCADDR
+8*n h
USB + 0486h
e f o
Receive endpoint n hub/port address
2
Word
RXHUBADDR
s
+8*n h
l e a P I - R
12.4.1
Re Pi B
Function Address Register
a
00 FADDR Function Address Register(Device mode only) 00
Bit
Name
15 14 13
n a n 12 11 10 9 8 7 6 5 4
FUNCTION_ADDRESS
3 2 1 0
Ba
Type RW
Reset 0 0 0 0 0 0 0

6:0 FUNCTION_ADDRESS FADDR is an 8-bit register that should be written with a 7-bit address of the peripheral
part of a transaction. When the USB2.0 controller is used in the peripheral mode
(DevCtl.bit2 = 0), the register should be written with the address received through a
SET_ADDRESS command, which will then be used for decoding the function address in
subsequent token packets. When the USB2.0 controller is used in the host mode
(DevCtl.bit2 = 1). The function address is configured by TXFUNCADDR and
RXFUNCADDR.
12.4.2 Power Management Register
f o r
12.4.2.1
01
Peripheral Mode
POWER_PERI
e a s e I - R 2
Power Management Register 20
Bit
Name
15 14 13
l
Re Pi B
12
P
11 10 9 8 7 6 5
ISOUP SOFT HSEN HSMO RESE RESU

DATE CONN AB DE T ME
4
SUSP
ENDM
3
ENAB
LESU
SPEN
2 1 0
a
ODE
DM
Ba
MT7623N
f o r
Type
Reset
e a s e I - R 2 RW
0
RW
0
RW
1
RU
0
RU
0
RW
0
RU
0
RW
0
Bit(s)
7
Name
ISOUPDATE
l
Re Pi B P
Description
When set by the CPU, the USB2.0 controller will wait for an SOF token from the time
TxPktRdy is set before sending the packet. If an IN token is received before an SOF
a n a token, then a zero length data packet will be sent.

Note: Only valid in the peripheral mode, and this bit only affects endpoints performing
n
isochronous transfers.
Ba
6 SOFTCONN If the Soft Connect/Disconnect feature is enabled, then the USB D+/D- lines is enabled
when this bit is set by the CPU and tri-stated when this bit is cleared by the CPU.
In the peripheral FS mode, clearing the Softcon bit may need execution latency until
USB BUS SE0 is detected by HW.
Execution Latency ~= 1ms, such as SOF Packet EOP or RESET.
In the peripheral HS mode, clearing the Softcon bit still needs execution latency until
USB BUS SE0 is detected by HW.
Execution Latency ~= 1us, such as HS idle.
Note: Only needed to be set in the peripheral Mode. For the host mode, this bit will be
set if DEVCTL[0] session bit is set and this bit should also be cleared if the session bit is
cleared by CPU.
5 HSENAB When set by the CPU, the USB2.0 controller will negotiate for the high-speed mode
when the device is reset by the hub. If not set, the device will only operate in the full-
speed mode.
r
4 HSMODE When set, this read-only bit indicates high-speed mode successfully negotiated during
o
the USB reset.
s f
In the peripheral mode, it becomes valid when the USB reset is completed (as indicated
e
by the USB reset interrupt).
2
In the host Mode, it becomes valid when the Reset bit is cleared. Remains valid in the
l e a I - R
duration of the session.
Note: Allowance is made for Tiny-J signaling in selecting the transfer speed.
P
Re Pi B
3 RESET Set when Reset signaling is present on the bus.
Note: This bit can be read/written by the CPU in the host mode but read-only in the
peripheral mode.
a
2 RESUME Set by the CPU to generate Resume signaling in the suspend mode. The CPU clears
n
this bit after 10ms (max. 15ms) to end the Resume signaling. In the host mode, this bit
a
is automatically set when Resume signaling from the target is detected while the
n
USB2.0 controller is suspended.
Ba
1 SUSPENDMODE In the host mode, the CPU sets up this bit to enter the suspend mode.
In the peripheral mode, set this bit to enter the suspend mode. Cleared when the CPU
reads the interrupt register or sets up the Resume bit above.
0 ENABLESUSPENDM Set by the CPU to enable SUSPENDM output
12.4.2.2 Host Mode

01 POWER_HOST Power Management Register 20
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SUSP
ENAB
HSEN HSMO RESE RESU LESU
ENDM
r
AB DE T ME SPEN
ODE
o
DM
Type
Reset
s e f 2
RW
1
RU
0
RW
0
RW
0
A0
0
RW
0
Bit(s) Name
l e a I - R
Description
P
Re Pi B
5 HSENAB When set by the CPU, the USB2.0 controller will negotiate for the high-speed mode
when the device is reset by the hub. If not set, the device will only operate in the full-
speed mode.
a
4 HSMODE When set, this read-only bit indicates high-speed mode successfully negotiated during
Ba
MT7623N
f o r
e a s e - 2
the USB reset.
R
In the peripheral mode, it becomes valid when the USB reset is completed (as indicated
I
l
by the USB reset interrupt).
3 RESET
Re Pi B P
In the host mode, it becomes valid when the Reset bit is cleared. Remains valid in the
duration of the session.
Note: Allowance is made for Tiny-J signaling in selecting the transfer speed.
Set when Reset signaling is present on the bus
a n a Note: This bit can be read/written by the CPU in the host mode but read-only in the
peripheral mode.
n
2 RESUME Set by the CPU to generate Resume signaling in the suspend mode. The CPU clears
Ba
this bit after 10ms (max. 15ms) to end the Resume signaling. In the host mode, this bit
is automatically set when the Resume signaling from the target is detected while the
USB2.0 controller is suspended.
1 SUSPENDMODE In the host mode, the CPU sets this bit to enter the suspend mode.
In the peripheral mode, set this bit to enter the suspend mode. Cleared when the CPU
reads the interrupt register or sets up the Resume bit above.
0 ENABLESUSPENDM Set by the CPU to enable SUSPENDM output
The “HS Enab” bit can be used to disable high-speed operation. Normally the USB MAC will
automatically negotiate for high-speed operation when it is reset. If this bit is cleared, however, the
USB MAC will remain in the full-speed mode even when connected to a high-speed-capable USB.
f o r
The “HS Mode” bit can be used to determine whether the USB MAC is in the high-speed mode or full-
speed mode. It will go high when the function successfully negotiates for high-speed operation during
a USB reset.
e a s e I - R 2
l P
The “Reset” bit can be used to determine when the Reset signaling is present on the USB. It will go
Re Pi B
high when the Reset signaling is detected and remain high until the bus reverts to an idle state.
a n a
The “Resume” bit is used to force the USB MAC to generate the Resume signaling on the USB to
perform remote wake-up from the suspend mode. Once set high, it should be left high for
Ba n
approximately 10ms (at least 1ms and no more than 15ms) then cleared.
The “Suspend Mode“ bit is set either to make the USB MAC enter the suspend mode (host mode)
or when the suspend mode is entered (peripheral mode). It will be cleared when the IntrUSB register
is read (as a result of receiving a suspend interrupt). It will also be cleared if the suspend mode is left
by setting the “Resume” bit to initiating a remote wake-up.
The “Enable SuspendM“ bit enables the SUSPENDM signal to indicate when the USB MAC is in the
suspend Mode. With this bit set to ‘1’, the SUSPENDM signal will be low whenever the USB MAC is in
the suspend mode and high at all other time.
f o r
e
12.4.3 Tx Interrupt Status Register
0002 INTRTX
l e a s - R 2
Tx Interrupt Status Register
I
0000
Re Pi B P
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name EP8_T EP7_T EP6_T EP5_T EP4_T EP3_T EP2_T EP1_T
EP0
X X X X X X X X
Type W1C W1C W1C W1C W1C W1C W1C W1C W1C
a
Reset 0 0 0 0 0 0 0 0 0
Ba
MT7623N
f o r
Bit(s) Name
e a s e I - R
Description
2
8
7
6
EP8_TX
EP7_TX
EP6_TX
l
Re Pi B P
T8 endpoint N interrupt event
5
4
EP5_TX
EP4_TX
a n a T5 endpoint N interrupt event

3
2
1
0
EP3_TX
EP2_TX
EP1_TX
EP0 Ba n T3 endpoint N interrupt event
Endpoint0 interrupt event
TXENDPOINTS can be read from the EPINFO register. The undefined endpoints bits are reserved.
12.4.4 Rx Interrupt Status Register

0004 INTRRX Rx Interrupt Status Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
f o r EP8_R EP7_R EP6_R EP5_R EP4_R EP3_R EP2_R EP1_R

X X X X X X X X
e
Type W1C W1C W1C W1C W1C W1C W1C W1C
Reset
l e a s I - R 2 0 0 0 0 0 0 0 0
Bit(s)
8
7
Name
EP8_RX
EP7_RX
Re Pi B P
Description
R8 endpoint N interrupt event
a
6 EP6_RX R6 endpoint N interrupt event
5
4
EP5_RX
EP4_RX
n a n R5 endpoint N interrupt event

Ba
RXENDPOINTS can be read from the EPINFO register. The undefined endpoints bits are reserved.
12.4.5 Tx Interrupt Enable Register

0006 INTRTXE Tx Interrupt Enable Register FFFF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
f o r EP8_T EP7_T EP6_T EP5_T EP4_T EP3_T EP2_T EP1_T

XE
RW
XE
RW
XE
RW
XE
RW
XE
RW
XE
RW
XE
RW
XE
RW
EP0_E
RW
Reset
e a s e I - R 2
1 1 1 1 1 1 1 1 1
Bit(s)
8
7
Name
EP8_TXE
EP7_TXE
l
Re Pi B P
Description
1'b0: Disable Tx endpoint N interrupt event
1'b1: Enable Tx endpoint N interrupt event
a n a
n
Ba
MT7623N
f o r
6 EP6_TXE
e a s e - 2
R
I
5
4
EP5_TXE
EP4_TXE
l
Re Pi B P
3 EP3_TXE
a n a 1'b1: Enable Tx endpoint N interrupt event

1
EP2_TXE
EP1_TXE
Ba n 1'b1: Enable Tx endpoint N interrupt event
0 EP0_E 1'b0: Disable Tx endpoint0 interrupt event
1'b1: Enable Tx endpoint0 interrupt event
INTRTXE provides interrupt enabling bits for the interrupts in INTRTX. Where a bit is set to 1,
MC_NINT will be asserted on the corresponding interrupt in the INTRTX status register becoming set.
Where a bit is set to 0, the interrupt in INTRTX status is still set but MC_NINT is not asserted.
o r
TXENDPOINTS can be read from the EPINFO register. The undefined endpoints bits are reserved.
f
12.4.6
a s e
Rx Interrupt Enable Register
e I - R 2
0008
Bit
Name
15
INTRRXE
14 13 l
Re Pi B
12 P
Rx Interrupt Enable Register
11 10 9 8 7 6 5 4
EP8_R EP7_R EP6_R EP5_R EP4_R EP3_R EP2_R EP1_R
3 2 1
FFFE
0
Type
a n a XE
RW
XE
RW
XE
RW
XE
RW
XE
RW
XE
RW
XE
RW
XE
RW
n
Reset 1 1 1 1 1 1 1 1
Ba
B
i
t
(
s
N
a
m
e
Description
)
8 E 1'b0: Disable Rx Endpoint N interrupt event
P 1'b1: Enable Rx Endpoint N interrupt event
8
_
R
X
E
r
o
s
7
e
_
R
f 2
a R
X
l e
E
P I -
Re Pi B
6
_
a
R
Ba
MT7623N
f o r
e a s e
X
E
I - R 2
l
Re Pi B
P
5
_
R
a
X
n
E
4
n a E 1'b0: Disable Rx Endpoint N interrupt event
Ba
4
_
R
X
E
3
_
R
X
E
2
_
R
X
f o r
1
e a s e
E
E
I - R 2 1'b0: Disable Rx Endpoint N interrupt event
l
Re Pi B P
1
_
R
X
a
E
n a n
INTRRXE provides interrupt enabling bits for the interrupts in INTRRX. Where a bit is set to 1,
Ba
MC_NINT will be asserted on the corresponding interrupt in the INTRRX status register becoming set.
Where a bit is set to 0, the interrupt in INTRRX status is still set but MC_NINT is not asserted.
RXENDPOINTS can be read from the EPINFO register. The undefined endpoints bits are reserved.
12.4.7 Common USB Interrupt Register

0 I Common USB Interrupt 0
A N Register 0
T
f o r R
U
e
S
l
B
e a s I
1
- R 2 B
1 1 1 1 1 9 8 7 6 5 4 3 2 1
P
i 5 4 3 2 1 0
Re Pi B
t
N V S D C S R R
a B E I O O E E
m U S S N F S S
a n a
n
Ba
MT7623N
f o r
e
e a s e I - R 2 S
E
S
R
C
O
N E
T
U
M
l
R E N _ E
Re Pi B P R
O
R
Q B
A
B
L
a
E
n
T W W W W W W W
a
y 1 1 1 1 1 1 1
n
p C C C C C C C
Ba
e
R
e
s 0 0 0 0 0 0 0
e
t
B N Description
i a
t m
( e
s
)
7 V Set when VBus drops below the VBus valid
B threshold during a session. Only valid when
f o r U
S
USB2.0 controller is 'A' device.
e
E
s 2
R
a R
R
l e P I - O
R
Re Pi B
6 S Set when Session Request signaling has been
E detected. Only valid when USB2.0 controller is 'A'
S device.
a
S
n
R
a
E
n
Q
Ba
5 D Set in the host mode when a device disconnection
I is detected. Set in the peripheral mode when a
S session ends. Valid at all transaction speeds.
C
O
N
4 C Set when a device connection is detected. Only
O valid in the host mode. Valid at all transaction
N speeds.
N
3 S Set when a new frame starts.
O
F
2 R Set in the peripheral mode when the Reset
E signaling is detected on the bus.
f o r S
E
Set in the host mode when babble is detected.
Note: Only active after the first SOF is sent.
e
T
s 2
_
a R
B
l e P I - A
B
Re Pi B
L
E
1 R Set when the Resume signaling is detected on the
a
E bus while the USB2.0 controller is in the suspend
Ba
MT7623N
f o r
e a s e I - R 2 S
U
mode.
l
M
Re Pi B P
E
0 S Set when the Suspend signaling is detected on
U the bus. Only valid in the peripheral mode.
S
a
P
n
E
a
N
12.4.8 Ba n
Common USB Interrupt Enable Register
D
0 I Common USB
B N Interrupt Enable
T Register
R
U
S
B
E
f o rB
i
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3
e
t
l e a s I
N
-
a
m
R 2 V
B S
P
D
Re Pi B
e U E
I C
S S S
S O
E S O
C N
R R F
O N
a
R E _
N _
n
O Q E
_ E
a
R _
E
n
_ E
Ba
E
T
y R R R R R
p W W W W W
e
R
e
s 0 0 0 0 0
e
t

7 VBUSERROR_E Enables VBusError interrupt
r
6 SESSREQ_E Enables SessReq interrupt
5
4
DISCON_E
CONN_E
e f o
Enables Discon interrupt
Enables Conn interrupt
2
3
2
SOF_E
RESET_BABLE_E
l e a sEnables SOF interrupt
I - R
Enables Reset/Babble interrupt
1
0
RESEUM_E
SUSPEND_E
Re Pi B P
Enables Resume interrupt
Enables Suspend interrupt
a n a
n
Ba
MT7623N
f o r
e a s e I - 2
INTRUSBE provides interrupt enabling bits for the interrupts in INTRUSB. Where a bit is set to 1,
R
MC_NINT will be asserted on the corresponding interrupt in the INTRUSB status register becoming
l
Re Pi B P
set. Where a bit is set to 0, the interrupt in INTRUSB status is still set but MC_NINT is not asserted
12.4.9
a
Frame Number Register
a n
000C
Bit
Name
Type
Reset
15
FRAME
14
Ba
13
n 12
Frame Number Register
11 10
0
9
0
8
0
7
0
6 5
FRAME_NUMBER
0
RU
0 0
4 3
0
2
0
1
0
0000
0

10:0 FRAME_NUMBER Frame is a 11-bit read-only register that holds the last received frame number.
FRAME NUBMER Frame is a 11-bit read-only register that holds the last received frame number.
12.4.10
r
Endpoint Selection Index Register
f o
e
0E INDEX Endpoint Selection Index Register 00
Bit
Name
15 14 13
l
12
e a s 11
I - R 2
10 9 8 7 6 5 4 3 2
SELECTED_ENDPOINT
1 0
P
Type
Re Pi B
RW
Reset 0 0 0 0
a
3:0 SELECTED_ENDPOINT
n a n Each Tx endpoint and Rx endpoint has its own set of control/status registers located
between USB+100h - USB+1FFh. In addition one set of Tx control/status and one set of
Rx control/status registers appear at USB+010h - USB+01Fh. Index is a 4-bit register
Ba
that determines which endpoint control/status registers are accessed. Before accessing
an endpoint's control/status registers at USB+010h - USB+01Fh, the endpoint number
should be written to the Index register to ensure that the correct control/status registers
appear in the memory map.
12.4.11 USB Endpoint 0 FIFO Register

00000020 FIFO0 USB Endpoint 0 FIFO Register FFFFFFFF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name FIFO_DATA[31:16]
Type Other
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
Type
15 14 13 12 11
f o r 10 9 8
FIFO_DATA[15:0]
7 6 5 4 3 2 1 0
e
Other
s 2
Bit(s) Name
l e a P I - R
Description
Re Pi B
31:0 FIFO_DATA The Endpoint FIFO registers provides 16 addresses for the CPU to access FIFOs for
each endpoint. Writing to these addresses will load data into TxFIFO for the
corresponding endpoint. Reading from these addresses will unload data from RxFIFO
a
for the corresponding endpoint.
Ba
MT7623N
f o r
e a s e - 2
1. Note: Transfers to and from FIFOs may be 8-bit, 16-bit or 32-bit as required, and
R
any combination of access is allowed provided the data accessed is contiguous.
I
l
However, all the transfers associated with one packet must be of the same width so
Re Pi B P
that the data are consistently byte-, word- or double-word-aligned. The last transfer
may however contain fewer bytes than the previous transfers in order to complete
an odd-byte or odd-word transfer. For DC/DTV projects, also refer to the
RISC_SIZE register to complete the FIFO access.Depending on the size of FIFO
a
and the expected maximum packet size, FIFO supports either single-packet or
n
double-packet buffering. However, burst writing of multiple packets is not supported
a
as flags need to be set after each packet is written.Following a STALL response or a
n
Tx strike out error on endpoint, the associated FIFO is completely flushed.
Ba
The programmers does not neet to use debugging tools to monitor or read the FIFO
region. The FIFO pointer will increase and cause unexpected errors in MAC state
machine.
12.4.12 USB Endpoint n FIFO Register

00000024 FIFO1 USB Endpoint 1 FIFO Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name FIFO_DATA[31:16]
Type Other
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset 0 0 0 0
f o0
r 0 0
FIFO_DATA[15:0]
0
Other
0 0 0 0 0 0 0 0
Bit(s) Name
e a s e I - R
Description
2
31:0 FIFO_DATA
l
Re Pi B P
The Endpoint FIFO register provides 16 addresses for the CPU to access the FIFO for
each endpoint. Writing to these addresses loads data into TxFIFO for the corresponding
endpoint. Reading from these addresses unloads data from RxFIFO for the
corresponding endpoint.
a
1. Note:Transfers to and from FIFOs may be 8-bit, 16-bit or 32-bit as required, and any
n a n combination of access is allowed provided the data accessed is contiguous.

However, all the transfers associated with one packet must be of the same width so
that the data are consistently byte-, word- or double-word-aligned. The last transfer
Ba
may however contain fewer bytes than the previous transfers in order to complete
an odd-byte or odd-word transfer. For DC/DTV projects, also refer to the
RISC_SIZE register to complete the FIFO access.Depending on the size of FIFO
and the expected maximum packet size, FIFO supports either single-packet or
double-packet buffering. However, burst writing of multiple packets is not supported
as flags need to be set after each packet is written.Following a STALL response or a
Tx strike out error on endpoint, the associated FIFO is completely flushed.
The programmers does not need to use debugging tools to monitor or read the FIFO
region. The FIFO pointer will increase and cause unexpected errors in the MAC state
machine.
12.4.13 Device Control Register

60 DEVCTL Device Control Register NA
Bit 1
5
1
4
1
3
1
f o2
r 1
1
1
0
9 8 7 6 5 4 3 2 1 0
e
Na B H
2
H S
s
m _ O
R
F L O E
a
e
-
D S
e I
S S S S
l
E T
D D VBUS T S
Re Pi B P
V M
E E R I
I O
V V E O
C D
Q N
E E
Ty
a
R R R RU R O O
Ba
MT7623N
f o r
p
e
e a s e I - R 2 U U U U t
h
t
h
l
e e
Re Pi B P
r r
Re
s
0 0 0 X X 0 0 0
e
a
t
Bit(s) Name
n a n Description
Ba
7 B_DEVICE This read-only bit indicates whether the USB2.0 controller is operating as the 'A'
device or the 'B' device. Only valid while a session is in progress.
Note: If the core is in Force_Host mode, this bit will indicate the state of the
HOSTDISCON input signal from PHY.
1'b0: 'A' device
1'b1: 'B' device

6 FSDEV This read-only bit is set when a full-speed or high-speed device has been detected
being connected to the port. (High-speed devices are distinguished from full-
speed by checking high-speed chirps when the device is reset.) Only valid in
the host mode.
5 LSDEV This read-only bit is set when a low-speed device has been detected being
connected to the port. Only valid in the host mode.
4:3 VBUS The read-only bits encode the current VBUS level as follows: (Only available with
r
OTG function equipped, else the register value is undefined.)
e f o
2'b00: Below SessionEnd
2'b01: Above SessionEnd, below AValid
2
2'b10: Above AValid, below VBusValid
2 HOSTMODE
l e a s I
2'b11: About VBusValid
- R
This read-only bit is set when the USB2.0 controller is acting as a host.
1
0
HOSTREQ
SESSION
Re Pi B P
When set, the USB2.0 controller will initiate host negotiation when the suspend
mode is entered. Cleared when host negotiation is completed. ('B' device only).
When operating as an 'A' device, this bit is set or cleared by the CPU to start or end
a session. When operating as a 'B' device, this bit is set/cleared by the USB2.0
a n a controller when a session starts/ends. It is also set by the CPU to initiate the
session request protocol. When the USB2.0 controller is in the suspend mode,
the bit may be cleared by the CPU to perform a software disconnect. Note:
Ba n Clearing this bit when the core is not suspended will result in undefined
behavior.
12.4.14 PWRUPCNT Register

61 PWRUPCNT Power Up Counter Register 0F
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PWRUPCNT
Type RW
Reset 1 1 1 1

3:0 PWRUPCNT
o r
Power-up counter limit
f
The power-up counter is used to count the K state duration during suspension, and
e a s e
when it is timed out, the resume interrupt will be issued. The register should be
I - R 2
configured according to the AHB clock speed.
12.4.15 l
Re Pi B P
Tx FIFO Size Register (Dynamic FIFO Sizing Only)
a
62 TXFIFOSZ Tx FIFO Size Register 00
Ba
MT7623N
f o r
Bit
Name
15 14 13 12
e a s e 11
I - R 210 9 8 7 6 5 4
TXDP
3 2
TXSZ
1 0
l
B
Type
Reset
Re Pi B P RW
0 0 0
RW
0 0
B
i
t
Name
a n a Description
4
(
s
)
Ba
TXDPB
n Defines whether the double-packet buffering is supported for TxFIFO
0: Support only single-packet buffering
1: Support double-packet buffering
3 TXSZ Maximum packet size allowed (before any splitting within FIFO of Bulk/High-
: Bandwidth packets prior to transmission)
0 If TxDPB = 0, FIFO will also be this size. If TxDPB = 1, FIFO will be twice this
size.
TxSZ[3:0]: Packet size (bytes)
4'b0000: 8
4'b0001: 16
4'b0010: 32
4'b0011: 64
f o r 4'b0100: 128
4'b0101: 256
4'b0110: 512
e a s e I - R 2
4'b0111: 1,024
4'b1000: 2,048 (single-packet buffering only)
l
Re Pi B
Only valid when configuring dynamic FIFO sizing. P
Others: No support
n a
The option of setting FIFO sizes dynamically only applies to Endpoints 1 ~.15. The Endpoint 0 FIFO
a
Ba n
has a fixed size(64 bytes) and a fixed location(start address 0)
It is the responsibility of the firmware (and the system designer) to ensure that all the Tx and Rx
endpoints that are active in the current USB configuration have a block of RAM assigned exclusively
to them which is at least as large as the maximum packet size set for the endpoint.
12.4.16 Rx FIFO Size Register (Dynamic FIFO Sizing Only)

6 RX Rx FIFO Size Register 0
3 F 0
I
f
F
O
o r
e a s e S
Z
I - R 2
l
B 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
N
i
t
a
Re Pi B
5 4
P 3 2 1 0
R
X RXSZ
a
m D
Ba
MT7623N
f o r
e
e a s e I - R 2 P
B
l
T
R
y
p
e
Re Pi B P R
W
RW
a
e
n
s 0 0 0 0 0
a
e
n
t
B
Ba
i
t
(
s
Na
m
e
Description
)
4 RX Defines whether double-packet buffering is supported for TxFIFO
D 0: Support only single-packet buffering
P
1: Support double-packet buffering
B
3 RX Maximum packet size allowed for (before any splitting within FIFO
: S of Bulk/High-Bandwidth packets prior to transmission)
0 Z If TxDPB = 0, FIFO will also be this size. If TxDPB = 1, FIFO will be
f o r twice this size.

RxSZ[3:0]: Packet size (bytes)
e
4'b0000: 8
l e a s I - R 2 4'b0001: 16
4'b0010: 32
4'b0011: 64
Re Pi B P
4'b0100: 128
4'b0101: 256
4'b0110: 512
4'b0111: 1,024
a n a 4'b1001: 4,096 (single-packet buffering only)

Others: No support
12.4.17
Ba n
Tx FIFO Address Register (Dynamic FIFO Sizing Only)
0 T Tx FIFO Address Register 0
0 X
6 F
4 I
F
O
A
D
D
B
i
t
1
f o5
r 1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1
N
a
m
e a s e I - R 2 TXFIFOADD
T
le
Re Pi B
y
p
e
P RW
a n a
n
Ba
MT7623N
f o r
R
e
e a s e I - R 2
l
s 0 0 0 0 0 0 0 0 0 0 0 0
Re Pi B P
e
t
a
B Name Description
n
i
a
t
n
(
Ba
s
)
1 TXFIFOADD 13-bit register which controls the start address of the selected Tx endpoint
2 FIFO
: TxFIFOadd[12:0]
0 Start address
13'h0000: 0000
13'h0001: 0008
13'h0002: 0010
13'h1FFF: FFF8
12.4.18 Rx FIFO Address Register (Dynamic FIFO Sizing Only)

0
0
RX
f
F
o r Rx FIFO Address Register 0
0
6
6
e a s e I
F
I - R 2
0
0
l
O
Re Pi B
A
D
D
P
B
i
t
1
5
a n
1
a 4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
N
a
m
e
Ba
D
na
t
a
E
r
O
v
e
r
R
U
r N RXFIFOADD
I I
n n
t t
r r
E E
n n
T
y R R
RW
p W W
e
R
e
s
f o r
e
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
s 2
e
a R
t
l e P I -
Re Pi B
B Na Description
i m
t e
a
(
B a
MT7623N
f o r
s
)
e a s e I - R 2
1
5
l
Re Pi B
Da
t
a
E P Enables data error interrupt
Note: This bit is only valid when the endpoint is operating in the
ISO mode.
a
r
n
r
a
I
n
n
Ba
t
r
E
n
1 Ov Enables overrun interrupt

4 e
r Note: This bit is only valid when the endpoint is operating in the
R ISO mode.
U
N
I
n
t
r
E
n
1
2
RX
F
f o r RxFIFOadd is a 13-bit register which controls the start address of

the selected Rx endpoint FIFO.
:
0
e a s
I
F
Oe I - R 2 RxFIFOadd[12:0]
Start address
l
Re Pi B
A
D
D
P
13'h0000: 0000
13'h0001: 0008
13'h0002: 0010
13'h1FFF: FFF8
a n a
n
12.4.19 HS_EOF1 Register
7C
Bit
Name
Type
Reset
15
HS_EOF1
14
Ba
13 12
Time buffer available on HS transaction Register
11 10 9 8 7
1
6
0
5
0
4
HS_EOF1
0
RW
0
3 2
0
1
0
0
0
80

7:0 HS_EOF1 Sets up for high-speed transactions the time before EOF to stop beginning new
transactions, in units of 133.3ns. (The default setting corresponds to 17.07us.). USB2.0
IP only.
12.4.20 FS_EOF1 Register
f o r
7D
Bit 15
FS_EOF1
14 13
e
12
a s e 11
I - R 2
Time buffer available on FS transaction Register
10 9 8 7 6 5 4 3 2 1 0
77
Name
Type
Reset l
Re Pi B P 0 1 1
FS_EOF1
1
RW
0 1 1 1
a n a
n
Ba
MT7623N
f o r
Bit(s)
7:0
Name
FS_EOF1
e a s e
Description
I - R 2
Sets up for full-speed transactions the time before EOF to stop beginning new
l
Re Pi B P
transactions, in units of 533.3ns. (The default setting corresponds to 63.46us.) The
default value will change to 8'hBE to meet 63.46us.
12.4.21 LS_EOF1 Register
a n a
7E
Bit
Name
Type
Reset
15
LS_EOF1
14
Ba
13
n 12
Time buffer available on LS transaction Register
11 10 9 8 7
0
6
1
5
1
4
LS_EOF1
1
RW
0
3 2
0
1
1
0
0
72

7:0 LS_EOF1 Sets up for low-speed transactions the time before EOF to stop beginning new
transactions, in units of 1.067us. (The default setting corresponds to 121.6us.). USB2.0
IP only. The default value will change to 8'hB6 to meet 121.6us.
12.4.22 RSTINFO Register

7F RST_INFO
f o r
Reset Information Register 00
Bit
Name
15 14 13 12
e
11
a s e 10
I - R 2
9 8 7 6
WTFSSE0
5 4 3 2
WTCHRP
1 0
l
Type RW RW
Reset
Bit(s) Name
Re Pi B P
Description
0 0 0 0 0 0 0 0
7:4 WTFSSE0
a n a
Signifies the SE0 signal duration before issuing the reset signal(for device only)
Duration = 272.8*WTFSSE0 + 2.5 usec(This register will only be reset when the
n
hardware is reset.)
3:0 WTCHRP
B a Sets up the delay to be applied from detecting reset to sending chirp K (for device only)
Duration = 272.8*WTCHRP + 0.1 usec(This register will only be reset when the
hardware is reset.)
12.4.23 Rx Data Toggle Set/Status Register

0080 RXTOG Rx Data Toggle Set/Status Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name EP8R EP7R EP6R EP5R EP4R EP3R EP2R EP1R
XTOG XTOG XTOG XTOG XTOG XTOG XTOG XTOG
Reset 0 0 0 0 0 0 0 0
Bit(s) Name
f o r
Description
8 EP8RXTOG
e a s e - R 2
Receives logical Endpoint n data toggle bit set/status
When read, these bits indicate the current state of the Endpoint n data toggle. If the
I
l
enable bit is high, the bit may be written with the required setting of the data toggle. If
Re Pi B
.
P
the enable bit is low, any value written will be ignored
Note: This register is word access.

1'b0: Logical Endpoint n RX data toggle bit = 0
a n a 1'b1: Logical Endpoint n RX data toggle bit = 1
n
Ba
MT7623N
f o r
7 EP7RXTOG
e a s e - R 2
I
l
Re Pi B
.
P
the enable is low, any value written will be ignored

6 EP6RXTOG
a n a 1'b1: Logical Endpoint n RX data toggle bit = 1

Ba n When read, these bits indicate the current state of the Endpoint n data toggle. If the
.
5 EP5RXTOG Receives logical Endpoint n data toggle bit set/status
.
r
o
s f
e
.
2
l e a I - R
P
Re Pi B
a
n
a
.
2 EP2RXTOG
Ba n Note: This register is word access.
.
r
.
o
s f
e
2
This register is word access.
l e a P I - R
Re Pi B
a n a
n
Ba
MT7623N
f o r
12.4.24
e a s e
Rx Data Toggle Enable Register
I - R 2
0082
Bit
Name
15
RXTOGEN
14 13
l
Re Pi B
12
P
Rx Data Toggle Enable Register
11 10 9 8 7 6 5 4
EP8R EP7R EP6R EP5R EP4R EP3R EP2R EP1R
XTOG XTOG XTOG XTOG XTOG XTOG XTOG XTOG
3 2 1
0000
0
Type
Reset
a n a EN
RW
0
EN
RW
0
EN
RW
0
EN
RW
0
EN
RW
0
EN
RW
0
EN
RW
0
EN
RW
0
Bit(s)
8
Name
EP8RXTOGEN
Ba n Description
Receives logical Endpoint n data toggle bit enabling
If the enable bit is set, the Endpoint n data toggle can be set.
1'b0: Forbid RISC writing EP n data toggle status with EP1RXTOG
1'b1: Allow RISC writing EP n data toggle status with EP1RXTOG
7 EP7RXTOGEN Receives logical Endpoint n data toggle bit enabling
If the enable bit is set, the endpoint n data toggle can be set.
f r
o
5 EP5RXTOGEN
e a s e - R 2
I
l
4 EP4RXTOGEN
Re Pi B P
a
n
a
n
Ba
r
e f o 2
l e a s I - R
12.4.25
0084 TXTOG
Re Pi B P
Tx Data Toggle Set/Status Register
Tx Data Toggle Set/Status Register 0000
Bit 15 14 13
a n a
12 11 10 9 8 7 6 5 4 3 2 1 0
n
Ba
MT7623N
f o r
Name
e a s e I - R 2 EP8TX EP7TX EP6TX EP5TX EP4TX EP3TX EP2TX EP1TX

TOG TOG TOG TOG TOG TOG TOG TOG
l
Reset
Bit(s) Name
Re Pi B P
Description
0 0 0 0 0 0 0 0
8 EP8TXTOG
a n a Transmits logical Endpoint n data toggle bit set/status

When read, the bit indicates the current state of the Endpoint n data toggle. If the enable
n
bit is high, the bit may be written with the required setting of the data toggle. If the
Ba
enable is low, any value written will be ignored
.
1'b0: Logical Endpoint n TX data toggle bit = 0
7 EP7TXTOG Transmits logical Endpoint n data toggle bit set/status
.
r
o
s
.
f
e 2
l e a I - R
P
Re Pi B
a n a .
n
Ba
.
.
r
o
2 EP2TXTOG
s e f
2
Transmits logical Endpoint n data toggle bit set/status
a R
l e I -
bit is high, the bit may be written with the required setting of the data toggle. Ifthe
P
Re Pi B
.
a n a
n
Ba
MT7623N
f o r
1 EP1TXTOG
e a s e - R 2
Transmits logical Endpoint n data toggle bit set/status
I
l
bit is high, the bit may be written with the required setting of the data toggle. If he enable
Re Pi B
.
P
is low, any value written will be ignored

a n a 1'b1: Logical Endpoint n TX data toggle bit = 1
12.4.26 Ba n
Tx Data Toggle Enable Register
0086 TXTOGEN Tx Data Toggle Enable Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name EP8TX EP7TX EP6TX EP5TX EP4TX EP3TX EP2TX EP1TX
TOGE TOGE TOGE TOGE TOGE TOGE TOGE TOGE
N N N N N N N N
Reset 0 0 0 0 0 0 0 0
Bit(s)
8
Name
EP8TXTOGEN
f o r
Description
Receives logical Endpoint 1 data toggle bit enabling
e a s e 2
R
I -
7 EP7TXTOGEN
l
Re Pi B P
a
n
6 EP6TXTOGEN
n a Receives logical Endpoint 1 data toggle bit enabling
Ba
5 EP5TXTOGEN Receives logical Endpoint 1 data toggle bit enabling
f r
o
2 EP2TXTOGEN
e a s e - 2
R
I
l
1 EP1TXTOGEN
Re Pi B P
a n a
n
Ba
MT7623N
f o r
e a s e - 2
R
I
l
Re Pi B P
a n a
12.4.27
000000A0
Bit 31
USB_L1INTS
30 Ba
29
n
USB Level 1 Interrupt Status Register(Word Access)
28
USB Level 1 Interrupt Status Register
27 26 25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name POWE DRVV VBUS
IDDIG DPDM QHIF_ PSR_I DMA_I USBC
RDWN BUS_I VALID QINT_ RX_IN TX_IN
_INT_ _INT_ INT_S NT_S NT_S OM_IN
_INT_ NT_S _INT_ STAT T_STA T_STA
STAT STAT TATU TATU TATU T_STA
STAT TATU STAT US TUS TUS
US US S S S TUS
US S US
Type RU RU RU RU RU RU RU RU RU RU RU RU
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
f o r
Description
11
US
a s e - 2
POWERDWN_INT_STAT Power -down interrupt status
R
When controller is in the host suspend mode, VBus will be valid, DP asserted, and this
e I
l
bit set. When the controller is in the peripheral mode, Avalid will be set, DP asserted,
10
Re Pi B P
and this bit set. When the controller is in the idle state, Avalid will be de-asserted,
linestate in SE0, and this bit set.
DRVVBUS_INT_STATUS DRVVBUS interrupt status
This bit shows the interrupt trigger status of DRVVBUS. The trigger polarity is
a n a
determined by DRVVBUS_INT_POL.
This interrupt is used in USB OTG charge pump control.
9
8
IDDIG_INT_STATUS
Ba
VBUSVALID_INT_STAT
n IDDIG interrupt status
This bit shows the interrupt trigger status of IDDIG. The trigger polarity is determined by
IDDIG_INT_POL.
This interrupt is used in USB OTG attachment.
VBUSVALID interrupt status
US This bit shows the interrupt trigger status of VBUSVALID. The trigger polarity is
determined by VBUSVALID_INT_POL.
This interrupt is used in USB attachment to host.
7 DPDM_INT_STATUS DPDM interrupt status
This bit shows the interrupt trigger status of DPDM. The trigger condition is whether DP
or DM goes high.
This interrupt is used in USB HOST mode to detect device attachment.
6 QHIF_INT_STATUS USBQ HIF command interrupt status
Only valid while WiMAX Q is available.
5 QINT_STATUS
o r
USBQ interrupt status
f
Only valid while USBQ is available.
4
3
PSR_INT_STATUS
DMA_INT_STATUS
e a s e - 2
Packet sequence recorder interrupt status
R
DMA interrupt status
I
l
2 USBCOM_INT_STATUS USB common interrupt status
1
0
RX_INT_STATUS
TX_INT_STATUS
Re Pi B P
Endpoint Rx interrupt status
Endpoint Tx interrupt status
a n a
n
Ba
MT7623N
f o r
e a s e I - 2
USB Level 1 interrupt status register. The USB interrupt will be fired only the mapped status and mask
R
are all set. The status is read -only since SW need to clear it on the Level 2 register.
12.4.28
l
Re Pi B P
USB Level 1 Interrupt Mask Register(Word Access)
000000A4 USB_L1INTM
a n a USB Level 1 Interrupt Mask Register 00000000

Bit
Name
Type
Reset
Bit
31
15
30
14
29
Ba
13
n 28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0
Name POWE DRVV
IDDIG
VBUS
DPDM QHIF_ PSR_I DMA_I USBC
RDWN BUS_I VALID QINT_ RX_IN TX_IN
_INT_ _INT_ INT_U NT_U NT_U OM_IN
_INT_ NT_U _INT_ UNMA T_UN T_UN
UNMA UNMA NMAS NMAS NMAS T_UN
UNMA NMAS UNMA SK MASK MASK
SK SK K K K MASK
SK K SK
Type RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0

11 POWERDWN_INT_UNM Unmasks POWERDWN interrupt
ASK
o r
1'b0: Mask interrupt
f
1'b1: Unmask interrupt
10
e a e
I - R
2
DRVVBUS_INT_UNMAS Unmasks DRVVBUS interrupt
K
s
9
8
IDDIG_INT_UNMASK
l
Re Pi B P
Unmasks IDDIG interrupt
VBUSVALID_INT_UNMA Unmasks VBUSVALID interrupt
SK
n a
a
n
7 DPDM_INT_UNMASK Unmasks DPDM interrupt
Ba
6 QHIF_INT_UNMASK Unmasks USBQ HIF command interrupt,
Only valid while WiMAX Q is available.
5 QINT_UNMASK Unmasks USBQ interrupt,
Only valid while USBQ is available
4 PSR_INT_UNMASK Unmasks packet sequence recorder interrupt
r
3 DMA_INT_UNMASK Unmasks DMA interrupt
f o
e 2
s
2 USBCOM_INT_UNMASK Unmasks USB common interrupt
l e a I -
R
P
Re Pi B
1 RX_INT_UNMASK Unmasks Endpoint Rx interrupt
a
0 TX_INT_UNMASK Unmasks Endpoint Tx interrupt
Ba
MT7623N
f o r
e a s e - 2
R
I
l
Re Pi B P
USB Level 1 interrupt unmask register. The interrupt will be fired only when unmask and status are
both 1.
a n a
12.4.29
000000A8
Bit
Name
31 30
Ba
USB_L1INTP
29
n
USB Level 1 Interrupt Polarity Register(Word Access)
28
USB Level 1 Interrupt Polarity Register
27 26 25 24 23 22 21 20 19 18
00000200
17 16
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name POWE DRVV VBUS
IDDIG
RDWN BUS_I VALID
_INT_
_INT_ NT_P _INT_
POL
POL OL POL
Type RW RW RW RW
Reset 0 0 1 0
Bit(s)
11
Name
POWERDWN_INT_POL
o r
Description
f
POWERDWN interrupt polarity
e a s e 2
1'b0: Interrupt trigger when POWERDWN is 1.
R
1'b1: Interrupt trigger when POWERDWN is 0.
I -
l
10 DRVVBUS_INT_POL DRVVBUS interrupt polarity
9 IDDIG_INT_POL
Re Pi B P
1'b0: Interrupt trigger when DRVVBUS is 1.
1'b1: Interrupt trigger when DRVVBUS is 0.
IDDIG interrupt polarity
a
1'b0: Interrupt trigger when IDDIG is 1.
n
1'b1: Interrupt trigger when IDDIG is 0.
8 VBUSVALID_INT_POL
n a VBUSVALID interrupt polarity
Ba
1'b0: Interrupt trigger when VBUSVALID is 1.
1'b1: Interrupt trigger when VBUSVALID is 0.
USB Level 1 interrupt polarity register. The interrupt polarity is configured in this register.
12.4.30 USB Level 1 Interrupt Control Register(Word Access)

000000AC USB_L1INTC USB Level 1 Interrupt Control Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit
Name
15 14 13 12 11
f o r 10 9 8 7 6 5 4 3 2 1 0
USB_I
e
NT_S
Type
Reset
l e a s I - R 2 YNC
RW
0
Bit(s)
0
Name
USB_INT_SYNC
Re Pi B P
Description
USB interrupt synchronization
a n a
n
Ba
MT7623N
f o r
e a s e - 2
1'b0: USB output interrupt is output directly.
R
1'b1: USB output interrupt is synchronized by MCU BUS clock registers.
I
l
Re Pi B
USB Level 1 interrupt control register.
P
12.4.31
n a
EP0 Control Status Register
a
12.4.31.1 Peripheral Mode
0102
Bit 15
CSR0_PERI
14
Ba
13
n 12
EP0 Control Status Register
11 10 9 8 7 6 5 4 3 2 1
0000
0
Name SERVI SERVI
FLUS CESE CEDR SEND SETU DATA SENT TXPK RXPK
HFIFO TUPE XPKT STALL PEND END STALL TRDY TRDY
DN RDY
Type A0 A0 A0 A0 RU A0 RW A0 RU
Reset 0 0 0 0 0 0 0 0 0

8 FLUSHFIFO The CPU writes a 1 to this bit to flush the next packet to be transmitted/read from the
f r
Endpoint 0 FIFO. Cleared automatically. The FIFO pointer is reset and the
o
TxPktRdy/RxPktRdy bit (below) is cleared. May be set simultaneously with TxPktRdy to
abort the packet that is currently being loaded into FIFO.
e a s e 2
Note: FlushFIFO should only be used when TxPktRdy/RxPktRdy is set. At other times, it
R
may cause data corruption.
I -
l
7 SERVICESETUPEDN The CPU writes 1 to this bit to clear the SetupEnd bit. Cleared automatically.
6
5
SERVICEDRXPKTRDY
SENDSTALL
Re Pi B P
The CPU writes 1 to this bit to clear the RxPktRdy bit. Cleared automatically.
The CPU writes 1 to this bit to terminate the current transaction. The STALL handshake
will be transmitted and then this bit will be cleared automatically. Note: FIFO should be
a
flushed before SendStall is set.
4 SETUPEND
n a n This bit will be set when a control transaction ends before the DataEnd bit has been set.
An interrupt will be generated and FIFO flushed at this time. Cleared by the CPU by
writing 1 to the ServicedSetupEnd bit.
Ba
3 DATAEND The CPU sets up this bit: When setting up TxPktRdy for the last data packet. When
clearing RxPktRdy after unloading the last data packet. When setting TxPktRdy for a
zero length data packet. Cleared automatically
2 SENTSTALL Set when a STALL handshake is transmitted. The CPU should clear this bit.
Write 0 to clear.
1 TXPKTRDY The CPU sets up this bit after loading a data packet into FIFO. Cleared automatically
when a data packet has been transmitted. An interrupt is also generated at this point (if
enabled).
0 RXPKTRDY Set when a data packet has been received. An interrupt is generated when this bit is
set. The CPU clears this bit by setting up the ServicedRxPktRdy bit.
12.4.31.2 Host Mode

0102 CSR0_HOST
f o r
EP0 Control Status Register 0000
Bit
Name
15 14 13 12
e
11
a s
DISPI
e 10
I - R 2 9 8
FLUS
7
NAKTI STAT
6 5 4
REQP ERRO SETU RXST TXPK RXPK
3 2 1 0
l
MEOU USPK
P
NG HFIFO KT R PPKT ALL TRDY TRDY
Re Pi B
T T
Type RW A0 A1 RW RW A1 A1 A1 A0 A1
Reset 0 0 0 0 0 0 0 0 0 0
a n a
n
B a
MT7623N
f o r
Bit(s)
11
Name
DISPING
e a s e
Description
I - R 2
The CPU writes 1 to this bit to disable transmitting PING token.
l
Re Pi B P
This bit can be set together with TXPKTRDY.
To clear DISPING function, SW writes 0 after each control transfer is done. The DisPing
function will be cleared when the next SETUP transaction is finished or OUT transaction
receives handshake token with NAK/NYET/Timeout.
a
Read "1" only in USB11 configuration.
n
Token PING is not supported in FS mode. USB2.0 IP for TX only.
8 FLUSHFIFO
n a The CPU writes 1 to this bit to flush the next packet to be transmitted/read from the
Endpoint 0 FIFO. Cleared automatically. The FIFO pointer is reset and the
Ba
TxPktRdy/RxPktRdy bit (below) is cleared. May be set simultaneously with TxPktRdy to
abort the packet that is currently being loaded into FIFO.
Note: FlushFIFO should only be used when TxPktRdy/RxPktRdy is set. At other times, it
may cause data corruption.
7 NAKTIMEOUT This bit will be set when Endpoint 0 is halted following the receipt of NAK responses for
longer than the time set by the NAKLimit0 register. The CPU clears this bit to allow the
endpoint to continue.
Write 0 to clear.
6 STATUSPKT The CPU sets up this bit at the same time as the TxPktRdy or ReqPkt bit is set, to
perform a status stage transaction. Setting up this bit ensures that the data toggle is set
to 1 so that a DATA1 packet is used for the status stage transaction.
5 REQPKT The CPU writes 1 to this bit to request an IN transaction. Cleared when RxPktRdy is set.
4 ERROR This bit will be set when three attempts have been made to perform a transaction with
no response from the peripheral. Cleared by the CPU. An interrupt is generated when
f o r
this bit is set.
Write 0 to clear.
e
3 SETUPPKT The CPU sets up this bit, at the same time as the TxPktRdy bit is set, to send a SETUP
l e a s - 2
token instead of an OUT token for the transaction.
R
This bit will be automatically clear by HW when the setup packet is transmitted.
I
Note: Setting up this bit will also clear DataToggle.
2
1
RXSTALL
TXPKTRDY
Re Pi B P
This bit will be set when a STALL handshake is received. The CPU should clear this bit.
Write 0 to clear.
The CPU sets up this bit after loading a data packet into the FIFO. Cleared
a n a automatically when a data packet has been transmitted. An interrupt is also generated
at this point (if enabled)
n
0 RXPKTRDY This bit is set when a data packet has been received. An interrupt is generated when
Ba
this bit is set. The CPU clears this bit by setting up the ServicedRxPktRdy bit.
Write 0 to clear.
12.4.32 EP0 Received bytes Register

0108 COUNT0 EP0 Received bytes Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name EP0_RX_COUNT
Type RU
Reset 0 0 0 0 0 0 0
r
6:0 EP0_RX_COUNT
f o
COUNT0 is a 7-bit read-only register that indicates the number of received data bytes in
the Endpoint 0 FIFO. The value returned changes as the contents of FIFO change and
e 2
s
is only valid while RxPktRdy (IDXEPR0.CSR0.bit0) is set.
l e a P I - R
Re Pi B
12.4.33 NAK Limit Register
10B NAKLIMT0 NAK Limit Register 00
a n a
n
Ba
MT7623N
f o r
Bit
Name
15 14 13 12
e a s e 11
I - R 2
10 9 8 7 6 5 4 3 2
NAKLIMIT0
1 0
l
Type RW
Reset
Bit(s) Name
Re Pi B P
Description
0 0 0 0 0
4:0 NAKLIMIT0
a n a (For host mode only) NAKLimit0 is a 5-bit register that sets up the number of
frames/microframes (high-speed transfers) after which Endpoint 0 should timeout on
n
receiving a stream of NAK responses. (Equivalent settings for other endpoints can be
Ba
made through their TxInterval and RxInterval registers.). The number of
frames/microframes selected is 2(m-1) (where m is the value set in the register, valid
values 2 - 16). If the host receives NAK responses from the target for more frames than
the number represented by the limit set in this register, the endpoint will be halted.
Note: Value of 0 or 1 disables the NAK timeout function.
12.4.34 CONFIGDATA
10F CONFIGDATA Core Configuration Register 1F
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name UTMI
DYNFI
MPRX MPTX BIGEN HBRX HBTX SOFT DATA
FOSIZI
r
E E DIAN E E CONE WIDT
NG
o
H
Type
Reset
s e f 2
RO
0
RO
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
1
Bit(s) Name
l e a I - R
Description
P
Re Pi B
7 MPRXE When set to 1, automatic amalgamation of bulk packets is selected.
6 MPTXE When set to 1, automatic splitting of bulk packets is selected.
5 BIGENDIAN Set to 1 indicates big-endian ordering is selected.
4
3
HBRXE
HBTXE
a n a Set to 1 indicates High-bandwidth Rx ISO endpoint support selected.

Set to 1 indicates High-bandwidth Tx ISO endpoint support selected.
2
1
0
DYNFIFOSIZING
SOFTCONE
UTMIDATAWIDTH
Ba n Set to 1 indicates dynamic FIFO sizing option is selected.
Set to 1 indicates soft connection/disconnection option is selected.
Indicates selected UTMI+ data width
1'b0: 8 bits
1'b1: 16 bits
12.4.35 TXMAP Register

0110 TX1MAP TX1MAP Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name M1 MAXIMUM_PAYLOAD_TRANSACTION
Type RW RW
Reset 0
f
0
o r 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
12:11
Name
M1
e a s e
Description
- R 2
Maxmum payload size for indexed TX endpoint , M1 packet multiplier m maximum
I
l
payload transaction register
10:0
RANSACTION
Re Pi B P
MAXIMUM_PAYLOAD_T The TxMaxP register defines the maximum amount of data that can be transferred
through the selected Tx endpoint in asingle operation. There is a TxMaxP register for
each Tx endpoint (except for Endpoint 0).Bits 10:0 define (in bytes) the maximum
payload transmitted in a single transaction. The value set can be up to 1024 bytes but is
a n a
n
Ba
MT7623N
f o r
e a s e - 2
subject to the constraints placed by the USB specification on packet sizes for Bulk,
R
Interrupt and Isochronous transfers in Fullspeed and High speed operation.
I
l
Re Pi B P
Where the option of High-bandwidth Isochronous endpoints or of packet splitting on Bulk
endpoints has been taken when the core is configured, the register includes either 2 or 5
further bits that define a multiplier m which is equal to one more than the value
recorded. In the case of Bulk endpoints with the packet splitting option enabled, the
a
multiplier m can be up to 32 and defines the maximum number of the USB packets (i.e.
n
packets for transmission over the USB) of the specified payload into which a single data
n a packet placed in FIFO should be split, prior to transfer. (If the packet splitting option is
not enabled, bit15-13 will not be implemented and bit12-11(if included) will be ignored.)
Ba
The data packet is required to be an exact multiple of the payload specified by bits 10:0,
which is itself required to be either 8, 16, 32, 64 or (in the case of High Speed transfers)
512 bytes. For Isochronous endpoints operating in high-speed mode and with the high-
bandwidth option enabled, m may only be either 2 or 3 (corresponding to bit 11 set or bit
12 set, respectively) and it specifies the maximum number of such transactions that can
take place in a single microframe. If either bit 11 or bit 12 is non-zero, the USB2.0
controller will automatically split any data packet written to FIFO into up to 2 or 3 USB
packets, each containing the specified payload (or less). The maximum payload for
each transaction is 1,024 bytes, so this allows up to 3072 bytes to be transmitted in
each microframe. (For Isochronous/Interrupt transfers in full-speed mode, bits 11 and 12
are ignored.) The value written to bits 10:0 (multiplied by m in the case of high-
bandwidth Isochronous transfers) must match the value given in the wMaxPacketSize
field of the standard endpoint descriptor for the associated endpoint (see USB
Specification Revision 2.0, Chapter 9). A mismatch can cause unexpected results.The
total amount of data represented by the value written to this register (specified payload *
m) must not exceed the FIFO size for the Tx endpoint and should not exceed half the
r
FIFO size if double-buffering is required.If this register is changed after packets have
f o
been sent from the endpoint, the Tx endpoint FIFO should be completely flushed (using
the FlushFIFO bit in TxCSR) after writing the new value to this register.
e 2
l e a s I - R
P
12.4.36 Tx CSR Register

Re Pi B
0112
n a
TX1CSR_PERI Tx1 CSR Register
a
0000
Bit
Name
15
AUTO
SET
14
ISO Ba
13
n 12
DMAR
EQEN
11
FRCD DMAR
ATAT EQMO
OG DE
10 9 8
SETT
XPKT
RDY_
TWIC
INCO
MPTX
7
CLRD
ATAT
OG
6 5
SENT SEND FLUS UNDE

STALL STALL HFIFO RRUN
4
FIFON
OTEM
PTY
3
TXPK
TRDY
2 1 0
E
Type RW RW RW RW RW A1 A1 A0 A1 RW A0 A1 RU A0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 AUTOSET If the CPU sets up this bit, TxPktRdy will be automatically set when data of the
maximum packet size (value in TxMaxP) are loaded into TxFIFO. If a packet of smaller
than the maximum packet size is loaded, TxPktRdy will have to be set manually.
r
14 ISO The CPU sets up this bit to enable the Tx endpoint for Isochronous transfers and clears
o
it to enable the Tx endpoint for Bulk or Interrupt transfers. Note: This bit only takes effect
12 DMAREQEN
s e f
in the peripheral mode. In the host mode, it always returns to 0.
The CPU sets up this bit to enable the DMA request for the Tx endpoint.
2
a R
11 FRCDATATOG The CPU sets up this bit to force the endpoint data toggle to switch and the data packet
l e I -
to be cleared from the FIFO, regardless of whether an ACK is received. This can be
P
used by Interrupt Tx endpoints that are used to communicate rate feedback for
Re Pi B
Isochronous endpoints.
10 DMAREQMODE The CPU sets up this bit to select DMA request mode 1 and clears it to select DMA
request mode 0.Note: This bit must not be cleared either before or in the same cycle as
a
the DMAReqEn bit is cleared.
Ba
MT7623N
f o r
8
7
SETTXPKTRDY_TWICE
INCOMPTX
e a s e I - 2
Indicates TxPktRdy had been set while it is 1'b1 already. Write 0 to clear.
R
When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this
l
Re Pi B P
bit is set to indicate where a large packet has been split into 2 or 3 packets for
transmission but insufficient IN tokens have been received to send all the parts.
Note: In anything other than a high-bandwidth transfer, this bit will always return to 0.
Write 0 to clear.
6
5
CLRDATATOG
SENTSTALL
a n a The CPU writes 1 to this bit to reset the endpoint data toggle to 0.
This bit is set when a STALL handshake is transmitted. FIFO is flushed and Tx interrupt
n
generated if enabled and the TxPktRdy bit is cleared. The CPU clears this bit.
Ba
Write 0 to clear.
4 SENDSTALL The CPU writes 1 to this bit to issue a STALL handshake to an IN token. The CPU
clears this bit to terminate the stall condition. Note: This bit has no effect where the
endpoint is being used for Isochronous transfers. Otherwise, CPU should wait
SENTSTALL interrupt generated before clearning the SENDSTALL bit.
3 FLUSHFIFO The CPU writes 1 to this bit to flush the latest packet from the endpoint TxFIFO. The
FIFO pointer is reset, the TxPktRdy bit is cleared and an interrupt is generated. May be
set simultaneously with TxPktRdy to abort the packet that is currently loaded into FIFO.
Note: FlushFIFO should only be used when TxPktRdy is set. At other times, it may
cause data corruption. If FIFO is double-buffered, FlushFIFO may need to be set twice
to ompletely clear FIFO.
2 UNDERRUN The USB sets up this bit if an IN token is received when the TxPktRdy bit not set. The
CPU clears this bit (writing 0 to it).
1 FIFONOTEMPTY The USB sets up this bit when there is at least 1 packet in TxFIFO. This bit will assert
r
automatically when TXPKTRDY is set by CPU and de-assert when CPU flushes FIFO or
o
sends a STALL packet.
0 TXPKTRDY
s e f
The CPU sets up this bit after loading a data packet into FIFO. Cleared automatically
2
R
enabled). TxPktRdy is also automatically cleared (interrupt is generated) prior to loading
l e a I -
a second packet into a double-buffered FIFO.
P
12.4.36.2 Host Mode
Re Pi B
0112
n a
TX1CSR_HOST Tx1 CSR Register
a
0000
n
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Ba
Name SETT NAKTI
FRCD DMAR XPKT MEOU CLRD FIFON
AUTO DMAR RXST FLUS ERRO TXPK
ATAT EQMO RDY_ T_INC ATAO OTEM
SET EQEN ALL HFIFO R TRDY
OG DE TWIC OMPT G PTY
E X
Type RW RW RW RW A1 A1 A0 A1 A0 A1 RU A0
Reset 0 0 0 0 0 0 0 0 0 0 0 0

15 AUTOSET If the CPU sets up this bit, TxPktRdy will be automatically set when data of the
maximum packet size (value in TxMaxP) are loaded into TxFIFO. If a packet of smaller
than the maximum packet size is loaded, then TxPktRdy will have to be set manually.
12 DMAREQEN The CPU sets up this bit to enable the DMA request for the Tx endpoint.
11 FRCDATATOG The CPU sets up this bit to force the endpoint data toggle to switch and the data packet
f r
to be cleared from FIFO, regardless of whether an ACK is received. This can be used by
o
Interrupt Tx endpoints that are used to communicate rate feedback for Isochronous
endpoints.
10 DMAREQMODE
e a s e - R 2
The CPU sets up this bit to select DMA request mode 1 and clears it to select DMA
request mode 0.Note: This bit must not be cleared either before or in the same cycle as
I
l
the DMAReqEn bit is cleared.
8
7
SETTXPKTRDY_TWICE
NAKTIMEOUT_INCOMP
TX
Re Pi B P
This bit indicates TxPktRdy has been set while it is 1'b1 already. Write 0 to clear.
Bulk endpoints only: This bit will be set when the Tx endpoint is halted following the
receipt of NAK responses for longer than the time set as the NAK Limit by the TxInterval
register. The CPU clears this bit to allow the endpoint to continue.Write 0 to clear.
a n a
n
Ba
MT7623N
f o r
6
5
CLRDATAOG
RXSTALL
e a s e I - 2
The CPU writes 1 to this bit to reset the endpoint data toggle to 0.
R
This bit is set when a STALL handshake is received. When this bit is set, any DMA
l
Re Pi B P
request that is in progress is topped, FIFO is completely flushed, Tx interrupt is
generated if enabled and the TxPktRdy bit is cleared (see below). The CPU clears this
bit.
Write 0 to clear.
a
3 FLUSHFIFO The CPU writes 1 to this bit to flush the latest packet from the endpoint TxFIFO. The
n
FIFO pointer is reset, the TxPktRdy bit is cleared and an interrupt is generated. May be
a
set simultaneously with TxPktRdy to abort the packet that is currently loaded into FIFO.
2 ERROR
Ba n Note: FlushFIFO should only be used when TxPktRdy is set. At other times, it may
cause data corruption. If FIFO is double-buffered, FlushFIFO may need to be set twice
to ompletely clear FIFO.
The USB sets up this bit when 3 attempts have been made to send a packet and no
handshake packet has been received. When the bit is set, an interrupt will be
generated, TxPktRdy cleared and FIFO completely flushed. The CPU clears this bit.
Valid only when the endpoint is operating in Bulk or Interrupt mode.
Write 0 to clear.
1 FIFONOTEMPTY The USB sets up this bit when there is at least 1 packet in TxFIFO. This bit will assert
automatically when TXPKTRDY is set by CPU and de-assert when CPU flush FIFO or
send a STALL packet.
0 TXPKTRDY The CPU sets up this bit after loading a data packet into FIFO. It is cleared automatically
enabled). TxPktRdy is also automatically cleared (interrupt is generated) prior to loading
a second packet into a double-buffered FIFO.
f o r
12.4.37
0114
RXMAP Register
RX1MAP
e a s e I - R 2
RX1MAP Register 0000
Bit
Name
Type
Reset
15 14 13
l
Re Pi B
12
0
M1
RW P11
0
10
0
9
0
8
0
7 6 5
MAXIMUM_PAYLOAD_TRANSACTION
0 0
RW
0 0 0 0
4 3 2 1
0
0
a n a
n
Ba
12:11 M1 Maxmum payload size for indexed RX endpoint , M1 packet multiplier m
10:0 MAXIMUM_PAYLOAD_T The RxMaxP register defines the maximum amount of data that can be transferred
RANSACTION through the selected Rx endpoint in a single operation. There is a RxMaxP register for
each Rx endpoint (except for Endpoint 0).Bits 10:0 define (in bytes) the maximum
payload transmitted in a single transaction. The value set can be up to 1,024 bytes but
is subject to the constraints placed by the USB specification on packet sizes for Bulk,
Interrupt and Isochronous transfers in full-speed and high-speed operations.
Where the option of high-bandwidth Isochronous endpoints or of combining Bulk
packets has been taken when the core is configured, the register includes either 2 or 5
further bits that define a multiplier m which is equal to one more than the value
recorded.
For Bulk endpoints with the packet combining option enabled, the multiplier m can be up
to 32 and defines the number of USB packets of the specified payload which are to be
combined into a single data packet within the FIFO. (If the packet splitting option is not
enabled, bit15-bit13 will not be implemented and bit12-bit11 (if included) will be
r
ignored.) For Isochronous endpoints operating in high-speed mode and with the high-
o
bandwidth option enabled, m may only be either 2 or 3 (corresponding to bit 11 set or bit
f
12 set, respectively) and it specifies the maximum number of such transactions that can
e
take place in a single microframe. If either bit 11 or bit 12 is non-zero, the USB2.0
s 2
controller will automatically combine the separate USB packets received in any
a - R
microframe into a single packet within the Rx FIFO. The maximum payload for each
l e I
transaction is 1024 bytes, so this allows up to 3072 bytes to be received in each
Re Pi B P
microframe.
(For Isochronous/Interrupt transfers in full-speed mode or if high-bandwidth is not
enabled, bits 11 and 12 will be ignored.) The value written to bits 10:0 (multiplied by m in
the case of high-bandwidth Isochronous transfers) must match the value given in the
wMaxPacketSize field of the standard endpoint descriptor for the associated endpoint
a n a
n
Ba
MT7623N
f o r
e a s e
results.
I - 2
(see USB Specification Revision 2.0, Chapter 9). A mismatch could cause unexpected
R
l
The total amount of data represented by the value written to this register (specified
Re Pi B P
payload * m) must not exceed the FIFO size for the OUT endpoint, and should not
exceed half the FIFO size if double-buffering is required.
12.4.38 RX CSR Register
a n a
0116
Bit 15 14 Ba
13
n
RX1CSR_PERI RX1 CSR Register
12 11 10 9 8 7 6 5 4 3 2 1
0000
0
Name KEEP
AUTO DISNY DMAR CLRD
DMAR ERRS INCO SENT SEND FLUS DATA OVER FIFOF RXPK
CLEA ISO ET_PI EQMO TATO
EQEN TATU MPRX STALL STALL HFIFO ERR RUN ULL TRDY
R DERR DE G
S
Type RW RW RW RW RW RW A1 A0 A1 RW A0 RU A1 RU A1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 AUTOCLEAR If the CPU sets up this bit then the RxPktRdy bit will be automatically cleared when a
f r
packet of RxMaxP bytes has been unloaded from the RxFIFO. When packets of smaller
o
than the maximum packet size are unloaded, RxPktRdy will have to be cleared
manually.
e a s e 2
Note: The maximum packet size-3,-2,-1 is just handled like the maximum packet size
R
which is auto cleared by hardware.
I -
l
14 ISO The CPU sets up this bit to enable the Rx endpoint for Isochronous transfers and clears
13
12
DMAREQEN
DISNYET_PIDERR
Re Pi B P
it to enable the Rx endpoint for Bulk/Interrupt transfers.
The CPU sets up this bit to enable the DMA request for the Rx endpoint.
The CPU sets up this bit to disable the sending of NYET handshakes. When set, all
a
successfully received Rx packets are ACK'd including at the point at which the RxFIFO
n
becomes full. Note: This bit only has any effect in High-speed mode, in which mode it
a
should be set for all interrupt endpoint.
n
This bit is set when there is a PID error in the received packet. It is cleared when
Ba
RxPktRdy is cleared or write 0 to clear.
request mode 0. DMA request mode 1: Rx endpoint interrupt is generated only when
DMA request mode 1 and receiving a short packet. RxDMAReq is generated when
receiving a Max-Packet-size packet.DMA request mode 0: No Rx endpoint interrupt.
RxDMAReq is generated when RxPktRdy is set.
9 KEEPERRSTATUS This bit is used when endpoint working with USBQ and in ISOCHRONOUS mode.
When this bit is set, the isochronous error, PIDERROR, INCOMPRX and DATAERROR
will be kept and only cleared by SW.
8 INCOMPRX This bit is set in a Isochronous transfer if the packet in the RxFIFO is incomplete
because parts of the data are not received. Cleared when RxPktRdy is cleared or write
0 to clear it.
Note: In anything other than a high-bandwidth transfer, this bit will always return to 0.
Write 0 to clear.
r
7 CLRDTATOG The CPU writes 1 to this bit to reset the endpoint data toggle to 0.
6 SENTSTALL
f o
This bit is set when a STALL handshake is transmitted. The CPU clears this bit. An
e
interrupt is generated when the bit is set.
2
s
Write 0 to clear.
5 SENDSTALL
l e a - R
The CPU writes 1 to this bit to issue a STALL handshake. The CPU clears this bit to
I
terminate the stall condition. Note: This bit has no effect where the endpoint is used for
P
Re Pi B
ISO transfers.
4 FLUSHFIFO The CPU writes 1 to this bit to flush the next packet to be read from the endpoint
RxFIFO. The RxFIFO pointer is reset and the RxPktRdy bit is cleared. Note: FlushFIFO
should only be used when RxPktRdy is set. At other times, it may cause data corruption.
a n a If RxFIFO is double buffered, FlushFIFO may need to be set twice to completely clear
n
Ba
MT7623N
f o r
3 DATAERR
e a s e
RxFIFO.
- R 2
This bit is set when RxPktRdy is set if the data packet has a CRC or bit-stuff error.
I
l
Cleared when RxPktRdy is cleared. Note: This bit is only valid when the endpoint is
2 OVERRUN
Re Pi B P
operating in the ISO mode. In the bulk mode, it always returns to 0.
This bit is set if an OUT packet cannot be loaded into RxFIFO. The CPU clears this bit
(writing 0 to it).
a
Note: This bit is only valid when the endpoint is operating in the ISO mode. In the bulk
n
mode, it always returns to 0. The new incoming packet will not be written to RxFIFO.
1 FIFOFULL
n a This bit is set when no more packets can be loaded into RxFIFO.
Ba
0 RXPKTRDY This bit is set when a data packet has been received (to RxFIFO). The CPU clears this
bit when the packet has been unloaded from RxFIFO. An interrupt will be generated
when the bit is set.
Write 0 to clear.
12.4.38.2 Host Mode

0116 RX1CSR_HOST Rx1 CSR Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SETR KEEP
DATA
AUTO DMAR DMAR CLRD ERR_
AUTO PIDER EQPK ERRS INCO RXST REQP FLUS ERRO FIFOF RXPK
CLEA EQEN EQMO ATAT NAKTI
REQ ROR T_TWI TATU MPRX ALL KT HFIFO R ULL TRDY
R AB DE OG MEOU
r
CE S
T
Type
Reset
RW
0
RW
0
RW
0
RU
0
RW
0
A1
0
RW
e
0
f oA1
0
A0
0
2
A1
0
RW
0
A0
0
A1
0
A1
0
RU
0
A1
0
Bit(s) Name
l e a s I - R
Description
15 AUTOCLEAR
Re Pi B P
If the CPU sets up this bit then the RxPktRdy bit will be automatically cleared when a
packet of RxMaxP bytes has been unloaded from RxFIFO. When packets of smaller
than the maximum packet size are unloaded, RxPktRdy will have to be cleared
manually.
a n a Note: The maximum packet size-3,-2,-1 is just handled like the maximum packet size
which is auto cleared by hardware.
n
14 AUTOREQ If the CPU sets this bit, the ReqPkt bit will be automatically set when the RxPktRdy bit is
Ba
cleared. Note: This bit is automatically cleared when a short packet is received.
13 DMAREQENAB The CPU sets up this bit to enable the DMA request for the Rx endpoint.
12 PIDERROR ISO transactions only: The core sets up this bit to indicate a PID error in the received
packet. Bulk/Interrupt transactions: The setting of this bit is ignored.
Write 0 to clear.
Note: This register is read -only in the ISO mode but reserved for read/write access in
other modes.
request mode 0. DMA request mode 1: Rx endpoint interrupt is generated only when
DMA request mode 1 and received a short packet. RxDMAReq is generated when
receiving a Max-Packet-size packet.DMA request mode 0: No Rx endpoint interrupt.
RxDMAReq is generated when RxPktRdy is set.
10 SETREQPKT_TWICE Indicates the ReqPkt had been set while it is 1 already. Write 0 to clear.
9 KEEPERRSTATUS Used when the endpoint working with USBQ and in the isochronous mode. When this
f o r
bit is set, the isochronous error, PIDERROR, INCOMPRX and DATAERROR will be
kept and only cleared by SW.
e
8 INCOMPRX This bit is set in a Isochronous transfer if the packet in the RxFIFO is incomplete
s 2
because parts of the data are not received. Cleared when RxPktRdy is cleared or write
a R
0 to clear. Note: In anything other than a high-bandwidth transfer, this bit will always
l e I -
return to 0.
P
Re Pi B
7 CLRDATATOG The CPU writes 1 to this bit to reset the endpoint data toggle to 0.
6 RXSTALL When a STALL handshake is received, this bit will be set and an interrupt generated.
The CPU clears this bit.
Write 0 to clear.
a n a
n
Ba
MT7623N
f o r
5
4
REQPKT
FLUSHFIFO
e a s e I - 2
The CPU writes 1 to this bit to request an IN transaction. Cleared when RxPktRdy is set.
R
The CPU writes 1 to this bit to flush the next packet to be read from the endpoint
l
Re Pi B P
RxFIFO. The RxFIFO pointer is reset and the RxPktRdy bit is cleared. Note: FlushFIFO
should only be used when RxPktRdy is set. At other times, it may cause data to be
corrupted. Also note that, if the RxFIFO is double buffered, FlushFIFO may need to be
set twice to completely clear the RxFIFO.
a
3 DATAERR_NAKTIMEOU In the bulk mode, this bit will be set when the Rx endpoint is halted following the receipt
n
T of NAK responses for longer than the time set as the NAK Limit by the RxInterval
a
register. The CPU clears this bit to allow endpoint to continue.Write 0 to clear.
n
When operating in the ISO mode, this bit is set when RxPktRdy is set if the data packet
Ba
has a CRC or bit-stuff error and cleared when RxPktRdy is cleared.
2 ERROR The USB sets up this bit when 3 attempts have been made to receive a packet and no
data packet has been received.The CPU clears this bit. An interrupt will be generated
Note: This bit is only valid when the Rx endpoint is operating in the bulk or interrupt
mode. In the ISO mode, it always returns to 0.
Write 0 to clear.
1 FIFOFULL This bit is set when no more packets can be loaded into the RxFIFO.
0 RXPKTRDY This bit is set when a data packet has been received (to RxFIFO). The CPU clears this
bit when the packet has been unloaded from RxFIFO. An interrupt will be generated
Write 0 to clear.
12.4.39 Rx Count Register
f o r
0118
Bit 15
RX1COUNT
14 13
e
12
a s e 11
I - R 2
Rx1 Count Register
10 9 8 7 6 5 4 3 2 1
0000
0
Name
Type
Reset 0 l
Re Pi B0
P
0 0 0 0
RXCOUNT
0
RU
0 0 0 0 0 0 0
Bit(s)
13:0
Name
RXCOUNT
a n a Description
14-bit read-only register that holds the number of received data bytes in the packet in
Ba n RxFIFO. Note: The value returned changes as FIFO is unloaded and is only valid while
RxPktRdy(RxCSR.D0) is set.
12.4.40 TxType Register

11A TX1TYPE Tx1Type Register 00
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_PROTOC
TX_SPEED TX_TARGET_EP_NUMBER
OL
Type RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit(s)
7:6
Name
TX_SPEED
f o r
Description
Operating speed of target device when the core is configured with multipoint option
e a s e
When the core is not configured with the multipoint option, these bits should not be
accessed.
I - R 2
2'b00: Unused
l
Re Pi B P
2'b01: High
2'b10: Full
a
2'b11: Low
Ba
MT7623N
f o r
5:4 TX_PROTOCOL
e a s e - R 2
The CPU sets up this bit to select the required protocol for the Tx endpoint.
2'b00: Illegal
I
l
2'b01: Isochronous
3:0
Re Pi B P
2'b10: Bulk
2'b11: Interrupt
TX_TARGET_EP_NUMB The CPU sets up this value to the endpoint number contained in the Tx endpoint
ER descriptor returned to the USB2.0 controller during device enumeration.
a n a
12.4.41
11B
Bit 15 14 Ba
13
n
TxInterval Register
TX1INTERVAL
12
Tx1Interval Register
11 10 9 8 7 6 5 4 3 2 1 0
00
Name TX_POLLING_INTERVAL_NAK_LIMIT_M
Type RW
Reset 0 0 0 0 0 0 0 0

7:0 TX_POLLING_INTERVA (For host mode only) TxInterval register is an 8-bit register that, for Interrupt and
L_NAK_LIMIT_M Isochronous transfers, defines the polling interval for the currently-selected Tx endpoint.
For Bulk endpoints, this register sets up the number of frames/microframes after which
the endpoint should timeout on receiving a stream of NAK responses. There is a
r
TxInterval register for each configured Tx endpoint (except for Endpoint 0).
f o
In each case the value that is set defines a number of frames/microframes (high-speed
transfers), as follows:
e 2
Transfer Type | Speed | Valid values (m) | Interpretation
l e a s R
Interrupt | Low Speed or Full Speed | 1-255 | Polling interval is m frames.
-
Interrupt | High Speed | 1-16 | Polling interval is 2^(m-1) microframes
I
Isochronous | Full Speed or High Speed | 1-16 | Polling interval is 2^(m-1)
Re Pi B P
frames/microframes
Bulk | Full Speed or High Speed | 2-16 | NAK Limit is 2^(m-1) frames/microframes. Note:
A value of 0 or 1 disables the NAK timeout function.
Note: the register should be set before TxType for Bulk endpoint.
a n a
12.4.42
11C
Bit 15 14 Ba
13
n
RxType Register
RX1TYPE
12
Rx1Type Register
11 10 9 8 7 6 5 4 3 2 1 0
00
Name RX_PROTOC
RXSPEED RX_TARGET_EP_NUMBER
OL
Type RW RW RW
Reset 0 0 0 0 0 0 0 0

7:6 RXSPEED Operating speed of target device when the core is configured with multipoint option
When the core is not configured with the multipoint option, these bits should not be
accessed.
r
2'b00: Unused
o
2'b01: High
s f
2'b10: Full
e
2'b11: Low
2
a R
5:4 RX_PROTOCOL The CPU sets up this bit to select the required protocol for the Tx endpoint.
l e I -
2'b00: Illegal
P
Re Pi B
2'b01: Isochronous
2'b10: Bulk
2'b11: Interrupt
3:0 RX_TARGET_EP_NUMB The CPU sets up this value to the endpoint number contained in the Tx endpoint
a
ER descriptor returned to the USB2.0 controller during device enumeration.
Ba
MT7623N
f o r
e a s e I - R 2
12.4.43
11D l
Re Pi B
RxInterval Register
P
RX1INTERVAL Rx1Interval Register 00
a
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset
n a n 0
RX_POLLING_INTERVAL_NAK_LIMIT_M
0 0 0
RW
0 0 0 0
Bit(s)
7:0
Name
Ba Description
RX_POLLING_INTERVA RxInterval register is an 8-bit register that, for Interrupt and Isochronous transfers,
L_NAK_LIMIT_M defines the polling interval for the currently-selected Rx endpoint. For Bulk endpoints,
this register sets up the number of frames/microframes after which the endpoint should
timeout on receiving a stream of NAK responses. There is a RxInterval register for each
configured Rx endpoint (except for Endpoint 0).
RX POLLING INTERVAL/NAK LIMIT (M), (host mode only)
In each case the value that is set defines a number of frames/microframes (high-speed
transfers), as follows:
Transfer Type Speed Valid values (m) Interpretation
Interrupt Low Speed or Full Speed 1 - 255 Polling interval is m frames.
High Speed 1 - 16 Polling interval is 2(m-1) microframes
Isochronous Full Speed or High Speed 1 - 16 Polling interval is 2(m-1)
f r
frames/microframes
o
Bulk Full Speed or High Speed 2 - 16 NAK Limit is 2(m-1) frames/microframes. Note:
Value of 0 or 1 disables the NAK timeout function.
e a e I - R 2
Note: the register should be set before RxType for Bulk endpoint.
s
12.4.44
l
Re Pi B P
Configured FIFO Size Register
a
11F FIFOSIZE1
n a n EP1 Configured FIFO Size Register NA
Ba
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RXFIFOSIZE TXFIFOSIZE
Type DC DC
Reset X X X X X X X X

7:4 RXFIFOSIZE Indicates the RxFIFO size of 2^n bytes, e.g. value 10 means 2^10 = 1,024 bytes
3:0 TXFIFOSIZE Indicates the TxFIFO size of 2^n bytes, e.g.: value 10 means 2^10 = 1,024 bytes.
The configured FIFO size register value is undefined if Dynamic FIFO is configured. The existing
endpoints are default to HW configured value 10. The non-exist endpoints are default 0.
If the dynamic FIFO is not configured, the register represents the corresponding endpoint’s FIFO size
setting.
f o r
e a s e I - R 2
USB+0120h ~ USB+012Fh: Endpoint 2 registers and their behaviors are the same as Endpoint 1.
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
e a s e I - 2
R
12.4.45
l
Re Pi B P
DMA Interrupt Status Register (Byte Access)
00000200 DMA_INTR
a n a DMA Interrupt Status Register 00000000

Bit
Name
Type
Reset
Bit
31
0
15
30
0
14
0
29
Ba
13
n 0
28
DMA_INTR_UNMASK_SET
W1
0
12
0
27
11
26
10
25
0
9
24
0
8
23
0
7
22
0
6
0
21
5
0 0
20
DMA_INTR_UNMASK_CLEAR
W1
4
0 0
19
3
18
2
17
1
16
0
0
Name DMA_INTR_UNMASK DMA_INTR_STATUS
Type RU W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31:24 DMA_INTR_UNMASK_S Sets DMA_INTR_UNMASK to 1
ET
23:16 DMA_INTR_UNMASK_C Clears DMA_INTR_UNMASK to 0
LEAR
15:8 DMA_INTR_UNMASK
r
Unmasks DMA interrupts
f o
The DMA interrupt will be generated when both DMA_INTR_UNMASK and
e
DMA_INTR_STATUS are 1.
7:0 DMA_INTR_STATUS
l e a s I - 2
Indicates DMA complete interrupt status, one bit per DMA channel implemented
R
Bit 0 is used for DMA channel 1; bit 1 is used for DMA channel 2 etc. Write 1 to clear it.
P
Note: DMA interrupt will be asserted after disabling the DMA enable when receiving a
Re Pi B
null packet even thought DMA_COUNT_M still does not achieve 0.
12.4.46
n a
DMA Limiter Register (Word Access)
a
00000210
Bit
Name
Type
Reset
31
DMA_LIMITER
30
Ba
29
n 28
DMA Limiter Register
27 26 25 24 23 22 21 20 19 18
00000000
17 16
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DMA_LIMITER
Type RW
Reset 0 0 0 0 0 0 0 0

7:0 DMA_LIMITER This register suppresses the bus utilization of the DMA channel. The value is from 0 to
255. 0 means no limitation, and 255 means totally banned. The value between 0 and
255 means certain DMA is permitted to use AHB every (4 x n) AHB clock cycles.
o r
Note: It is not recommended to limit bus utilization of the DMA channels because this
f
will increase the latency of response to the masters, and the transfer rate decreases as
e
well. Before using it, the programmer must make sure that the bus masters have some
s 2
protective mechanism to avoid entering wrong states.
l e a P I - R
Re Pi B
12.4.47 DMA Configuration Register (Word Access)
00000220 DMA_CONFIG DMA Configuration Register 00000004
a n a
n
Ba
MT7623N
f o r
Bit
Name
31 30 29 28
e a s e 27
I - R 226 25 24 23 22 21 20 19 18 17 16
l
Type
Reset
Bit
Name
15 14 13
Re Pi B
12
P
11 10 9 8 7 6 5 4 3
BOUN
AHBW DARY
2 1 0
a
DMA_ACTIVE AHB_HPROT MCU_LOCK_
DMAQ_CHAN_SEL AIT_S _1K_C
n
_EN _2_EN SEL
EL ROSS
Type
n a _EN
Ba
RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 1 0 0

11:10 DMA_ACTIVE_EN The two bits control usb_active.
2'b00: usb_active depends on all DMAEN of DMA channel control register
.
2'b01: usb_active ties to 1
2'b10: usb_active ties to 0
2'b11: usb_active depends on ep_active, dma_active and all DMAEN of DMA channel
control register(OR logic)
9:8 AHB_HPROT_2_EN The two bits control the AHB master interface HPROT2 function operateing in non-
bufferable/bufferable/last transfer non-bufferable mode.
2'b00: All write transfers of a burst will be accessed by bufferable mode except for the
f o r
last transfer of a burst
e
2'b01: AHB master HPROT2 is always accessed by non-bufferable mode.
6:4 DMAQ_CHAN_SEL
l e a s - R 2
2'b10: AHB master HPROT2 is always accessed by bufferable mode
2'b11: Reserved
I
Selects DMA channel used by USB_DMAQ if it is available
3:2 MCU_LOCK_SEL
Re Pi B P
It will not affect if USB_DMAQ is not available.
Issues fix TXQ and FIFO PIO operation concurrent
(HW patch & Bug Fix only. Not a normal function.)
a
2'b00: No lock
n
2'b01: Lock 1 level (IP clock)
a
2'b10: lock 2 level (IP clock)
n
2'b11: No lock
Ba
1 AHBWAIT_SEL Selects AHBWAIT behavior
Set to 1 to return to old DMA master AHB wait condition.
This bit is used to test DMA FIFO overflow bug.
0 BOUNDARY_1K_CROS Enables 1k boundary page crossing
S_EN Set to 1 to force burst transfer regardless 1k boundary crossing.
Note: It will violate AHB 1k boundary specification but gain some bus performance.
12.4.48 DMA Channel M Control Register (Word Access)

0204 DMA_CNTL_0 DMA Channel 0 Control Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
Name DMAR
o
DMAA DMAC BURST_MOD BUSE DMAM DMAD DMAE
f
EQUE ENDPNT INTEN
BORT HEN E RR ODE IR N
ST
Type
Reset
A0
0
RU
0
RU
e
0
a s e
0
RW
0
I -
RU
R
0
2 0 0
RW
0 0
RW
0
RW
0
RW
0
Other
0
Bit(s)
13
Name
DMAABORT l
Re Pi B P
Description
If SW needs abort the current DMA transfer, set DMAABORT=1 & DMAEN=0, after the
transfer is aborted completely, DMA interrupt occurs.
a
12 DMAREQUEST Indicate whether DMA transfer is requesting or not. 1 means DMA is requesting.
Ba
MT7623N
f o r
11
10:9
DMACHEN
BURST_MODE
e a s e I - 2
DMA channel enable monitor bit
R
2'b00: Burst Mode 0 : Bursts of unspecified length
8 BUSERR
l
Re Pi B P
2'b01: Burst Mode 1 : INCR4 or unspecified length
2'b10: Burst Mode 2 : INCR8, INCR4 or unspecified length
2'b11: Burst Mode 3 : INCR16, INCR8, INCR4 or unspecified length
Bus error
7:4
3
ENDPNT
INTEN
a n a Endpoint DMA will transfer with

Enables interrupt
2 DMAMODE
Ba n DMA mode
DMA mode 0: Single packet operation
DMA mode 1: Multi packets operation, with the configuraiton of DMAReqMode in
RXCSR bit 11. DMA mode 1 supports both known size or unknown size transaction.
1 DMADIR Direction
0 : DMA write (Rx endpoint)
1 : DMA read (Tx endpoint)
0 DMAEN Enables DMA
The bit will be cleared when the DMA transfer is completed. Programmers should not
disable DMA_EN before the transfer is completed. If the programeers disables DMA_EN
when transferring, DMA will not stop immediately untill the last bus transfer is
completed.
r
The DMA Channel count information can be read from RAMINFO. The legal values of M are 1 ~ 8.
f o
DMA_CNTL_M offset = DMA_CNTL_0 offset + (10h*M-1).
e 2
12.4.49
l e a s I - R
DMA Channel M Address Register (Word Access)
00000208
Bit 31
DMA_ADDR_0
30 29
Re Pi B
28
P
DMA Channel 0 Address Register
27 26 25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
Reset 0 0 0
a n a0 0 0
DMA_ADDR_0[31:16]
0 0
RW
0 0 0 0 0 0 0 0
Bit
Name
Type
Reset
15
0
14
0
13
Ba
0
n 12
0
11
0
10
0
9
0
8
DMA_ADDR_0[15:0]
0
RW
0 0
7 6 5
0
4
0
3
0
2
0
1
0
0

31:0 DMA_ADDR_0 32-bit DMA start address
Updated (increased) by USB2.0 controller automatically while multiple packet DMA
(DMA mode = 1) is used.
DMA_ADDR_M offset = DMA_ ADDR_0 offset + (10h*M-1).
12.4.50
f o r
DMA Channel M Byte Count Register (Word Access)
0000020C
Bit 31 30 29
e
28
a s e 27
I - 2
DMA_COUNT_0 DMA Channel 0 Byte Count Register
R 26 25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
Reset
Bit 15 14 13
l
Re Pi B
12 P
11 10 9 8
0
7
0
6
DMA_COUNT_0[23:16]
0
5
0
RW
4
0 0
3 2
0
1
0
0
a
Name DMA_COUNT_0[15:0]
Ba
MT7623N
f o r
Type
Reset 0 0 0 0
e a s e 0
I - R 20 0 0
RW
0 0 0 0 0 0 0 0
Bit(s)
23:0
Name
DMA_COUNT_0
l
Re Pi B P
Description
24-bit DMA transfer count with byte unit
Updated (decreased) by USB2.0 controller automatically while each packet is
a n a transferred.
Ba n
DMA_COUNT_M offset = DMA_ COUNT_0 offset + (10h*M-1).
12.4.51 EPn RxPktCount Register (Word Access)

0300 EP0RXPKTCOU EP0 RxPktCount Register 0000
NT
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name EP0RXPKTCOUNT
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
f o r
Description
15:0 EP0RXPKTCOUNT
e a s e
transfer
I - R 2
Sets up the number of packets of Rx Endpoint n size MaxP to be transferred in a block
Only used in Host mode when AutoReq is set. Has no effect in Peripheral mode or when
l
Re Pi B P
AutoReq is not set.
RqPktCount (host mode only) For each Rx Endpoint 1 - 15, the USB2.0 controller
provides a 16-bit RqPktCount register. This read/write register is used in the host mode
to specify the number of packets that are to be transferred in a block transfer of one or
more Bulk packets of length MaxP to Rx Endpoint n. The core uses the value recorded
a n a in this register to etermine the number of requests to issue where the AutoReq option
(included in the RxCSR register) has been set.Note: Multiple packets combined into a
n
single bulk packet within the FIFO count as one packet.
Ba
The RX Endpoint count information can be read from EPINFO. The legal values of N are 0 ~ 15.
EP(N)RXPKTCOUNT offset = EP0RXPKTCOUNT offset + (4h*N).
12.4.52 Transmit Endpoint n Function Address (Word Access)

0480 T0FUNCADDR T0 Function Address Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name T0FuncAddr
Type RW
Reset 0 0 0 0 0 0 0
Bit(s) Name
f o r
Description
6:0 T0FuncAddr
e a s e - R 2
7 -bit read/write register recording the address of the target function to be accessed
through the associated endpoint (Endpoint 0)
I
l
Needs to be defined for each Tx endpoint that is used.
Re Pi B P
Note: TxFuncAddr must be defined for Endpoint 0.
The TX Endpoint count information can be read from EPINFO. The legal values of N are 0 ~ 15.
a n a
n
Ba
MT7623N
f o r
e a s e
T(N)FUNCADDR offset = T0FUNCADDR offset + (8h*N).
I - R 2
12.4.53 l
Re Pi B P
Transmit Endpoint n Hub/Port Address (Word Access)
a
0482 T0HUBADDR T0 HUB Address Register 0000
Bit
Name
15 14 13
n a n 12 11 10 9 8 7
T0Mult
6 5 4 3 2 1 0
Ba
T0PortAddr iTransl T0HUBAddr
ator
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

14:8 T0PortAddr Only needs to be written where a full or low speed device is connected to Tx Endpoint n
via a high speed USB 2.0 hub carrying out the necessary transaction translation
In such circumstances, the 7-bit read/write registers is used to record the port of that
USB 2.0 hub through which the target associated with the endpoint is accessed.
Note: If Endpoint 0 is connected to a hub, TxHubPort must be defined. Only valid if RTL
defines USB_HUB. This register is only valid @ FS/LS is plugged in at HUB.
7 T0MultiTranslator Bit 8 should record whether the hub has multiple transaction translator .
r
Only valid if RTL defines USB_HUB. This register is only valid @ FS/LS is plugged in at
o
HUB
f
.
e
1'b0: Single transaction translator
6:0 T0HUBAddr
l e a s I - R 2
1'b1: Multiple transaction translators
8 -bit read/write register to be written where a full or low speed device is connected to
P
Tx Endpoint n via a high -speed USB2.0 hub carrying out the necessary transaction
Re Pi B
translation to convert between high speed transmission and full/low speed transmission
The lower 7 bits record the address of this USB 2.0 HUB.
Note: If Endpoint 0 is connected to a hub, TxHubAddr must be defined for EP0. Only
valid if RTL defines USB_HUB
a n a . This register is only valid @ FS/LS is plugged in at HUB .
Ba n
The TX Endpoint count information can be read from EPINFO. The legal values of N are 0 ~ 15.
T(N)HUBADDR offset = T0HUBADDR offset + (8h*N).
12.4.54 Receive Endpoint n Function Address (Word Access)

0484 R0FUNCADDR R0 Function Address Register 0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name R0FuncAddr
Type RW
Reset 0 0 0 0 0 0 0
Bit(s)
6:0
Name
R0FuncAddr
f o r
Description
7 -bit read/write register recording the address of the target function to be accessed
e
through the associated endpoint (Endpoint 0)
l e a s I - 2
Needs to be defined for each Rx endpoint that is used.
R
Note: RxFuncAddr does not exist on EP0.
Re Pi B P
R(N)FUNCADDR offset = R0FUNCADDR offset + (8h*N).
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
12.4.55
0486 l
Re Pi B P
Receive Endpoint n Hub/Port Address (Word Access)
R0HUBADDR R0 HUB Address Register 0000
a
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
n a n R0PortAddr
R0Mult
iTransl
ator
R0HUBAddr
Ba
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

14:8 R0PortAddr Only needs to be written where a full or low speed device is connected to Rx Endpoint n
via a high -speed USB 2.0 hub carrying out the necessary transaction translation
In such circumstances, the 7-bit read/write register is used to record the port of that USB
2.0 hub through which the target associated with the endpoint is accessed.
Note: The RxPortAddr doest not exist on EP0. Only valid if RTL defines USB_HUB. This
register is only valid @ FS/LS is plugged in at HUB.
7 R0MultiTranslator Bit 8 records whether the hub has multiple transaction translator
Only valid if RTL defines USB_HUB. This register is only valid @ FS/LS is plugged in at
HUB
r
.
f o
1'b0: Single transaction translator
1'b1: Multiple transaction translators
e 2
s
6:0 R0HUBAddr 8 -bit read/write register needing to be written where a full or low speed device is
a - R
connected to Rx Endpoint n via a high -speed USB2.0 hub carrying out the necessary
e I
transaction translation to convert between high -speed transmission and full/low -speed
l
Re Pi B P
transmission
The lower 7 bits record the address of this USB 2.0 HUB.
Note: RxHubAddr does not exist on EP0. Only valid if RTL defines USB_HUB
. This register is only valid @ FS/LS is plugged in at HUB.
a n a
Ba n
R(N)HUBADDR offset = R0HUBADDR offset + (8h*N).
12.5 USBQMU Register Definition

USBQMU Base Address
USB P0: +11200000h
USB P1: +11270000h
12.5.1 Queue Control Registers (QCR0-QCR3)
f o r
00000800 QCR0
e a s e I - R 2
Queue Control Register 0 80000000
Bit 31
Name Q_CS
30 29
16B_E
N
l
Re Pi B P
28 27 26 25 24 23 22 21
T7Q_ T6Q_ T5Q_ T4Q_ T3Q_
CS_E CS_E CS_E CS_E CS_E
N N N N N
20
T2Q_C
S_EN
19
T1Q_ T0Q_
CS_E CS_E
N N
18 17 16
Type RW
a n a RW RW RW RW RW RW RW RW
n
Ba
MT7623N
f o r
Reset
Bit
1
15 14 13 12
e a s e 11
I - R 2
10 9 8
0
7 6
0 0
5
0
4
0
3
0
2
0
1
0
0
l
Name R7Q_ R6Q_ R5Q_ R4Q_ R3Q_ R2Q_ R1Q_ R0Q_
Type
Reset
Re Pi B P CS_E CS_E CS_E CS_E CS_E CS_E CS_E CS_E
N
RW
0
N
RW
0
N
RW
0
N
RW
0
N
RW
0
N
RW
0
N
RW
0
N
RW
0
Bit(s) Name
a n a Description
31 Q_CS16B_EN
Ba n Tx 0 Queue Descriptor Checksum Validation Enable

This bit is used to enable or disable 16 bytes checksum. (wimax only)
1'b0: Disable 16 bytes checksum, therefore, 12 bytes checksum for GPD and BD.
1'b1: Enable 16 bytes checksum, therefore, 16 bytes checksum for GPD and BD.
23 T7Q_CS_EN Transmit Queue (T7Q) Descriptor Checksum Validation Enable
This bit is used to enable or disable the descriptor checksum validation function for TXQ.
1'b0: Disable the descriptor checksum validation function for TxQ.
1'b1: Enable the descriptor checksum validation function for TxQ.
f o r
e
l e a s - 2
R
I
19 T3Q_CS_EN
Re Pi B P
Transmit Queue (T3Q) Descriptor Checksum Validation Enable
18 T2Q_CS_EN
a n a Transmit Queue (T2Q) Descriptor Checksum Validation Enable

17 T1Q_CS_EN
Ba n 1'b0: Disable the descriptor checksum validation function for TxQ.

Transmit Queue (T1Q) Descriptor Checksum Validation Enable
7 R7Q_CS_EN RxQ Receive 7 Queue Descriptor Checksum Validation Enable
This bit is used to enable or disable the descriptor checksum validation function for
RXQ.
1'b0: Disable the descriptor checksum validation function for RXQ.
1'b1: Enable the descriptor checksum validation function for RXQ.
6 R6Q_CS_EN
o r
RxQ Receive 6 Queue Descriptor Checksum Validation Enable
f
e
RXQ.
5 R5Q_CS_EN
l e a s - R 2
I
Re Pi B RXQ.
P

a n a
n
Ba
MT7623N
f o r
4 R4Q_CS_EN
e a s e - R 2
I
l
RXQ.
3 R3Q_CS_EN
Re Pi B P
a
n
RXQ.
a
n
Ba
RXQ.
RXQ.
RXQ.
r
e f o 2
s
00000804 QCR1 Queue Control Register 1 00000000
Bit
Name
31 30 29
R0Q_DATA_BUF_SI
l e a
28 27 26 25 24 23 22 21
P I -
R6Q_DATA_BUF_SI
R 20 19
R2Q_DATA_BUF_SI
18 17 16
R5Q_DATA_BUF_SI
Re Pi B
ZE ZE ZE ZE
Type RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name R1Q_DATA_BUF_SI
ZE
a n a R4Q_DATA_BUF_SI
ZE
R7Q_DATA_BUF_SI
ZE
R3Q_DATA_BUF_SI
ZE
n
Type RW RW RW RW
Ba
Reset 0 0 0 0 0 0 0 0 0 0 0 0

30:28 R0Q_DATA_BUF_SIZE R0Q Queue Data Buffer Size
This field indicates the size of the data buffers used in xxx queue. Each bit in this field
represents a specific data buffer size. The field definition is shown as follows.
3'b000: 32 bytes
3'b001: 64 bytes
3'b010: 128 bytes
3'b011: 256 bytes
3'b100: 512 bytes
3'b101: 1K bytes
3'b110: 2K bytes
3'b111: 4K bytes
26:24 R6Q_DATA_BUF_SIZE
o r
R6Q Queue Data Buffer Size
f
e
l e a s - 2
3'b000: 32 bytes
R
3'b001: 64 bytes
I
3'b010: 128 bytes
Re Pi B P
3'b011: 256 bytes
3'b100: 512 bytes
3'b101: 1K bytes
3'b110: 2K bytes
a
3'b111: 4K bytes
Ba
MT7623N
f o r
e a s e - R 2
I
l
Re Pi B P
3'b000: 32 bytes
3'b001: 64 bytes
3'b010: 128 bytes
3'b011: 256 bytes
a
3'b100: 512 bytes
n
3'b101: 1K bytes
a
3'b110: 2K bytes
18:16
Ba
R5Q_DATA_BUF_SIZE
n 3'b111: 4K bytes
3'b000: 32 bytes
3'b001: 64 bytes
3'b010: 128 bytes
3'b011: 256 bytes
3'b100: 512 bytes
3'b101: 1K bytes
3'b110: 2K bytes
3'b111: 4K bytes
3'b000: 32 bytes
f r
3'b001: 64 bytes
o
3'b010: 128 bytes
3'b011: 256 bytes
e a s e 2
3'b100: 512 bytes
R
3'b101: 1K bytes
I -
3'b110: 2K bytes
l
Re Pi B P
3'b111: 4K bytes
a
3'b000: 32 bytes
n
3'b001: 64 bytes
a
3'b010: 128 bytes
n
3'b011: 256 bytes
Ba
3'b100: 512 bytes
3'b101: 1K bytes
3'b110: 2K bytes
3'b111: 4K bytes
3'b000: 32 bytes
3'b001: 64 bytes
3'b010: 128 bytes
3'b011: 256 bytes
3'b100: 512 bytes
3'b101: 1K bytes
3'b110: 2K bytes
3'b111: 4K bytes
r
f o
e 2
3'b000: 32 bytes
l e a s3'b001: 64 bytes
- R
3'b010: 128 bytes
I
3'b011: 256 bytes
Re Pi B P
3'b100: 512 bytes
3'b101: 1K bytes
3'b110: 2K bytes
3'b111: 4K bytes
a n a
n
Ba
MT7623N
f o r
e a s e I - R 2
00000808
Bit 31
QCR2
30 29
l P
Queue Control Register 2
Re Pi B
28 27 26 25 24 23 22 21 20 19 18
Name CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_
00000000
17 16
TX_M TX_M TX_M TX_M TX_M TX_M TX_M TX_M
a
TX_ZL TX_ZL TX_ZL TX_ZL TX_ZL TX_ZL TX_ZL TX_ZL
ULTIE ULTIE ULTIE ULTIE ULTIE ULTIE ULTIE ULTIE
n
P7 P6 P5 P4 P3 P2 P1 P0
P7 P6 P5 P4 P3 P2 P1 P0
Type
Reset
RW
0
RW
0
RW
0
n a RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Ba
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CFG_ CFG_
TX_PA TX_S
DDIN DUHD
G R
Type RW RW
Reset 0 0

31 CFG_TX_ZLP7 Transmit ZLP configuration
When cfg_tx_multiep = 1, sending of ZLP is based on ZLP field in GPD. When
cfg_tx_multiep = 0, this bit determines whether to send ZLP or not.
1'b0: Do not send ZLP packet
r
1'b1: Send ZLP packet
30 CFG_TX_ZLP6
f o
Transmit ZLP configuration
e
2
s
a R
l e I -
P
Re Pi B
a
28 CFG_TX_ZLP4
n a n Transmit ZLP configuration

Ba
r
o
24 CFG_TX_ZLP0
s e f
2
Transmit ZLP configuration
l e a I - R
P
Re Pi B
23 CFG_TX_MULTIEP7 Multi endpoint configuration
a
This bit determines whether the endpoint is connected to multiple endpoint or not.
Ba
MT7623N
f o r
e a s e - 2
When this bit is set, the HW will also parse TGL and Target Endpoint Number to
R
determine whether or not to set data toggle and what endpoint number to program this
I
l
GPD for. (host mode only)
Re Pi B P
1'b0: Single endpoint
1'b1: Multi-endpoint
a n a When this bit is set, the HW will also parse TGL and Target Endpoint Number to
21 CFG_TX_MULTIEP5
Ba n 1'b0: Single endpoint

Multi endpoint configuration
19 CFG_TX_MULTIEP3
o r
f
e a s e 2
R
-
I
l
18 CFG_TX_MULTIEP2
Re Pi B P
a
n
a
n
Ba
1 CFG_TX_PADDING
r
Transmit Padding Configuration
f o
This bit determines sending of padding bytes to make each GPD word aligned.
e
(cfg_sduhdr=1 only. Reserved when cfg_sduhdr=0)
0 CFG_TX_SDUHDR
l e a s - R 2
1'b0: Do not send padding
1'b1: Send padding
I
Transmit SDU header configuration
Re Pi B P
This bit determines sending of 4 byte pre-defined SDU header. (wimax only)
1'b0: Do not send SDU header
1'b1: Send SDU header
a n a
n
Ba
MT7623N
f o r
0000080C QCR3
a s e R 2
Queue Control Register 3
e I -
00000000
l
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P7 P6 P5
Re Pi B
P4 P
Name CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_
RX_ZL RX_ZL RX_ZL RX_ZL RX_ZL RX_ZL RX_ZL RX_ZL
P3 P2
RX_M RX_M RX_M RX_M RX_M RX_M RX_M RX_M
P1 P0
ULTIE ULTIE ULTIE ULTIE ULTIE ULTIE ULTIE ULTIE
P7 P6 P5 P4 P3 P2 P1 P0
Reset
Bit
0
15
0
14 13
0 0
12
0
11
a n a
0
10 9
0
8
0
RW
0
7
RW
0
6
RW
0
RW
0
5
RW
0
4
RW
0
RW
0
3
RW
0
2 1 0
Type RW RW Ba
RW
n
Name CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_
RX_C RX_C RX_C RX_C RX_C RX_C RX_C RX_C
OZ7 OZ6 OZ5 OZ4 OZ3 OZ2 OZ1 OZ0
RW RW RW RW RW
CFG_ CFG_
RX_M RX_S
AXPH DUHD
B
RW
R
RW
Reset 0 0 0 0 0 0 0 0 0 0

31 CFG_RX_ZLP7 Receive ZLP configuration
This bit determines whether or not to expect ZLP if packets end on max packet
boundary (only used when cfg_rx_multiep = 0)
1'b0: Do not expect ZLP
1'b1: Expect ZLP
f r
o
29 CFG_RX_ZLP5
e a s e - R 2
1'b1: Expect ZLP
Receive ZLP configuration
I
l
28 CFG_RX_ZLP4
Re Pi B P
1'b1: Expect ZLP
a n a This bit determines whether or not to expect ZLP if packets end on max packet
n
Ba
1'b1: Expect ZLP
1'b1: Expect ZLP
1'b1: Expect ZLP
24 CFG_RX_ZLP0
f r
1'b1: Expect ZLP
o
e a s e - R 2
I
l
1'b1: Expect ZLP
23 CFG_RX_MULTIEP7
Re Pi B P
Receive multiple endpoint configuration
This bit determines whether or not to parse the GPD for data toggle and endpoint
number on receive side (Host mode only)
a
Ba
MT7623N
f o r
22 CFG_RX_MULTIEP6
e a s e - 2
1'b1: Multiple endpoint
R
I
l
Re Pi B P
a
21 CFG_RX_MULTIEP5 Receive multiple endpoint configuration
n
a
n
Ba
r
o
17 CFG_RX_MULTIEP1
s e f
2
a R
l e I -
P
Re Pi B
a
n
15 CFG_RX_COZ7
n a Empty data receive ZLP and jump to next GDP configuration
Ba
This bit determines whether or not jump to next GPD when ZLP is received and current
GPD still have no data.
1'b0: Do not jump to next GPD
1'b1: Jump to next GPD
14 CFG_RX_COZ6 Empty data receive ZLP and jump to next GDP configuration
o r
f
e
11 CFG_RX_COZ3
l e a s - R 2
Empty data receive ZLP and jump to next GDP configuration
I
P
Re Pi B
a
Ba
MT7623N
f o r
e a s e - 2
R
I
l
Re Pi B P
a n a 1'b0: Do not jump to next GPD

n
Ba
1 CFG_RX_MAXPHB This bit is only used in high bind-width endpoints. Please refer to USB MAC register
RxMaxP for the meaning of M. For example, if M=2, and only DATA1&DATA0 (with
maxpayload for each packet), it is treated as short packet if CFG_RX_MAXPHB=0, and
treated as maxpkt if CFG_RX_MAXPHB=1.
1'b0: only if (M+1) packets with size of maxpayload are received, it is treated as maxpkt
for high bind-width endpoints
1'b1: even less than (M+1) packets are received, but each packet size is maxpayload, it
is still treated as maxpkt.
0 CFG_RX_SDUHDR Receive SDU header configuration
This bit determines whether or not to parse an SDU header on receive side
1'b0: No SDU header
f o r
1'b.1: SDU header
e a s e I - R 2
l
Re Pi B P
12.5.2 RX Queue Command and Status Registers (RQCSRn)
The RX Queue count information can be read from QMU_HWVER register. The legal values of n is 1
~ 8.
a n a
n
RQCSRn = RQCSR0 offset + 0x10h*(n-1)
Ba
00000810 RQCSR0 RX Queue Command and Status Register 0 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RXQ_ RXQ_
RXQ_ RXQ_
ACTIV RESU STAR
STOP
E ME T
Type RU A0 A0 A0
Reset 0 0 0 0

15 RXQ_ACTIVE
o r
RX Queue 0 Active
f
This bit is used to indicate whether the RX Queue is in the active state. When the HIF
e a s e - R 2
Controller is reset, the queue is in the inactive state by default. After receiving a START
or RESUME command and executing it without error, the queue enters the active state.
When the queue is empty or stopped by a STOP command, it returns to the inactive
I
l
state.
2 RXQ_STOP
Re Pi B P
1'b0: Inactive
1'b1: Active
RX Queue 0 Stop
a
This bit is used to issue a STOP command to the RX Queue.
Ba
MT7623N
f o r
1 RXQ_RESUME
e a s e - 2
In the case of RBEQ_STOP, all 4 best effort queues are stopped together.
R
RX Queue 0 Resume
I
0 RXQ_START
l
Re Pi B P
This bit is used to issue a RESUME command to the RX Queue.
RX Queue 1 Start
This bit is used to issue a START command to the RX Queue.
a n a
Ba n
12.5.3 RX Queue Starting Address Registers (RQSARn)
~ 8.
RQSARn = RQSAR0 offset + 0x10h*(n-1)
00000814 RQSAR0 RX Queue Starting Address Register 0 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RXQ_START_ADDR0[31:16]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RXQ_START_ADDR0[15:0]
Type
Reset 0 0 0 0 0
f o r
0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s
)
Name
e a s e
Description
I - R 2
31:0 RXQ_START_ADD
R0
l
Re Pi B P
a n a
B a n
12.5.4 RX Queue Current Pointer Registers (RQCPRn)
~ 8.
RQCPRn = RQCPR0 offset + 0x10h*(n-1)
00000818 RQCPR0 RX Queue Current Pointer Register 0 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RXQ_CURR_PTR0[31:16]
Type RU
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RXQ_CURR_PTR0[15:0]
Type
r
RU
o
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
s e f
Description
2
31:0 RXQ_CURR_PTR0
l e a P I - R
Re Pi B
a n a
n
Ba
MT7623N
f o r
12.5.5 RX Timeout Register n (RQTRn)
e a s e I - R 2
~ 8.
l
Re Pi B
RQTRn = RQTR0 offset + 0x10h*(n-1) P
00000890 RQTR0
a n a RX Timeout Register 0 00000000
n
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Ba
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RXQ_TIMEOUT0
Type RW
Reset 0 0 0 0 0 0 0 0

7:0 RXQ_TIMEOUT0 RX Timeout Register
This 8 bit register sets the number of 8K cycles for USB Queue to wait after receiving
USB packet before it treats the GPD as done and writes length and HWO back into
GPD.
f o r
e a s e I - R 2
l
Re Pi B P
12.5.6 RX Queue Last Done Pointer Register n (RQLDPRn)
~ 8.
n a
RQLDPRn = RQLDPR0 offset + 0x10h*(n-1)
a
00000900
Bit
Name
Type
31
RQLDPR0
30 29
Ba n RX Queue Last Done Pointer Register 0
28 27 26 25 24 23 22 21
RXQ_LAST_DONE_PTR0[31:16]
RU
20 19 18
00000000
17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name RXQ_LAST_DONE_PTR0[15:0]
Type RU
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31:0 RXQ_LAST_DONE_PTR Last Done Pointer Register. As the QMU complete the last transaction in RXQ queue, it
r
0 will update this register to the last-done pointer as the same time as updating RQCPRn,
o
and the FW can see this pointer to fast de-queue after sense the RQCPRn been
f
changed.
e
This pointer will be reset to 0 as initialization, and it will be forced to the starting address
l e a s I - 2
(RQSARn) after the "Start" command been issued.
R
Re Pi B P
a n a
n
Ba
MT7623N
f o r
e a s e R 2
12.5.7 Tx n Queue Command and Status Register (TQCSRn)
I -
~ 8.
l
Re Pi B
TQCSRn = TQCSR0 offset + 0x10h*(n-1) P
The TX Queue count information can be read from QMU_HWVER register. The legal values of n is 1
a n a
n
00000A00 TQCSR0 TX Queue Command and Status Register 0 00000000
Ba
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TXQ_ TXQ_
TXQ_ TXQ_
ACTIV RESU STAR
STOP
E ME T
Type RU A0 A0 A0
Reset 0 0 0 0

15 TXQ_ACTIVE TX Queue 0 Active
r
This bit is used to indicate the current state of the TQ.
o
1'b0: Inactive
2 TXQ_STOP
s e f
1'b1: Active
2
TX Queue 0 Stop
a R
This bit is used to stop the operation of the TQ.
l e I -
Note that in HIF-SDIO, this Queue STOP command clears TX FIFO and clear data
P
count in TQDCR.
Re Pi B
1 TXQ_RESUME TX Queue 0 Resume
This bit is used to resume the operation of the TQ.
0 TXQ_START TX Queue 0 Start
a n a This bit is used to start the operation of the TQ.
Ba n
~ 8.
TQCSRn = TQCSR0 offset + 0x10h*(n-1)
12.5.8 TX n Queue Starting Address Register (TQSARn)

~ 8.
TQSARn = TQSAR0 offset + 0x10h*(n-1)
00000A04 TQSAR0
f o r
TX Queue Starting Address Register 0 00000000
e
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
l e a s I - R 2TXQ_START_ADDR0[31:16]
RW
P
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Re Pi B
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TXQ_START_ADDR0[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
a n a
n
B a
MT7623N
f o r
Bit(s) Name
e a s e I - R
Description
2
31:0 TXQ_START_ADDR0
l
Re Pi B P
TX Queue Starting Address
The starting address of the T0Q.
a n a
Ba n
12.5.9 TX n Queue Current Pointer Register (TQCPRn)
~ 8.
TQCPRn = TQCPR0 offset + 0x10h*(n-1)
00000A08 TQCPR0 TX Queue Current Pointer Register 0 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TXQ_CURR_PTR0[31:16]
Type RU
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
Reset
f o r TXQ_CURR_PTR0[15:0]
RU
e
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
B Name
l e a s I - R 2
Description
P
i
Re Pi B
t
(
s
)
3
1
TXQ_CURR_
PTR0
a n a TX Queue Current Pointer

The current pointer of the T0Q.
:
0
Ba n
12.5.10 USB General Control and Status Register (USBGCSR)
00000B00 USBGCSR USB General Control and Status Register 00008000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name BUS_ QUE_
QUE_ QUE_ QUE_ QUE_ QUE_ QUE_ QUE_ QUE_
EN_HI
RST_ EN_R EN_R EN_R EN_R EN_R EN_R EN_R EN_R
F_CM
QUE X7 X6 X5 X4 X3 X2 X1 X0
D
Type RW
Reset
Bit
0
15 14 13 12
f
11
o r 10 9
RW
0
8
RW
0
RW
7
0
RW
0
6
RW
0
RW
0
5
RW
0
RW
0
4
RW
0
3 2 1 0
Name QUE_
CG_DI
e a s e I - R 2 QUE_ QUE_ QUE_ QUE_ QUE_ QUE_ QUE_ QUE_ QUE_

EN_HI EN_T EN_T EN_T EN_T EN_T EN_TX EN_T EN_T
l
S F_EVT X7 X6 X5 X4 X3 2 X1 X0
P
Type
Re Pi B
RW RW RW RW RW RW RW RW RW RW
Reset 1 0 0 0 0 0 0 0 0 0
a
Ba
MT7623N
f o r
31 BUS_RST_QUE
e a s e - R 2
Bus Resets Queue
When this bit is set to 1, a bus reset on USB will also trigger a card reset. Wimax only.
I
l
Used for debugging
24 QUE_EN_HIF_CMD
Re Pi B P
1'b0: Card does not reset on bus reset
1'b1: Card resets on bus reset
a
23 QUE_EN_RX7 USB QMU Enable
n a n This field is used to reflect the USB QMU control USB DMA or not. Each bit
corresponds to each endpoint in the USB.
If all QUE_EN_XX bits are set to zero, then the USB DMA channel is allowed to be
Ba
directly used for software.
1'b0: USB Queue is Controlled by Software
1'b1: USB Queue is Controlled by QMU
This field is used to reflect the USB QMU control USB DMA or not. Each bit
f o r
e
l e a s - 2
R
I
19 QUE_EN_RX3
Re Pi B P
USB QMU Enable
a n a This field is used to reflect the USB QMU control USB DMA or not. Each bit
n
Ba
r
o
16 QUE_EN_RX0
s e f
USB QMU Enable
2
a R
l e I -
P
Re Pi B
15 QUE_CG_DIS The EPQ control can be turned off if it is not serviced to enhance dynamic power.
a
1'b0: The CG cells inserted in QMU is enabled, so the clock can be turned off dynamicly.
Ba
MT7623N
f o r
8 QUE_EN_HIF_EVT
e a s e I - 2
1'b1: The CG cells in QMU is disabled.
R
7 QUE_EN_TX7
l
Re Pi B P
USB QMU Enable
a
n
a
6 QUE_EN_TX6
Ba n USB QMU Enable

5 QUE_EN_TX5 USB QMU Enable
r
o
s f
e
2
a R
3 QUE_EN_TX3
l e I -
USB QMU Enable
P
Re Pi B
a n a 1'b0: USB Queue is Controlled by Software

n
Ba
f r
o
e a s e I - R 2
l
Re Pi B P
a n a
n
Ba
MT7623N
f o r
12.5.11
a s e R
USB Firmware Register 1 (USB_FW1)
e I - 2
00000B04
Bit 31
USB_FW1
30 29
l
Re Pi B P
USB Firmware Register 1
28 27 26 25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
a n a FW1[31:16]
RW
n
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Ba
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FW1[15:0]
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31:0 FW1
12.5.12 USB Firmware Register 2 (USB_FW2)
f o r
00000B08
Bit 31
USB_FW2
30 29
a s e - R
28 27 26 25 24 23
e I 2
USB Firmware Register 2
22 21 20 19 18
00000000
17 16
l
Name FW2[31:16]
Type
Reset
Bit
Name
0
15
0 0
14 13
Re Pi B
12
0
P
0
11
0
10
0
9
0
8
RW
0
FW2[15:0]
7 6
0 0
5
0
4
0
3
0
2
0
1
0
0
Type
Reset 0 0 0
a n a0 0 0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s) Name
31:0 FW2
Ba n Description
12.5.13 TnQ USB Stream Constraint Register (T0QUSBSC)
00000B80 T0QUSBSC T0Q USB Stream Constraints 00000020

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
r
Name SPCOUNT
Type
Reset
Bit 15 14 13 12 11 10 9 8
0
e
7
f o 2
6
0 0
5
0
4
RW
0
3
0
2
0
1
0
0
Name
Type
l e a s I - R
SSIZE
RW
P
Reset 0 0 0 0 0 1 0 0 0 0 0
Bit(s) Name
Re Pi B
Description
a
23:16 SPCOUNT USB QMU Maximum Stream PDU Count
B a
MT7623N
f o r
e a s e
Example:
I - 2
0x00 TXQ is packet mode
R
l
0x10 Maximum stream PDU count = 0x10 = 16
Re Pi B P
If there are already 16 GPD send to host, QMU will stop this stream regardless of the
constraint of empty or stream size.
10:0 SSIZE USB QMU Maximum Stream Size
This register is not valid when SPCOUNT is smaller than 2.
a n a The unit of this register is 64 bytes.

Example:
0x40 Maximum stream size = (0x40)*(64) = 4096 bytes
12.5.14 Ba n
QMU Interrupt Status and Acknowledgement Register (QISAR)
00000C00 QISAR QMU Interrupt Status and Acknowledgement Register 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RBEQ RBEQ RBEQ RBEQ
TxEP_ TxQ_E RxEP_ RxQ_ RxBE RBEQ _EMP _EMP _EMP _EMP RBEQ RxQ_ TxQ_E
ERR_I RR_IN ERR_I ERR_I Q_ER _DEQ TYBE TYBE TYBE TYBE _DON EMPT MPTY
NT T NT NT R_INT _INT Q3_IN Q2_IN Q1_IN Q0_IN E_INT Y_INT _INT
T T T T
Type
Reset 0 0
f o0
r
W1C W1C W1C W1C W1C W1C W1C
0 0 0 0
W1C W1C W1C
0 0 0
W1C
0
W1C
0
W1C
0
e
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
a s - R 2
Name R7Q_ R6Q_ R5Q_ R4Q_ R3Q_ R2Q_ R1Q_ R0Q_ T7Q_ T6Q_ T5Q_ T4Q_ T3Q_ T2Q_D T1Q_ T0Q_
DONE DONE DONE DONE DONE DONE DONE DONE DONE DONE DONE DONE DONE ONE_I DONE DONE
l e I
_INT _INT _INT _INT _INT _INT _INT _INT _INT _INT _INT _INT _INT NT _INT _INT
Type
Reset 0 0 0
Re Pi B
0 0 0
P
W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C
0 0 0 0 0 0 0 0 0 0
a
28 TxEP_ERR_INT
n a n TxEP Error Interrupt

This bit is set to 1 when a USB packet error occurs in the USB MAC and signifies to SW
Ba
that the HW Queue may need to be stopped and restarted. The corresponding endpoint
for the error occurred is specified in the Tx Endpoint Error Indication Register.
27 TxQ_ERR_INT TxQ Error Interrupt
This bit is set to 1 when the TxQ detects errors and stops its operation. The
corresponding reasons for the errors are specified in the Tx Queue Error Indication
Register.
26 RxEP_ERR_INT RxEP Error Interrupt
This bit is set to 1 when a USB packet error occurs in the USB MAC and signifies to SW

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MT7623N

Datasheet for Development Board

Ba n Steven Liu Update ETHSYS

List of Figures ...................................................................................................................................... 11

List of Tables ........................................................................................................................................ 12

1.1 Introduction ......................................................................................................................... 13

1.2 Block Diagram .................................................................................................................... 13

Register Definition .............................................................................................................. 64

Feature list ........................................................................................................................ 225

2.3 Block Diagram .................................................................................................................. 225

2.5 PLL Related Control ......................................................................................................... 228

Top Reset Generate Unit ......................................................................................................... 310

Block Diagram .................................................................................................................. 310

3.4 Register Definition ............................................................................................................ 311

3.5 Programming Guide ......................................................................................................... 317

External Interrupt Controller ................................................................................................... 369

5.1 Introduction ....................................................................................................................... 369

5.2 Feature list ........................................................................................................................ 369

5.3 Block Diagram .................................................................................................................. 369

5.4 Register Definition ............................................................................................................ 370

Feature list ........................................................................................................................ 446

7.3 Block Diagram .................................................................................................................. 447

7.4 Register Definition ............................................................................................................ 447

8 UART .......................................................................................................................................... 471

8.1 Introduction ....................................................................................................................... 471

9.3 Block Diagram .................................................................................................................. 490

9.4 Register Definition ............................................................................................................ 490

10 Pulse-Width Modulator (PWM) ................................................................................................ 512

10.1 Introduction ....................................................................................................................... 512

10.2 Feature list ........................................................................................................................ 512

10.3 Block Diagram .................................................................................................................. 512

11.2 Feature list ........................................................................................................................ 549

11.5 Programming Guide ......................................................................................................... 555

12.2 Feature list ........................................................................................................................ 556

12.3 Block Diagram .................................................................................................................. 557

12.4 USB MAC Register Definition ........................................................................................... 557

n a n © 2019 MediaTek Inc. Page 7 of 1305

13 MSDC Controller ....................................................................................................................... 679

13.1 Introduction ....................................................................................................................... 679

13.2 Feature list ........................................................................................................................ 679

13.3 Block Diagram .................................................................................................................. 680

13.4 Register Definition ............................................................................................................ 680

14.3 Block Diagram .................................................................................................................. 839

Infrared Receiver ...................................................................................................................... 924

15.3 Block Diagram .................................................................................................................. 924

15.4 Register Definition ............................................................................................................ 925

16 HDMI Transmitter ..................................................................................................................... 952

16.1 Introduction ....................................................................................................................... 952

16.2 Feature list ........................................................................................................................ 952

17.2 Feature list ...................................................................................................................... 1016

18.1 Introduction ..................................................................................................................... 1037

18.2 Feature List ..................................................................................................................... 1037

18.3 Block Diagram ................................................................................................................ 1037

18.4 Register Definition .......................................................................................................... 1038

20.2 Feature List ..................................................................................................................... 1073

21 USB2.0 (in USB3.0) ................................................................................................................. 1181

21.1 Introduction ..................................................................................................................... 1181

21.2 Feature list ...................................................................................................................... 1181

21.3 Block Diagram ................................................................................................................ 1181

23.1 Introduction ..................................................................................................................... 1190

23.2 Feature List ..................................................................................................................... 1190

23.3 Block Diagram ................................................................................................................ 1191

1.2 Block Diagram