NuMicro

ADC

NuMicro@nuvoton.com

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Agenda
Features
ADC Block Diagram
ADC Function Descriptions
ADC Operation Modes
ADC Operation Flow and Sample Code

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Features

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ADC General Features (I)
12-bit SAR ADC
Analog input voltage range:
0~Vref (Max to 5.0V).
Operation voltage:
AVDD=3.0V~5.5V;
Input channel:
Up to 8 single-end analog input channels
4 pairs of differential analog input channel.
Up to 600KHz conversion rate.
The maximum ADC operating frequency is 16M Hz
Three operation modes
Single mode
Single-cycle mode
Continuous scan mode
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ADC General Features (II)
An A/D conversion can be started by
Software trigger
External trigger pin (STADC pin)
Conversion results are held in data registers for each channel
with VALID and OVERRUN indicators.
The ADC equips with a digital compare function. User can use
this function to monitor the conversion result of a user-specific
channel.
Channel 7 support 3 input sources:
external analog voltage
internal bandgap voltage
output of internal temperature sensor
Support Self-calibration to minimize the conversion error.
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ADC Block Diagram

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 ADC Configuration
Control
Conversion Results

A/D Control Register

A/D Channel Enable

Register (ADCHER)

A/D Data Register 0

A/D Data Register 1

A/D Data Register 7

A/D Status Register

Register (ADCMR)

Rgister (ADCALR)
A/D Calibration
A/D Compare
APB Bus

(ADDR0)

(ADDR1)

(ADDR7)

(ADSTR)
(ADCR)
ADC PDMA

:
.
External Trigger Pin Request
4 options: falling/rising
/high/low
VALID & OVERRUN
PDMA_nDREQ

STADC(PB.8) Digatal Control Logics ADINT

& ADF
ADC Clock Generator

SAR[1:0]
Reference Voltage
ADC Interrupt
Input
Request

adc_start & adc_clk

cal_finish and adc_finish

Successive
Approximations Register
VREF 12-bit DAC
&
Calibration
Channel Selection
chsel[2:0]

AIN[0]
8 to 1 Analog

AIN[1] + Analog Control Logics

MUX
...

ADC7 -
00
VBG 01 AIN[7]* Comparator
VTEMP
00
AVSS 01
Sample and Hold
Analog Macro
PRESEL[1:0]
* AIN[7] source is selected by PRESEL[1:0]
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ADC Function Descriptions

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ADC Register Map
Register Offset R/W Description Reset Value
ADC_BA = 0x400E_0000
ADDR0 ADC_BA+0x00 R A/D Data Register 0 0x0000_0000
ADDR1 ADC_BA+0x04 R A/D Data Register 1 0x0000_0000
ADDR2 ADC_BA+0x08 R A/D Data Register 2 0x0000_0000
ADDR3 ADC_BA+0x0C R A/D Data Register 3 0x0000_0000
ADDR4 ADC_BA+0x10 R A/D Data Register 4 0x0000_0000
ADDR5 ADC_BA+0x14 R A/D Data Register 5 0x0000_0000
ADDR6 ADC_BA+0x18 R A/D Data Register 6 0x0000_0000
ADDR7 ADC_BA+0x1C R A/D Data Register 7 0x0000_0000
ADCR ADC_BA+0x20 R/W A/D Control Register 0x0000_0000
ADCHER ADC_BA+0x24 R/W A/D Channel Enable Register 0x0000_0000
ADCMPR0 ADC_BA+0x28 R/W A/D Compare Register 0 0x0000_0000
ADCMPR1 ADC_BA+0x2C R/W A/D Compare Register 1 0x0000_0000
ADSR ADC_BA+0x30 R/W A/D Status Register 0x0000_0000

ADCALR ADC_BA+0x34 R/W A/D Calibration Register 0x0000_0000

ADPDMA ADC_BA+0x40 R/W ADC PDMA current transfer data 0x0000_0000

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ADC Clock Source
ADC_S(CLKSEL1[3:2])

ADC_EN(APBCLK[28])

22M
11 ADC_CLK
10
÷ (ADC_N+1)
PLL_Fout
01 ADC_N(CLKDIV[23:16])
12M
00

The maximum ADC clock frequency is 16MHz

The ADC clock frequency =
(ADC clock source frequency) / (ADC_N+1);
ADC_N is an 8-bit pre-scaler

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ADC Input Channel Setting
The ADC input pins share with GPIO port A
The ADC input pins must be configured in input type
Single-end input mode
Channel 0 ~ Channel 7 share with GPA0~GPA7
Differential input mode
Channel 0 ~ Channel 3
Differential input channels are the paired channels of single-end input channels

Differential input paired Single-end input channel

channel
0 0 1
1 2 3
2 4 5
3 6 7
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Self-Calibration

User can write 1 to CALEN bit in ADCALR register to

enable the self calibration function. The CAL_DONE bit
reflects the calibration state.
The timing of self-calibration
After power on
After switching input mode between single-end and
differential

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Result Monitor Function
Two digital comparators.
Compare the ADC result of the specified channel with a user defined compare value
stored in CMPD(ADCCMPRx[27:16])
When the conversion of the channel specified by CMPCH is completed, the
comparing action will be triggered automatically.

CMPCH(ADCMPRx[5:3]) CMPCOND(ADCMPRx[2])
CHANNEL(ADSR[6:4])
Channel Addr. CMPMATCNT
(ADCMPRx[11:8])

RSLT < CMPD

ADDRx[11:0] 0
12-bit Match CMPFx(ADSR[2:1])
Comparator RSLT >=CMPD Counter
8 to 1 Analog

AIN[0] A/D 1
MUX

analog
....

AIN[7] macro
Note:
CMPD=ADCMPRx[27:16]
RSLT=ADDRx[11:0]

CMPD(ADCMPRx[27:16])

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ADC Interrupt

Three interrupt sources

ADF: completion of a ADC operation mode
CMPF0: Condition match monitored by ADC comparator0
CMPF1: Condition match monitored by ADC comparator1

ADF
ADIE

CMPF0
ADINT
CMPIE0

CMPF1
CMPIE1
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ADC Operation Modes

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Single Mode
1 2 8 9 20

ADC_CLK

ADST

sample

ADDRx[11:0] ADDRx[11:0]

ADF

A/D conversion is to be performed only once on the

specified single channel.
If software enables more than one channel in single mode,
only the lowest channel will be converted and the other
enabled channels will be ignored.
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Single-Cycle Scan Mode
Channel0 Channel2 Channel3 Channel7

ADST

chsel[2:0] 3'b000 3'b010 3'b011 3'b111

sample

SAR[11:0] R0 R2 R3 R7

ADDR0 R0

ADDR2 R2

ADDR3 R3

ADDR7 R7

Single-cycle scan on channel 0, 2, 3 and 7 (ADCHER[7:0] = 8'b10001101)

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Continuous Scan Mode
Channel0 Channel2 Channel3 Channel7 Channel0 Channel2

ADST
Software clear ADST

chsel[2:0] 3'b000 3'b010 3'b011 3'b111 3'b000 3'b010 3'b011 3'b111 3'b010

sample

ADDR0

ADDR2

ADDR3

ADDR7

Continuous scan on channel 0, 2, 3, and 7 (ADCHER[7:0] = 8'b10001101)

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ADC operation flow

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 Step 1
Configure ADC input
channels

Configure ADC clock

Step 2

Set ADC operation mode

Step 3

Step 4
Select ADC conversion
channel

Enable ADC interrupt

Step 5

Start conversion Step 6

No

Wait ADC interrupt Step 7

Yes

Get the conversion result

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Sample Code(1/2)
/*----------------------------------------------------------------------------
MAIN function
----------------------------------------------------------------------------*/
int32_t main (void)
{
/* Step 1. GPIO initial */
//Set input mode
GPIOA->PMD.PMD1=0;
//Disable digital input path
GPIOA->SCH|=0x00020000;
//Set ADC function
SYS->GPAMFP.ADC1=1;

/* Step 2. Enable and Select ADC clock source, and then enable ADC module */
//Select 22Mhz for ADC
SYSCLK->CLKSEL1.ADC_S = 2;
//ADC clock source = 22Mhz/2 =11Mhz;
SYSCLK->CLKDIV.ADC_N = 1;
//Enable clock source
SYSCLK->APBCLK.ADC_EN = 1;

/* Step 3. Select Operation mode */

//Enable ADC module
ADC->ADCR.ADEN = 1;
//Single end input
ADC->ADCR.DIFF = 0;
//Single mode 21
ADC->ADCR.ADMD = 0;
Sample Code(2/2)

/* Step 4. Select ADC channel */

ADC->ADCHER.CHEN = 0x02;

/* Step 5. Enable ADC interrupt */

//clear the A/D interrupt flags for safe
ADC->ADSR.ADF =1;
ADC->ADCR.ADIE = 1;
// To enable the ADC interrtupt
NVIC_EnableIRQ(ADC_IRQn);

/* Step 6. Conversion start */

ADC->ADCR.ADST=1;
/* Step 7. wait ADC interrupt */
while(1)
{
if (ADC_INT_FLAG==0)
break;
}
}

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Condition
ADC
Input channel:ADC7
Clock source: 11MHz (22MHz/2)
Operation mode: Single mode
PWM
Output Channel:PWM0
Clock source: 0.66Hz (22.1184MHz/((255+1)*2)/(65535+1))
PWM duty is defined by ADC value
LCD
Display ADC value

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 ADC+PWM Block Diagram
VCC

Flash
ADC7 VR1
ADC 20K

GPA7
Cortex-M0
SPI
ADC Value: 277

LCD Panel
PWM0
NUC140V3AN LED

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 Run “Smpl_ADC_PWM” Code

Customer_CD Readme.txt

NUC1xx BSP
NUC1xx_BSP Driver Reference Guide

NuvotonPlatform_Keil

Sample

NUC1xx-LB_002

Smpl_ADC_PWM Smpl_DrvADC_PWM. uvproj

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Thank you

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