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Xilinx Design Flow

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The Integrated Software Environment

Design Entry
Advanced Design HDL Edit and Entry

¾System Generator for DSP

Techniques ¾CORE IP Generator
¾Synplicity Synplify and Synplify Pro
¾GNU Embedded Tools ¾Synplicity Amplify physical synthesis
¾Architecture Wizards
¾Wind River Xilinx Edition ¾MentorGraphics LeonardoSpectrum
¾ECS Schematic Editor
¾Embedded Development Kit ¾Mentor Graphics Precision RTL
¾StateCAD State Diagram Editor
¾IMPACT physical synthesis
¾RTL Checker
¾System ACE Configuration ¾Synopsys FPGA Compiler II

Manager ¾Xilinx Synthesis Technology (XST)

Verification Technologies Implementation

¾ModelSim Xilinx Edition ¾Floorplanner and PACE
¾Static Timing Analyzer ¾Constraints Editor
¾ChipScope Pro ¾Timing Driven Place & Route
¾XPower power estimation ¾Modular Design
¾Formal Verification support Board Level Integration ¾Incremental Design
¾3rd Party HDL simulation ¾IBIS Models ¾Timing Improvement Wizard
¾ChipViewer ¾STAMP Models
¾FPGA Editor with Probe ¾LMG Smart Models 3rd party partner tools
¾HDL Bencher testbench generator ¾HSPICE Models

One solution for all your logic design needs

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Xilinx Design Flow

Plan & Budget Create Code/ HDL RTL

Schematic Simulation
Functional Synthesize
Translate to create netlist


Place & Route

Attain Timing Timing Create

Closure Simulation Bit File

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Creating a Project

Select File Æ New Project

New Project Wizard guides
you through
the process
Project name
and location
Target device
Software flow
Create or add source

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Creating and Adding
Source Files

To include an existing source file,

double-click Add Existing Source
To create a new source file,
double-click Create New Source
and choose the type of file
HDL file
State diagram
Constraints file

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Text Entry

Color coding helps you quickly

understand and enter the design
Blue = Reserved words
Pink = Signal type
Green = Comments
Black = User input

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Language Templates

‹ Two methods to open templates:

Language Icon
Edit -> Language Templates
‹ Language Templates provide common
templates for designs:
Component instantiation
Language templates
Synthesis templates

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Schematic Source File

Files with .sch extension

Selecting this source type
will open the ECS (Engineering
Capture System) schematic editor

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Options and Symbols

The Options tab selections Components are divided into

change, depending on categories
which function is selected Exact symbols are located in the
For example, if you are Symbol box
adding a net name, the net
name options would be
Symbol Name Filter for easier
shown search
Rotate 0, 90,180, 270
Mirror and rotate 0, 90, 180,

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State Diagram Source

Files with .dia extension

Selecting this surce type
will invoke StateCAD

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Implementation Status

ISE will run all of the necessary steps

to implement the design
Synthesize HDL code
Place & Route
Progress and status are indicated by icons
Green check mark ( ) indicates that the process
was completed successfully
Yellow exclamation point ( ! ) indicates warnings
Yellow question mark ( ? ) indicates a file that is
out of date
Red “X” indicates errors

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Simulating a Design

To simulate a design:
In the Sources in Project window,
select a testbench file
In the Processes for Source window,
expand ModelSim Simulator
Double-click Simulate
Behavioral Model or
Simulate Post-Place & Route
• Can also simulate after Translate
or after Map

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Each process can be expanded to view

sub-tools and sub-processes
• Floorplan
• Assign Package Pins
• Analyze timing
Place & Route
• Analyze timing
• Floorplan
• FPGA Editor
• Analyze power
• Create simulation model

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Program the FPGA

There are two ways to program an

Through a PROM device
• You will need to generate a file
that the PROM programmer will
Directly from the computer
• Use the iMPACT configuration tool

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3rd Party Simulation Integration

ISE 6.1i is designed and tested to run with the leading HDL simulators in the
Cadence NC-Sim
Model Technology ModelSim
Synopsys VCS-MX and Scirocco
All Xilinx libraries and netlists conform to IEEE VHDL-93, VITAL-2000 and Verilog-
2001 standards
Other simulators are available to perform Xilinx CPLD and FPGA verification

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3rd Party Synthesis Integration

Synplify/Pro 7.3.1
Ability to use the parity bit in Virtex™-II, Virtex-II Pro™, and Spartan™-3
devices to optimize Block RAM implementations
Improved area optimization for Virtex-II, Virtex-II Pro, and Spartan-3 devices

Precision 2003b
Support Virtex-E/-II/-II Pro, Spartan-II/-IIE/-3
Advanced design analysis
LeonardoSpectrum 2003b
Support Spartan-3 family
FCII v3.8
Support for Spartan-3 devices
Support for all Virtex-II Pro devices

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Simulation Tool

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Simulation in the FPGA Environment

Source Templates and

Wizards, HDS, IPX,
RTL Simulation Design Entry
Xilinx LogiCORE,
CORE Generator
Highest performance
Many spins HDL RTL ModelSim
RTL Simulation
• highest throughput
Functional Simulation Leonardo Spectrum
• Does function match RTL Golden
model HDL Gate Functional ModelSim
Functional Simulation
Gate Level Simulation
• Highest impact on simulation run time Place & Route Xilinx ISE
• Full timing
• Does function match RTL Golden HDL Gate HDL Gate
Timing Timing VITAL or
model Verilog
Gate Level Simulation


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HDL Bencher

Creates timing constrained

VHDL and Verilog
self-checking testbenches
No knowledge of
HDL or scripting required

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Create a New Source

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Create a New Source

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HDL Bencher

Unit under test is analyzed, when

Port problems
Syntax violations

Design timing selected

Clocked or combinatorial?

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Create Waveforms

Data values
1, 0 ,X ,Z, U
Double-click bit signal to toggle value
Pattern wizard assigns a range of cell values
WaveTable assign signals like a spreadsheet
By default, decimal values are shown in the WaveTable
Waveform values are checked as they are entered
Validation check for non-binary inputs only (for example, hex, or decimal)

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Toggling bit values is the easiest way to assign bit signals

Simply click directly on the signal’s waveform at the time where changes should
take place

Click directly on these boxes, at the time

where signals should toggle

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Pattern Wizard

Aids complex waveform input

To access, click a signal at the time it should be changed to access value cell editor

Click in this area Click here for Pattern Wizard

Note: light blue background = input assignment,
light yellow background = output assignment

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Pattern Wizard

Available patterns

Pattern description
Changes depending on the
pattern selected

Count unit in clock cycles

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Waveform file extensions are TBW

Waveform file can be seen in the Sources in

Project window of the Project Navigator

To view testbench:
In Sources in Project Window, select the TBW file
Then in the Processes for Current Source window,
click View Behavioral Testbench

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Modelsim In ISE (FPGA)
•RTL Simulation

•Functional Simulation
•Does function match RTL
Golden model

•Gate Level Simulation

( only gate delay)

•Gate Level Simulation

( gate delay + wire delay)

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Modelsim In ISE

TestBench type code

Simulation process

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Top Answer Records Hits

#15338: How do I compile simulation Models

#16233: BlockRAM Collision Errors
#10629: What are $setup and $hold violations
#15501: How do I install SmartModels?
#6537: How do I use the glbl.v file for Verilog?
#15969: Using the ASYNC_REG constraint

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CORE Generator

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What are Cores?

A core is a ready-made function that you can instantiate into your design as a
“black box”
Cores can range in complexity
Simple arithmetic operators, such as adders, accumulators, and multipliers
System-level building blocks, including filters, transforms, and memories
Specialized functions, such as bus interfaces, controllers, and microprocessors
Some cores can be customized

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Sample Functions

LogiCORE solutions
DSP functions AllianceCORE solutions
• Time skew buffers, FIR filters, Peripherals
• DMA controllers
Math functions
• Programmable interrupt controllers
• Accumulators, adders, multipliers,
integrators, square root • UARTs
Memories Communications and networking
• Pipelined delay elements, single • ATM
and dual-port RAM • Reed-Solomon encoders / decoders
• Synchronous FIFOs • T1 framers
PCI master and slave interfaces, PCI Standard bus interfaces
bridge • PCMCIA, USB

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Invoking the CORE Generator System

From the Project Navigator, select

Project → New Source
Select IP (CoreGen & Architecture
Wizard) and enter a filename
Click Next, then select the type of

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Xilinx CORE Generator System GUI

Cores can be organized by function,

vendor, or device family

Core type, version, device

support, vendor, and status

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Core Customize Window

Core Overview tab provides version information

and a brief functional description

Parameters Web Links

tab allows tab provides
you to direct access
customize to related
the core Web pages
Contact tab provides
information about the vendor
Data sheet

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CORE Data Sheets

Performance expectations (not




Resource utilization

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Architecture Wizard

Architecture Wizard contains

two wizards:
Clocking Wizard
RocketIO Wizard
Double-click Create New
Select IP (CoreGen & Architecture
then click Next
• Expand Clocking and
select desired function
• Expand I/O Interfaces
and select RocketIO*

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DCM Wizard --General Setup Options

Select which pins are required

Define attributes:
Input Clock Frequency
CLKIN Source
Divide By Value
Feedback Source
Feedback Value
Duty Cycle Correction
Phase Shift (DPS)

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DCM Wizard– DFS setting

Frequency synthesizer
Select M / D value
Specify frequency
“Calculate” button for jitter
Period jitter is evaluated for CLKFX output

Note: This dialog appears only if the

CLKFX output was selected

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Where Can I Learn More?

Xilinx IP Center

Software updates
Download new cores as they are released
Tech Tips on
Software manuals: CORE Generator Guide
DCM constraints: Online Software Manuals → Constraints Guide
DCM architecture:
Virtex-II, Virtex-II Pro, Spartan-3 Data Sheets → Detailed Description
Virtex-II, Virtex-II Pro, Spartan-3 User Guides → Design Considerations → DCM
DCM timing parameters:
Virtex-II, Virtex-II Pro, Spartan-3 Data Sheets → Electrical Characteristics
Virtex-II, Virtex-II Pro, Spartan-3 Interactive Data Sheets →

© Memec (MG 001-04) 02.27.04