Electronic Devices and Circuits

(EL-324)
LABORATORY MANUAL
FALL 2016

(LAB# 11)
Study of Field Effect Transistors and their Curves
Engr. Muhammad Sajjad

Student Name: ___________________________

Roll No: _____________ Section: ___________

Date performed: _____________________, 2016

Manual Submission Date: ______________, 2016

_______________________________
LAB ENGINEER SIGNATURE & DATE

MARKS AWARDED: /10

______________________________________________________________________________________________________________________________________________________

NATIONAL UNIVERSITY OF COMPUTER AND EMERGING SCIENCES, ISLAMABAD

Prepared by: Engr. Naveed Iqbal Version: 2.0

Last Edited by: Engr. Muhammad Sajjad Updated: FALL 2016
Verified by: Dr. Durdana Habib
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LAB: 11 Study of Field Effect Transistors and Their Curves

Objectives of the Exercise:
 Introduction to Field effect transistors with emphasis on MOSFETs.
 Introduction to different characteristic parameters related to MOSFET and their Measurement/Calculation.
 Analysis of Transistor circuit to with the help of these parameters.

Equipment Required:
 PMOS(BS-250)
 Resistors
 Multimeter
 CRO
 Probes
 Jumper Wires
 Wire Stripper

Theory:
The acronym ‘FET’ stands for field effect transistor. It is a three-terminal unipolar solid state device
in which current is controlled by an electric field as is done in vacuum tubes.
Broadly speaking, there are two types of FETs:
1) Junction field effect transistor (JFET)
2) Metal-oxide semiconductor FET (MOSFET)
It is also called insulated-gate FET (IGFET). It may be further subdivided into:
a) Depletion- enhancement MOSFET i.e. DEMOSFET
b) Enhancement- only MOSFET i.e. E-only MOSFET
The FET family tree is shown below:

Fig 11.1: FET Family

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Structure of MOSFET:
The MOSFETs are the most widely used FETs. Strictly speaking, MOSFET devices belong to the
group of Insulated Gate Field Effect Transistor (IGFETs). As the name implies, the gate is insulated
from the channel by an insulator. In most of the cases, the insulator is formed by a silicon dioxide
(SiO2), which leads to the term MOSFET. MOSETs like all other IGFETs has three terminals, which
are called Gate (G), Source (S), and Drain (D). In certain cases, the transistors have a fourth terminal,
which is called the bulk or the body terminal. In PMOS, the body terminal is held at the most positive
voltage in the circuit and in NMOS, it is held at the most negative voltage in the circuit.

Fig 11.2: Physical Structure of MOSFET

a) Enhancement MOSFET i.e. EMOSFET:

If the channel between the drain and the source is an induced channel by applying volatges at
the gate, the transistor is called enhancement transistor.
b) Depletion MOSFET i.e. DEMOSFET
If the channel between the drain and the source I physically implmented, the transistor is
called depletion transistor.

Principle of the operation of a MOSFET:

When we put the drain and source on ground potential and apply a positive voltage to the gate, the
free holes (positive charges) are repelled from the region of the substrate under the gate (channel
region) due to the positive voltage applied to the gate. The holes are pushed away downwards into the
substrate leaving behind a depletion region. At the same time, the positive gate voltage attracts
electrons into the channel region. When the concentration of electrons near the surface of the substrate
under the gate is higher than the concentration of holes, an n region is created, connecting the source

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and the drain regions. The induced n-region thus forms the channel for current flow from drain to
source. The channel is only a few nanometres wide.

Fig 11.3: The enhancement-type NMOS transistor

with a positive voltage applied to the gate. An n channel is
induced at the top of the substrate beneath the gate

Now if a voltage is applied between drain and source electrodes an electron current can flow through
the induced channel. Increasing the voltage applied to the gate above a certain threshold voltage
enhances the channel.
In the case of an enhancement type NMOS transistor the threshold voltage is positive.
Whereas an enhancement type PMOS transistor has a negative threshold voltage.

Fig 11.4: An NMOS transistor with VGS > Vt and with a small VDS applied

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Properties:
Unlike the BJT, current flow is due to only one type of charge particles, either electrons (N-type)
or holes (P-type). So FET is known as unipolar device.
The name “field effect” is derived from the fact that the current is controlled by an electric field
set up in the device by an externally applied voltage (VGS). Thus FET is a voltage controlled device.
The gate-channel junction looks like a diode that never conducts hence the gate draws no current.
This is the major difference between normal transistors and FET. Consequently FETs have extremely
large gate input impedances.

MOSFET IV Characteristics:
Based on the physical foundation briefly established so far, we will introduce now the description of
the I-V characteristics of enhancement n-type MOSFETs. The output curves of an enhancement n-
type MOSFET are shown in figure below. The curves are called output curves, because the drain
current ID is shown as a function of drain source voltage, VDS. The drain current is shown for
different gate voltage VGS. Based on the output curves three different device regions of operation can
be distinguished: cut-off region, linear (triode) region and saturation region. Digital circuits usually
make excursions into all three regions, whereas analog circuits such as amplifiers typically only use
the saturation region.

Fig 11.5: OUTPUT Curves of NMOS

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MOSFET Regions of Operation:

a) Cut-off Region: MOSFETs are in the cut-off region when there is no current flow between
source and drain terminals. This happens when the gate-to-source voltage is less than the
threshold voltage, i.e., VGS < Vt.

b) Linear (Triode) Region: For voltages higher than the threshold voltage, the transistor
operates in the linear or triode region if at the same time the voltage VDS is smaller than VGS
− Vth. In this case, the current flow is a function of both gate-to-source voltage and the drain-
to-source voltage.

c) Saturation Region: The MOSFET is in the saturation region if VDS > VGS − Vth. In this
case, the drain current is primarily a function of the gate-to-source voltage,

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Testing a MOSFET :
1. Switch your multimeter to the Diode test position.
2. Hold the Black lead to the MOSFET's source terminal.

3. Touch the GATE terminal momentarily with the Red lead.

4. Then touch the DRAIN terminal with the Red lead without touching the GATE
terminal with your fingers.
5. The multimeter should show a low reading now. (The MOSFET is now ON)

6. With the RED and BLACK leads still connected to the DRAIN and Source terminals
of the MOSFET, now touch the GATE terminal with your finger. The Multimeter
should immediately show an open cct. (The MOSFET is now OFF)

Fig 11.6: NMOS Pin outs

Fig 11.7: Testing MOSFET with DMM

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LAB TASKS
Task 1:
Implement the following Circuit and then determine the values for the VG,VD,VS,VSD,VSG and ID .




V
DD VGG VG VD VS VSG VSD ID

10V 0V


10V 5V

Task 2:

Using the circuit shown above one can generate a set of drain characteristic curves that show how the
drain current ID, varies with the drain-to-source voltage VSD, for specified values of gate to source
voltages, VSG
1) First Set VDD and VGG equal to zero.
2) Measure VD, VG and VS. Justify the Readings that you get. What should be the ideal case
readings under this situation?
3) Increase the VGG to value mentioned in the table and obtain value of VSG , at this value fix the
VGG. Sweep the VDD according to the value in table, and record the values of ID at reasonable
points along the sweep.
4) The step shall generate a curve. This is the first curve among the set of curves which we shall
generate.
5) Repeat the above step for higher values of VGG and correspondingly a higher value of VSG.
6) Record the reading to generate a total of 5 curves.
7) Draw DC Load Line and identify the Cutoff and Saturation on the set of curves.

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Fill in the table according to your Readings and Draw the Plots for Id vs. Vsd on the same Graph.

Vdd Vsg, where Vgg=3v Id Vsd

4V
8V
12V
16V
20V

Vdd Vsg, where Vgg=4v Id Vsd

4V
8V
12V
16V
20V

Vdd Vsg, where Vgg=5v Id Vsd

4V
8V
12V
16V
20V

Vdd Vsg, where Vgg=6v Id Vsd

4V
8V
12V
16V
20V

Vdd Vsg, where Vgg=7v Id Vsd

4V
8V
12V
16V
20V

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Task 3:
 Using the data obtained during the previous task, draw characteristic curves.

Task 4:
A technician is using a digital multimeter (with a “diode check” feature) to identify the terminals
of a power MOSFET:

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The technician obtains the following “diode check” voltage measurements, in this order:

1. Black lead on middle terminal, Red lead on right terminal = 0.583 volts
2. Red lead on middle terminal, Black lead on right terminal = O.L. (open)
3. Black lead on middle terminal, Red lead on left terminal = O.L. (open)
4. Black lead on middle terminal, Red lead on right terminal = 0.001 volts
5. Red lead on middle terminal, Black lead on right terminal = 0.001 volts

Explain why the fourth and fifth measurements are so different from the first and second, respectively,

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Student's feedback: Purpose of feedback is to know the strengths and weaknesses of the
system for future improvements. This feedback is for the 'current lab session'. Circle your
choice:

[-3 = Extremely Poor, -2 = Very Poor, -1 = Poor, 0 = Average, 1 = Good, 2 = Very Good, 3 =
Excellent]:
The following table should describe your experience with:
S# Field Rating Describe your experience in words
1 Overall Session -3 -2 -1 0 1 2 3
2 Lab Instructor -3 -2 -1 0 1 2 3
3 Lab Staff -3 -2 -1 0 1 2 3
4 Equipment -3 -2 -1 0 1 2 3
5 Atmosphere -3 -2 -1 0 1 2 3

Any other valuable feedback:

__________________________________________________________________________
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Student's Signature: _________________________________

AWARDED

Correctness

Conclusion
Originality
of results

Initiative
Neatness
MARKS

Attitude

TOTAL

TOTAL 10 10 10 20 20 30 100

EARNED

Lab Instructor's
Comments:_________________________________________________________________
__________________________________________________________________________
__________________________________________________________________________

Lab Instructor's Signature: ________________________

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