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Trench Isolation
lat nc
w
Iso Tre
o
all
ow
Sh
all
Sh
n+ p+ p+ nn++ nnn+++
Substrate 070330-03
Comments:
• If the n+ to p+ spacing is large, the Bird’s beak can be compensated using techniques
such as poly buffered LOCOS
• At some point as the n+ to p+ spacing gets smaller, the restricted bird’s beak leads to
undesirable stress effects in the transistor.
• An important advantage of STI is that it minimizes the heat cycle needed for n+ or p+
isolation compared to LOCOS. This is a significant advantage for any process where
there are implants before STI.
;; ;
M4
Salicide Salicide M3
Salicide M2
M1
n+ n+ p+ p+
STI Source/drain STI Source/drain STI
extensions extensions
Deep p-well Deep n-well p-substrate
031211-02
In addition to NMOS and PMOS transistors, the technology provides:
1.) A deep n-well that can be utilized to reduce substrate noise coupling.
2.) A MOS varactor that can serve in VCOs
3.) At least 6 levels of metal that can form many useful structures such as inductors,
capacitors, and transmission lines.
Transistors
fT as a function of gate-source overdrive, VGS-V T (0.13μm):
Typical, 25°C
70
60 NMOS
Slow, 70°C
50
fT (GHz) 40
Typical, 25°C
20
10
0
0 100 200 300 400 500
|VGS-VT| (mV) 030901-07
The upper frequency limit is probably around 40 GHz for NMOS with an fT in the
vicinity of 60GHz with an overdrive of 0.5V and at the slow-high temperature corner.
Resistors
1.) Diffused and/or implanted resistors.
2.) Well resistors.
3.) Polysilicon resistors.
4.) Metal resistors.
Capacitors
Polysilicon-polysilicon
capacitors:
Metal-metal capacitors:
Protective Insulator Layer
Metal Via
Top
Vias connecting top Metal
Capacitor plate to top metal
dielectric Capacitor Top Metal Second level
Inter-
Vias connecting bottom from top metal
mediate
Capacitor bottom plate plate to lower metal Third level
Oxide
Layers Vias connecting bottom from top metal
plate to lower metal Fourth level
from top metal
060530-01
Inductors
Top view and cross-section of a planar inductor:
Top Metal
Top Metal
W
S Next Level
Metal
Vias Oxide
Next Level Oxide
Metal
D
Silicon Substrate
N turns
030828-01
D
Starting Material
The substrate should be highly doped to act like a good conductor.
Substrate
p+ n+
n-well p-well
Substrate
p+ n+
Shallow Shallow Shallow
Trench Trench Trench
Isolation Isolation Isolation
n-well p-well
Substrate
n+
Shallow Shallow Shallow
Trench Trench Trench
Isolation Isolation Isolation
n-well p-well
Substrate
p+ n+
Shallow Shallow Shallow
Trench Trench Trench
Isolation Isolation Isolation
n-well p-well
Substrate
p+ n+
Shallow Shallow Shallow
Trench Trench Trench
Isolation Isolation Isolation
n-well p-well
Substrate
Sidewall Sidewall
Spacers Spacers
p+ n+
Shallow Shallow Shallow
Trench Trench Trench
Isolation Isolation Isolation
n-well p-well
Substrate
n+ p+ p+ n+ n+ p+
implant implant implant implant implant implant
n+ p+ p+ n+ nn++ p+
Shallow Shallow Shallow
Trench Trench Trench
Isolation Isolation Isolation
n-well p-well
Substrate
Polycide Polycide
Substrate
Completed Fabrication
After multiple levels of metal are applied, the fabrication is completed with a thicker top-
level metal and a protective layer to hermetically seal the circuit from the environment.
Note that metal is used for the upper level metal vias. The chip is electrically connected
by removing the protective layer over large bonding pads.
Tungsten Plug
TEOS
SOG
Polycide
Sidewall
TEOS/BPSG Spacer
Poly
Gate
Fig. 2.8-20
Metal 3
Aluminum
Vias
Metal 2
Tungsten
Plugs
Metal 1
Transistors Fig.180-11
SUMMARY
• DSM technology typically has a minimum channel length between 0.35μm and 0.1μm
• DSM technology addresses the problem of excessive depletion region widths in
junction isolation techniques by using shallow trench isolation
• DSM technology may have from 4 to 8 levels of metal
• Lightly doped drains and sources are a key aspect of DSM technology