Documente Academic
Documente Profesional
Documente Cultură
endmodule
· The following Verilog HDL code implements a single-cycle CPU with
interrupt/exception mechanism
// instruction fields
// control signals
wire v; // overflow
// datapath wires
// control unit
regrt,m2reg,aluc,shift,
aluimm,pcsrc,jal,sext,
cause,exc,wsta,wcau,
wepc,mtc0,mfc0,selpc);
// datapath
endmodule
· The following Verilog HDL code implements the control unit of the single-
cycle CPU. Control signals related to interrupt and exceptions are added.
pcsrc,jal,sext,intr,inta,v,sta,cause,exc,wsta,wcau,wepc,
input z, v; // z, v flags
output wreg,regrt,jal,m2reg,shift,aluimm,sext,wmem;
wire i_addi = ̃op[5] &̃op[4] & op[3] &̃op[2] &̃op[1] &̃op[0]; // i format
wire i_andi = ̃op[5] &̃op[4] & op[3] & op[2] &̃op[1] &̃op[0];
wire i_ori = ̃op[5] &̃op[4] & op[3] & op[2] &̃op[1] & op[0];
wire i_xori = o
̃ p[5] &̃op[4] & op[3] & op[2] & op[1] &̃op[0];
wire i_lw = op[5] &̃op[4] &̃op[3] &̃op[2] & op[1] & op[0];
wire i_sw = op[5] &̃op[4] & op[3] &̃op[2] & op[1] & op[0];
wire i_bne = ̃op[5] &̃op[4] &̃op[3] & op[2] &̃op[1] & op[0];
wire i_lui = ̃op[5] &̃op[4] & op[3] & op[2] & op[1] & op[0];
wire i_j = ̃op[5] &̃op[4] &̃op[3] &̃op[2] & op[1] &̃op[0]; // j format
wire i_jal = o
̃ p[5] &̃op[4] &̃op[3] &̃op[2] & op[1] & op[0];
wire c0type = o
̃ p[5] & op[4] &̃op[3] &̃op[2] &̃op[1] &̃op[0];
wire i_eret = c0type & op1[4] &̃op1[3] &̃op1[2] &̃op1[1] &̃op1[0] &
// 0 1 : i_syscall
// 1 0 : unimplemented_inst
// 1 1 : overflow
// 0 1 : sta
// 1 0 : cau
// 1 1 : epc
// 0 1 : epc
// 1 0 : exc_base
// 11:x
assign wsta = exc | mtc0 & rd_is_status | i_eret; // write status reg
assign wreg = i_add | i_sub | i_and| i_or | i_xor| i_sll| i_srl| i_sra|
endmodule
· The following Verilog HDL code implements the ALU. Overflow flag output
v is added to the ALU.
module alu_ov (a,b,aluc,r,z,v); // 32-bit alu with zero and overflow flags
assign z = ̃|r; // z = (r == 0)
endmodule
· The following Verilog HDL code implements the instruction memory. Instead of
using general Verilog HDL statements, here we show how to use an LPM (library of
parameterized modules), provided by Altera, to implement memories. lpm_rom is a
read-only memory module and can be initialized with a memory initialization file
.inclock(), // no clock
.outclock(), // no clock
rom.lpm_widthad = 6, // 2 ̂ 6 = 64 words
endmodule
· The following Verilog HDL code implements the data memory. We also use LPM. lpm_ram_dq is a
synchronous random access memory module that needs a clock. The input signals of the
memory,including address, data in, and write control, must be registered using inclock. The output
signal can be either unregistered or registered using outclock.
endmodule