Core Deep Learning With Hifive Unleashed Expansion Kit

Core Deep Learning with
HiFive Unleashed Expansion Kit
Krishnakumar (KK)
Product Marketing
Programmable Solutions BU
Microsemi Corporation
© 2018 Microsemi, a wholly owned subsidiary of Microchip Technology Inc. 1
Agenda
 Introduction to Mi-V Ecosystem
 Mi-V HiFive Unleashed Expansion Board

• Hardware
• Tools
 Deep Learning with Microsemi FPGA and RISC-V

• Setup
• Convolutional Neural Network Overview
• Microsemi FPGA Advantage
• Deep Learning Demo
© 2018 Microsemi 2
Microsemi Invests In The RISC-V Ecosystem
 The Mi-V™ RISC-V ecosystem is a continually

expanding comprehensive suite of tools and
design resources to fully support RISC-V
designs.
 Mi-V™ ecosystem aims to increase adoption of

RISC-V ISA and Microsemi's soft CPU product
family.
 Introduced the first soft CPUs for FPGAs
 Mi-V ecosystem enabled numerous RTOS
© 2018 Microsemi 3
CPUs: Mi-V Soft CPU Roadmap
Core LE’s CoreMark Cache Mul/Div Floating Point Availability
CORE_RISCV_AXI4 10K 2.01 8K I and D Yes N/A Now
Mi_V_RV32IMA_L1_AHB 10K 2.01 8K I and D Yes N/A Now
Mi_V_RV32IMAF_L1_AHB 26K 2.01 8K I and D Yes Single Precision Now
Mi_V_RV32I_AHB 4K - N/A N/A N/A Q2’18
Mi_V_RV32IMA_L1_AXI 10K 2.01 8K I and D Yes N/A Q2’18
 Mi_V_RV32I_AHB Mi_V_RV32IMAFC_L1_AHB
• Small core, with debug, 4K LE’s Mi-V = Mi-V RISC-V Ecosystem
RV32I = 32 bit integer machine
M = Multiply and Divide
A = Atomic Instructions
 Additional cores can be added F = Single Precision Floating Point
D = Double Precision Floating Point
based on customer demand C = Compressed Instructions
L1 = Instruction and Data Cache
AHB = AHB Bus Interface
AXI = AXI Bus Interface
© 2018 Microsemi 4
Mi-V Eclipse Based IDE
Eclipse IDE Design Flow PMOD Arduino Shield
Firmware Sample MikroBus

Catalog Projects
Compiler Programmer/
JTAG Dongle
Demo/Eval Boards
Debugger
 A single tool chain for RISC-V and ARM MCUs

• Easy migration from ARM to RISC-V
 Running on Linux or Windows Hosts
 Bundled with example projects and RTOSs
 https://github.com/RISCV-on-Microsemi-FPGA
© 2018 Microsemi 5
Firmware Catalog
 Drivers for Microsemi RISC-V Soft CPUs

• Updates pushed to your desktop
• Release notes
• User guides
 Version Controlled
 MISRA/Netrino compliant
© 2018 Microsemi 6
Mi-V RISC-V Soft CPU RTOS Support Available Today
 Open Source
• FreeRTOS
• Huawei LiteOS
• MyNewt
• Zephyr
 Commercial
• Express Logic - ThreadX
• SiLabs - Micrium µC/OSIII
• Segger - embOS
These RTOS already run on the Mi-V soft RISC-V CPUs
© 2018 Microsemi 7
Solutions: Example Designs on Github
 Design examples targeted to various boards

• Hello world printf via UART
• Interrupt blinky
• Touch screen Tic-tac-toe
• Crypto processor with RISC-V
 Getting started building a RISC-V tutorial
© 2018 Microsemi 8
Mi-V Development and Evaluation Boards
Arrow Everest Board (Price $499)

Microsemi PolarFire Eval Kit (Price $1495)
Microsemi RTG4 Development Kit EVEREST-DEV-BOARD
MPF300-EVAL-KIT_ES
Microsemi PolarFire Splash Kit (Price $699) Future Avalanche Board (Price $179) Future RISCV Board (Price $99)
MPF300-SPLASH-KIT-ES AVMPF300TS-01 FUTUREM2GL-EVB
© 2018 Microsemi 9
HiFive Unleashed Development Platform
© 2018 Microsemi 10
Mi-V HiFive Unleashed Expansion: Advancing the Ecosystem
 Enables the community to port tools, OS’s, middleware, packages to RISC-V

 Makes software development easier
 Enables standard and custom peripherals
• Supporting the community supports our soft

CPUs for our FPGAs
• Supporting the community supports the Mi-V
ecosystem and vice versa
PolarFire HiFive Unleashed Development Platform
 Designed for
Expandability
 Pre-programmed with a
ChipLink to PCIe Root
Port Bridge
 Enables Root Complex on

the HiFive Unleashed
Board
 Stay tuned for FPGA

developer versions
PolarFire Mi-V HiFive Unleashed Development Platform
SiFive Motherboard
JTAG
JTAG
Power
Tree
SDCard
SPI SDCard
64b+ECC
SiFive
FMC
DDR4
U500
QSPI
SPI
Flash
GMII
GbE Ethernet
RJ45
MDI
PHY Switch
HiFive Unleashed + Unleashed Expansion Board
Resources
 Microsemi docs
• https://www.microsemi.com/hifive-unleashed-expansion-board
 Sifive Docs
• https://www.sifive.com/documentation/boards/hifive-unleashed/hifive-unleashed-getting-started-
guide/
 SiFive Forum
• https://forums.sifive.com/c/hifive-unleashed
 SiFive Freedom Unleashed SDK

• https://github.com/sifive/freedom-u-sdk
Where to Buy?
 CrowdSupply – Sold-out
• https://www.crowdsupply.com/microsemi/hifive-unleashed-expansion-board
 New campaign under plan
 For immediate needs, please contact me

• krishnakumar.r@microsemi.com
Deep Learning using Microsemi
FPGA and RISC-V
Inference Setup
Input data Trained Model Prediction
Deep Learning Setup
Training data Network training
Training algorithm
Evaluate
Inference
Model Prediction
Convolutional Neural Networks (CNNs)
Traditional Image Processing Pipeline

Input Output • Traditionally hand-crafted features
• Time consuming design
Pedestrian
Hand-Crafted Car
• Application Specific
SIFT, HOG, Gabor Trainable Animal
Filters etc. • Deep Learning
Road
• Feature Learning
Feature Extractor Classifier • Trainable Feature Extractor
• Requires lots of training data
Deep Learning
Input Output • Became viable with improvements
Trainable in
Pedestrian
Convolutional • Training Techniques
Layers with Car
optional pooling
Trainable Animal
• Availability of Training Data
and activation Road • Processing power
functions
Feature Extractor Classifier
Deep Learning Model
The Microsemi FPGAs Advantage
CNN Complexity
You Only Look Once:

Redmon et al, 2016
Convolution layers Fully connected layers
CNN Complexity Overview
Computation complexity External memory access

6.000 5.549 35.000
Weights required (Million)

29.360
Layer operations (GOP)
5.000 30.000
25.000
4.000 3.699 3.699
20.000
3.000
15.000
2.000 1.850
9.437
10.000
1.040 6.021
1.000 4.719
5.000
0.442 1.180
0.029 0.006 0.005
0.000 0.000
1 2 3 4 5 6 7 1 2 3 4 5 6 7
Convolution layers Fully connected layers Convolution layers Fully connected layers
INT8 Matrix Multiplication – Microsemi
Dot Product Matrix Computation

oj = a1*w11 + a1*w12 + a1*w13 + …. a2*w21 + a2*w22 + a2*w23 + ….
Figure: Math Block in PolarFire

CDL Design Space Exploration
• Implementation can either be

computation-bounded or memory- Computational roof (GOPS)
Attainable performance
bounded
• Model performance to off-chip
(GOPS)
memory traffic
Design 2
𝐶𝑜𝑚𝑝𝑢𝑡𝑎𝑡𝑖𝑜𝑛𝑎𝑙 𝑟𝑜𝑜𝑓
𝐴𝑡𝑡 𝑃𝑒𝑟𝑓 = 𝑚𝑖𝑛 ቊ Design 1
𝐶𝑇𝐶 𝑟𝑎𝑡𝑖𝑜𝑛 × 𝐵𝑊
Computation to communication ratio (OP/Byte

access)
A Scalable Solution
Tiny YOLO v2.0 – PolarFire vs Zynq US+
Parameters PolarFire Zynq UltraScale+
Frame Rate 30fps 16fps
Device Power 3.5W 6W
mAP
(mean average 45.1 48.5
precision score)
Operating
200MHz n/a
Frequency
Microsemi’s Advantage in Deep Learning Summary
Higher processing power due to efficient math block
Low power consumption
Scalable Deep Learning design provides optimum

performance for available resources
PolarFire Tiny Yolo Video
Thank You
krishnakumar.r@microsemi.com

Core Deep Learning With Hifive Unleashed Expansion Kit

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Core Deep Learning with

HiFive Unleashed Expansion Kit

 Introduction to Mi-V Ecosystem

 Mi-V HiFive Unleashed Expansion Board

 Deep Learning with Microsemi FPGA and RISC-V

 The Mi-V™ RISC-V ecosystem is a continually

 Mi-V™ ecosystem aims to increase adoption of

 Introduced the first soft CPUs for FPGAs

 Mi-V ecosystem enabled numerous RTOS

Firmware Sample MikroBus

 A single tool chain for RISC-V and ARM MCUs

 Drivers for Microsemi RISC-V Soft CPUs

These RTOS already run on the Mi-V soft RISC-V CPUs

 Design examples targeted to various boards

 Getting started building a RISC-V tutorial

Arrow Everest Board (Price $499)

 Enables the community to port tools, OS’s, middleware, packages to RISC-V

• Supporting the community supports our soft

 Enables Root Complex on

 Stay tuned for FPGA

 SiFive Freedom Unleashed SDK

 New campaign under plan

 For immediate needs, please contact me

Input data Trained Model Prediction

Training data Network training

Traditional Image Processing Pipeline

You Only Look Once:

Convolution layers Fully connected layers

Computation complexity External memory access

Weights required (Million)

Dot Product Matrix Computation

Figure: Math Block in PolarFire

• Implementation can either be

Computation to communication ratio (OP/Byte

Parameters PolarFire Zynq UltraScale+

Frame Rate 30fps 16fps

Device Power 3.5W 6W

Higher processing power due to efficient math block

Low power consumption

Scalable Deep Learning design provides optimum

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