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Ingo Sander
ingo@imit.kth.se
ASIC
RTL Model Post Synthesis Post Lay-Out Sell off
Placement
Development Logic Simulation Simulation
Ingo Sander ASIC Design 3 Ingo Sander ASIC Design 4
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The ASIC Design Process The ASIC Design Process
Post Synthesis Logic Simulation Floorplanning
– The synthesized circuit must be simulated, mainly to – Blocks are assigned
check if the timing is correct. Synthesis has introduced
library parts with delay, thus the simulation has to
for different
check for sufficient register setup and hold times or components on a
hazards, etc. chip.
System Partitioning Placement Routing
– If the gate-level circuit is very large, it may be needed
– Standard cells are – Connections are
to partition it into smaller parts. This may require the
repetition of earlier steps. placed within each made between cells
block and blocks
Ingo Sander ASIC Design 7 Ingo Sander ASIC Design 8
Design Compiler
ASIC Design Flow
(Synthesis Tool Suite)
SystemC VHDL / Verilog Liberty (.lib)
RTL / beh. RTL behavioral
Design
DC Ultra
Design Vision
FloorPlan
Manager
Compiler ACS DesignWare
Library
2
Synopsys Tool Suite Synopsys Tool Suite
RTL Synthesis RTL Synthesis
Synthesis FPGA Synthesis ClockTree Syn.
Sys temC Behav ioral
(V)H DL C. Presto Librar y Co mp iler
Com pil er VHD L / Ve rilogCom pil er
Design
Design
DC Ul tra Desig n Visi o n
FPGA
Compiler
Flo orPla n
Compiler
Ma na ger
Desig n
Com pil er
ACS
Compiler II
ClockTree
Test
DF TCCo
ommpiler
piler BSD C om piler Po wer Co m piler Mo dule C om piler
Compiler
Veri log, VHDL, EDIF Netl ist
Floorplanning
dc_shell
Floorplan
.db
S. + Placement Viewer/Editor
Milkyway
Physical Enterprise
Verilog Equivalence
Design
Compiler Design
GDS II
Columbia
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ASIC Synthesis Half-Adder
(Synopsys Design Compiler) (Implementation independent)
LIBRARY ieee;
• Report: USE ieee.std_logic_1164.ALL;
– This command documents the properties of the
synthesized circuit. ENTITY HalvAdder IS
PORT (
– It is important to understand the information given by a : IN std_logic;
the reports of the synthesis tool. b : IN std_logic;
s : OUT std_logic_vector(1 DOWNTO 0));
• Save: END HalvAdder;
– This command allows to save the design at each step.
The *.db format is used internally by Synopsys. The ARCHITECTURE Bool OF HalvAdder IS
BEGIN -- Bool
circuit can also be saved into VHDL-format (*.vhd) s(1) <= a AND b;
in order to allow for simulation of the synthesized s(0) <= a XOR b;
circuit. END Bool;
Half-Adder
Script for Half-Adder Synthesis
(Implementation independent)
analyze -format vhdl -lib WORK
./source/halvadder.vhd
elaborate HalvAdder -arch "Bool" -lib WORK -
update
write -format db -output ./unmapped/halvadder.db
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Synthesized VHDL Description Synthesized VHDL Description
library IEEE; library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;
use work.CONV_PACK_HalvAdder.all;
package CONV_PACK_HalvAdder is
-- define attributes entity HalvAdder is
attribute ENUM_ENCODING : STRING; port( a, b : in std_logic;
end CONV_PACK_HalvAdder; s : out std_logic_vector (1 downto 0));
end HalvAdder;
Report Files
Synthesized VHDL Description
(Timing)
architecture SYN_Bool of HalvAdder is ****************************************
component ad20 Report : timing
port( A, B : in std_logic; Z : out std_logic); -path full
end component; -delay max
-max_paths 1
Design : HalvAdder
component ex20
Version: 2002.05-SP2
port( A, B : in std_logic; Z : out std_logic);
Date : Fri Mar 14 11:11:10 2003
end component; ****************************************
begin
U7 : ad20 port map( A => b, B => a, Z => s(1)); Operating Conditions: quick_max Library:
U8 : ex20 port map( A => b, B => a, Z => s(0)); cx4001_core_max
end SYN_Bool; Wire Load Model Mode: top
Report Files
Critical Path
(Timing)
Startpoint: a (input port)
Endpoint: s<1> (output port)
Path Group: (none)
Path Type: max
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CX4001-Library Element CX4001-Library Element
AD20 EX20
Number of ports: 4
Number of nets: 4
Number of cells: 2
Number of references: 2
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Report Files Report Files
(Timing) (Area)
Point Incr Path Number of ports: 4
-----------------------------------------------------------
Number of nets: 5
input external delay 0.00 0.00 r
a (in) 0.00 0.00 r
Number of cells: 3
U7/Z (ex20) 0.30 0.30 r Number of references: 3
s<0> (out) 0.00 0.30 r
data arrival time 0.30 Combinational area: 6.000000
max_delay 0.00 0.00
Noncombinational area: 0.000000
output external delay 0.00 0.00 Net Interconnect area: undefined (No wire
data required time 0.00 load specified)
-----------------------------------------------------------
data required time 0.00 Total cell area: 6.000000
data arrival time -0.30
-----------------------------------------------------------
Total area: undefined
slack (VIOLATED)
Ideal delay vs. area curve Ideal delay vs. area curve
Delay Delay
Bad Startposition for the synthesis
algorithm
Area Area
7
To get a good starting position! Synthesis of a modulo-4 counter
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Counter03 IS
THINK
PORT (
clk : IN std_logic;
resetn : IN std_logic;
three : OUT std_logic);
END Counter03;
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Synthesis Result Timing Report
(CX4001-unconstrainded) (unconstrained)
Point Incr Path
-----------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
state_reg<1>/CP (dfnpc) 0.00 0.00 r
state_reg<1>/Q (dfnpc) 0.51 0.51 r
U45/Z (iv10s) 0.29 0.79 f
U49/Z (nd21) 0.32 1.12 f
U47/Z (ad20) 0.42 1.53 f
state_reg<0>/D (dfnpc) 0.00 1.53 f
data arrival time 1.53
Synthesis Result
Comparison
(CX4001-Speed)
Constraint
Unconstrained (Speed)
Delay 1.53 ns 0.85 ns
(Arrival Time)
Area 17.25 14.25
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Synthesis Result Altera MAX 7000 Family
(Max7000) (Macrocell)
T-Flip-Flop
Macrocell can be used as
combinational or sequential output
Delay: 1.5 ns
Timing Report
(MAX 7000)
Point Incr Path
-----------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
state_reg<0>/CLK (DFF) 0.00 0.00 r
state_reg<0>/Q (DFF) 1.00 1.00 f
U45/A_OUT (INV) 0.50 1.50 r
state_reg<0>/D (DFF) 0.00 1.50 r
data arrival time 1.50
Set-Up Time is
clock clk (rise edge) 10.00 10.00
clock network delay (ideal) 0.00 10.00 larger than
state_reg<0>/CLK (DFF) 0.00 10.00 r network delay!
library setup time -2.00 8.00
data required time 8.00
-----------------------------------------------------------
data required time 8.00
data arrival time -1.50
-----------------------------------------------------------
slack (MET) 6.50
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