Tn0613 Technical Note: ST System-On-Chip (Soc) Debug Interfaces

TN0613
Technical note
ST system-on-chip (SoC) debug interfaces
Synopsis
ST has developed an extensive family of debug interfaces that support host-target
connection and facilitate debug functionality.
The purpose of this document is to describe the target board requirements for connecting to
the various interfaces. It is intended to be read by board design engineers.
December 2011 8339250 Rev 3 1/19

www.st.com
Contents ST system-on-chip (SoC) debug interfaces
Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 JTAG interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Type A debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Type C debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Type H debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Type J debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 LVDS interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Type F debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Type G debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3 Type K debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/19 8339250 Rev 3

ST system-on-chip (SoC) debug interfaces Overview
1 Overview
Table 1 summarizes the relevant types of debug interface for custom board designs.
Table 1. Debug interfaces

Debug Debug
Features
interface support
– 20-way IDC target connection

Type A – notASEBRK JTAG
– 3V3 JTAG
Type C JTAG
– Automatic I/O voltage sensing
– LVDS connection
Type F JTAG
– notASEBRK
– LVDS connection
Type G – notASEBRK JTAG
– Altera ISP EPLD programming support
– MIPI-34 connection JTAG and
Type H
– Automatic I/O voltage sensing trace signals
– Intelligent software configurable LVDS connector JTAG and

Type I
(defined for use in future ST development boards) trace signals
Type J JTAG
– 3V3 JTAG
JTAG and
Type K – LVDS direct connection
trace signals
Note: 1 If your target board does not support trace, it is still possible to connect to one of the types
that does, for example a Type K, by not wiring in the trace pins.
2 Some connections have optional pins and these are identified in the appropriate pinout
description.
3 In the tables in this document, in the Signal direction column, “From SoC” means a signal
from the SoC on the processor board, and “To SoC” means a signal to the SoC on the
processor board.
8339250 Rev 3 3/19

JTAG interfaces ST system-on-chip (SoC) debug interfaces
2 JTAG interfaces
This chapter describes the various JTAG interfaces in the following sections:
● Section 2.1: Type A debug interface
● Section 2.2: Type C debug interface on page 6
● Section 2.3: Type H debug interface on page 8
● Section 2.4: Type J debug interface on page 11
2.1 Type A debug interface

Type A is a 2 x 10-way IDC connection (Figure 1) providing a standard JTAG debug
interface. The wiring of a Type A debug interface on the processor board is shown in
Figure 2 and Figure 3.
This interface should be used on ST40-based development boards.
Figure 1. JTAG debug 2 x 10-way IDC connector
19 1
20 2
Table 2. Type A pin allocation

Pin Signal name Signal direction Pin Signal name Signal direction
Even
GROUND Not applicable 11 TCK To SoC
pins
1 Reserved Not applicable 13 TDI To SoC
3 TRIGOUT From SoC 15 TDO From SoC
5 TRIGIN To SoC 17 notSYSRESET To SoC
7 notASEBRK Bi-directional 19 notTRST To SoC
9 TMS To SoC
4/19 8339250 Rev 3

ST system-on-chip (SoC) debug interfaces JTAG interfaces
Figure 2. Type A JTAG interface wiring
Processor board
VREF
SoC
10 K
JTAG interface connector
47R TRIGOUT
TRIGIN
47R notASEBRK1
TMS
TCK
TDI
47R TDO
notSYSRESET
notPOWERONRESET
notTRST
10 K
1. Only connect for SoCs with notASEBRK support.
Figure 3. Type A with TAPMux JTAG interface wiring
Processor board
VREF
SoC
10 K
47R TRIGOUT
TRIGIN
47R notASEBRK1
TMS
TCK
TDI
47R TDO
notSYSRESET
notPOWERONRESET
notTRST
10 K
1. Only connect for SoCs with notASEBRK support.
8339250 Rev 3 5/19

2.2 Type C debug interface

Type C is a 2 x 10-way IDC connection (Figure 4) providing a standard JTAG debug
interface. The wiring of a Type C debug interface on the processor board is shown in
Figure 5.
This interface should be used on STxP70 and ARM-based (not Cortex-A9) development
boards.
19 1
20 2
Table 3. Type C pin allocation

1 VREF From SoC 2 VSUPPLY From SoC

3 notTRST To SoC 4 GROUND
5 TDI To SoC 6 GROUND
7 TMS To SoC 8 GROUND
9 TCK To SoC 10 GROUND
11 RTCK From SoC 12 GROUND Not applicable
13 TDO From SoC 14 GROUND
15 notSYSRESET Bi-directional 16 GROUND
17 DBGRQ To SoC 18 GROUND
19 DBGACK From SoC 20 GROUND
Note: VREF between 1V8 and 3V3 must be provided from the SoC in order to support
Multi-volt I/O.
6/19 8339250 Rev 3

Figure 5. Type C JTAG interface wiring
Processor board
VREF
SoC
10 K
47R DBGACK
DBGRQ
TMS
TCK
TDI
47R TDO
notPOWERONRESET notSYSRESET
notTRST
RTCK1
10 K
1. Only connect for SoCs with RTCK support.
8339250 Rev 3 7/19

2.3 Type H debug interface

Type H is used to define a MIPI-34 connection (Figure 6) that provides both standard JTAG
signals and trace signals in two voltage domains.
● The voltage of the JTAG signals are defined by VREF_DEBUG.
● The voltage of the trace signals are defined by VREF_TRACE.
The wiring of a Type H debug interface on the processor board is shown in Figure 7.
This interface should be used on ARM Cortex-A9 based development boards.
Further information on the MIPI connectors can be found in the MIPI Alliance
Recommendation for Test & Debug: Debug and Trace Connectors (TDC), version 1.00.00,
MIPI Alliance Inc., 5 June 2007.
Figure 6. MIPI-34 connector

33 1
34 2
Table 4 lists the required pin allocation for the MIPI-34 connector on the target board.
Note: Connection to the trace signals by the target is optional, depending on whether your target
supports trace or not.
Table 4. Type H pin allocation

Pin Signal name Description Signal direction Voltage
JTAG signals
1 VREF_DEBUG Debug port reference voltage.
2 TMS IEEE 1149.1 JTAG signal To SoC VREF_DEBUG
3 GROUND N/A
4 TCK IEEE 1149.1 JTAG signal To SoC VREF_DEBUG
5 GROUND N/A
6 TDO IEEE 1149.1 JTAG signal From SoC VREF_DEBUG
7 KEY Pin removed N/A
8 TDI IEEE 1149.1 JTAG signal To SoC VREF_DEBUG
This pin is GROUND on the target board and
connects to TARGET_PRESENCE_DETECT
9 GROUND From SoC
(+3V3) on the host, using a weak pull-up on
the host interface.
8/19 8339250 Rev 3

Table 4. Type H pin allocation (continued)

Pin Signal name Description Signal direction Voltage
Target reset signal. Open drain active low

10 notSYSRESET signal. May be used bi-directional to drive or To SoC VREF_DEBUG
sense the target reset signal.
11 GROUND N/A
Return debug clock (optional). If unused tie to
12 RTCK From SoC VREF_DEBUG
GROUND.
13 GROUND N/A
IEEE 1149.1 JTAG signal with pull-down
14 TRST_PD From SoC VREF_DEBUG
resistor on target
15 GROUND N/A
16 notTRST IEEE 1149.1 JTAG signal To SoC VREF_DEBUG
17 GROUND N/A
18 TRIGIN Target debug halt request To SoC VREF_DEBUG
19 GROUND N/A
20 TRIGOUT Target debug halt acknowledge From SoC VREF_DEBUG
Trace signals
21 GROUND N/A
Trace clock pin. If unused should be
22 TRC_CLK connected to GROUND or driven to a low From SoC VREF_TRACE
logic level.
23 GROUND N/A
24 TRC_DATA0 Trace data pin. If unused tie to GROUND. From SoC VREF_TRACE
25 GROUND N/A
27 GROUND N/A
29 GROUND N/A
31 GROUND N/A
User selectable,
Asynchronous serialized control stream to
32 TRC_EXT To SoC defaults to
configure the trace port on the target.
VREF_DEBUG
33 GROUND N/A
34 VREF_TRACE Trace port reference voltage.
8339250 Rev 3 9/19

Figure 7. Type H JTAG interface wiring
Processor board
VREF
SoC
10 K
47R TRIGOUT
TRIGIN
TMS
TCK
TDI
47R TDO
notPOWERONRESET notSYSRESET
notTRST
RTCK1
1. Only connect for SoCs with RTCK support, otherwise pulldown.
10/19 8339250 Rev 3

2.4 Type J debug interface

Type J is a 2 x 5-way IDC connection (Figure 8) providing a JTAG debug interface. It is used,
for example, on the STi7111-SAT platform for the target debug connection.
The wiring of a Type J debug interface on the processor board is shown in Figure 9.
This interface should be used on ST40-based development boards with a reduced pinout.
9 1
10 2
Table 5. Type J pin allocation

1 TCK To SoC 2 notASEBRK Bi-directional

3 TMS To SoC 4 GROUND
5 TDO From SoC 6 GROUND N/A
7 TDI To SoC 8 GROUND
9 notTRST To SoC 10 notSYSRESET To SoC
Figure 9. Type J JTAG interface wiring
Processor board
VREF
SoC
10 K
47R notASEBRK1
TMS
TCK
TDI
47R TDO
notSYSRESET
notPOWERONRESET
notTRST
10 K
8339250 Rev 3 11/19

LVDS interfaces ST system-on-chip (SoC) debug interfaces
3 LVDS interfaces
This chapter describes the various LVDS interfaces in the following sections:
● Section 3.1: Type F debug interface
● Section 3.2: Type G debug interface
● Section 3.3: Type K debug interface on page 16
An example of an LVDS connector is shown in Figure 10.
Figure 10. LVDS host-target connector
34 1
68 35
Note: All LVDS signals should be buffered using a suitable LVDS buffer.
The pin definitions for the LVDS connectors include four CODE pins. These are read by the
ST Micro Connect to identify the type of connection used. For a Type F connection the code
pins are set as 0101, for a Type G connection the code pins are set as 0110 and for a Type
K connection the code pins are set as 1000.
The wiring of Type F and Type G debug interfaces on the processor board is shown in
Figure 11.
12/19 8339250 Rev 3

ST system-on-chip (SoC) debug interfaces LVDS interfaces
Figure 11. Target board Type F and Type G circuitry

STMC2 Type F circuitry +3V3
notBoardReset
R319
TARGET
10K
IC53
CN32
CODE = 0101 = Type 'F'
MAX9122 PROCESSOR
For 1.6mm PCB 2
CODE = 0110 = Type 'G' LVDS_notTRST+ R364
STMC_LVDSCON 15
notTRST
R360 LVDS_notTRST- 1 0R
68 0R
68 34 34 R361 DNF
R362 DNF LVDS_notRESET+ 3
67 R365
67 33 33 R363 0R 14
LVDS_notRESET- 4 0R
66
66 32 32
LVDS_TDI+ 6
65 R366
11
65 31 31 TDI
LVDS_TDI- 5 0R
64
64 30 30
LVDS_CLKIN+ 7
63 R367
10
63 29 29 TCK
LVDS_CLKIN- 8 0R
62 +3V3_LVDS
62 28 28
LVDS_notTRST- 16
R318
R320
R369
61
10K
10K
10K
61 27 27 LVDS_notTRST+ 9 LVDSBUF_notEN
60 VCC=+3V3_LVDS
60 26 26
59 LVDS_notRESET-
59 25 25 LVDS_notRESET+
58 LVDS_MODE_SEL-
58 24 24 LVDS_MODE_SEL+
IC54
57 LVDS_TDI- MAX9123
57 23 23 LVDS_TDI+
LVDS_USEROUT+ 15
56 2
56 22 22 notASEBRK
LVDS_CLKIN- LVDS_USEROUT- 16
55
55 21 21 LVDS_CLKIN+
LVDS_TRIGOUT+ 14
54 3 R322 47R
54 20 20
+3V3
TrigOut
LVDS_CLKOUT- LVDS_TRIGOUT- 13
53
53 19 19 LVDS_CLKOUT+
LVDS_TDO+ 11
52 +5V_LVDS 6 R321 47R
52 18 18 TDO
R368
10K
LVDS_TDO- 12
51
51 17 17 TP253
R370
10K
LVDS_CLKOUT+ 10
50 7
50 16 16 LVDSBUF_notEN
LVDS_CLKOUT- 9
49 +3V3_LVDS
49 15 15
LVDS_EPLD_SPARE3- 1
48 8
48 14 14 LVDS_EPLD_SPARE3+ LVDSBUF_notEN
47 LVDS_TDO-
VCC=+3V3_LVDS +3V3 +3V3
47 13 13 LVDS_TDO+
46 LVDS_EPLD_SPARE2-
46 12 12 LVDS_EPLD_SPARE2+
LVDS_TRIGOUT-
R373
R371
45
10K
10K
45 11 11 LVDS_TRIGOUT+
IC55
44 LVDS_EPLD_SPARE1- MAX9122
44 10 10 LVDS_EPLD_SPARE1+
LVDS_USEROUT- LVDS_TMS+ 2
43 R372
15
43 9 9 LVDS_USEROUT+ TMS
LVDS_EPLD_TDO- LVDS_TMS- 1 0R IC50-1
42 74LCX07
42 8 8 LVDS_EPLD_TDO+
R323
10K
LVDS_TMS- LVDS_USERIN+ 3
41 14 1 2
41 7 7 LVDS_TMS+
LVDS_EPLD_TCK- LVDS_USERIN- 4
40 VCC=+3V3
40 6 6 LVDS_EPLD_TCK+
LVDS_USERIN- LVDS_TRIGIN+ 6
39 11
39 5 5 LVDS_USERIN+ TrigIn
LVDS_EPLD_TMS- LVDS_TRIGIN- 5
38
38 4 4 LVDS_EPLD_TMS+
LVDS_TRIGIN- LVDS_SPAREIN+ 7 240R
37 10
37 3 3 LVDS_TRIGIN+
R374
10K
LVDS_EPLD_TDI- LVDS_SPAREIN- 8 R382
36 +3V3_LVDS 1
36 2 2 LVDS_EPLD_TDI+ GREEN
LVDS_SPAREIN- 16
35 9 LD9-B
35 1 1 LVDS_SPAREIN+ LVDSBUF_notEN
2
VCC=+3V3_LVDS
SHIELD=CHASSIS
Pins 1-34 = SCSI-5 +VE signals

Pins 35-68 = SCSI-5 -VE signals
STMC2 Type G extra circuitry
NOTE: If remote power on feature used, buffers should be powered from STMC2 +5V_LVDS.
+5V_LVDS IC52
R375
LP3964-3.3 +3V3_LVDS
1K
L42 2 Vin Vout 3

3V3
R317
FBEAD_SMT
10K
800mA notRemotePowerOn
600mA
C482 C481 1 notSD ADJ 4 C484 C491 C483 C488 C487 C489 C485 TR5
GND
20V 50V 20V 50V 50V 50V 50V 50V 50V MMBT2222A e.g. Connect to ATX P_ON signal.
47u 1U 47u 100n 100n 100n 100n 100n 100n
5
IC57
MAX9122
LVDS_MODE_SEL+ 2
R379
15
TargetDebugModeSel
LVDS_MODE_SEL- 1 0R e.g. Connect to processor mode pin to force boot from JTAG.
LVDS_EPLD_TCK+ 3
R380
14
AuxTck
LVDS_EPLD_TCK- 4 0R
LVDS_EPLD_TMS+ 6
R383
11
AuxTms
LVDS_EPLD_TMS- 5 0R
LVDS_EPLD_TDI+ 7
R384
10
AuxTdi
LVDS_EPLD_TDI- 8 0R
+3V3
16 +3V3
9
R359
3 10K
VCC=+3V3_LVDS 2 TARGET EPLD
J26-A 1 LVDSBUF_notEN
IC56
MAX9123
LVDS_EPLD_TDO+ 15
2
AuxTdo
LVDS_EPLD_TDO- 16
LVDS_EPLD_SPARE1+ 14
3
UserFeedback1
LVDS_EPLD_SPARE1- 13
6
UserFeedback2
LVDS_EPLD_SPARE2- 12
7
notPowerOnReset
LVDS_EPLD_SPARE3- 9
+3V3_LVDS
1
8 LVDSBUF_notEN
VCC=+3V3_LVDS
8339250 Rev 3 13/19

3.1 Type F debug interface

Type F is used to define a 68-pin LVDS connection (see Figure 10) that provides a JTAG
debug interface. It does not provide an EPLD programming interface.
Note: This interface is not recommended for new designs, Type G should be used instead.
Table 6 lists the target pin allocation.
Table 6. Type F pin allocation

Signal Signal
Pin Signal name Pin Signal name
direction direction
1 LVDS_SPAREIN+ To SoC 35 LVDS_SPAREIN- To SoC

2 NC N/A 36 NC N/A
3 LVDS_TRIGIN+ To SoC 37 LVDS_TRIGIN- To SoC
4 NC N/A 38 NC N/A
5 LVDS_notASEBRKOUT_notSRST+ From SoC 39 LVDS_notASEBRKOUT_notSRST- From SoC
6 NC N/A 40 NC N/A
7 LVDS_TMS+ To SoC 41 LVDS_TMS- To SoC
8 NC N/A 42 NC N/A
9 LVDS_USEROUT+ From SoC 43 LVDS_USEROUT- From SoC
10 NC N/A 44 NC N/A
11 LVDS_TRIGOUT+ From SoC 45 LVDS_TRIGOUT- From SoC
12 NC N/A 46 NC N/A
13 LVDS_TDO+ From SoC 47 LVDS_TDO- From SoC
14 NC N/A 48 NC N/A
15 GROUND N/A 49
GROUND N/A
16 LVDSBUF_notEN To SoC 50
17 51
+5V_LVDS N/A +5V_LVDS N/A
18 52
19 LVDS_CLKOUT+ From SoC 53 LVDS_CLKOUT- From SoC
20 GROUND N/A 54 GROUND N/A
21 LVDS_CLKIN+ To SoC 55 LVDS_CLKIN- To SoC
23 LVDS_TDI+ To SoC 57 LVDS_TDI- To SoC
24 NC N/A 58 NC N/A
25 LVDS_notSYSRESET+ To SoC 59 LVDS_notSYSRESET- To SoC
26 NC N/A 60 NC N/A
27 LVDS_notTRST+ To SoC 61 LVDS_notTRST- To SoC
28 NC N/A 62 NC N/A
14/19 8339250 Rev 3

Table 6. Type F pin allocation (continued)

Signal Signal
direction direction
29 63
30 64
NC N/A NC N/A
31 65
32 66
33 CODE3 (GROUND) From SoC 67 CODE2 (Do not connect) From SoC
3.2 Type G debug interface

Type G is used to define a 68-pin LVDS connection (see Figure 10) that provides a JTAG
debug interface and an EPLD programming interface. It is used, for example, on the
HD-GEN-MB peripheral board for the target debug connection.
Table 7. Type G pin allocation

Signal Signal
direction direction
1 LVDS_SPAREIN+ To SoC 35 LVDS_SPAREIN- To SoC

2 LVDS_EPLD_TDI+ To SoC 36 LVDS_EPLD_TDI- To SoC
4 LVDS_EPLD_TMS+ To SoC 38 LVDS_EPLD_TMS- To SoC
6 LVDS_EPLD_TCK+ To SoC 40 LVDS_EPLD_TCK- To SoC
8 LVDS_EPLD_TDO+ From SoC 42 LVDS_EPLD_TDO- From SoC
9 LVDS_USEROUT+ From SoC 43 LVDS_USEROUT- From SoC
10 BOOT_FROM_ROM_FEEDBACK1+ From SoC 44 BOOT_FROM_ROM_FEEDBACK1- From SoC
14 LVDS_notSYSRESET_RTN+ From SoC 48 LVDS_notSYSRESET_RTN- From SoC
15 GROUND N/A 49
GROUND N/A
16 LVDSBUF_notEN To SoC 50
17 51
18 52
8339250 Rev 3 15/19

Table 7. Type G pin allocation (continued)

Signal Signal
direction direction

24 LVDS_MODE_SEL+ To SoC 58 LVDS_MODE_SEL- To SoC
26 NC N/A 60 NC N/A
28 62
29 63
30 NC N/A 64 NC N/A
31 65
32 66
34 CODE1 (Do not connect) From SoC 68 CODE0 (GROUND) From SoC
3.3 Type K debug interface

Type K is used to define a 68-pin LVDS connection (see Figure 10 on page 12) that provides
a debug and trace signal interface. It is used, for example, on the STiH415-HVK board for
target debug and trace connection.
Table 8. Type K pin allocation

Signal Signal
direction direction
JTAG signals
1 LVDS_PWRON+ To SoC 35 LVDS_PWRON- To SoC
2 LVDS_EPLD_TDI+ To SoC 36 LVDS_EPLD_TDI- To SoC
4 LVDS_EPLD_TMS+ To SoC 38 LVDS_EPLD_TMS- To SoC
6 LVDS_EPLD_TCK+ To SoC 40 LVDS_EPLD_TCK- To SoC
8 LVDS_EPLD_TDO+ From SoC 42 LVDS_EPLD_TDO- From SoC
9 NC N/A 43 NC N/A
16/19 8339250 Rev 3

Table 8. Type K pin allocation (continued)

Signal Signal
direction direction

14 LVDS_notSYSRESET_RTN+ From SoC 48 LVDS_notSYSRESET_RTN- From SoC
15 GROUND N/A 49
GROUND N/A
16 LVDS_BUF_notEN To SoC 50
17 51
18 52
Trace signals
24 NC N/A 58 NC N/A
26 LVDS_STMRTN+ To SoC 60 LVDS_STMRTN- To SoC
28 LVDS_STMDATA0+ From SoC 62 LVDS_STMDATA0- From SoC
32 LVDS_STMCLK+ From SoC 66 LVDS_STMCLK- From SoC
33 CODE3 (Do not connect) From SoC 67 CODE2 (GROUND) From SoC
34 CODE1 (GROUND) From SoC 68 CODE0 (GROUND) From SoC
8339250 Rev 3 17/19

Revision history ST system-on-chip (SoC) debug interfaces
4 Revision history
Table 9. Document revision history

Date Revision Changes
04-Aug-2011 1 Initial release.

Updated Table 1: Debug interfaces on page 3 to include Type F.
Added Figure 3: Type A with TAPMux JTAG interface wiring on
page 5.
Updated Chapter 3: LVDS interfaces on page 12 to include Type F.
17-Nov-2011 2 Added Figure 11 on page 13 and Section 3.1: Type F debug
interface on page 14.
Corrected Type K code pins value in Chapter 3: LVDS interfaces on
page 12.
Corrected Code pin settings in Table 7: Type G pin allocation on
page 15.
Changed name of document to ST system-on-chip (SoC) debug
06-Dec-2011 3
interfaces.
18/19 8339250 Rev 3

ST system-on-chip (SoC) debug interfaces
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ST system-on-chip (SoC) debug interfaces

December 2011 8339250 Rev 3 1/19

2/19 8339250 Rev 3

Table 1. Debug interfaces

– 20-way IDC target connection

– Intelligent software configurable LVDS connector JTAG and

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2.1 Type A debug interface

Figure 1. JTAG debug 2 x 10-way IDC connector

Table 2. Type A pin allocation

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Figure 2. Type A JTAG interface wiring

1. Only connect for SoCs with notASEBRK support.

Figure 3. Type A with TAPMux JTAG interface wiring

1. Only connect for SoCs with notASEBRK support.

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2.2 Type C debug interface

Figure 4. JTAG debug 2 x 10-way IDC connector

Table 3. Type C pin allocation

1 VREF From SoC 2 VSUPPLY From SoC

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Figure 5. Type C JTAG interface wiring

1. Only connect for SoCs with RTCK support.

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2.3 Type H debug interface

Figure 6. MIPI-34 connector

Table 4. Type H pin allocation

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Table 4. Type H pin allocation (continued)

Target reset signal. Open drain active low

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Figure 7. Type H JTAG interface wiring

1. Only connect for SoCs with RTCK support, otherwise pulldown.

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2.4 Type J debug interface

Figure 8. JTAG debug 2 x 5-way IDC connector

Table 5. Type J pin allocation

1 TCK To SoC 2 notASEBRK Bi-directional

Figure 9. Type J JTAG interface wiring

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Figure 10. LVDS host-target connector

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Figure 11. Target board Type F and Type G circuitry

Pins 1-34 = SCSI-5 +VE signals

STMC2 Type G extra circuitry

L42 2 Vin Vout 3

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3.1 Type F debug interface

Table 6. Type F pin allocation

1 LVDS_SPAREIN+ To SoC 35 LVDS_SPAREIN- To SoC

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Table 6. Type F pin allocation (continued)

3.2 Type G debug interface

Table 7. Type G pin allocation

1 LVDS_SPAREIN+ To SoC 35 LVDS_SPAREIN- To SoC

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Table 7. Type G pin allocation (continued)

20 GROUND N/A 54 GROUND N/A

3.3 Type K debug interface

Table 8. Type K pin allocation

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Table 8. Type K pin allocation (continued)