Course Coverage

VLSI Course covers the following broad areas:

Industry focused &
Placement oriented- VLSI Front-End:
Basic Engineering Circuit Analysis
Design Training Programme Digital Design: Combinational Logic and
Sequential Logic with Timing analysis.
Verilog HDL
System Verilog & DFT basics
SEMICON Labs, a premier VLSI training
PERL scripting / C-shell/Tcl scripting
institute, offers a 6-month Industry focused,
Placement oriented training programme in VLSI Design
in Hyderabad.

SEMICON Labs has been closely associated with M/S

Adept Chips Services Pvt Ltd, a VLSI design services
organization based out of Bangalore.

Course Flow:
This VLSI course is primarily backend-oriented covering,
Physical design (PD) & Physical Validation (PV).
However, a detailed focus is given to fill gaps in digital
design concepts & Verilog HDL. The course is framed
with 4 months of classroom sessions & 2 months hands
on Project.

The course will be handled by persons having a rich

experience in the VLSI industry. Theory sessions will be Back-End:
ably backed by lab sessions where each student will get Floor Planning
exposure to latest EDA tools from Cadence / Mentor Placement & Routing
Graphics. During this course students will also get the Static Timing Analysis (STA)
benefit of Guest lectures and Tech-Talks from Silicon Macro / SC Based layout Techniques
Industry professionals. During the course and also at the DRC / ERC
end, the students are assessed and ranked based on Parasitic Extraction & Routing Delays
their performance. Overall, the course content and
coverage is focused on the fundamentals and concepts
to raise the standard of the students to set their career
paths in the industry.
Eligibility:
Graduate engineers (2018/2019) in
ECE/EEE/IE/MSc.(Electronics) who have secured at Placement:
least 65% marks in BE / BTech / ME / MTech are eligible About 10-12 top performers
to apply. Candidates must not have any backlogs at the will be absorbed by Adept Chip
time of applying. Services Pvt Ltd. and a few other
Silicon Service organisations based
on their requirements. This absorption
will be based on performance in the
Selection Criteria: screening interview. Placement will be as
Interested candidates may send their resumes to per industry standard package. Potential
anand.moghe@semiconlabs.com on or before 15th opportunity will exist for a few to get
DEC , 2019. Entrance test of duration One hour for the paid Internships.
selection of candidates will be held in Hyderabad and
the date / time of entrance test will be informed to the Placement assistance will be
candidates through email. Candidates will be tested in provided for all other
General Aptitude and basics of Electrical Engineering., (remaining) students on
Digital Design, C language and CMOS principles. successful completion
of 6 months course.
Selection to the course will be based on the
performance in the written test and personal interview
(only for candidates who qualify in written test).

Apply by 31st December 2019

Course is expected to start on 15th Jan, 2020.

Intake: 28

Course Fee:
VLSI Course (Front End & back end) Course Director:
Module: Rs 1,00,000/- (Rupees one Anand S Moghe
lakh only) to be paid across three
installments. Contact : anand.moghe@semiconlabs.com
WebSite : www.semiconlabs.com
Mail To: hr@semiconlabs.com
Phone: 9000923262
9347822722

Venue:
Semicon Labs SEMICON LABS
12-13-26 Vissvaas Crest, Street No 5, Krishnagiri Enclave, A PREMIER VLSI TRAINING INSTITUTE
Tarnaka, Hyderabad 500007
INDUSTRY FOCUSED & PLACEMENT ORIENTED
(Near Sanman Hotel at Tarnaka Crossroads)