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Module 7 (3 hours):
Circuit-level low power techniques and power
estimation basics
Jan. 2007
Eui-Young Chung
School of Electrical and Electronic Engineering
Yonsei University
Course
Course Goals
Goals
2
Contents
Contents
3
Trend
Trend of
of power
power consumption
consumption
4
Trend
Trend of
of power
power consumption
consumption
5
Trend
Trend of
of power
power consumption
consumption
6
Trend
Trend of
of power
power consumption
consumption
7
Contents
Contents
8
Types
Types of
of power
power dissipation
dissipation
z Dynamic power
z By charging and discharging capacitances
z Short-circuit power
z Due to the short duration in which both NMOS and PMOS are
turned on
z Static power
z Can be ideally ignored in CMOS, but in pseudo NMOS
z Leakage power
z Reverse biased PN-junction current
9
Dynamic
Dynamic power
power
dvc (t )
ic (t ) = CL
dt
t1
Es = ∫ Vic (t )dt
t0
t1 dvc (t ) V
Es = CLV ∫ dt = CLV ∫ dvc = CLV 2
t0 dt 0
t1 t1 dvc (t ) V 1
Ecap = ∫ vc (t )ic (t )dt = CL ∫ vc (t ) dt = CLV ∫ vc dvc = CLV 2
t0 t0 dt 0 2
1
Ec = Es − Ecap = CLV 2 (Ed is same to Es)
2
P = Es f = CLV 2 f
10
Short-circuit
Short-circuit power
power
z Output loading
z Energy dissipation
z β
E short = τ ( V tp − V tn ) 3
12
z β: transistor size
z τ: the duration of input signal
11
Impact
Impact of
of load
load capacitance
capacitance
12
Impact
Impact of
of input
input slope
slope
ic increase decrease no
change
13
Leakage
Leakage power
power
z Leakage mechanisms
14
Leakage
Leakage mechanisms
mechanisms
15
Two
Two major
major leakage
leakage components
components (I)
(I)
z Largely depends on
z Fabrication process
z Junction area
z Temperature
16
Two
Two major
major leakage
leakage components
components (II)
(II)
17
Contents
Contents
18
Power
Power and
and the
the circuit
circuit design
design styles
styles
19
Nonclocked
Nonclocked –
– Fully
Fully complementary
complementary logic
logic
z Aka. CMOS
z Active mode
z Switching / short-circuit current
z Glitches or spurious transistions due to different delays
through different paths of the circuit
z Stand-by mode
z Leakage current
z High noise margin Î can reduce the threshold voltage
z Performance degrading factor
z Large PMOS Î Large input capacitance / weak output
driving
20
Nonclocked
Nonclocked –
– NMOS
NMOS and
and pseudo-NMOS
pseudo-NMOS
NMOS Pseudo-NMOS
21
Nonclocked
Nonclocked –
– DCVS
DCVS
22
Nonclocked
Nonclocked –
– Pass
Pass transistor
transistor logic
logic (PTL)
(PTL)
Level restorer
Domino NAND
24
Clocked
Clocked –
– DCSL1
DCSL1
25
Clocked
Clocked –
– DCSL2
DCSL2
26
Clocked
Clocked –
– DCSL3
DCSL3
27
Leakage
Leakage concisous
concisous design
design -- SATS
SATS
z SATS
z Self-adjusting threshold voltage scheme
z Measure the leakage of a representitive MOS
z If the measured value > the expected value
z Decrease the back bias for NMOS, increase it for PMOS
z Vth will be increased
28
Leakage
Leakage concisous
concisous design
design -- MTCMOS
MTCMOS
z Multithreshold CMOS
z Uses both high- and low-threshold voltage MOSFETs
z Active mode: SL is set to high / Sleep mode: SL is set to low
z The “on” resistance of sleep transistors is small
z Some designs only use eigther header or footer
z Cell-based MTCMOS Î area penalty / easy to design
z Block-based MTCMOS Î area efficiency / hard to design
29
Leakage
Leakage conscious
conscious design
design -- DTMOS
DTMOS
30
Special
Special latches
latches and
and flip-flops
flip-flops
31
Example
Example of
of low
low power
power flip-flops
flip-flops
32
Self-gating
Self-gating flip-flop
flip-flop
33
Double
Double edge
edge flip-flop
flip-flop
34
Contents
Contents
35
Sizing
Sizing –
– Inverter
Inverter chain
chain (I)
(I)
z Assumption
z Fixed P/N size ratio for all inverters Î Same rise/fall time
z Fixed stage ratio Î K
z Simple analysis: Ci/Ci-1 = K Î CN/C0 = KN
z N = ln(CN/C0) / lnK
36
Sizing
Sizing –
– Inverter
Inverter chain
chain (II)
(II)
z Delay
z D = NKd = ln(CN/C0) * (K /
lnK) * d
z d: intrinsic delay of the N −1 N −1
K N −1
P = ∑ Pi = ∑ K i P0 = P0
inverter under a single load i =0 i =0 K −1
z D is minimized when K = e τ
P0 = C1V 2 f + τS 0 f = Kf (C0V 2 + S0 )
z Power K
z Pi = KPi-1 P0 ∝ K , K n = C N / C0
z P = IV P∝
K
z V: unchanged
K −1
z I = C(dv/dt)
37
Sizing
Sizing –
– Inverter
Inverter chain
chain (III)
(III)
z Power/Delay vs. K
38
Contents
Contents
39
Circuit-level
Circuit-level power
power analysis
analysis
40
SPICE
SPICE basics
basics
41
SPICE
SPICE power
power analysis
analysis
42
Discrete
Discrete transistor
transistor modeling
modeling // analysis
analysis
z Typical methods
z Circuit model
z Approximate the complex equations into a linear equation
z Tabular transistor model
z Express the transistor models in tabular forms
z Switch model
z Consider a transistors as a two-state switch (on / off)
43
Circuit
Circuit model
model
I ds = f (Vgs , Vds )
∂ ∂
≈ f (Vgso , Vdso ) + f (Vgso , Vdso )(Vgs − Vgso ) + f (Vgso , Vdso )(Vds − Vdso )
∂Vgs ∂Vds
ids ≈ i0 + g m v gs + rds
44
Tabular
Tabular transistor
transistor model
model
45
Switch
Switch model
model
I ds = f (Vgs , Vds )
∂ ∂
≈ f (Vgso , Vdso ) + f (Vgso , Vdso )(Vgs − Vgso ) + f (Vgso , Vdso )(Vds − Vdso )
∂Vgs ∂Vds
46
Contents
Contents
47
Power
Power characterization
characterization for
for cell
cell library
library
48
Power
Power characterization
characterization flow
flow
010110
110111 A large # of
Circuit
000100 current Average Power
……… Simulator
waveforms
Probability Analysis
Average Power
Values tools
49
Simulation-based
Simulation-based cell
cell characterization
characterization
z Parameters
z Input pattern (logical value)
z Input slope
z Output loading capacitance
z Process condition
z Total # of runs of simulation is the multiplication of the
possible number of values of each parameter
z Some parameters are continuous
z Input slope, output loading capacitance
z Piece-wise linear approximation is widely used
z Process / operation condition: BEST / TYPICAL / WORST
50
Example:
Example: 2-input
2-input NAND
NAND (I)
(I)
8 simulation runs!
51
Example:
Example: 2-input
2-input NAND
NAND (II)
(II)
z Input slope
z Depending on the predecessor
z Capacitance
z Depending on the successor
z proportional to the # of fan-outs
z If we consider four points for capacitance
z Total # of simulation runs for a single input
z 2 (rise / fall) * 4 (# of input slopes) * 4 (# of capacitance
points) = 32 points
52
Example:
Example: 2-input
2-input NAND
NAND (III)
(III)
z Total # of simulations
z For dynamic power
z (2 * 2) * S * C * P
z For static power
z 22 * P
53
Additional
Additional factors
factors to
to be
be characterized
characterized
z Output slope
z Used as an input slope of the successor
z Need to know for each simulation point
z Input capacitance
z Used for computing the total output capacitance of the
predecessor
z Can be esitmated by the area of gate (W/L) and tox
z Parasitics: Cgs / Cgd
z All the information should be included in the library
54
Tool
Tool flow
flow
input pattern
generator
Circuit
simulator
Simulation
Analyzer
55
Contents
Contents
56
Probability-based
Probability-based power
power estimation
estimation
57
Modeling
Modeling of
of signals
signals
58
Signal
Signal probability
probability and
and activity
activity
z Signal probability
1 +T
P ( g ) = lim
T →∞ 2T ∫
−T
g (t )dt
z P(g=1) : signal probability
z Signal activity
ng (T )
A( g ) = lim
T →∞ T
z ng(t): # of transitions of g(t) in the time interval
between –T/2 and +T/2
59
Signal
Signal probabilities
probabilities of
of simple
simple gates
gates
z Assumption z Inverter
z g1, g2, …, gn are independent
z Output signal probability
z Determined by the given z AND gate
boolean function
z NOT: 1 –
z AND: multiply
z OR gate
z OR Î NOT (NOT (OR))
60
Signal
Signal probability
probability calculation
calculation (I)
(I)
61
Signal
Signal probability
probability calculation
calculation (II)
(II)
z n: # of independent inputs
z p: # of products
z αi: some integer
z Called as the sum of probability products of f
62
Signal
Signal probability
probability calculation
calculation (III)
(III)
p n
P( f ) = ∑ α i (∏ P
li , k
z mi , k
( xk ) P ( xk ))
i =1 k =1
z P( xi ) = P( xi ) = 1 − P( xi )
z mi,k and li,k are either 0 or 1, cannot be 1 simultaneously
z sk = xk or x’k
63
Signal
Signal probability
probability calculation:
calculation: Example
Example
64
Signal
Signal probability
probability using
using BDD
BDD (I)
(I)
z f xi = f ( x1 ,...,0, xi +1 ,..., xn ) c
z Example
0 1
z f = ab + c
65
Signal
Signal probability
probability using
using BDD
BDD (II)
(II)
z P(f)
z P ( x1 • f x1 + x1 • f x )
1
z P( x1 • f x1 ) + P( x1 • f x1 )
z P( x1 ) • P( f x1 ) + P ( x1 ) • P( f x1 )
66
Summary
Summary
67
References
References
z http://public.itrs.net
z Gary K. Yeap, “Practical Low Power Digital VLSI Design”,
Kluwer Academic Publishers, 1997
z Kaushick Roy and Sharat C. Prasad, “Low Power CMOS
VLSI: Circuit Design”, Wiley Interscience, 2000
z Kiat-Seng Yeo, Kaushik Roy, “Low Voltage, Low Power
VLSI Subsystems”, McGraw-Hill, 2004
68
Assignment
Assignment
69