Documente Academic
Documente Profesional
Documente Cultură
Submitted By
Pramod M (05EC78)
BACHELOR OF TECHNOLOGY
October 2008
1
Design And Layout Of 2KB SRAM Memory
For 180nm Technology
June 2008
This report details the training in the area of Mixed Signal Design at Sankalp
Semiconductor,Hubli. The training involved lectures on Mixed Signal Design
flow and basic circuit theory including operation on MOSFETs.This report
contains the implementation of SRAM memory in 180nm technology and
the issues involved in layout design.The memory is implemented using Ca-
dence tools namely Schematic-Composer,Virtuso,Assura.The access time for
memory is intended to be within 20ns.
Acknowledgment
1
Contents
1 Introduction 3
3 Project Definition 6
4 Memory Architecture 7
7 Conclusion 24
2
Chapter 1
Introduction
The Semiconductor industry tries to catchup with Moore’s law by scaling the
size of the devices. Reduction in the size of the device guarantees reduction
of its parasitic capacitances but,the parasitics of the metal interconnect be-
comes dominant and the leakage current of the device becomes significantly
large.A well designed layout of chip ensures better performance.
In a typical CMOS chip, nearly 90% of the chip area is occupuied by dig-
ital circuits whereas only around 10% is occupied by analog.As more and
more discrete components get intergrated into the chip, its important that
the interface between them is well defined. As an example consider a mo-
bile phone that can play FM and mp3 and record videos. This requies a
separate RF module for FM reception,an mp3 decoder, DSP processor for
video compression, a memory module to store the video, power management
unit to signal sleep and wake cycle and most importantly the RF module for
high frequncy telephone signal tranception. All these modules if integrated
on a PCB requires a lot of area and the mobile becomes clumsy and power
hungy. Integrating all the modules on a single chip saves power and hence
it becomes compact and reliable.This nessasiates a robust analog design
for the chip that can sense the analog world and process them digitally and
provide the results back to environment.
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Chapter 2
In the design of a Analog MOS chip the following steps are involved [1].
1. System Specification: The system requirements are defined in this
stage by specifying quantities like power consumption, interface signals,
frequency of operation, input and output relationship,technology for
fabrication,supply voltage etc. are specified. Certain quantities may
be more specific to a particular design like for an op amp quantities
like slew rate,bandwidth etc.
2. Architecture: The complete architecture of the design is specified,
in this stage of top down design the specifications of the individual
modules in the whole system is defined.Multiple architectures undergo
a system simulation and the most optimal design is chosen.
3. Circuit Design: Circuits for each of the modules are designed and
simulated for different process corners to meet the specifications.These
corners are :
(a) Process Corner: During the fabrication of the chip, there will be
process variation across the wafer and across the chip. Due to
these variations devices may have different threshold voltages,this
affects the speed of the device.The circuit must satisfy the specifi-
cations even with these variations.So all the pmos are assumed to
be fast and the nmos to be slow and the simulation is done with
this assumption and for other permutations also.
(b) Temperature variations: The design has to be robust to tempera-
ture variations in the range of −40◦ C to 125◦ C.
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(c) Power Supply variations: The circuit must be able to reject the
noise in the power supply and tolerate a variation ±10%.
4. Layout: The circuit is laid out for a given technology and a Design
Rule Check (DRC) and Layout vs Schematic (LVS) is performed. Once
the layout is extracted for parasitics,this netlist is simulated and con-
formed with the specifications(Back annotation).
After each of the steps simulations are performed to ensure the specifica-
tions are not violated. If the design deviates from the specifications the cycle
restarts from the previous steps.
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Chapter 3
Project Definition
The following are the specifications for 2KB SRAM memory to be designed
with 180nm technology.
1. Access time tA (time to access the data after providing valid address )
:20ns
6
Chapter 4
Memory Architecture
7
Chapter 5
The SRAM memory will include the following blocks which will be detailed
in the subsequent sections [3].
1. Bit Cell: This is the basic storage element in the memory.
3. Sense Amplifier: Amplifies the difference between the bit and bit lines
thereby reducing tread .
4. Write Circuit: Selectively discharges either bit or bit line for writing
data.
5. Column Decoder: Selects one of the 16 columns of the bit cells ⇒ 4:16
Decoder.
6. Row Decoder: Selects one of the 128 rows of bit cells ⇒ 7:128 Decoder.
8
Figure 5.1: Schematic of the bit cell
The figure 5.1 shows the layout of the bit cell using 180nm technology.The
dimensions of the bit cell is 3.6µm × 4.55µm.The supply to the bit cell is by
M etal1 and runs horizontally whereas the ground lines uses M etal2 and runs
vertically.The extracted netlist contained around 208 parasitic capacitors.
The cell is designed ssymmetricallyso that the cells can be arrayed.
The simulation of the read and write operation is shown in figures 5.1
and 5.1 respectively.
5.2 Precharge
The precharge circuit is used to charge the bit and bit bar lines to the supply
voltage before a read or write operation. The load capacitance of the seen by
the precharge circuit is the large pparasiticcapacitance of the bit and bit bar
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Figure 5.2: Layout of the bit cell
lines. This circuit uses a large pmos ttransistorof width 12µm and it is enable
by EN signal.The figure 5.2 shows the schematic.
The layout of the precharge ccircuitis shown in figure 5.2. The Metal 1
at the ccenterand at the extremes is connected to Vdd and the pmos source
is connected to the bit and bit bar lines.
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Figure 5.3: Simulation of Bit cell read operation
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Figure 5.4: Simulation of bit cell write operation
12
Figure 5.5: Schematic of the precharge circuit
13
Figure 5.6: Layout of the precharge circuit
14
Figure 5.7: Schematic of Sense amplifier
15
Figure 5.9: Simulation of extracted netlist of Sense amplifier
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Figure 5.10: Schematic of Write Circuit
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Figure 5.11: Layout of Write circuit
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Figure 5.13: Layout of Column Decoder
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Figure 5.14: Simulation of extracted netlist of Column Decoder
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Figure 5.15: Schematic of 3:8 deoderdecoderayout of 7:128 decoder
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Figure 5.16: Simulation of extracted netlist of 7:128 decoder
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Chapter 6
23
Chapter 7
Conclusion
24
Figure 7.1: Layout of 2KB SRAM
25
Bibliography
[4] http://www.cedcc.psu.edu/khanjan/vssram.htm
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