ICT114

Examination – July Semester 2019

Computer Architecture
Wednesday, 13 November 2019 1:00 pm – 3:00 pm

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Time allowed: 2 hours

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INSTRUCTIONS TO STUDENTS:

1. This examination contains FOUR (4) questions and comprises SEVEN (7)
printed pages (including cover page).

2. You must answer ALL questions.

3. All answers must be written in the answer book.

4. This is a closed-book examination.

5. Calculators are NOT allowed in this examination.

6. E114 processor instruction set summary (Appendix 1) and a partial ASCII codes
table (Appendix 2) are attached.

At the end of the examination

Please ensure that you have written your examination number on each answer book used.

Failure to do so will mean that your work cannot be identified.

If you have used more than one answer book, please tie them together with the string
provided.

THE UNIVERSITY RESERVES THE RIGHT NOT TO MARK YOUR

SCRIPT IF YOU FAIL TO FOLLOW THESE INSTRUCTIONS.

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Examination – July Semester 2019
Answer all questions. (Total 100 marks)

Question 1

An 8-bit microprocessor has an 8-bit wide memory. Explain how the data is represented,
structured and stored in the following scenarios:

(a) If 8-bit 2’s complement representation is used to represent integers, what is the
range of decimal values it can represent?
(3 marks)

(b) An 8-bit binary code word 1101 01102 is to be interpreted as a fixed-point fraction
with four bits before and four bits after the binary point. Assume that both the
integral and fractional parts are unsigned representation. Express your answer as
a decimal number. Show your working.
(3 marks)

(c) Use the binary and decimal number systems to express TWO (2) unsigned
magnitude integers 3716 and A216 in 8-bit binary and decimal, respectively.
(4 marks)

(d) Given A = 3310 and B = 6510.

(i) Express the decimal numbers 3310 and 6510 in 8-bit sign-magnitude
representation.
(2 marks)

(ii) Show how the microprocessor computes the arithmetic operation 3310 –
6510 in 2’s complement representation. Convert the result to decimal and
show it is equal to -32. Show your working.
(6 marks)

(e) This microprocessor uses the specifications shown in Figure Q1(e) for 32-bit
floating point number representation. If the representation in hexadecimal
number is 40E0, determine the decimal value of the representation.

Figure Q1(e)
(7 marks)

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Examination – July Semester 2019
Question 2

(a) Sketch a block diagram of a simple system bus architecture consisting of a data
bus, an address bus and a control bus. The diagram should include a CPU block,
a memory block and an I/O block.
(6 marks)

(b) Describe the main function of the control bus.

(2 marks)

(c) Describe TWO (2) problems of this bus architecture.

(4 marks)

(d) A computer system has a 20-bit address bus and can address an 8-bit wide
memory. The memory contains:

32 Kbytes of system ROM, and

512 Kbytes of user RAM

The system ROM and user RAM form a contiguous block of memory starting at
address 0. The rest of the address range after user RAM is not used.

Draw the memory map for this computer system. Indicate the starting and ending
addresses in hexadecimal for each block of memory and any unused space. Show
how the memory addresses are obtained.
(13 marks)

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Examination – July Semester 2019
Question 3

This question is based on the EASY68K simulated processor. Assume the contents of all
data and address registers are equal to zero before the start of the program. All numbers
are in hexadecimal.

Demonstrate how instructions of the program are executed by using the E114 Processor
Instruction Set of the EASY68K simulator.

Figure Q3 shows an incomplete main program and a subroutine. The program is designed
to test each value in an array of positive integers. For each array element, if the value is
equal to 5, it is replaced by 8, i.e. the program overwrites the original array value.
Otherwise, the value remains unchanged.

ORG $1000
START MOVE.B #$08, D0
MOVE.L #$0300, A1
LOOP BSR TEST
SUB.B <<1>>, D0
BNE <<2>>
STOP #$2700

ORG $1100
TEST <<3>> A1, A2
MOVE.B (A1)+, D1
SUB.B <<4>>, D1
BNE <<5>>
MOVE.B <<6>>, (A2)
B1 RTS

END START

Figure Q3

(a) The main program includes a loop. Which register is being used as a loop counter?
How many elements are there in the array?
(2 marks)

(b) State the lowest and highest addresses of the array in hexadecimal.
(2 marks)

(c) Determine the missing items <<1>> to <<6>> to create the complete program.
(12 marks)

(d) Identify the addressing mode used in each of the following instructions:

(I) MOVE.L #$0300, A1

(II) MOVE.B (A1)+, D1
(III) MOVE.B $500, D2
(IV) MOVE D3, D4
(4 marks)

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Examination – July Semester 2019
(e) (i) What is a stack?
(2 marks)

(ii) Describe TWO (2) important usages of a stack.

(3 marks)

Question 4

Discuss the use of different techniques in Input/output modules by answering the

following questions.

(a) Describe the differences between memory-mapped I/O and isolated I/O.
(12 marks)

(b) Software poll and hardware poll are two methods a processor uses to identify
which device issued an interrupt. Briefly describe these TWO (2) methods.
(6 marks)

(c) Describe ONE (1) disadvantage each for software poll and hardware poll.
(3 marks)

(d) Describe how software poll and hardware poll assign priorities when more than
one device is requesting for interrupt service.
(4 marks)

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Examination – July Semester 2019
 Appendix 1 E114 Processor Instruction Set Summary
Operation NZ BWL Description Remarks
Move
MOVE <EA1>,<EA2> ** XXX move data

Arithmetic
ADD <EA1>, An or Dn ** XXX add binary
SUB <EA1>, An or Dn ** XXX subtract binary

Logical
AND <EA3>, Dn ** XXX logical AND
NOP <EA3>, Dn -- no operation
OR <EA3>, Dn ** XXX logical OR
NOT Dn ** XXX logical NOT

Control
BRA <Label> -- branch always
BSR <Label> -- branch subroutine
BNE <Label> -* branch not equal
BMI <Label> *- branch on negative
BPL <Label> *- branch on positive
JMP <Label> -- jump always
RTS -- return from subroutine
STOP #$2700 stop
- flag not affected , * flag affected
<EA1> = Dn, An, (An), (An)+, $<data>, #$<data>
<EA2> = same as <EA1> except #$<data>
<EA3> = Dn, #<data>

An: Address register A0 to A7

Dn: Data register D0 to D7
(An) : Content of address whose address is in An
(An)+: Similar to (An) but after instruction An=An+1 for.B, An+2 for .W and An+4 for .L
$nnnn: 16-bit Hexadecimal address
$nnnnnnnn: 32-bit Hexadecimal address
#$nn: 8-bit immediate Hexadecimal data
#$nnnn: 16-bit immediate Hexadecimal data
#$nnnnnnnn: 32-bit immediate Hexadecimal data

T121 Stack operation

MOVE.L Dn,-(A7)
- Push operation: Dn data store on the stack. A7-4 =A7 after operation
MOVE.L (A7)+,Dn
Pop operation: Stack data is put back to Dn. A7+4 =A7 after operation

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Examination – July Semester 2019
 Appendix 2 Partial ASCII Table
Char Binary Hex Char Binary Hex Char Binary Hex
00100000 20 A 01000001 41 a 01100001 61
! 00100001 21 B 01000010 42 b 01100010 62
" 00100010 22 C 01000011 43 c 01100011 63
# 00100011 23 D 01000100 44 d 01100100 64
$ 00100100 24 E 01000101 45 e 01100101 65
% 00100101 25 F 01000110 46 f 01100110 66
& 00100110 26 G 01000111 47 g 01100111 67
‘ 00100111 27 H 01001000 48 h 01101000 68
( 00101000 28 I 01001001 49 i 01101001 69
) 00101001 29 J 01001010 4A j 01101010 6A
* 00101010 2A K 01001011 4B k 01101011 6B
+ 00101011 2B L 01001100 4C l 01101100 6C
, 00101100 2C M 01001101 4D m 01101101 6D
- 00101101 2D N 01001110 4E n 01101110 6E
. 00101110 2E O 01001111 4F o 01101111 6F
/ 00101111 2F P 01010000 50 p 01110000 70
0 00110000 30 Q 01010001 51 q 01110001 71
1 00110001 31 R 01010010 52 r 01110010 72
2 00110010 32 S 01010011 53 s 01110011 73
3 00110011 33 T 01010100 54 t 01110100 74
4 00110100 34 U 01010101 55 u 01110101 75
5 00110101 35 V 01010110 56 v 01110110 76
6 00110110 36 W 01010111 57 w 01110111 77
7 00110111 37 X 01011000 58 x 01111000 78
8 00111000 38 Y 01011001 59 y 01111001 79
9 00111001 39 Z 01011010 5A z 01111010 7A

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Examination – July Semester 2019