SEMESTER’S TEACHING PLAN

COMMUNITY COLLEGE MINISTRY OF HIGHER EDUCATION MALAYSIA

Module Lecturer : AHMAD KHAIRULNIZAM B. ZULKIFLI Session : JULY

2010
Module Code & Name : ETE 315 - DIGITAL SYSTEM FUNDAMENTALS Course :
STE 4

Assessment
Week
(Quiz / Test / Implementati
(Planning Topic, Sub Topic and Objectives Notes
Assignment / on Date
Date)
Hands-on)
Submit RMS to
12 – 16
ORIENTATION WEEK KJKK / Program
July 2010 Leader

Week 1 1.0 NUMBER SYSTEM

Objective: At the end of this lesson,
student will able to: Tutorial 1
20 July 2010
(4 hour) 1.1Explain the decimal, binary, octal and
hexadecimal number systems and convert
from one system to another.
1.1.1 Explain the binary number system:
23 July 2010 Quiz 1
a. Summation
(1 hour)
b. Subtraction
1.1.2 Convert binary number to decimal
number and vice versa.
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 1.1.3 Convert octal number to binary number
and vice versa.
1.1.4 Convert hexadecimal number and vice
versa.

Week 2 2.0 CODE SYSTEM

27 July 2010 Objective: At the end of this lesson,

student will able to: Assignment 1
(4 hour)
30 July 2010 2.1 Explain BCD-binary code.
2.1.1 Convert BCD code to binary and vice
(1 hour)
versa.

Week 3 2.0 CODE SYSTEM

3 Aug 2010 Objective: At the end of this lesson,

student will able to: Practical 1
(4 hour)
2.1 Explain BCD-binary code.
2.1.2 Identify the applications
6 Aug 2010
a. Decoder display circuit logic diagram.
(1 hour)
b. Encoder display circuit logic diagram.

Week 4 3.0 LOGIC GATES

10 Aug 2010 Objective: At the end of this lesson,

1ST FRP Check
(4 hour) student will able to:
3.1 Identify logic gates, symbols, operation
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13 Aug 2010 and function of each
(1 hour) gate.
3.1.1 Introduction to logic.

Week 5 3.0 LOGIC GATES

Objective: At the end of this lesson,

17 Aug 2010 student will able to:

(4 hour) 3.1 Identify logic gates, symbols, operation
and function of each
gate. Test 1
20 Aug 2010
3.1.2 Draw and identify the symbol of the
(1 hour)
following logic gates:
a. NOT gate.
b. AND gate.
c. OR gate.
d. NAND gate.
e. NOR gate.
f. Exclusive-OR gate.
g. Exclusive-NOR gate.

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 Week 6 3.0 LOGIC GATES

24 Aug 2010 Objective: At the end of this lesson,

(4 hour) student will able to:
3.1 Identify logic gates, symbols, operation
and function of each
24 Aug 2010
gate.
(1 hour)
3.1.3 Draw the electrical equivalent circuit of
the above logic
gates operation.
3.1.4 Explain the function of the logic gates
above.
3.1.5 Explain the applications of gates above.

Week 7 3.0 LOGIC GATES

3 Sept 2010 Objective: At the end of this lesson, Practical 2

(5 hour) student will able to:

3.1 Identify logic gates, symbols, operation
and function of each
gate.
3.1.6 Construct the output table of he logic
gates above.
3.1.7 Identify the logic IC for the gates above
from the data
sheets.
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 3.1.8 Identify the IC pins from the data
sheets.
3.1.9 Construct and test the logic gates
above using IC on a
breadboard to get the output.

6 –17
SEMESTER BREAK
Sept 2010

Week 8 4.0 LOGIC NETWORK

21 Sept Objective: At the end of this lesson,

2010 student will able to:

(4 hour) 4.1 Combinational logic gates to produce logic

networks and the
application of Boolean identities.
24 Sept
4.1.1 Construct NAND gate using AND and
2010
NOT gates.
(1 hour)

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 Week 9 4.0 LOGIC NETWORK

28 Sept Objective: At the end of this lesson,

student will able to: Assignment 2
2010
(4 hour) 4.1 Combinational logic gates to produce logic
networks and the
application of Boolean identities.
1 Oct 2010
4.1.2 Construct NOR gate using OR and NOT
(1 hour)
gates.

Week 10 4.0 LOGIC NETWORK

5 Oct 2010 Objective: At the end of this lesson,

(4 hour) student will able to:

4.1 Combinational logic gates to produce logic
networks and the
8 Oct 2010
application of Boolean identities.
(1 hour)
4.1.3 Use Boolean identities.
4.1.4 Construct combinational logic circuit
from a Boolean
expression.

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 Week 11 4.0 LOGIC NETWORK

12 Oct 2010 Objective: At the end of this lesson,

student will able to: Practical 3
(4 hour)
4.1 Combinational logic gates to produce logic
networks and the
15 Oct 2010
application of Boolean identities.
(1 hour)
4.1.5 Construct a combinational logic circuit.
4.1.6 Test the circuit by using: a. Logic probe.
b. IC tester.

Week 12 5.0 ARITHMETIC CIRCUIT

19 Oct 2010 Objective: At the end of this lesson,

student will able to: 2ND FRP Check
(4 hour)
5.1 Basic elements of arithmetic circuits, half
adder.
22 Oct 2010
5.1.1 Derive output table for half adder.
(1 hour)
5.1.2 Draw the logic circuit for half adder.
5.1.3 Construct and test half adder circuit.

Week 13 5.0 ARITHMETIC CIRCUIT

26 Oct 2010 Objective: At the end of this lesson,

(4 hour) student will able to:

5.2 Basic elements of arithmetic circuits, full
adder.
29 Oct 2010
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 (1 hour) 5.1.1 Derive output table for full adder. Quiz 2
5.1.2 Draw the logic circuit for full adder.
5.1.3 Construct and test full adder circuit.

Week 14 5.0 ARITHMETIC CIRCUIT

2 Nov 2010 Objective: At the end of this lesson,

student will able to: Practical 4
(5 hour)
5.3 Test and troubleshoot the above circuits.

Week 15 5.0 ARITHMETIC CIRCUIT

9 Nov 2010 Objective: At the end of this lesson,

(4 hour) student will able to:

5.3 Test and troubleshoot the above circuits.
PB &
12 Nov 2010
Attendance %
(1 hour)
Submission

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 15 Nov 2010
-
EXAMINATION WEEK
10 Dec 2010

Prepared by : Approved by:

...........................................................................
.....................................................................
.
(AHMAD KHAIRULNIZAM B. ZULKIFLI)
(NOR ZALINA BT. MOHD YUSOF)
Date : 14 July 2010
Head of Engineering & Skills Dept / Courses
Date :

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