HARDWARE EXPERIMENT 1

Experiment:

Single Stage BJT Amplifier

Aim :

To design a single stage CE amplifier using BJT and to analyze its frequency response.

Theory:

CE amplifier is widely used in audio frequency applications and in radio and TV receivers.

Base current controls the collector current. Smaller base current results in a larger collector
current. The emitter base junction is forward biased and the collector base is reverse biased.
Rb1,Rb2 provides voltage divider biasing which provides independence against the variations
in β. The Coupling capacitors Cc couples the ac signal to the input of the amplifier and blocks
dc. It also isolates the input signal source and the voltage divider circuit.Xc1 < Rin /10. Where
Rin=R1||R2|| hfere and re = 25mV / I E is the internal emitter resistance of the transistor and
25 mV is the temperature equivalent voltage. The bypass capacitor bypasses the signal
currents to the ground. XCE < RE /10. BC107 is selected with hFE of 100 to 500 depending on
the requirement of Av. For distortion-less output the operating point should be in the middle
of the load line so VcEQ= 50% VCC. . IC for BC 107 is 2 mA. RE provides current series
feedback.

It stabilizes the operating point against temperature variations. 10% of Vcc is fixed across RE.
40% OF Vcc flows across Rc

DESIGN:

DC BIASING CONDITIONS

Consider Vcc = 12V , I c= 2mA (BC 107)

VRC= 40% of VCC = 4.8 V

VRE= 10% of VCC = 1.2 V

VCE= 50% of VCC = 6 V

Design of RE

RE= VRE/ IE = VRE/ IC = 1.2/ 2m = 0.6K=600 ohm

Design of Rc

RC= VRC/ IC = 2.4K ohm

Design of Voltage Divider R1 and R2

hfe (min) = 100

IB=IC/ hfe (min) = 0.02m = 20µ A

Assume that 10 IB flows through R1 and 9IB flows through R2.

VR2= VBE+V RE = 0.7+ 1.2=1.9V

R2= VR2/ 9 IB= 1.9/(9* 20 µ A) = 10K

VCC-VR2 = V R1

12- 1.9 = VR1

10.1= VR1

R1= VR1/ 10 IB= 10.1/(10* 20u) = 10.1/200 µ A = 50K

XCE ≤ RE/ 10

CE ≥ 1 2 *  *100 * 68 = 23 µF ≈ 22 µF

Circuit Diagram:

Procedure:

1. Check the dc bias conditions by removing the input signal and the capacitors.
2. Connect the capacitors and apply a 100mV peak to peak sinusoidal signal from the
function generator to the input circuit. Observe the input and output waveforms on the CRO.
3. Keeping the input voltage constant vary the frequency of the input signal from 0 to 1
MHz. Measure the output voltage.
4. Using the input voltage and the output voltage calculate the gain in dB plot the frequency
response characteristics with gain in dB on the y-axis and log f on the x-axis. Mark log fL and
fH corresponding to 1/√2 of the maximum gain.
5. Calculate the bandwidth BW= fH- fL
6. Repeat the same procedure by removing CE.

Table:

Vin=100mV

Sl. No Frequency (in Hz) Output voltage Av=20

(Vout in volt) log10(Vout/Vin)
1 590 2 26.02
2 952 2.2 26.848
3 1560 2.4 27.604
4 2567 2.4 27.604
5 3091 2.4 27.604
6 4522 2.5 27.958
7 5435 2.5 27.958
8 6028 2.5 27.958
9 10730 2.5 27.958
10 334600 2.5 27.958
11 436500 2.5 27.958
12 495400 2.4 27.604
13 620900 2 24.02
Graph:

Frequency Response
Gain(dB)

Frequency (Hz)

Inference:

Bandwidth increases and gain decreases in the absence of CE.