NANDHA ENGINEERING COLLEGE

(AUTONOMOUS)
SEMINAR PPT 2
NAME : R.MONISHA
REG NO :19VLF04
DEPT&YEAR : M.E-VLSI DESIGN/II-YEAR
SUBJECT : LOW POWER VLSI DESIGN
TITLE : SOFTWARE DESIGN FOR LOW POWER
DATE :
SOFTWARE DESIGN FOR LOW POWER
 INTRODUCTION
• Power dissipation of digital systems have been continued to
be focused on hardware design.

• The manner in which software uses and directs the hardware

can have a substantial impact on the power dissipation.

• No efficient and accurate tools to estimate overall effect of

software design on power dissipation.
 SOURCES OF SPD
• Memory system takes 1/10t to 1/4th fraction of the power
budget.

• More sensitive DSP power applications such as

video processing.

• System buses with large switching activity.

• Data paths in ALUs and FPUs.

• Control logic and clock distribution.

• Program’s energy dissipation is proportional to

the number of execution cycles of the program.
 SOFTWARE POWER ESTIMATION
• Lower level approach - Use gate level simulation and
power estimation tools.

• Higher level approach - Estimate power based on

frequency of execution of instruction sequence.

Gate level Power Estimation

• Most accurate method available assuming detailed gate level

description is available.

• Too slow for low power optimization, but more important in

evaluating the power dissipation behavior of a processor design.
Architectural Level Power Estimation
• Less precise but much faster

• Is implemented in a Power Estimation Simulator called

ESP(Early design Stage Power and performance
simulator).
Bus Switching Activity
• Bus activity is assumed to be representative.

• Requires knowledge about architecture of processor, op-

codes for instruction set, input data to a program, etc.
 SOFTWARE POWER OPTIMIZATION

A prerequisite to optimizing a program for low power

must always be to design an algorithm that maps well to
available hardware and is efficient for the problem at hand in
terms of both time and storage complexity.

Algorithm Computations to match Computational Resources

• In parallel processor applications, a typical problem is to

structure software in a way that maximizes the available
parallelism.
PARALLEL COMPUTING RESOURCES CAN
THEN BE USED TO SPEED UP PROGRAM
EXECUTION
In low-power DSP synthesis, a typical problem is to design
an algorithm to allow a circuit implementation that minimizes
power dissipation given throughput and area constraints. Often
a low-power DSP design will also exploit parallelism in an
algorithm, but the objective is to shorten critical paths so that
supply voltages can be lowered while maintaining overall
performance.
ALGORITHM COMPUTATIONS TO MATCH
COMPUTATIONAL RESOURCE
(ONE AND TWO ADDER)
• If two adders are available, then the algorithm illustrated in
figure makes sense because it permits two additions to be
performed simultaneously.
• However, the principle is still applicable. The basic
principle is to try to match the degree of parallelism in an
algorithm to the number of parallel resources available
• In the general case, one cannot manipulate the parallelism
of an algorithm quite so conveniently.
THANK YOU