618 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO.

3, MARCH 2010

Analysis of the Impact of High-Order

Integrator Dynamics on SC Sigma-Delta
Modulator Performances
Andrea Pugliese, Francesco Antonio Amoroso, Gregorio Cappuccino, Senior Member, IEEE, and
Giuseppe Cocorullo, Member, IEEE

Abstract—The impact of high-order integrator dynamics on are required to define well-founded specifications on the inte-
switched-capacitor sigma-delta modulator (61M) performances grator dynamic performances, because the actual impact of the
is investigated in this paper. An advanced generic integrator-set- integrator-settling time on the modulator characteristics cannot
tling model to take into account high-order dynamic effects is
presented and validated by means of transistor-level simulations of be simply predicted analytically [4], [25], [26].
circuits implemented in a commercial 0.35 m CMOS technology. Although first-order settling models are conventionally used
The model is used through the paper to carry out an exhaustive to describe the settling of SC integrators [1]–[4], [21]–[27], the
behavioral analysis for second-order single-bit 61Ms charac- latter show high-order dynamics in many practical situations. In
terized by first-, second-, and third-order integrator dynamics, fact, real op-amps are generally characterized by high-order be-
showing how high-order poles and zeros can affect the 61M
characteristics remarkably. The proposed analysis provides useful havior, as occurs in common two-stage configurations [5]–[8],
guidelines to fix a convenient integrator poles/zeros placement in [28]–[30], and even in single-stage topologies [10]–[12]. More-
order to achieve an effective 61M design flow. over, further poles and zeros in the transfer function are intro-
Index Terms—Behavioral modeling, operational amplifier (op- duced by the external integrator feedback network [31]. It is
amp), settling time, sigma-delta modulator (61Ms), switched- worth pointing out that complex-poles and zeros cause oscilla-
capacitor (SC) integrator, transient response. tions [31] and initial undershoots [23] in the integrator response,
which can strongly affect the overall performances.
As a consequence of the limited prediction capability of
I. INTRODUCTION the integrator first-order models, early design specifications
resulting from conventional behavioral simulations can be
IGMA-DELTA modulators are widely employed inadequate in real circuit designs. This may force the designer
S in many modern applications, such as telecommunications,
multimedia, sensor-interface and measurement systems, espe-
to adjust the circuit parameters in the transistor-level design
phase on the basis of the actual integrator time response.
cially to implement low-power, high-resolution analog-to-dig- Unfortunately, the integrator-settling time is directly related
ital converters (ADCs) [1]–[20]. Owing to the architec- to amplifier transistor dimensions and bias currents, which also
tures complexity, early design specifications for modulator sub- control the dc gain, output swing, and noise [30]. Moreover,
circuits are commonly fixed by means of behavioral simulations op-amp bias currents play a fundamental role in determining the
based on high-level system descriptions. Time-consuming tran- overall modulator power consumption, which is an additional
sistor-level simulations are instead usually performed at the end important characteristic to be taken into account in modern
of the design flow to verify the circuit operation correctness portable applications.
[1]–[10]. Thus, the integrator parameters tuning in the transistor-level
One of the most critical blocks is the integrator, whose design phase can give rise to ineffective trial-and-error proce-
performances depend mainly on the dc gain, the speed, the dures with the aim of achieving the desired performances.
Well-defined early design guidelines to place adequately the
output swing, and the noise characteristics of the operational
amplifier (op-amp) used to implement it. In particular, the integrator poles, and zeros are, therefore, desirable to avoid
integrator-settling time is a crucial design concern in well-es- wasting the advantages of behavioral analysis for making the
tablished switched-capacitor (SC) [1]–[4], [21]–[24], modulator design more affordable and efficient.
To this aim, the impact of high-order integrator dynamics on
which are the most popular architectures in standard CMOS
mixed-signal circuits [2], [9]. Accurate behavioral simulations the overall modulator characteristics is investigated in this paper
by exploiting a generic integrator-settling model. The latter is
introduced in Section II and validated by means of transistor-
Manuscript received April 23, 2008; revised October 21, 2008 and January
12, 2009. First published June 02, 2009; current version published March 05,
level simulations related to designs carried out in a commercial
2010. This paper was recommended by Associate Editor H. Schmid. 0.35 m CMOS technology (Section III).
The authors are with the Department of Electronics, Computer Sci- The model is then applied to analyze the effects of first-,
ence and Systems, University of Calabria, Cosenza 87036, Italy (e-mail: second-, and third-order integrator-settling behavior on modu-
a.pugliese@deis.unical.it; f.amoroso@deis.unical.it; cappuccino@deis.
unical.it; cocorullo@deis.unical.it). lator performances, according to the analysis strategy presented
Digital Object Identifier 10.1109/TCSI.2009.2023946 in Section IV. In Section V, the proposed behavioral analysis is
1549-8328/$26.00 © 2010 IEEE

Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:427 UTC from IE Xplore. Restricon aply.
PUGLIESE et al.: ANALYSIS OF THE IMPACT OF HIGH-ORDER INTEGRATOR DYNAMICS 619

Fig. 1. Fully differential SC integrator.

Fig. 3. Generic integrator responses: linear (dashed line) and slew-rate-limited

(continuous line).

2) the effects related to the feedforward signal path

through the integration capacitances are negligible,
Fig. 2. Generic integrator feedback model. i.e., ;
3) and are algebraic factors, that is to say the
resistances associated to transistors used as switches are
carried out for a typical second-order single-bit . Finally, negligible [31].
some conclusions are reported in Section VI. The generic linear time response at the th integration phase
, plotted in Fig. 3, can be carried out by means of the
II. PROPOSED GENERIC INTEGRATOR-SETTLING
inverse Laplace transformation
BEHAVIORAL MODEL
A typical fully differential SC integrator used in [7], (4)
[10], [14] is shown in Fig. 1.
In the sampling phase ( high), the input signal is sam- where
pled by the sampling capacitance . In the integration phase
( high), the charge is transferred from to the integration (5)
capacitance , causing a change in the output voltage .
The following equation relates and at the th inte- is the sampled voltage at the th sampling phase.
gration phase: If the derivative of does not exceed the op-amp slew
rate , then . Otherwise, slew rate limita-
(1)
tions occur in the response, as depicted in Fig. 3 (continuous
where is the clock period and is the output change at the line). The response is in general not affected by limitations
end of the integration phase. depends on the integrator time during the initial period , being the time instant at which
response . If the sampling and the integration phases have the derivative of just equals . After this phase in which
the same durations (as normally occurs), is given by still holds, slew rate limitations dominate the re-
sponse from to the time instant . During the slewing period
(2) , the dynamics is modeled by a straight line of slope
[1]–[3] starting at the point , to ensure the conti-
is determined by both linear and slewing integrator char- nuity of both and its derivative at .
acteristics. The linear integrator behavior can be conveniently Finally, for , the integrator response can be modeled
analyzed in the Laplace domain by using the generic feedback by a linear response (namely ) whose maximum slope is
model in Fig. 2 [23], [31]. In the model, , , and just and is given by
are the feedback, feedforward, and open-loop amplifier transfer
(6)
functions, respectively. is the transfer function from to
the summing node at the amplifier input. The integrator transfer
where and
function is then given by
is the integrator dc gain. It is worth pointing out that the
maximum of the derivative of occurs in general at
(3)
, i.e.,

It is worth pointing out that (3) is a single-pole transfer func- (7)

tion only if the following assumptions are verified:
1) is a single-pole transfer function; where .

Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:427 UTC from IE Xplore. Restricon aply.
620 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 3, MARCH 2010

Fig. 4. SC integrator operation during the integration phase.

The aforementioned equations give the boundary constraints

to connect opportunely and the straight line of slope ,
in order to guarantee the continuity of both and its deriva-
tive at the time [34]. By means of simple geometric consid-
erations, the following expression for describing the slew-rate-
limited response , reported in Fig. 3, can be carried out

Fig. 5. Fully differential single-stage telescopic cascode op-amp.

(8)
When the op-amp in the figure is used, the slew-rate of the
where
integrator is given by [36]
(9)
(10)
With respect to previous models presented in the literature,
(8) can be generalized to describe the integrator time response where is the bias current, which flows in the MOSFETs M1,2,
whatever the system transfer function is. This turns out to and
be very useful to predict high-order settling behavior normally
occurring in real SC integrator implementations, as will be dis- (11)
cussed in the next section.
is the total op-amp capacitance load [23]. By considering the
III. PROPOSED MODEL TRANSISTOR-LEVEL VALIDATION
circuit in Fig. 4, assuming that the op-amp dc gain is much
In real situations, the circuit of Fig. 4 well describes the greater than one, and neglecting without loss of generality,
operation of the scheme of Fig. 1 during the integration phase the following second-order transfer function can be derived to
[4], [31]. is the on-resistance of the switches, is the describe the linear operation of the integrator, as shown in (12)
parasitic op-amp input capacitance, and is the total lumped at the bottom of this page, where is the transconductance
capacitance to be driven by the integrator. According to the of MOSFETs M1,2.
circuit in the figure, and to be used in (4)–(9) depend It is worth noting that if , (12) degenerates to
on both the op-amp characteristics (such as transistor bias a single-pole single-zero transfer function whose response can
currents, transconductances, output resistances, and parasitic be well predicted by models already available in the literature
capacitances) and the external op-amp feedback network.To [22], [23]. Instead, for nonnull switch resistances, (12) presents
demonstrate the accuracy and usefulness of the proposed a second pole whose effect on the integrator time response can
model, the circuit in Fig. 4 was designed in a commercial 0.35 be accurately predicted in accordance with the proposed settling
m CMOS technology by employing typical single-stage and model by using (10)–(12) in (4)–(9).
two-stage topologies to implement the op-amp. As an example, the circuit in Fig. 4 was designed by choosing
A , A, , , and
A. SC Integrator With Single-Stage op-amp . Moreover, four different values of (0 , 1 ,
The schematic of a typical single-stage cascode op-amp is 2.5 , 10 ) were considered, corresponding to four different
shown in Fig. 5. pole/zero placements of (12), as indicated in Table I.

(12)

Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:427 UTC from IE Xplore. Restricon aply.
PUGLIESE et al.: ANALYSIS OF THE IMPACT OF HIGH-ORDER INTEGRATOR DYNAMICS 621

Fig. 6. Predicted (dashed line) and HSPICE (continuous line) integrator step responses for different R values when the telescopic cascode op-amp is used: (a)
R = 0
; (b) R ; (c) R : ; (d) R = 1 k

. = 2 5 k
= 10 k

TABLE I
POLES/ZEROS PLACEMENT OF INTEGRATOR WITH SINGLE-STAGE OP-AMP

The plots in Fig. 6 show the integrator responses obtained

from HSPICE simulations (continuous lines) in all the consid-
ered situations. The remarkable difference between the four re-
sponses clearly evidences the strong impact of the further pole Fig. 7. Fully differential two-stage Miller-compensated op-amp.
introduced by the switch resistance, which tends to move
closer to the other pole and zero when increases (see
Table I). Interestingly, it appears that the approaching between low-voltage CMOS technologies in order to guarantee a suitable
the two system poles tends to reduce significantly the initial dc gain preserving an adequate output swing as well [28]–[30].
undershoot of the response [see Fig. 6(b)–(d)] with respect to The schematic of a typical fully differential two-stage Miller-
the case in which the integrator really behaves as a first-order compensated op-amp is shown in Fig. 7. In the circuit, MOS-
system [see Fig. 6(a)]. FETs M1-M5 and M6-M9 are used to implement the first and
The actual time response of SC integrators using single-stage the second amplifier stages, respectively, and is the Miller
op-amps can be accurately described by exploiting the proposed compensation capacitance.
high-order settling model, whose high-prediction capability is When the op-amp in the figure is used, the slew-rate of the
highlighted by the dashed-line plots of Fig. 6. For example, the integrator is given by the lowest slew rate of the two amplifier
error between the predicted and the actual responses is less than stages, i.e., [36]
0.01%, when the integrator response enters into the 0.01% ac-
curacy band with respect to the steady-state value.
(13)
B. SC Integrator With Two-Stage op-amp
Cascode amplifier topologies tend to reduce even signifi- where and are the bias currents of the MOSFETs M1/M2
cantly the maximum output swing achievable. For this reason, and M7/M9, respectively, and is the total op-amp ca-
two-stage cascade op-amps are widely employed in modern pacitance load (11). Under the normally verified assumptions

Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:427 UTC from IE Xplore. Restricon aply.
622 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 3, MARCH 2010

TABLE II
POLES/ZEROS PLACEMENT OF INTEGRATOR WITH TWO-STAGE OP-AMP

that the op-amp dc gain is much greater than one, and the par-
asitic capacitances are negligible with respect to and
[28], [30], the following three-pole two-zero transfer function
describes the linear operation of the circuit in Fig. 4:

Fig. 8. Predicted (dashed line) and HSPICE (continuous line) integrator step
responses for different R values when the two-stage Miller-compensated
op-amp is used: (a) R = 0
; (b) R = 2 5 k

: ; (c) R = 5 k
; (d)
where and are the transconductances of M1/M2 and
(14)
R = 10 k
.

M7/M9, respectively. For this case, the design example was car-
ried out by choosing , , sponse descriptions prove to be excessively rough, hiding crit-
A, A, , , ical information about the actual system dynamics.
and . As a consequence, inappropriate choices of the integrator pa-
Four different values of (0 , 2.5 , 5 , 10 ) were rameters can result from conventional behavioral simu-
also considered, corresponding to four different pole/zero place- lations based on classical first-order settling models. Interest-
ments of (14), as indicated in Table II. It is worth noting that ingly, the previous results evidence how the changing of the
the integrator is characterized by high-order behavior even if distance between the system poles and zeros (i.e., the relative
, showing two zeros and two complex poles . system poles/zeros placement) causes remarkable variations in
For nonnull switch resistances, (14) presents a further real pole the shape of high-order integrator time responses.
, which tends to move closer to the other poles and zeros when In the following, the impact of the integrator relative poles/
increases (see Table II). zeros placement on the overall performances will be in-
The plots in Fig. 8 show the integrator responses obtained vestigated by performing a behavioral analysis based on the pro-
from HSPICE simulations (continuous lines) for all the consid- posed model. To this aim, a suitable strategy will be first defined
ered resistance values. As noticeable from the figure, the pres- in the next section to describe second- and third-order dynamics
ence of two complex poles causes oscillation in the integrator typically occurring in real SC integrator designs and to compare
response. Interestingly, it also appears that the approaching be- them to first-order dynamics.
tween the real pole and the complex ones tends to reduce the
amplitude of the oscillations other than the initial undershoot of IV. ANALYSIS STRATEGY
the response.
These important high-order effects in the integrator response In the presence of first-order dynamics, the linear inte-
can be captured by using (13) and (14) in the proposed set- grator-settling behavior can be described by the following
tling model (4)–(9), whose high-prediction capability is fur- transfer function:
ther confirmed by the dashed-line plots of Fig. 8. For instance,
the error between the predicted and the actual responses is less (15)
than 0.01%, when the integrator response enters into the error
band identified by the 0.01% accuracy level with respect to the being the integrator dc gain. The pole is related to the
steady-state value. integrator loop-gain unity frequency gain-bandwidth ( ) in
accordance with the relationship .
C. Discussion of Analysis Results From (4) and (15), the linear time response at the th integra-
tion phase is given by
The previously reported design examples clearly show that
the time response of real SC integrators is typically character- (16)
ized by significant high-order phenomena such as undershoots
(overshoots in the case of negative steps) and oscillations. In Since the maximum of the derivative of (16) occurs at ,
the presence of high-order behavior, the first-order integrator re- both and are null. Therefore, by using (16) in (6)–(9),

Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:427 UTC from IE Xplore. Restricon aply.
PUGLIESE et al.: ANALYSIS OF THE IMPACT OF HIGH-ORDER INTEGRATOR DYNAMICS 623

Fig. 9. Possible pole/zero placements analyzed: (a) first-order system; (b) second-order system with two real poles and one zero; (c) second-order system with two
complex poles and one zero; (d) third-order system with three real poles and two zeros; (e) third-order system with two complex poles and one real pole ( < 1)
and two zeros; (f) third-order system with two complex poles and one real pole ( 1) and two zeros. 

the conventional expression of the slew-rate-limited single-pole A. Second-Order Dynamics

integrator response is obtained [1]–[3] The following generic transfer function with two poles and
one zero can be usefully considered to analyze the settling be-
havior of integrators, showing a second-order dynamics, such as
the real integrator studied in Section III-A
(17)
where . (18)
It is evident from (17) that the integrator dynamics is con-
trolled by the system pole and in the case of first-order When , the system (18) presents two real poles. In
settling behavior. Instead, in the case of second- and third-order accordance with the previously discussed normalization, the
settling behaviors, the number of parameters that control the in- second pole can be written as [see Fig. 9(b)],
tegrator response increases. To carry out a coherent investiga- being the lowest frequency pole. When , there are two
tion of the impact of the integrator settling order on per- complex poles whose damping factor, natural frequency, and
formances, an appropriate analysis strategy is then advisable. real part are given by , , and , respectively. In this case,
A convenient method is to express properly the pole/zero po- is fixed equal to [see Fig. 9(c)]. In both situations, the
sitions of high-order systems with respect to the first-order pole zero is expressed as . The linear time response (4) of
system , whose frequency is assumed as normalization factor (18) thus becomes
[35] (i.e., as a reference frequency) in the analysis, as pictorially
reported in Fig. 9. For high-order systems, in the case that the
lowest frequency pole is real, it is accounted as the frequency
of the reference pole . Otherwise, if two complex poles are
the nearest to the imaginary axis, their real part is accounted as
frequency. In both cases, other system poles and zeros are
written as a function of . In this manner, by also considering (19)
the same op-amp slew rate for all the systems under examina-
tion, the effects of relative pole/zero placements on high-order where and
integrator-settling characteristics can be consistently analyzed. .

Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:427 UTC from IE Xplore. Restricon aply.
624 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 3, MARCH 2010

The slew-rate-limited integrator response for (18) can be

then obtained by substituting (19) in (6)–(9). Clearly, when
in (19), the proposed generic settling model describes
single-pole single-zero integrator responses assumed in [23].

B. Third-Order Dynamics
Fig. 10. Second-order modulator model.
The settling behavior of integrators showing a third-order dy-
namics, such as the one studied in Section III-B, can be analyzed
by using the following generic transfer function with three poles V. BEHAVIORAL ANALYSIS
and two zeros
The impact of high-order integrator-settling behavior on the
overall performances is investigated in the following by
(20) performing in MATLAB an extensive behavioral analysis based
on the strategy introduced in the previous sections. A typical
single-bit second-order is analyzed. A sinusoidal input
When , the integrator presents three real poles signal of amplitude 0.5 V and frequency 23 kHz, a signal band-
[see Fig. 9(d)]. In this case, the lowest frequency pole is width of 100 KHz, and a sampling frequency of 50 MHz are
, and the other two poles are written as and also considered.
. When , the integrator The modulator output amplitude is assumed to be 3 V. Both
presents two complex poles and one real pole, which is written the first and second integrator gains are fixed equal to 0.5, and a
as . If , the real pole is fixed equal to [see signal-to-noise and distortion ratio (SNDR) at least equal
Fig. 9(e)], otherwise [see Fig. 9(f)]. In all the three to 92 dB is assumed as the target in order to guarantee 15-bits of
cases, the two zeros are expressed as and . resolution [1]. The SNDR is calculated by exploiting the proce-
By referring to the situations in Fig. 9(d)–(f), the linear time dure suggested in [2]. The modulator behavioral model structure
response (4) of (20) is given by (21)–(23) (as shown at the is depicted in Fig. 10.
bottom of this page), respectively. Without loss of generality, only the nonidealities of the first
The slew-rate-limited integrator response for (20) can integrator are taken into account in the model for the sake of sim-
then be obtained by substituting (21)–(23) in (6)–(9) in accor- plicity. In fact, both the second integrator and the comparator
dance with the proposed model. can be reasonably assumed to be ideal blocks, because their

(21)

(22)

(23)

Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:427 UTC from IE Xplore. Restricon aply.
PUGLIESE et al.: ANALYSIS OF THE IMPACT OF HIGH-ORDER INTEGRATOR DYNAMICS 625

Fig. 11. Proposed integrator-settling behavioral model.

Fig. 13. Dependence of modulator SNDR on f and SR for a first-order inte-

grator.

Fig. 12. (a) SNDR versus op-amp dc gain; (b)SNDR versus op-amp output
swing; (c) SNDR versus C (switch thermal noise); (d) SNDR versus clock
jitter.

nonidealities can be neglected owing to the noise shaping ac-

tion [2], [3]. According to (1), the first integrator is modeled by
using the proposed settling description, as shown in Fig. 11. Ob-
Fig. 14. 2-D plots showing the 61M SNDR trend for different integrator
viously, the model of Fig. 11 can be used in a complete dynamic behavior: (a) SNDR versus  in the presence of two complex poles
behavioral analysis along with the models already available in with ! = 2 200 MHz; (b) SNDR versus  in the presence of two real poles
the literature describing the effects of other noise sources such as 0
and one RHP zero ( = 2:75); (c) SNDR versus  in the presence of two
0
complex poles with ! = 2 250 MHz and one RHP zero ( = 2); (d) in
the op-amp finite dc gain and output swing, the clock jitter, and the presence of two complex poles with ! = 2 200 MHz and one real pole
the switch thermal noise [1]–[4]. For the sake of completeness, ( = 1:1).
some behavioral simulation results showing the dependence of
the modulator SNDR on the previously discussed aspects are
summarized in Fig. 12. As shown in the figure, dB strategy previously discussed. It is worth pointing out that the
can be reached by fixing the dc gain greater than 50 dB, the presented analysis has, anyway, a general validity regardless of
output swing greater than 1.8 V, the clock jitter less than 1 ns, the specific choice of and , which is indeed directly related
and (corresponding to an input-referred to the characteristics and specifications (e.g., the order,
noise less than ). Once the earlier noise related pa- the sampling rate, and the desired SNDR) of the specific con-
rameters are set, the integrator-settling limitations remain to be sidered modulator. In fact, as discussed in Section III, the high-
taken into account in order to reach actually the desired order effects on the shape of the integrator response are deter-
performances. mined by the relative distance between the system poles/zeros,
The impact of the integrator settling on the modulator SNDR i.e., by their relative position with respect to the reference an-
will be analyzed in the following. gular frequency of .
First, behavioral simulations are carried out for a single-pole
integrator whose linear performances are described by A. Second-Order Integrator Dynamics
(16), aiming to identify suitable and SR values to reach The analysis is first carried out by considering an all-pole in-
dB. The 3-D plot of Fig. 13 shows the dependence tegrator [see Fig. 9(b) and (c) with ]. In the case of
of SNDR on SR and the pole frequency in Hz . real poles, simulation results show that dB can
White regions in the plot identify the couples, which be obtained for all possible relative pole placements, i.e., for all
allow dB. For example, MHz (i.e., values of , because no undershoots and oscillations occur in
MHz) and s can be reasonably the integrator response. In the case of complex poles, the mod-
chosen. ulator behavior differs significantly from the previous case. In
Starting from these and values, the impact of second- fact, as evidenced in the plot in Fig. 14(a), the complex-poles
and third-order integrator dynamics on the modulator perfor- damping factor strongly affects the SNDR. Moreover, it is
mances will be investigated, in accordance with the analysis worth pointing out that a clear difficulty in fixing a suitable value

Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:427 UTC from IE Xplore. Restricon aply.
626 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 3, MARCH 2010

Fig. 15. 3-D plots of the 61M SNDR trend for different integrator dynamic behavior: (a) SNDR versus (; ) in the presence of two real poles p = 2 200 MHz
and p = p , and one RHP zero z = p ; (b) SNDR versus ( ;  ) in the presence of three real poles, one RHP zero ( = 2) and one LHP zero ( = 2); 0
(c) SNDR versus ( ) in the presence of two complex poles and one real pole ( < 1), one RHP zero ( = 2) and one LHP zero ( = 2); (d) SNDR versus 0
(;  ) in the presence of two complex poles with ! = 250 MHz, one real pole ( 1), one RHP zero ( = 2) and one LHP zero ( = 2).  0

for comes now from the nonmonotonic relationship SNDR– .

Thus, the chosen values of and SR do not suffice to achieve
reliably a satisfactory SNDR value. As an example,
MHz and s prove to be instead adequate
to this aim, guaranteeing dB even for small values
of .
For finite values of , the overall performances re-
markably deviate from the previously analyzed cases. In fact,
whereas the presence of a left-half plane (LHP) zero has
a negligible impact on the SNDR, a right-half plane (RHP) zero
in the integrator transfer function tends to affect consid-
erably the modulator characteristics. The 3-D plot of Fig. 15(a)
shows SNDR versus when the integrator is characterized
by two real poles and one RHP zero. As evidenced, a significant Fig. 16. PSD of the modulator output when the integrator presents two real
degradation of the system performances occurs for . poles and one RHP zero.
Moreover, the SNDR is less than 92 dB for all values when
. The desired modulator performances can be instead
reached by carefully choosing for . This aspect The aforementioned nontrivial results seem to contrast with
is further highlighted in the 2-D plot of Fig. 14(b), which reports the intuitive idea that the higher the second-pole frequency, the
SNDR versus when . It is evident from the plot that faster the integrator response, resulting in better modulator per-
the increasing of tends to worsen the modulator performances. formances. Actually, a smaller initial undershoot arises in the re-
This situation can be also analyzed by comparing the power sponse when decreases [see Fig. 17(a)], causing the improve-
spectral densities (PSDs) of the modulator output for different ment of the integrator-settling performances, and as a conse-
values, as an example for and (see Fig. 16). quence of the modulator SNDR.
The plots in the figure show the presence of a noise peak in the Interestingly, Fig. 14(b) evidences that taking advantage of
signal band (localized at 69 kHz, i.e., the third harmonic of the fixing suitably ( appears a reasonable choice for the
input signal), which is higher when . case under examination) allows dB to be reached

Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:427 UTC from IE Xplore. Restricon aply.
PUGLIESE et al.: ANALYSIS OF THE IMPACT OF HIGH-ORDER INTEGRATOR DYNAMICS 627

For example, from Fig. 14(c) it appears that has to be

fixed to reliably achieve dB, when .

B. Third-Order Integrator Dynamics

The analysis is first carried out by neglecting zeros
[Fig. 9(d)–(f) with and ]. In both the
cases of three real poles and two complex poles plus one real
pole with , simulations results show that dB
for all relative pole/zero placements. Instead, the modulator
performances tend to be degraded when the real pole moves
away from the complex ones for . In this case, the desired
SNDR can be indeed reliably achieved for and
. For , the effect of the real pole on the SNDR
fades away and the SNDR– dependence reverts to the one
reported in Fig. 14(a).
For instance, the SNDR– relationship for .1 is
depicted in Fig. 14(d). The comparison between the plots in
Fig. 14(a) and (d) clearly highlights that a proper placement
of the third real pole near to the complex poles pair guaran-
tees a significant enhancement of the modulator SNDR for
the considered values of and SR ( MHz,
s). This is because the approaching of the
real pole to the complex ones tends to cause the reduction of
the oscillations [33] in the integrator response, as shown by
the designs of SC integrators, employing two-stage op-amps
Fig. 17. Integrator time responses: (a) second-order for  and  =2 = 10
when = 02 75 : ; (b) third-order for  : and  : when  =04 =08 = 2 and presented in Section III-B.
 = 02 . The designs of Section III-B also evidence that the position
of the real pole is directly controlled by the integrator switch
resistances, which can then be conveniently fixed to take advan-
without the necessity of increasing and/or SR with respect tage of the modulator performances improvement arising from
to the considered values (i.e., MHz and the dampening of the oscillations in the integrator response.
s). Therefore, the earlier presented results further confirm the im-
Therefore, the availability of well-founded guidelines to portance of using the proposed behavioral analysis in order to
place conveniently the second integrator pole is fundamental guarantee the efficiency of the design flow. The presence
to prevent the designer from choosing unknowingly larger of zeros in the integrator transfer function considerably affects
op-amp bandwidth and slew-rate values than the ones which the modulator performances also in the case of third-order sys-
are really needed to achieve the desired performances, tems. For example, this can be appreciated by considering one
thereby avoiding power wasting. In the design of real SC RHP and one LHP zeros whose angular frequencies are twofold
integrators characterized by a second-order behavior (such as the one of (i.e., , ) [32]. The simulation
the ones using single-stage op-amps), these guidelines can be results related to situations in Fig. 9(d) and (e) are reported in
for instance very useful to fix a suitable switch resistance range Fig. 15(b) and (c), respectively. The plot in Fig. 15(b) evidences
in order to benefit from the reduction of the integrator response that unlike the all-pole system, the relative placement of the
undershoot resulting from the approaching of the two poles, three real poles (i.e., the couple of values for and ) has
as shown in Section III-A. The aforementioned discussion to be carefully chosen to obtain dB in the pres-
clarifies the practical usefulness of the proposed analysis in ence of the zeros. In particular, suitable values to achieve reli-
order to identify, since the behavioral simulation phase, able modulator performances are and . Simi-
crucial design aspects, which are otherwise neglected in con- larly, the couple has to be carefully fixed when the system
ventional approaches based on first-order settling descriptions has two complex poles and one real pole with , as shown
(single-pole, as well as single-pole single-zero models) [1]–[4], in Fig. 15(c). In this case, and can be rea-
[22], [23] assuming implicitly . sonably chosen. Differently from the all-pole system, the more
Finally, an integrator transfer function characterized by one distant the complex poles from the real one (i.e., ), the
RHP zero and two complex poles with MHz worse the modulator performances. Also this situation directly
is analyzed. In this case, the SNDR– relationship for a given comes from the diverse amplitudes of initial undershoots/over-
value of is nonmonotonic, similarly to the situation depicted in shoots occurring in the integrator response for different values
Fig. 14(a), and dB for all if . Moreover, of . As an example, the integrator responses for and
in the presence of one RHP zero, MHz and are compared in Fig. 17(b).
s guarantee the desired modulator performances only if Finally, simulations show that dB cannot be ob-
is carefully chosen, differently from the system without zero. tained by properly choosing and in the case of two complex

Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:427 UTC from IE Xplore. Restricon aply.
628 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 3, MARCH 2010

poles with MHz and one real pole with . In

order to achieve reliable performances, can be increased,
e.g., MHz proves to be a suitable design choice.
In this case, the target SNDR value can be reached for
and (see Fig. 15(d)).

C. Application to the Circuit Design Practice

To further show the usefulness of the proposed analysis

in practical designs, behavioral simulations were carried out
for the under examination (see Fig. 10) by consid-
ering the SC integrator (see Fig. 4) implemented by using the
two-stage Miller-compensated op-amp in Fig. 7. For example,
, , , A ,
Fig. 18. 1 V-amplitude integrator step responses predicted by the proposed
and A were considered. For this inte- model when: R = 0
(dashed line); R = 1 k
(continuous line); R =
grator, SR is given by (13) and , where 5 k
(dotted line).
is the integrator feedback factor
[31] and
TABLE III
INTEGRATOR POLES/ZEROS ( GBW = 200 MHz AND SR = 200 V=s)
(24)

is the op-amp unity-gain frequency [28], [30]. On the basis of

the considered values of , , , , and ( is
neglected without loss of generality), and from (11), (13), and
(24), the specifications on GBW and SR obtained by assuming that choosing allows the integrator-settling perfor-
a first-order integrator dynamics (i.e., MHz and mances to be significantly improved with respect to the other
s to achieve dB) directly trans- examined cases.
late into the following specifications for the compensation ca- In fact, as further evidenced by the inset in the figure, the three
pacitance and the op-amp stage bias currents: , integrator responses show a remarkably different settling error
A, and A. Actually, as discussed in with respect to the steady-state value (1 V) at ns, which
Section III-B, the integrator under examination is characterized is the duration of the integration phase (the considered sampling
by a third-order settling behavior, whose effects on the overall frequency is 50 MHz). This is caused by the different integrator
performances can be analyzed by using (13) and (14) in poles/zeros placements, as summarized in Table III. Evidently,
the proposed accurate high-order settling model. guarantees a suitable relative placement between
To quantify the impact of these high-order effects, a behav- the real pole , the complex poles , and the zeros of
ioral analysis based on the proposed model was then carried out the system.
starting from the circuit parameters previously determined on Instead, in accordance with the results of the previous theo-
the basis of the first-order integrator-settling description. The retical analysis in Section V-A and V-B, moving the real pole
results of this analysis clearly prove that the high-order inte- toward very high frequencies (i.e., ) by minimizing ,
grator-settling effects can cause the modulator SNDR to be sig- or placing it at lowest frequencies with respect to the complex
nificantly less than 92 dB when they are not properly controlled poles (i.e., ) by fixing excessively large values of (as it
by placing suitably the system poles and zeros. occurs for ), prove to be inadequate design choices.
In particular, as expected, the modulator SNDR strongly de- Therefore, it is evident that a blind early design choice of
pends on the switch resistance , which directly controls the can cause a strong worsening of the modulator performances.
relative position of the real pole with respect to the two com- This may force the designer to perform time-consuming
plex poles and the two zeros present in (14) (Section III-B). For trial-and-error transistor-level simulations aiming to reach the
instance, if or are chosen, the fixed desired SNDR by adjusting the circuit parameters, e.g.,
values of GBW and SR prove to be actually inadequate to guar- by increasing the op-amp stage transconductances and bias
antee the desired modulator performances ( dB currents (i.e., the power consumption and the silicon area) in
and dB result from simulations, respectively). order to increase GBW and SR with respect to the values previ-
Interestingly, dB can be instead conveniently ously determined by considering a first-order integrator-settling
reached by fixing without the necessity of in- model. For this reason, the well-founded early design criterion
creasing GBW and SR. The aforementioned results come di- to fix conveniently , arising from the proposed behavioral
rectly from the strong dependence of the integrator-settling be- analysis, proves to be crucial aiming to carry out an efficient
havior on , as highlighted by the plots in Fig. 18. It appears design.

Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:427 UTC from IE Xplore. Restricon aply.
PUGLIESE et al.: ANALYSIS OF THE IMPACT OF HIGH-ORDER INTEGRATOR DYNAMICS 629

VI. CONCLUSION [11] T. O. Salo, S. J. Lindfors, T. M Hollmann, J. A. M. Jarvinen, and K. A.

I. Halonen, “80-MHz bandpass 16 modulators for multimode digital
The impact of high-order integrator dynamics on SC IF receivers,” IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 464–474,
performances has been investigated in this paper. To this aim, Mar. 2003.
[12] S. K. Gupta and V. Fong, “A 64-MHz clock-rate 61 ADC with 88-dB
a generic integrator-settling behavioral model was developed.
0
SNDR and 105 dB IM3 distortion at a 1.5-MHz signal frequency,”
The proposed model, validated by means of transistor-level IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1653–1661, Dec. 2002.
simulations of circuits implemented in a commercial 0.35 m [13] S. Reekmans, P. Rombouts, and L. Weyten, “Mismatch insensitive
CMOS technology, was specialized to carry out an exhaustive double-sampling quadrature bandpass 61 Modulation,” IEEE Trans.
Circuits Syst I: Reg. Papers, vol. 54, no. 7, pp. 2599–2607, Jul. 2006.
comparative analysis of the modulator characteristics in the [14] L. Yao, M. S. J. Steyaert, and W. Sansen, “1-V 140- W 88-dB audio
presence of first-, second-, and third-order integrator dynamics. sigma-delta modulator in 90-nm CMOS,” IEEE J. Solid-State Circuits,
The behavioral simulation results related to a typical vol. 39, no. 11, pp. 1809–1818, Nov. 2004.
[15] J. Roh, S. Byun, Y. Choi, H. Roh, Y.-G. Kim, and J.-K. Kwon, “A
single-bit second-order show that the modulator perfor- 0.9-V 60- W 1-bit fourth-order delta-sigma modulator with 83-dB
mances tend to be remarkably affected by high-order effects, dynamic range,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp.
such as oscillations and initial undershoots/overshoots, which 361–370, Feb. 2008.
[16] R. Schoofs, M. S. J. Steyaert, and W. M. C. Sansen, “A design-op-
commonly occur in the responses of real SC integrators. In the timized continuous-time delta-sigma for WLAN applications,” IEEE
presence of these effects, conventional behavioral simulations Trans. Circuits Syst. I: Reg. Papers, vol. 54, no. 1, pp. 209–217, Jan.
based on first-order integrator-settling descriptions can result 2007.
[17] Z. Ye and M. P. Kennedy, “Reduced complexity MASH delta-sigma
in fixing inadequate early design circuit specifications, leading modulator,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 54, no. 8,
to costly parameters tuning in the transistor-level design phase, pp. 725–729, Aug. 2007.
with the aim of meeting the desired performances. [18] G. Yu and P. Li, “Efficient look-up-table-based modeling for robust
design of 61 ADCs,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol.
Instead, the behavioral analysis based on the proposed generic 54, no. 7, pp. 1513–1528, Jul. 2007.
integrator-settling model allows precise guidelines to be defined [19] M. Kwon and G. Han, “An I/Q-channel time-interleaved bandpass
in order to take advantage of a convenient placement of the sigma-delta modulator for a low-IF receiver,” IEEE Trans. Circuits
Syst. II: Exp. Briefs, vol. 54, no. 3, pp. 252–256, Mar. 2007.
high-order integrator poles and zeros. In the circuit practice, [20] B. Jalali-Farahani and M. Ismail, “Adaptive noise cancellation tech-
these guidelines directly translate into identifying well-founded niques in sigma-delta analog-to-digital converters,” IEEE Trans. Cir-
criteria to fix suitably important transistor-level integrator cuits Syst. I: Reg. Papers, vol. 54, no. 9, pp. 1891–1899, Sep. 2007.
[21] V. F. Dias, G. Palmisano, P. O’Leary, and F. Maloberti, “Fundamental
parameters such as the bias currents, transistor dimensions, and limitations of switched-capacitor sigma-delta modulators,” Inst. Electr.
frequency compensation elements of the op-amp, as well as the Eng. Proc. G Circuits, Devices Syst., vol. 139, no. 1, pp. 7–32, Feb.
switch resistances. As shown, the proposed behavioral analysis 1992.
[22] R. del Rìo, F. Medeiro, B. Pèrez-Verdù, and A. Rodriguez-Vazquez,
proves to be very useful in order to guarantee the effectiveness “Reliable analysis of settling errors in SC integrators- application to
of the design flow. the design of high-speed 61 modulators,” in Proc. IEEE Int. Symp.
Circuits Syst., May 2000, pp. 417–420.
[23] A. A. Hamoui, T. Alhajj, and M. Taherzadeh-Sani, “Behavioral mod-
REFERENCES eling of opamp gain and dynamic effects for power optimization of
[1] F. Maloberti, P. Estrada, P. Malcovati, and A. Valero, “Validation of delta-sigma modulators and pipelined ADCs,” in Proc. IEEE Int. Symp.
data converter specifications with behavioral modelling specifications,” Low Power Electr. Des., Oct. 2006, pp. 330–333.
in Measurement. New York: Elsevier, 2002, vol. 31, pp. 31–245. [24] F. Medeiro, B. Pèrez-Verdù, A. Rodrìguez-Vazquez, and J. L. Huertas,
[2] P. Malcovati, S. Brigati, F. Francesconi, F. Maloberti, P. Cusinato, and “Modeling OpAmp-induced harmonic distortion for switched-capac-
A. Baschirotto, “Behavioral modeling of switched-capacitor sigma- itor SD modulator design,” in Proc. IEEE Int. Symp. Circuits Syst.,
delta modulators,” IEEE Trans. Circuits Syst. I: Fundam. Theory Appl., 1994, pp. 445–448.
vol. 50, no. 3, pp. 352–364, Mar. 2003. [25] R. Naiknaware and T. Fiez, “142 dB 16 ADC with a 100nV LSB in
[3] H. Zare-Hoseini, I. Kale, and O. Shoaei, “Modeling of switched-capac- a 3V CMOS process,” in Proc. IEEE Custom Integr. Circuits Conf.,
itor delta-sigma modulators in simulink,” IEEE Trans. Instrum. Meas., Orlando, 2000, pp. 5–8.
vol. 54, no. 4, pp. 1646–1654, Aug. 2005. [26] L. A. Williams and B. A. Wooley, “A third-order sigma-delta modu-
[4] G. Suarez, M. Jimenez, and F. O. Fernandez, “Behavioral modeling lator with extended dynamic range,” IEEE J. Solid-State Circuits, vol.
methods for switched-capacitor 61 modulators,” IEEE Trans. Circuits 29, no. 3, pp. 193–202, Mar. 1994.
Syst. I: Reg. Papers, vol. 54, no. 6, pp. 1236–1244, Jun. 2007. [27] W. Sansen, H. Qiuting, and K. A. Halonon, “Transient analysis of
[5] G. Bernardinis, F. Borghetti, V. Ferragina, A. Fornasari, U. Gatti, P. charge transfer in SC filters-gain error and distortion,” IEEE J. Solid-
Malcovati, and F. Maloberti, “A wideband 280-MHz four-path time-in- State Circuits, vol. SC-22, no. 2, pp. 268–276, Apr. 1987.
terleaved bandpass sigma-delta modulator,” IEEE Trans. Circuits Syst [28] G. Palumbo and S. Pennisi, Feedback Amplifiers Theory and Design.
I: Reg. Papers, vol. 53, no. 7, pp. 1423–1432, Jul. 2006. Boston, MA: Kluwer, 2002.
[6] J. Yu and F. Maloberti, “A low-power multi-bit 61 modulator in [29] P. J. Hurst, S. H. Lewis, J. P. Keane, F. Aram, and K. C. Dyer, “Miller
90-nm digital CMOS without DEM,” IEEE J. Solid-State Circuits, compensation using current buffers in fully differential CMOS two-
vol. 40, no. 12, pp. 2428–2436, Dec. 2005. stage operational amplifiers,” IEEE Trans. Circuits Syst. I: Reg. Papers,
[7] R. Gaggl, A. Wiesbauer, G. Fritz, C. Schranz, and P. Pessl, “A 85-dB vol. 51, no. 2, pp. 275–285, Feb. 2004.
dynamic range multibit delta-sigma ADC for ADSL-CO applications [30] G. Palmisano, G. Palumbo, and S. Pennisi, “Design procedure for
in 0.18- m CMOS,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. two-stage CMOS transconductance operational amplifiers: A tutorial,”
1105–1114, Jul. 2003. Analog Integr. Circuits Signal Process., vol. 27, pp. 179–189, 2001.
[8] K.-S. Lee, S. Kwon, and F. Maloberti, “A power-efficient two-channel [31] U. Chilakapati and T. S. Fiez, “Effect of switch resistance on the SC
time-interleaved 61 modulator for broadband applications,” IEEE J. integrator settling time,” IEEE Trans. Circuits Syst. II: Analog Digit.
Solid-State Circuits, vol. 42, no. 6, pp. 1206–1215, Jun. 2007. Signal Process., vol. 46, no. 6, pp. 810–816, Jun. 1999.
[9] E. Dallago, P. Malcovati, D. Miatton, T. Ungaretti, and G. Venchi, [32] A. Marques, Y. Geerts, M. Steyaert, and W. Sansen, “Settling time
“Analysis of sigma-delta converters for MEMS sensors using power analysis of third-order systems,” in Proc. IEEE Int. Conf. Electron.,
supply voltage as reference,” Inst. Electr. Eng. Proc. Circuits Devices Ciruits Syst., Lisboa, 1998, vol. 2, pp. 505–508.
Syst., vol. 53, no. 5, pp. 473–479, Oct. 2006. [33] A. Pugliese, G. Cappuccino, and G. Cocorullo, “Design procedure for
[10] L. Zhang, H. J. Kim, V. Nadig, and M. Ismail, “A 1.8 V tri-mode 61 settling time minimization in three-stage nested-miller amplifiers,”
modulator for GSM/WCDMA/WLAN wireless receiver,” Analog In- IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 55, no. 1, pp. 1–5, Jan.
tegr. Circuits Signal Process., vol. 49, pp. 323–341, Sep. 2006. 2008.

Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:427 UTC from IE Xplore. Restricon aply.
630 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 3, MARCH 2010

[34] C. Azzolini, P. Milanesi, and A. Boni, “Accurate transient response Gregorio Cappuccino (M’00–SM’08) received
model for automatic synthesis of high-speed operational amplifiers,” the Laurea degree (magna cum laude) in computer
in Proc. IEEE Int. Symp. Circuits Syst., May 2006, pp. 5716–5719. science engineering from the University of Calabria,
[35] A. Pugliese, G. Cappuccino, and G. Cocorullo, “Settling time min- Cosenza, Italy, and the Ph.D. degree in electronics
imization of operational amplifiers,” in Lecture Notes in Computer from the Politecnico of Turin, Torino, Italy, in 1992
Science. Berlin, Germany: Springer-Verlag, 2007, vol. 4644, pp. and 1998, respectively.
107–116. In 1993, he joined the Electronic Components
[36] S. Rabii and B. A. Wooley, “A 1.8-V digital-audio sigma-delta modu- and Electromagnetism Institute of National Council
lator in 0.8- m CMOS,” IEEE J. Solid-State Circuits, vol. 32, no. 6, of Research, where he was involved in the design
pp. 783–796, Jun. 1997. of a Synthetic Aperture Radar Data Processor.
Since 1994, he has been with the Department of
Andrea Pugliese was born in 1969. He received the Electronics, Computer Science and Systems, University of Calabria, where he
Master’s degree in computer science engineering and is currently an Associate Professor. His research and teaching interests include
the Ph.D. degree in electronics engineering from the digital and analog electronics, mixed-signal silicon circuit and system design,
University of Calabria, Cosenza, Italy. and high-speed interconnects.
He was with STMicroelectronics, Catania, Italy, Dr. Cappuccino is an Associate Editor of the Journal of Circuits, Systems
as sustain engineering for memory device designers. and Computers. He was the recipient of the University of Calabria Young Re-
In 2002, he joined the Department of Electronics, searchers Award for 1999 and University of Calabria Learning Enhancement
Computer Sciences and Systems, University of Cal- Project Award in 1999.
abria, where he is currently an Assistant Researcher
of electronics. His main research interests include
frequency compensation operational amplifier tech-
nique, delta-sigma analog-to-digital converters modulation, and low-voltage Giuseppe Cocorullo (M’93) was born in 1952. He
low-power CMOS analog design. received the Dr. Eng. degree in electronics from the
University of Naples, Naples, Italy, in 1978.
From 1983 to 1992, he was with the National
Council of Research, Research Institute for Elec-
Francesco Antonio Amoroso was born in 1983. tromagnetism and Electronic. Components, Naples,
He received the Master’s degree in electronics en- Italy, where he was In-Charge of the Microelec-
gineering from the University of Calabria, Cosenza, tronic Department. Since 1992, he has been an
Italy, in 2006. Associate Professor of electronics at the University
He is currently with the Department of Elec- of Calabria, Cosenza, Italy, where he has also been
tronics, Computer Sciences and Systems, University a Full Professor of electronics since 2000, and
of Calabria. His research interests include the design where he is currently with the Department of Electronics, Computer Science
of high-speed low-power analog and mixed-signal and Systems. His main research interest include silicon optoelectronics and
CMOS circuits, sigma-delta analog-to-digital con- application-specific IC design.
verters, and operational amplifiers for switched-ca-
pacitor applications.

Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:427 UTC from IE Xplore. Restricon aply.