Digital Logic FPGA Lab Manual

Lab 1 – Introduction
Due Date: Today + 1 Week
LabVIEW FPGA is an add‐on for LabVIEW that targets FPGA devices, which in turn enables graphical
programmers with the benefit of developing customized, reconfigurable hardware. The Digital Logic VI
Library is a collection of common logic devices used for developing circuits in the form of a digital
schematic. Although, using the Digital Logic VI Library is not a traditional approach for developing in
LabVIEW FPGA, it is a helpful tool for introducing digital logic fundamentals. The following lab serves as
an introduction to using the Digital Logic VI Library in LabVIEW FPGA.
In this lab experiment, the student will design a combinational logic circuit (CLC) derived from a given
truth table. This lab requires some knowledge of fundamental digital logic concepts, including basic logic
gates and truth tables. Both of which are discussed in the Background & Theory section of this lab
handout.
Objectives
9 Derive the Sum‐of‐Products and Product‐of‐Sums expressions from a given truth table.
9 Design and implement a combinational logic circuit.
9 Become familiar with using logic devices and FPGA I/O on the Spartan‐3E Starter Board.
9 Integrate a seven‐segment display module.
PreLab Preparation
Write the SOP and POS Boolean expressions derived from the following truth table. Additionally, create
the logic circuit for the truth table using the SOP form for one output and the POS form for the other.

Background & Theory
Truth Tables
One common way to express the particular function of a logic circuit is called a truth table. Truth tables
show all permutations of the inputs with their corresponding output values in terms of logic level states.
Logic level states are typically expressed as 1 and 0, HIGH and LOW, or True and False. Figure 1 shows
the schematic symbol and the truth table for an OR gate with two inputs.

Figure 1 ‐ OR Gate Schematic and Truth Table
A gate or logic circuit’s truth table must have as many rows as there are possibilities of unique input
combinations. For a single‐input gate, like the inverter, there are only two input possibilities, namely 0
and 1. For a two‐input gate there are four possibilities (00, 01, 10, and 11), and thus four rows for the
corresponding truth table. For a three‐input logic device, there are eight possibilities and so forth. The
input columns are typically written in binary order as shown below in Figure 2.

Figure 2 ‐ Three‐Input Truth Table
SumOfProducts & ProductOfSums
A simple method for converting a truth table into a CLC is found in a standard form of Boolean
expression called the Sum‐of‐Products (SOP) form. An SOP expression is literally a sum of Boolean terms
called minterms. A minterm is a multiplicative combination of Boolean variables whose output equals 1.
An example of an SOP expression is ABC + BC + DE, where ABC, BC, and DE are minterms. SOP
expressions may be generated from truth tables using the following steps:
1. Determine which rows of the table have an output of 1.
2. Derive each row’s minterm, such that the output is 1 given that row’s input state.
3. Sum the minterms.
Figure 3 illustrates a truth table conversion to an SOP expression.
A’B’C
O = A’B’C + AB’C’ + AB’C + ABC’
AB’C’
AB’C
ABC’

Figure 3 ‐ Truth Table to SOP Conversion
SOP expressions can easily be implemented as a set of AND gates feeding into a single OR gate. Figure 4
shows a CLC implementation of the previous SOP expression. Notice how the AND gates correspond to
the minterms found above.

Figure 4 ‐ CLC Realization of Truth Table
Product‐of‐Sums (POS) expressions are another way of representing truth tables. A POS expression is a
product of Boolean terms called maxterms. A maxterm is a summation of Boolean variables whose
output equals 0. To generate a POS expression from a truth table, perform the following steps:
1. Determine which rows of the table have an output of 0.
2. Derive each row’s maxterm, such that the output is 0 given that row’s input state.
3. Multiply the maxterms.
Conversely to SOP expressions, POS expressions can be implemented as a set of OR gates feeding into a
single AND gate. Figure 5 shows the same truth table expressed as a POS and its corresponding CLC.
A + B + C
A + B’ + C
A + B’ + C’
O = (A + B + C) (A + B’ + C) (A + B’ + C’) (A + B + C)
A + B + C
Figure 5 ‐ Truth Table to POS CLC Conversion
The SOP and POS standard Boolean forms are powerful tools when applied to truth tables. They can be
used to derive a Boolean expression—and ultimately, an actual logic circuit.
Workstation Details
PC Desktop / Laptop with LabVIEW FPGA 8.5.1 or later
Spartan‐3E Starter Board with USB Cable and Power Supply Wall Adapter

Lab Procedure
Task
Create a digital logic design from the following truth table using LabVIEW FPGA and the Digital Logic VI
Library devices.
Requirements
• Use SOP for at least 3 outputs and POS for at least 3 outputs.
• Develop test plan for verifying design. In other words, plan a way to test the design after
downloading it to the Spartan‐3E Starter Board.
• Verify the design using the Spartan‐3E Starter Board—slide switches as inputs and LED’s as
outputs.
• Demonstrate to lab instructor.
Tips
• Choose SOP / POS implementations wisely to cut down on gates, wires, and design time.
• Find out how to add and use FPGA I/O such as switches and LED’s in the schematic:
http://zone.ni.com/reference/en‐XX/help/371599C‐01/lvfpgahelp/creating_fpgaio/ .
• Keep the schematic design neat and easy to understand (i.e. clean wiring, text labels, etc).
PostLab Questions
• How many rows would a truth table require for an n‐input logic circuit?
• What do the True and False Boolean constants represent in reality?
• When would it be best to use the POS form of an output to derive a logic circuit?
• Do SOP or POS expression forms represent an output function as minimal as possible or can they
be reduced further? Justify your reasoning.
• What is your favorite part of this lab? Least favorite part? Why?

Lab Report
Submit an individual lab report at the beginning of the next lab session with the following sections and
requirements:
• Cover Sheet – Include title, name, class, section, date due, date submitted, and professor and
lab assistant names
• Introduction – Summarize the lab procedure in a few sentences. Do not rewrite what is written
in this lab handout.
• Design – Explain your design and its purpose, test plan and results, obstacles encountered and
how you resolved them. Include images.
• Conclusion – Discuss your overall experience and how it relates to digital logic and electronics
concepts.
• Post‐Lab Questions – Answer all questions completely.

The lab report should be single‐spaced, typed, and a minimum of 1½ pages (excluding images). Neatness
and clarity are also required.

Lab 2 – Karnaugh Maps
In this lab experiment, the student will design a minimized, seven‐segment display decoder circuit using
Karnaugh maps. This lab requires knowledge of Karnaugh map simplification which is briefly discussed
in the Background & Theory section of this lab handout.
Objectives
9 Create minimal logic circuits using Karnaugh map simplification.
9 Design a minimal seven‐segment display decoder.
9 Implement decoder circuit in LabVIEW FPGA.
PreLab Preparation
For this lab, you will design digital hardware to interface with a seven‐segment display module. Read the
following manual and note the layout of the segments as well as their assigned pins:
http://www.digilentinc.com/Data/Products/PMOD‐SSD/Pmod%20SSD_rm.pdf.
Create a truth table with inputs for a 4‐bit binary number and outputs for each of the seven‐segments of
the display. Fill the output values so the segments will be lit to represent the decimal value of binary
input. For example, the row with the binary input equal to 0111 should have a corresponding output
row with the A, B, and C segments set to 1 to indicate a decimal value of 7 on the display. Since you are
only concerned with single digit decimal values (0 – 9), mark the remaining unused rows as Don’t Cares.
Background & Theory
Karnaugh Map
A Karnaugh map is a handy tool used to derive a minimal Boolean expression from a non‐simplified
form. Ultimately, the primary use of a Karnaugh map is realizing a minimal CLC.
Similar to the number of rows in truth table, a Karnaugh map consists of 2n cells, where n is the number
of Boolean input variables. Each cell represents two significant aspects of a Boolean function—a variable
combination and its corresponding output value. The cells are formed in a square or rectangle fashion
and arranged such that neighboring cells have a single variable difference, otherwise known as Gray
code ordering. For simplicity, the input values are placed as column and row labels. A truth table
represented as a Karnaugh map is shown in Figure 1.
C 0 1
AB
00 0 1
01 0 0
11 1 0
10 1 1

Figure 1 ‐ Karnaugh Map Representation of Truth Table
After transferring the truth table to a Karnaugh map, cells with common output values, either all 0s or
all 1s, are grouped into the largest possible rectangles such that the number of cells in the groups is
equal to 2i and i is some integer value. Valid cell group arrangements include 4 cells in a line, 2 cells high
by 4 cells long, 2 cells by 2 cells, etc. The cells can be used more than once only if it generates the least
number of groups. Also, all cells sharing the chosen common output must be contained within a
grouping.
The groups generated can be converted to a Boolean expression. Each group represents a minimal
minterm (1s) or maxterm (0s). The term is minimized by eliminating variables whose non‐inverted and
inverted forms appear within the same cell group. The terms are then used to derive an SOP or POS
expression form of the represented logic function, which may then be converted to a CLC. When
choosing the POS form, the variable combination is supposed to equal 0, as is the case when deriving a
POS from a truth table. Therefore, the variable’s inverse is used when determining a maxterm. Figure 2
illustrates a Karnaugh map translated to minimized SOP and POS expression forms. Notice how cells can
also wrap around the map.
CD
00 01 11 10
AB
00 1 0 0 1
SOP (1’s): AC + A’D’ + B’D’
K‐map Color
01 1 0 0 1
POS (0’s): (A+D’) (C+D’) (A’+B’+C)
11 0 0 1 1
K‐map Color
10 1 0 1 1

Figure 2 ‐ Karnaugh Map to Minimized SOP and POS Expression Forms
Furthermore, an output state level may be a Don't Care which represents a state that is negligible,
typically because it will never occur. These cells should only be grouped if the resulting cell group is
larger than the group formed without it. In other words, only use Don’t Cares if it further simplifies the
Boolean express; otherwise, ignore it.
SevenSegment Display
A seven‐segment display (SSD) is an electronic device used for displaying numerical values. The device
typically consists of seven segments arranged in a figure 8. Any digit, as well as some alphabet letters,
can be displayed when the correct segments are activated. An example of an SSD as well as possible
outputs can be seen in Figure 3.

Figure 3 ‐ Seven‐Segment Display with Numeric Outputs

Workstation Details
Digilent Seven‐Segment Display (PMOD‐SSD) or similar hardware
Lab Procedure
Task
Using the truth table created in the Pre‐Lab Preparation, design minimal logic circuits in LabVIEW FPGA
for each segment output of the SSD using the Karnaugh mapping technique discussed in the Background
and Theory section.
Requirements
• Implement the design as a subVI. Create a top‐level VI design that uses an instance of the SSD
subVI.
• Use slide switches as inputs and tie outputs to the appropriate I/O port pins connected to the
seven‐segment display module. (Refer to the SSD reference manual).
• Create a test plan to verify the design. Debug when necessary.
Tips
• Keep the schematic design neat and easy to understand (i.e. clean wiring, text labels, etc) in
order to make debugging simpler.
• Implement the design as a subVI. (For more information on how to create a LabVIEW subVI,
search the National Instruments website at www.ni.com ).
• Create a top‐level VI design that uses an instance of the SSD subVI.
• Use slide switches as inputs and tie the outputs to the appropriate I/O pins connected to the
seven‐segment display module. (Refer to the SSD reference manual).
PostLab Questions
• What are the benefits of making a CLC as minimal as possible?
• Are there other “minimized” ways of expressing a digital function? If so, what are they and are
they better than minimized SOP or POS? Why?
• Which segment required the least amount of circuitry? What makes this so?
• Describe in detail the test plan used to verify the SSD design, as well as the debugging process
used to correct any errors.
Lab Report
requirements:
lab assistant names
concepts.


Lab 3 – Combinatorial Logic Devices
In the previous lab, the student built their first combinational logic device commonly referred to as a
decoder. In the following lab sessions, the decoder and other combinational logic devices will be
applied. In today’s lab experiment, the student will design, implement, and verify a 4‐bit, 2:1
multiplexer. Learning to develop such a device will be greatly beneficial for the lab project. This lab
requires knowledge of Karnaugh map simplification, as well as knowledge on how to create higher level
devices by cascading / combining lower level devices.
Objectives
9 Create a 4‐bit, 2:1 multiplexer device.
9 Implement multiplexer circuit in LabVIEW FPGA.
9 Verify design on Spartan‐3E Starter Board with onboard hardware.
Background & Theory
Combinational logic devices, or combinatorial devices, are circuits built solely from basic logic gates.
These circuits are used with a specific purpose and can be represented as a truth table. This section
provides a brief discussion on a few combinatorial devices commonly used in digital logic design. In the
next lab session, the remaining combinatorial devices will be discussed.
Decoders / Encoders
In the previous lab, a device was designed with a specific purpose to convert binary codes to a code
relevant for a seven‐segment display. This process of translating ambiguous information into something
understood by the device receiving the data is called decoding. Therefore, the resulting device is known
as a decoder. Conversely, translating data into something ambiguous is called encoding and may be
achieved using an encoder.

Figure 1 ‐ 3‐to‐8 Line Decoder with Enable
A line decoder is the simplest type of decoder that translates a binary input into a one‐hot code. For
example, a 3‐to‐8 line decoder will activate Data Output 4 when the Input Address is 1002, where
Address Bit 0 is the least significant bit.
A priority encoder is a simple type of encoder that works in the reverse operation of a line decoder. For
instance, in the case of the 2‐bit priority encoder shown in Figure 2, if Data Input 2 is activated, the
output would be 102, with Output Code 0 as the least significant bit.

Figure 2 ‐ 2‐Bit Priority Encoder with Enable
However, what if more than one input is activated? When this occurs, the highest data input (or lowest,
depending on the priority encoder’s design) is given priority and the active lower data inputs (or higher)
are ignored.
Multiplexers / Demultiplexers
Therefore, a multiplexer, or selector, is a multiple‐input, single‐output device whose output is
determined by a set of select lines. In contrast, a demultiplexer is a single‐input, multiple‐output device
that does the inverse of multiplexing by sending an input to a selected output path. (A common use for
multiplexers is a technique known as multiplexing and will be implemented in a later lab). Figure 3
shows the conventional schematic symbol for a multiplexer.

Figure 3 ‐ 2:1 Multiplexer with Enable
For the multiplexer shown, the Selector input determines which data input is connected to the output
when the device is enabled. In other words, Data Output will be the same value (ON or OFF) as the
selected data input. A demultiplexer works in the opposite manner with a single data input being
connected to a selected data output.
The multiplexer above is only 1‐bit wide since a single bit line is connected to a single output bit line.
Suppose there was a need to select a group of signals from multiple groups of signals. For example, a 2:1
multiplexer might have to accommodate for n‐bit inputs, requiring an n‐bit, 2:1 multiplexer.
Logical Shifter
A logical shifter is a device that shifts and outputs an input a specified number of times. For example, if
the input of a 4‐bit, left‐shift logical shifter pictured was 10112 and the shift input was set to 102, the
output would be the input shifted three times to the left, or 11002. (Note that logical shifters may be
configured to shift to the left or right and the shift‐in value can be set to 0 or 1).

Figure 4 ‐ 4‐Bit Logical Shifter

Workstation Details
Lab Procedure
Task
Design a 4‐bit, 2:1 multiplexer using only the combinatorial logic devices mentioned in the Background
and Theory section.
4
Data Input 0
4
Data Input 0
4
Data Input 1
Select Line
Requirements
• Implement the design as a subVI. Create a top‐level VI design that uses an instance subVI.
• Use slide switches, push buttons, and LED’s appropriately when verifying and demonstrating the
design.
• Demonstrate working design to lab instructor.
Tips
• Unclear about how a multiplexer behaves? Ask the lab instructor.
• Begin with a black box view approach, only considering the external inputs and outputs.
• Be sure to consider bit order while designing. The Digital Logic VI Library device inputs and
outputs start with the least significant bit at the top.
• Bus inputs and outputs together to cut down on wire clutter. The Bus and Bus Tap devices can
be found under General Devices.
• Today’s lab is meant to be thought‐provoking. There is more than one solution, so refrain from
getting help from other students.
PostLab Questions
• Write succinct definitions (complete with illustrations) for each of the mentioned digital devices,
based on your own research and written using your own words. Also, identify which two of
these digital functions are usually performed by the same integrated circuit.
• Mathematically, what is happening to the data going through a logical left shift device? Logical
right shift device? (Think in terms of the input and output value).
• Give three examples in life that could be used to express the functionality of any of the
mentioned devices. For example, two roads that merge into one at a traffic light could represent
a 2:1 multiplexer with the traffic light acting as the select line.
Lab Report
requirements:
lab assistant names
concepts.


Lab 4 – Binary‐to‐BCD Converter
In this lab experiment, the student will apply their knowledge of combinatorial devices including
multiplexers and adders in order to design, implement, and verify an 8‐Bit Binary‐to‐BCD converter. This
will be achieved using the Shift‐Add‐3 algorithm discussed in the Background and Theory section.
Objectives
9 Understand how adder and magnitude comparator devices function.
9 Create an 8‐bit Binary‐to‐BCD Converter device.
9 Implement digital circuit in LabVIEW FPGA.
9 Verify design on Spartan‐3E Starter Board with onboard hardware.
Background & Theory
Adder
An adder is a device that outputs the sum of two inputs, typically in binary form. A half‐adder does
binary addition on two inputs and outputs a sum and carry value, while a full‐adder, similar to the one
shown in Figure 1, does binary addition on three inputs, one being the carry value. A full‐adder may be
cascaded to create a ripple carry adder—ripple because the carry value ripples from one adder stage to
the next.

Figure 1 ‐ 4‐Bit Adder
Magnitude Comparator
A magnitude comparator outputs the relationship between two binary inputs in terms of magnitude.
Typically, the device outputs whether Input A is greater than, less than, or equal to Input B as shown in
Figure 2.

Figure 2 ‐ 4‐Bit Magnitude Comparator
A common misconception for beginning digital logic students is the output of the magnitude comparator
is a data value; however, this is not the case. In digital electronics, all wire paths can be categorized into
three types: control signals, data paths, or both. The operand inputs of a magnitude comparator are
data paths, since they are actual values. The outputs are control signals because they indicate
something about the data.
BinarytoBCD Converter
The binary number system is appropriate for digital logic systems, since there are only two values an I/O
can have, namely Vcc (ON) or ground (OFF). However, it is not ideal for human interaction. Instead, it
would be more useful to indicate significant values in decimal form. A medium between the binary
system and the decimal system is binary‐coded decimal (BCD). A binary number in BCD form has each of
its decimal digits represented as a 4‐bit, binary value. For example, 110110112 (219) would be
represented as 00102 00012 10012. By pairing each digit with a SSD decoder, the output can be displayed
in decimal form using an SSD decoder. (Although only a single SSD decoder is necessary).
In order to output the decimal value of a binary number that requires multiple decimal digits (i.e. any
number greater than 9), a conversion from binary to BCD must take place using a Binary‐to‐BCD
converter. It is possible to build such a device using the same Karnaugh mapping method as in Lab 1;
however, as the number of input bits increases, this can become cumbersome. A more efficient design
method would be ideal. One such implementation is called the Shift‐Add‐3 algorithm.
Given a 4‐bit binary number less than 1010, no conversion is required. In other words, 0 – 9 are already in
correct BCD format. However, a binary number equal to 1010 or more requires some modification. The
corresponding BCD value can be found by subtracting 1010 from the original number to obtain the ones
digit, and adding a one to the tens BCD value. (Adding a one to the tens BCD value is equivalent to
adding 0001 00002, or 16, to the original number). An example of this process is shown in Table 1 using
12 as the input binary value.
Table 1 ‐ Binary‐to‐BCD Conversion
Operation Value
1. Start with 12 0000 11002
2. Subtract 10 0000 00102
3. Add 16 0001 00102
BCD Output 1 2
Instead of subtracting 1010 and adding 16, simply add 6 if the number is greater than or equal to 1010.
This works well for 4‐bit binary numbers; however, for larger numbers, shift the input one bit at a time,
up to the number of bits in the number. At each shift add 6 to a digit if the number is 1010 or greater. The
following table shows this process using 70 (101 00112) as the example number.
Table 2 – Shift‐Add‐6 Algorithm for Binary‐to‐BCD Conversion
Operation Tens Ones Input
Binary Input 1000110
Shift Left 1 000110
If >= 10, Add 6 1 000110
Shift Left 10 00110
If >= 10, Add 6 10 00110
Shift Left 100 0110
If >= 10, Add 6 100 0110
Shift Left 1000 110
If >= 10, Add 6 1000 110
Shift Left 1 0001 10
If >= 10, Add 6 1 0111 10
If >= 10, Add 6 11 0101 0
Shift Left 110 1010
If >= 10, Add 6 111 0000
BCD Output 7 0
Notice after adding 6 (calculations highlighted in bold), a bit is carried into the next digit. This means five
output bits are needed at each step rather than four. However, there may be a better solution in order
to reduce the number of outputs. When a binary number is shifted once to the left, it is actually being
doubled. Therefore, each step of the process is 2 or 2 6. The latter can be simplified to 2 3 .
Since is not doubled yet, the condition changes to 5 instead of 10. Effectively, the order of
operations is being switched which limits the output to four bits, since the maximum sum possible is
11002. As a result, the new algorithm shifts and adds 3 to a digit if it is greater than 5. Table 3 shows the
same conversion using the Shift‐Add‐3 algorithm.
Table 3 – Shift‐Add‐3 Algorithm for Binary‐to‐BCD Conversion
Operation Tens Ones Input
Binary Input 1000110
Shift Left 1 000110
If >= 5, Add 3 1 000110
Shift Left 10 00110
If >= 5, Add 3 10 00110
Shift Left 100 0110
If >= 5, Add 3 100 0110
Shift Left 1000 110
If >= 5, Add 3 1011 110
If >= 5, Add 3 1 1010 10
If >= 5, Add 3 11 1000 0
Shift Left 111 0000
BCD Output 7 0
The same procedure may be applied for any number of input bits by shifting and conditionally adding
until all input bits have been shifted (i.e. for an 8‐bit input, 8 shifts are required). In order to implement
this in circuit form, a 4‐bit device that adds 3 when the input is 5 or greater is necessary. The converter
design can then be arranged diagonally as shown in Figure 3 to satisfy the algorithm’s shifting
requirement.
Ones Digit
8‐Bit
Binary Input
Tens Digit
Hundreds Digit

Figure 3 ‐ Binary‐to‐BCD Converter Diagonal Arrangement
Workstation Details
Lab Procedure
Task
• Design an 8‐bit, Binary‐to‐BCD converter.
Requirements
• Implement the design as a subVI. Create a top‐level VI design that uses an instance subVI.
• Use slide switches, push buttons, and LED’s appropriately when verifying and demonstrating the
design.
Tips
• Begin by designing and verifying the “Add 3, if Greater or Equal to 5” device. Create this as a
subVI in order to reuse it.
• Use any design method or any devices discussed as well as previously designed devices.
• Be sure to consider bit order while designing.
• There are plenty of FPGA I/O to verify the design. Be creative.
PostLab Questions
• In the Background and Theory section, it is stated, “When a binary number is shifted once to the
left, it is actually being doubled.” Modify this statement so that it applies to any number system
(i.e. binary, octal, hexadecimal, and decimal).
• The Binary‐to‐BCD converter is built using the Shift‐Add‐3 algorithm. Why is this method better
than the previous method of creating a decoder design? What benefits might a decoder design
have?
• A ripple carry adder ripples the carry value from one full‐adder to the next. What is an inherent
problem in this design? What solutions exist to avoid this problem? Additionally, how is this
relevant to the Binary‐to‐BCD converter?
• Instead of using the initial process of shifting and adding 16, the Shift‐Add‐3 algorithm was used
to reduce the number of outputs. Why is this significant?
Lab Report
requirements:
lab assistant names
concepts.


Lab 5 – Sequential Logic Devices
In this lab experiment, the student will design, implement, and verify an 8‐bit Binary‐to‐Seven‐Segment
decoder/driver. The students will also be introduced to sequential devices beginning with various flip‐
flops as well as digital techniques such as multiplexing and display refreshing.
Objectives
9 Learn about flip‐flops, multiplexing, and SSD circuitry
9 Design a display refresher device.
9 Design an 8‐bit Binary‐to‐Seven‐Segment decoder/driver.
Background & Theory
Sequential logic devices are digital devices capable of holding a value, otherwise known as memory. The
output of a sequential device typically reflects the value being held. The internal value of a sequential
device depends on its inputs and sometimes its present value. Sequential devices are edge‐triggered and
update their internal value on the rising and/or falling edge of an input—typically, a clock input. This
section provides a brief discussion on the most fundamental sequential device—the flip‐flop.
FlipFlop
A flip‐flop is a single‐bit, memory element. There are different types of flip‐flops. The most basic flip‐flop
is the D flip‐flop, or data flip‐flop as shown in Figure 1. Its internal value, expressed by Data Output,
updates to Data Input’s value on the appropriate clock edge. (Note: All flip‐flops in the Digital Logic VI
Library are positive‐edge‐triggered). Flip‐flops may have extra inputs such as Asynchronous Set/Reset,
Clock Enable, etc. to provide additional functionality.

Figure 1 – Data Flip‐Flop
A T flip‐flop, or toggle flip‐flop typically inverts, or toggles, its internal value when its Toggle Input is
active. Conversely, its internal value is held when Toggle Input is inactive. The T flip‐flop differs from a D
flip‐flop since its internal value depends on the internal value itself as well as an input. A common T flip‐
flop application is a clock divider. Lastly, the J‐K flip‐flop is the most flexible flip‐flop. It has the ability to
function as either a D or T flip‐flop.
BCDtoSevenSegment Decoder/Driver
After completing the previous lab, the output of the 8‐bit Binary‐to‐BCD converter should be 12 bits—
four for each BCD value of each decimal digit (ones, tens, and hundreds). (Since the SSD hardware only
has two digits, only consider the ones and tens digit). These values can easily be decoded to their SSD
equivalent using the previously designed SSD decoder; however, the SSD hardware module does not
have inputs to accommodate for multiple SSD decoders. Instead, the SSD implements a common‐
cathode circuit for each set of segments and adds additional hardware (inverters) so that only one set of
segments is activated at a time, as illustrated in Figure 2. If the SSD was configured to display both digits
simultaneously, it would require significantly more signals—14 rather than 8!
Segment A
Segment B Anodes
Segment C
Segment D
A1 A2
B1 B2
C1 C2
D1 D2
E1 E2
F1 F2
Segment E G1 G2
Segment F CAT1 CAT2
Segment G
Cathode
Common Cathode

Figure 2 – Seven‐Segment Display Circuitry
The SSD circuitry is built with the assumption that the human eye won’t be able to notice the fast
switching between segments. According to the SSD documentation, each set of segments must be
driven for 1 to 16 ms in order for both digits to appear illuminated. This is equivalent to a refresh rate of
1 kHz to 60 Hz. (See PMOD‐SSD documentation for further details). A clock input frequency greater than
1 kHz could be easily divided to achieve a rate within this range.
Since the SSD module requires a single set of segment signals, there is need for only one SSD decoder.
Therefore, the ones and tens digit must be multiplexed. Multiplexing is a technique used in
communications where multiple sources share a common signal path and can be achieved using a
multiplexer device. In this case, the sources are the ones and tens digit in BCD form and the common
signal path is the SSD decoder input, labeled Digit in Figure 3.
Ones
8‐Bit Digit Segment

Binary Input Outputs
Tens
Figure 3 – Multiplexing Setup
However, the multiplexing setup is incomplete since nothing is driving the multiplexer’s select line.
When should the ones digit be sent? When should the tens digit be sent? Assuming the delays from the
multiplexer inputs to the segment outputs are negligible, the ones digit should be selected when the
right segment’s cathode is grounded and vice versa for the tens digit. Essentially, the same signal driving
the SSD cathode can be used to for selecting the correct digit output of the multiplexer. This form of
multiplexing, known as time‐division multiplexing, shares the signal path by allocating a certain amount
of time for each input. In this case, the multiplexer alternately outputs the ones and tens binary code for
1 to 16 ms.
Workstation Details
Lab Procedure
Tasks
• Design and implement a clock divider that satisfies the SSD module refreshing requirements.
• Design an 8‐bit Binary‐to‐Seven‐Segment decoder/driver by integrating the Binary‐to‐BCD
converter, SSD decoder, and any other necessary devices.
Requirements
• Implement each design as a subVI. Create a top‐level VI design that uses an instance subVI.
• Use slide FPGA I/O appropriately when verifying and demonstrating the design.
Tips
• The Spartan‐3E Starter Board has an onboard clock of 50 MHz and can be accessed using the
Clock device in the General Devices category of the Digital Logic VI Library.
• Verify the refresher device using an oscilloscope or logic analyzer.
PostLab Questions
• What must be done to a J‐K flip‐flop so that it acts like a D flip‐flop? T flip‐flop? D flip‐flop with
an active‐low data input? Illustrate.
• The required refresh rate is 1 KHz to 60 Hz. What might happen above and below this threshold?
• The SSD module allows for only two digits. Given the same refreshing specifications, what design
modifications would be necessary if the SSD module had four digits? Explain.
Lab Report
requirements:
lab assistant names
concepts.


Lab 6 – Pulse Width Modulation
Due Date: Today + 2 Weeks
In this lab experiment, the student will be introduced to the concept of pulse width modulation (PWM).
They will design, implement, and verify a PWM controller using previously discussed logic devices, as
well as, the data register and bidirectional counter. The PWM controller will play an integral part in DC
motor control portion of the course project.
Objectives
9 Understand PWM and how it is used in electronic design.
9 Design a PWM controller and achieve a specific PWM signal.
9 Implement and verify design in LabVIEW FPGA with Spartan‐3E Starter Board.
Background & Theory
Data Register
A data register is essentially a group of data flip‐flops and is used to hold a multi‐bit data value. Similar
to a flip‐flop, the data value is updated on a clock edge. Registers have many uses including fast data
access, state machines, and pipelining.

Figure 1 – Data Register
Counter
A counter is a sequential device similar to a data register. However, it has the ability to increment or
decrement the internal data value on a clock edge. Some counters are unidirectional, such as up‐
counters and down‐counter. The counter provided in the Digital Logic VI Library is bidirectional and
changes counting direction based on the Up/Down Mode Selector input. Additionally, the provided
counter has the ability to be cascaded in order to create larger counters.

Figure 2 – Bidirectional Counter
Pulse Width Modulation
It is important to understand some basic terms before learning about pulse width modulation. A digital
signal that repeats itself can be described in terms of it maximum voltage ( ), period ( ), and the
pulse duration ( ). As illustrated in Figure 3, is the maximum voltage of the signal, is the duration
of the signal that is repeating, and is the duration of the period that is active.

Figure 3 – Digital Signal
Frequency ( ) is the inverse of the period. In other words, frequency can simple be described as the
number of time a signal repeats itself in one second. Similar to the pulse duration, the duty cycle ( ) of
a signal is the pulse duration relative to the period. It is described in a fraction or percentage form. For
example in Figure 3, assume the pulse duration is half of the period, or . The signal could then be
described as having a duty cycle of 50%, since it is active for 50% of the time.
Pulse width modulation (PWM) is a digital signaling technique that involves the modulation, or
changing, of a digital signal’s duty cycle in order to imitate an analog signal. One common application of
PWM is power control. Some examples of this include DC motor control and LED brightness control. The
amount of power an analog device receives is directly proportional to the product of and the duty
cycle of the PWM input signal. For example, a 3.3 V signal at 50% duty cycle would imitate an analog
signal equivalent to 1.75 V as shown in Figure 4.
3.3
825
0
DC = 25%
3.3
1.75
0
DC = 50%
3.3
2.48
0
DC = 75%
Figure 4 – Duty Cycle Examples
Another factor to consider when using PWM is the frequency. The PWM frequency affects the
performance of the device and power efficiency. The optimal frequency value varies amongst different
devices; therefore, refer to the device’s documentation. If the PWM frequency is outside of the
suggested threshold, the device may function abnormally or become damaged.
PWM Controller Design #1
One way to design a PWM controller involves configuring a data register, bidirectional counter, and T
flip‐flop as shown in Figure 4.
Load
Data Data PWM

Up/Down Terminal
Count
Clock

Figure 5 – PWM Controller Design #1
Initially, while the PWM output is low, the counter is loaded with the data register value and begins
counting down to zero. When the counter reaches zero, terminal count triggers the T flip‐flop and the
PWM output becomes high which toggles the counter direction. The counter is reloaded with the data
register value, counts up, and reaches its maximum value. Terminal count pulses and toggles the PWM
output and counter direction. The process repeats itself.
The data register value affects the duty cycle of the PWM signal—the lower the number, the larger the
duty cycle and vice versa. In addition, ; where, is the PWM frequency, is the clock
frequency, and is the bit width of the bidirectional counter.
PWM Controller Design #2
Another design for a PWM controller involves a data register, counter, and magnitude comparator
arranged as shown in Figure 6. Initially, while the PWM output is low, the counter is loaded with the
data register value and begins counting either down to zero or up to its maximum value. The counter is
reloaded with the data register value and repeats this counting process. The changing count value from
the counter is compared with a constant value through the magnitude comparator. A PWM signal
output is generated from the less‐than or greater‐than output, depending on the magnitude comparator
input arrangement.
Load
Data
Terminal PWM
Count
Clock
Data
Constant

Figure 6 – PWM Controller Design #2
The data register value affects the resulting PWM frequency, such that ; where
is the number of unique values from the data register value to the terminal count value—
either zero or all ones, depending on the count direction. Finally, the constant magnitude comparator
input acts as a marker for where the active and inactive state meet, thus affecting the duty cycle.
Workstation Details
Oscilloscope or Logic Analyzer
Lab Procedure
Task
• Design and implement a PWM controller with the ability to output a 5 kHz signal with at least 4
different duty cycles.
Requirements
• Implement the design as a subVI. Create a top‐level VI design that uses an instance of the subVI.
• Verify the correct signal output using an oscilloscope or logic analyzer.
Tips
• Use the designs discussed in the Background and Theory section. Implement a different PWM
controller design for extra credit.
• Start simple and aim for a single duty cycle value at 5 kHz. Reevaluate the design to achieve
another duty cycle. Decide what can be done to achieve multiple duty cycles.
• Cascade counters to achieve a larger count.
PostLab Questions
• In the previous lab, a clock dividing circuit was required to create a refresher device. A common
way of achieving such a device is cascading T flip‐flops until the desired clock rate is found. What
sequential device is the equivalent of cascading T flip‐flops? Explain.
• Devices controlled by PWM have an optimal PWM frequency range. What might happen if a
PWM signal is above this range? Below it?
Lab Report
requirements:
lab assistant names
• Design – Explain your design and its purpose, testing results, obstacles encountered and how
you resolved them. Include images.
concepts.


Lab 7 – Quadrature Encoding
In this lab experiment, the student will be introduced to the concept of pulse width modulation (PWM).
They will design, implement, and verify a PWM controller using previously discussed logic devices, as
well as, the data register and bidirectional counter. The PWM controller will play an integral part in DC
motor control for the course project.
Objectives
9 Understand PWM and how it is used in electronic design.
9 Design a PWM controller and achieve a specific PWM signal.
9 Implement and verify design in LabVIEW FPGA with Spartan‐3E Starter Board.
Background & Theory
Quadrature Encoding
A quadrature encoder, or rotary encoder, is a type of incremental encoder used in mechanical systems
to determine how much an axis rotates and in what direction. The encoder generates two quadrature
signals (QA and QB) with magnetic or optical hardware. These signals are out of phase by 90° in order to
convey direction. For example, if QA leads QB, the axis is rotating in one direction; however, if QB leads
QA, the axis is rotating in the other direction. Figure 1 illustrates the notion of leading.
QA
(a)
QB
QA
(b)
QB

Figure 1 – (a) Signal QA leading Signal QB (b) Signal QB leading Signal QA
The amount of rotation is determined by counting the number of steps. Steps may refer to either the
number of pulse sets (2 in the example above) or the number of edges (10 in the above case). The
number of steps can be used to determine measurements such as distance, RPM, etc.
Quadrature Decoder/Counter Design
A quadrature decoder is hardware that converts the quadrature encoded signals into relevant signals—
namely the direction of rotation and a step indicator. Combined with a counter device, the movement
and rotational distance can be determined. The hardware for a quadrature decoder is relatively simple
as shown in Figure 2.
QA
Count
Direction
QB
Count
Enable
Clock

Figure 2 – Quadrature Decoder Design using D Flip‐Flops
The use of multiple flip‐flops to capture the edges of the incoming quadrature signal is to avoid
metastability. In electronics, metastability occurs when a memory device holds an invalid value. For
example, a flip‐flop value can become metastable if the data value input changes during the setup to
hold period. In other words, the input value was not stable while the device started lock in the value.
Workstation Details
DC Motor with Quadrature Encoder Feedback
Lab Procedure
Task
• Design and implement a Quadrature Decoder/Counter device that outputs the direction and
number of revolutions for a DC motor shaft.
Requirements
Tips
• Use the PWM controller from the previous lab to drive the DC motor and receive valid
quadrature signals to decode.
• Use an LED to indicate turn direction and the remaining LEDs for counting the number of
revolutions.
PostLab Questions
• What is the maximum frequency the quadrature encoded signals can a quadrature decoder
handle on a Spartan‐3E Starter Board? Explain.
• What other factors must be known in order to calculate the distance a DC motor platform
travels? RPM?
• Name 3 other devices that use quadrature encoded signals. How are they used in those
applications?
Lab Report
requirements:
lab assistant names
concepts.


Lab 8 – Finite State Machines
Due Date: Today + 2 Weeks
In this lab experiment, the student will learn about finite states machines. They will use state machines
to design a 4‐bit up counter. This is the final lab before beginning the course project. Concepts covered
here are imperative for the student’s success in the project.
Objectives
9 Understand finite state machines and how to use them in design.
9 Design a 4‐bit up counter using a state machine design approach.
Background & Theory
Finite State Machines
A finite state machine (FSM) is an abstract model used to describe the behavior of an object. The best
way to understand FSM’s is through example. Figure 1 below shows a simple FSM for a system that
unlocks when a correct button sequence is pressed.
ed
d
se
se
s
es
es
es
r
r
’ P
’ P
’ P
‘2
‘1
‘9
S0 S1 S2 S3
Wrong
Button
Wrong Button
Door Opened

Figure 1 – State Machine Example
Each circle represents a state in the system, while each arrow represents a transition to another state.
The arrow labels are events that trigger the state transition. In this example, state 0 (S0) represents a
state when the lock is enabled. S0 moves to S1 after button ‘2’ is pressed. S1 has two options for the next
state—S2 if ‘1’ is pressed, otherwise S0. S2 is similar to S1. S3 represents a state where the lock is disabled
and enables once the door is opened.
Workstation Details
Lab Procedure
Task
• Design and implement a 4‐bit counter as a finite state machine.
Requirements
• The counter must have the following inputs:
o Initialize/Reset
o Run/Hold’
o 1 Hz Clock
Tips
• Carefully consider what type of hardware to use for each input i.e. buttons, switches, etc.
• Use a LED’s to indicate the count.
• Break the design into components and verify each one before integrating all of them.
PostLab Questions
• What would be seen on the LED’s if the clock is left at 50 MHz? Explain.
• Model a quadrature decoder as an FSM? How does it differ from the design given in the
previous lab?

Lab Report
requirements:
lab assistant names
concepts.


Digital Logic FPGA Lab Manual

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Lab 1 – Introduction

8‐Bit Digit Segment

Data Data PWM

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