Chapter 2

VHDL and Digital Circuit Primitives

Digital circuit primitive gates are basic building components such as AND, NAND,
NOR, and INVERTER used by synthesis tools to construct designs. In this chapter,
we will use VHDL to describe these basic digital circuit primitive gates to show how
basic digital circuit gates can be described in VHDL so that the synthesis tools can get
the design we want. It is important to understand the correspondence between VHDL
and basic digital circuit gates.

2.1 FLIP-FLOP

A D flip-flop is the most common sequential element used in the digital design. Fig-
ure 2-1 shows a D flip-flop schematic symbol. It has two inputs, D and CLK, which
represent data and clock, respectively. It has a data output port Q. The following
VHDL code can be used to model the D flip-flop. The IEEE library and
std_logic_1164 package are referenced in lines 1 and 2. Input and output ports are
described in the VHDL entity from lines 3 to 7.

Figure 2-1 D flip-flop symbol.

EL
2,1 Flip-Flop 5

1 library IEEE;
2 use IEEE.std_logic_1164.all;
3 entity DFF is
4 port(
5 CLK, D : in std_logic;
6 Q out std_logic);
:

7 end DFF;
8 architecture RTL of DFF is
9 begin
10 seg0 : process
11 begin
12 wait until CLK'event and CLK = '1';
13 Q <= D;
14 end process;
15 end RTL;

The behavior of the D flip-flop is modeled inside the VHDL architecture from
lines 8 to 15. A concurrent process statement (lines 10 to 14) is used. Recall that dur-
ing the initialization phase of the simulation, every object (which is not initialized
with a value) is initialized to its leftmost value of its basic type. Type std_logic is an
enumerated type with values (`U', 'X', '0', '1', 'Z', 'W', `L', 'H' and '-') to indicate
certain conditions such as uninitialized, forcing unknown, forcing '0', forcing '1',
high impedance, weak unknown, weak '0', weak '1', and don't care, respectively.
Since D, CLK, and Q are declared as std_logic type, they are initialized to the unini-
tialized value `U'. Every concurrent process statement is evaluated until it is sus -
pended. In this case, after D, CLK, and Q are initialized to `U', the process statement
is evaluated from the beginning (line 11) until line 12. The process is then suspended
as it waits for the rising edge of the clock signal CLK. Figure 2-2 shows the simula -
tion waveform obtained by running the following QuickVHDL simulation commands:
run 50, force D 0, force CLK 0, run 50, force CLK 1, run 50, force CLK 0, force D 1,
run 50, force CLK 1, run 50, force CLK 0, run 50, force CLK 1, run 50, force CLK 0,
force D 0, run 50, force CLK 1, run 50, force CLK 0, run 50, force CLK 1, run 50.
Basically, we use the run command to advance the simulation time, and use the force
command to change the input signal values.
The first command, run 50, advances the simulation time to 50 ns. Signals CLK,
D, and Q have the same value `U' since their values have not been assigned. At time
50 ns, D and CLK are both set to '0'. The simulation time is advanced to 100 ns where
the clock signal CLK is assigned to '1'. At this time, the process statement proceeds
through lines 12, 13, 14, and back to 11. It is again suspended at line 12. The output
signal Q is updated from `U' to '0'. Signal D is assigned to '1' at time 150 ns. At time
200 ns, clock signal CLK is assigned to '1', the process statement is executed again
(line 12, 13, 14, back to 11), and suspended once more at line 12. Signal Q is updated
to '1' and the simulation process is repeated as before.
6 Chapter 2 VHDL and Digital Circuit Primitives

250 ns SOO ns

Figure 2-2 D flip-flop simulation waveform.

From the simulation waveform, it is easy to see that signal Q follows signal D
with a delay. Whatever the value of signal D before the rising edge of the clock CLK,
it is captured as the value of signal Q. This is the reason we often refer to a D flip-flop
as a delay flip-flop.
Note that the DFF VHDL code is synthesized to the schematic shown in Figure
2-1. The D flip-flop has only one Q output; output Qn (inverted Q) is not connected.
We can modify the DFF VHDL slightly to include the Qn output as shown in line 6. A
temporary signal DFF is declared in line 9, which is used in line 14. Output signals Q
and Qn are assigned in line 16. The DFFQN VHDL code is synthesized to the sche -
matic as shown in Figure 2-3.

1 library IEEE;
2 use IEEE.std logic_1164.all;
3 entity DFFQN is
4 port(
5 CLK, D : in std_logic;
6 Q, Qn : out std_logic);
7 end DFFQN;
8 architecture RTL of DFFQN is
9 signal DFF : std_logic;
10 begin
11 seq0 : process
12 begin
13 wait until CLK'event and CLK = '1';
14 DFF <= D;
15 end process;
16 Q <= DFF; Qn <= not DFF;
17 end RTL;
2.1 Flip-Flop 7

DE>
H D1
C E> 0
L E> _ n

Figure 2-3 D flip-flop with Qn output.

The above D flip-flop is the simplest version. It does not have the synchronous
or asynchronous reset input. Also, there are other ways to write VHDL to infer D flip-
flops. The following VHDL code shows various ways to infer D flip-flops.
1 library IEEE;
2 use IEEE.std_logic_1164.all;
3 entity FFS is
4 port(
5 CLOCK : in std_logic;
6 ARSTn : in std logic;
7 SRSTn : in std_logic;
8 DIN : in std_logic_vector(5 downto 0);
9 DOUT : out std_logic_vector(5 downto 0));
10 end FFS;

The ffs.vhd code infers six flip-flops with four process statements. Note that
each process statement has the expression (CLOCK'event and CLOCK = '1') to
check the rising edge of the clock signal CLOCK in lines 15, 20, 32, and 38. Every
target signal (signals appearing on the left-hand side of the signal assignment state-
ments) affected by the rising edge expression infers a number of flip-flops depending
on the target signal width.
Processes seq0 (lines 13 to 17) and seql (lines 18 to 26) use a wait statement
inside a process statement without a sensitivity list. The target signal to infer a flip-
flop can have a Boolean expression on the right-hand side of the signal assignment
statements as in lines 16, 24, and 26. The target signal value can also be affected by
other sequential statements such as the if statement in lines 21 to 25. These Boolean
expressions and sequential statements would result in combination circuits before
the D input of the D flip-flop as shown in Figure 2-5 synthesized schematic. Processes
seq2 (lines 28 to 35) and seq3 (lines 36 to 46) use a process statement with a sensi-
8 Chapter 2 VHDL and Digital Circuit Primitives

tivity list. There is no wait statement inside the process statement. As we recall, a
process statement should have either a sensitivity list or at least a wait statement,
but not both.

11 architecture RTL of FFS is

12 begin
13 seq0 : process
14 begin
15 wait until CLOCK'event and CLOCK = '1';
16 DOUT(0) <= DIN(0) xor DIN(1);
17 end process;
18 seql : process
19 begin
20 wait until CLOCK'event and CLOCK = '1';
21 if (SRSTn = '0') then
22 DOUT(1) <= '0';
23 else
24 DOUT(1) <= DIN(1) nand DIN(2);
25 end if;
26 DOUT(4) <= SRSTn and (DIN(1) nand DIN(2));
27 end process;
28 seq2 : process (ARsTn, CLOCK)
29 begin
30 if (ARSTn = '0') then
31 DOUT(2) <= '0';
32 elsif (CLOCK'event and CLOCK = '1') then
33 DOUT(2) <= DIN(2) nor DIN(3);
34 end if;
35 end process;
36 seq3 : process (CLOCK)
37 begin
38 if (CLOCK'event and CLOCK = '1') then
39 DOUT(5) <= SRSTn and DIN(3);
40 if (SRSTn = '0') then
41 DOUT(3) <= '0';
42 else
43 DOUT(3) <= DIN(3);
44 end if;
45 end if;
46 end process;
47 end RTL;
2.1 Flip-Flop 9

___C L O C K

__ARSTnE>

DIN[5:0]

SRSTn

Figure 2-4 Synthesized schematic for ffs.vhd.

The input signals SRSTn and ARSTn are used to synchronously and asynchro-
nously reset the flip-flops. SRSTn is used in lines 21, 26, 39, and 40 to show various
ways to synchronously reset the flip-flops. The synchronous behavior .is modeled by
checking the rising edge before the SRSTn signal affects the target signal values. In
other words, the event on signal SRSTn will not change the result until the clock ris-
10 Chapter 2 VHDL and Digital Circuit Primitives

ing edge is tested true. For example, lines 21 to 25 show the if statement using
SRSTn to assign DOUT(1) after the clock rising edge check in line 20. Lines 26, 39,
and 40 to 44 are also using SRSTn to synchronously reset the flip-flops. If the reset
check and the target signal are assigned before the rising edge clock check, the flip-
flop will have asynchronous behavior; the change of the flip-flop output value does
not wait until the rising edge of the clock. For example, in process seq2, line 30
checks whether the asynchronous reset signal and line 31 assigns DOUT(2) before the
rising edge clock check in line 32. DOUT(2) infers a flip-flop with the asynchronous
reset input connected to the ARSTn signal.
Note that the D input of DOUT(1) and DOUT(4) flip-flops, (also DOUT(3) and
DOUT(5)) are connected together. DOUT(4) (DOUT(5)) is modeled with one state-
ment in line 26 (39), compared to DOUT(1) (DOUT(3)) with five lines 21 to 25 (40 to
44).
Note that process seq2 (line 28) has a sensitivity list with two signals ARSTn
and CLOCK while process seq3 has only one signal CLOCK (line 36) in the sensitiv-
ity list.
Figure 2-5 shows another synthesized schematic for the same ffs.vhd VHDL
code. Note that the flip-flops with synchronous inputs are synthesized with cell name
SFD2. The synchronous reset inputs of the flip-flops are either connected to the
SRSTn directly or the output of a combination circuit gate. The schematic in Figure
2-4 does not use any synchronous reset flip-flops so that the synchronous behavior is
done by combining the SRSTn signal with combinational gates to feed the D inputs of
the flip-flops. The cells being used in Figure 2-4 are listed below. The area of each cell
is shown in the rightmost column. The unit of the area is commonly referred to as the
gate count. The normal two input NAND (NOR), or the inverter has the gate count of
one. Note that FD1 flip-flop has a gate count of seven. The total gate count is 52. You
are encouraged to develop a feeling and sense of close estimate of the gate count for
any design, even before it is designed.
1 Cell Reference Library Area
2
3 DOUT_reg2[1] FD1 lca300k 7.00
4 DOUT_reg2[4] FD1 lca300k 7.00
5 DOUT_reg3[2] FD2 lca300k 8.00
6 DOUT_reg4[3] FD1 lca300k 7.00
7 DOUT_reg4[5] FD1 lca300k 7.00
8 DOUT_reg[0] FD1 lca300k 7.00
9 U59 NR2 lca300k 1.00
10 U60 AN2 lca300k 2.00
11 U61 A06 lca300k 2.00
12 U62 IV lca300k 1.00
13 U63 EO lca300k 3.00
14
15 Total 11 cells 52.00
2.1 Flip-Flop 11

The following summarizes the gate count for the schematic in Figure 2-5.
1 Cell Reference Library Area
2
3 DOUT_reg2[1] SFD2 lca300k 8.00
4 DOUT_reg2[4] FD1 lca300k 7.00
5 DOUT_reg3[2] FD2P lca300k 9.00
6 DOUT_reg4[3] SFD2 lca300k 8.00
7 DOUT_reg4[5] SFD2 lca300k 8.00
8 DOUT reg[0] FD1 lca300k 7.00
9 U50 AN2 lca300k 2.00
10 U51 ND2 lca300k 1.00
11 U52 NR2 lca300k 1.00
12 U53 EO lca300k 3.00
13
14 Total 10 cells 54.00

E,7t77!Pi:› DOUT[5:2]
SFD2

___C L O C K

__SRSTnE2>

SFD2

SFD2

ARSTr1:2>__ D NE31
FD2P

FD1

AN2

ND FD1

LI1 DIN(5:01

D
E2 l

Figure 2-5 Schematic for ffs.vhd with synchronous reset D flip-flop.

12 Chapter 2 VHDL and Digital Circuit Primitives

Schematics Figure 2-4 and Figure 2-5 are synthesized from the same VHDL
code. They function exactly the same except for their speed differences. Their total
gate counts are also different. As we have stated above, it is a common practice to use
synthesis tools to try to meet the speed requirements with the lowest possible gate
count by using synthesis constraints. The synthesis constraints will be illustrated
throughout later chapters.
A JK flip-flop can be described with the following VHDL code. When J&K is
"10", the output is set to `1'. When J&K is "01", the output is cleared to 0'. When
J&K is "11", the output toggles (reverses) the previous value. When J&K is "00", the
output retains its previous value. Figure 2-6 shows the synthesized schematic. The JK
flip-flop has a gate count of nine.
The function of a JK flip-flop can also be implemented with a D flip-flop. Figure
2-7 shows an example. It has a total gate count of 12. You can see that the same
functionality (same VHDL code) can be synthesized with different schematics. This is
achieved by synthesis commands to use only the D flip-flops.

1 library IEEE;
2 use IEEE.std_logic_1164.all;
3 entity JKFF is
4 port(
5 CLK, J, K : in std_logic;
6 Q : out std_logic);
7 end JKFF;
8 architecture RTL of JKFF is
9 signal FF : std_logic;
10 begin
11 seq0 : process
12 variable JK : std_logic_vector(1 downto 0);
13 begin
14 wait until CLK'event and CLK = '1';
15 JK := J & K;
16 case JK is
17 when "10" => FF <= '1';
18 when "01" => FF <= '0';
19 when "11" => FF <= not FF;
20 when others => null;
21 end case;
22 end process;
23 Q <= FF;
24 end RTL;
2.1 Flip-Flop 13

FJ<1
>
30

Figure 2-6 Synthesized schematic for jkff.vhd.

1•1111•111 ■

lUX21

>
<E>_ FD1

cL<E>_

Figure 2-7 Synthesized schematic for jkff.vhd with D flip-flop.

The synchronous and asynchronous reset for a JK flip-flop is similar to the D flip-
flop. It is also common to have synchronous and asynchronous preset D and JK flip-
flops. What do we do when a flip-flop has both asynchronous preset and reset (clear)?
The following VHDL code can be used. Figure 2-8 shows the synthesized schematic.
What would happen if both SETn and CLRn are asserted to '0'? From a VHDL point of
view, lines 12 to 15 imply that CLRn is checked first; it has higher priority over the SETn.
Note that if statements always infer a priority of execution.
1 library IEEE;
14 Chapter 2 VHDL and Digital Circuit Primitives

2 use IEEE.std_logic_1164.all;
3 entity DFFSC is
4 port(
5 CLK, D, SETn, CLRn : in std logic;
6 Q : out std logic);
7 end DFFSC;
8 architecture RTL of DFFSC is
9 begin
10 seg0 : process (SETn, CLRn, CLK)
11 begin
12 if (CLRn = '0') then
13 Q <= '0';
14 elsif (SETn = '0') then
15 Q <= '1';
16 elsif (CLK'event and CLK = '1') then
17 Q <= D;
18 end if;
19 end process;
20 end RTL;

5
DE>
=DS

c L <E>

Figure 2-8 Synthesized schematic for dffsc.vhd.

The dffcs.vhd VHDL code is similar to dffsc.vhd, except the check of CLRn and
SETn is reversed as shown in lines 12 to 15. Figure 2-9 shows the synthesized sche-
matic. Note that extra gates of an inverter and a NAND gate are used to ensure the pri-
ority of CLRn and SETn described in the VHDL code. This is not the same as the
priority of the cell FD3.
2.2 Latch 15

1 library IEEE;
2 use IEEE.std_logic_1164.all;
3 entity DFFCS is
4 port(
5 CLK, D, SETn, CLRn : in std_logic;
6 Q : out std_logic);
7 end DFFCS;
8 architecture RTL of DFFCS is
9 begin
10 seg0 : process (SETn, CLRn, CLK)
11 begin
12 if (SETn = '0') then
13 Q <= '1';
14 elsif (CLRn = '0') then
15 Q <= '0';
16 elsif (CLK'event and CLK = '1') then
17 Q <= D;
18 end if;
19 end process;
20 end RTL;

Figure 2-9 Synthesized schematic for dffcs.vhd.

2.2 LATCH

A basic latch has two inputs, LE (latch enable) and D (data), and an output Q. When
the latch enable input LE is asserted, Q gets the same value as D. When LE is deas-
serted, Q retains its old value. The following VHDL code shows various ways to