Ans2) So we know that as AXI Lite uses single address for single data but AXI memory mapped

use
single address for multiple data hence the throughput will incresease by 50% as in the case of AXI
stream firstly first data will come then second but in case of second AXI memory mapped the output
will come one after other there will be burst of output.

Ans 3) 1.

Code of top_seq module :

module top_seq(

input clk,

output wire [3:0] a

);

reg[3:0] present_state=4'b1110,next_state;

reg clear = 1'b0;

parameter s0 = 4'b1110,s1 = 4'b1100,s2 = 4'b1010,s3 = 4'b0110,s4 = 4'b0100,s5 = 4'b0010,s6 =

4'b0000,s7=4'b1000;

always @(posedge clk)

begin

if(clear==1)

begin

present_state <= s0; // if clear 1 then present state must change to s0

clear<=1'b0;

end

else

present_state <= next_state; // if clear not 1 present state must change

end

always @(present_state)

begin
 next_state<=present_state;

if(present_state == s0)// ssiging nex_state to different state on the basis of present state

next_state<=s1;

else if(present_state==s1)

next_state<=s2;

else if(present_state==s2)

next_state<=s7;

else if(present_state==s7)

next_state<=s3;

else if(present_state==s3)

next_state<=s4;

else if(present_state==s4)

next_state<=s5;

else if(present_state==s5)

next_state<=s6;

else

clear = 1'b1;

end

assign a = present_state; // output based on present state

endmodule

I have made this using a fsm mealy machine and taken the states as the 14,12,10,8,6,4,2,0 and
changing the state with each clk posedge and as it return at last it will return to s0 as I have taken
a clear operation there.

2) CODE OF top_seq module :

module top_seq(
input clk,

output wire [2:0] a

);

reg[2:0] present_state=3'b001,next_state;

reg clear = 1'b0;

parameter s0 =3'b001,s1 =3'b010,s2=3'b111; // different states of the machine

always @(posedge clk)

begin

if(clear==1)

begin

present_state <= s0; // if clear 1 then present state must change to s0

clear<=1'b0;

end

else

present_state <= next_state; // if clear not 1 present state must change

end

always @(present_state)

begin

next_state<=present_state;

if(present_state == s0)// assiging next_state to different state on the basis of present state

next_state<=s1;

else if(present_state==s1)

next_state<=s2;

else
 clear = 1'b1;

end

assign a = present_state; // output based on present state

endmodule

I have made this using a fsm mealy machine and taken the states as the 1,2,7 and changing the
state with each clk posedge and as it return at last it will return to s0 as I have taken a clear
operation there.

Ans 5 : Logical Operators : works on Boolean statement and return a Boolean output.

Example :

a=4’b0000;

b=4’b0001

if(a == 4’b0000 && b==4’b0001)

it will return true as both the Boolean statement are true.

Bitwise Operators : perform an operation on each bit of the operand.

Example : 1001 & 1110 = 1000