1

CMOS – Transistors and Inverters

Dr. Jerry L. Hudgins

Department of Electrical Engineering
University of South Carolina

Transistor Review 8/12/03

Complimentary-MOS Logic (CMOS)
2

PMOS (P-channel enhancement-mode Metal Oxide Semiconductor transistor)

S S S

G B G G

D D D
D D D

G B G G

S S S
NMOS (N-channel enhancement-mode Metal Oxide Semiconductor transistor)

Transistor Review 8/12/03

 Definition of Symbols
3

Symbol Description Typical Values and Units

ID Drain Current 1 µA to 100 mA
VDS Drain-Source Voltage -3 to 3 V
VGS Gate-Source Voltage -3 to 3 V
VT MOS Threshold Voltage -0.8 to 0.8 V
µn Surface Electron Mobility 400 cm2/Vs
µp Surface Hole Mobility 150 cm2/Vs
Cox Oxide Capacitance per Unit Area 3 to 10 fF/µm2
W Effective Channel Width 0.2 to 3 µm
L Effective Channel Length 0.1 to 0.5 µm
Esat Saturation Electric Field Value 1 to 5 V/µm

Transistor Review 8/12/03

Definitions of Some Derived Symbols
4

Process Transconductance Parameters (A/V2)

k’n = µnCox = µnεox/tox
k’p = µpCox = µpεox/tox

Gain Factors (A/V2)

kn = k’n(Wn/Ln)

kp = k’p(Wp/Lp)

Transistor Review 8/12/03

 Metal Oxide Semiconductor
5

Field-Effect Transistor Behavior

In the resistive region of operation for NMOS:

µ nCox  W   2
VDS  W 
2
VDS 
ID =   (V − VT )VDS − = µ n ox 
C   GS
(V − V )V − κ (VDS )
VDS  L   GS 2  L 
T DS
2 
1+
Esat L
1
κ (VDS ) =
V
1 + DS
Esat L

For long channels or small drain-source voltages, κ approaches 1 and the expression
for the drain current reduces to the traditionally used equation describing a MOSFET
in its resistive region of operation. VDS/L is approximately the average electric field
in the channel.

Transistor Review 8/12/03

 Metal Oxide Semiconductor
6

Field-Effect Transistor Behavior

In the saturation region of operation for NMOS:

 
2
W VDSsat
I Dsat = µ nCox  (V −
  GS T DSsat
V )V − κ (VDSsat ) = vsat CoxW (VGS − VT − VDSsat )
L  2 
VGS − VT
VDSsat =
V − VT
1 + GS
Esat L

When the electric field in the channel reaches the saturation value, then all carriers
at the drain reach the saturation drift velocity (vsat = 105 cm/s) and the drain current
remains constant (to first order at IDsat) with respect to increases in drain-source
voltage.

Transistor Review 8/12/03

 7

PMOS Equations
In the resistive region of operation for PMOS:
− µ p Cox  W  VDS2
 W 
2
VDS 
ID =   (VGS − VT )VDS −  = − µ p ox 
C  (VGS − VT )VDS − κ (VDS )
VDS  L  2  L  2 
1+
Esat L 1
κ (VDS ) =
V
1 + DS
Esat L

In the saturation region of operation for PMOS:

 
2
W VDSsat
I Dsat = − µ p Cox  (V −
  GS T DSsat
V )V − κ (VDSsat ) = −vsat CoxW (VGS − VT − VDSsat )
L  2 
VGS − VT
VDSsat =
VGS − VT
1+
Esat L

Transistor Review 8/12/03

 CMOS Buffer/Inverter – Static 8

Operation
VDD dc Transfer Curve

3.5

Vin Vout 2.5

Vout
CL 1.5

0.5

0
0 0.5 1 1.5 2 2.5 3 3.5
Vin

Vin = 0 V → VGSp < 0 V, VGSn = 0 V → PMOS “On”, NMOS “Off” → Vout ≈ VDD

Vin = VDD → VGSp = 0 V, VGSn > 0 V → PMOS “Off”, NMOS “On” → Vout ≈ 0 V

No dc current path from source to ground so ideally no power dissipation!

Transistor Review 8/12/03

 Transfer Curve Information
9

ƒ Gate threshold voltage, VTH

dc Transfer Curve

3.5

ƒ Noise Margins 2.5

Vout
1.5

0.5

0
0 0.5 1 1.5 2 2.5 3 3.5
Vin

ƒ Small-signal gain of gate at its threshold

voltage

Transistor Review 8/12/03

 10

Threshold Voltage
VDD dc Transfer Curve with Gate Threshold

3.5

3 NMOS off NMOS sat

PMOS res PMOS res
Vin Vout 2.5

2
NMOS sat

Vout
CL 1.5 PMOS sat
1
NMOS res NMOS off
0.5
PMOS sat PMOS res
0

VTH = 1.43 V for this example 0 0.5 1 1.5

Vin
2 2.5 3 3.5

Gate Threshold Voltage is defined as

VTH ≡ Vin that gives the same value of Vout
It is the boundary between logic states.

Transistor Review 8/12/03

 Threshold Voltage
11

 VDSsatn   VDSsatp 
VTn +  + r VDD + VTp + 
 2   2 
VTH =
1+ r
 Wp 
µ p  VDSsatp
k pVDSsatp  Lp  vsatpW p
r= = =
k nVDSsatn  Wn  vsatnWn
µ n  VDSsatn
 Ln 
Assumes identical oxide thicknesses for NMOS and
PMOS, and ignores channel length modulation
effects.
Transistor Review 8/12/03
 12

Noise Margins
dc Transfer Curve
VDD
3.5
VOH Slope is -1
3

Vin Vout
2.5

Vout
CL 1.5

0.5

VOL 0

The points corresponding 0 0.5 1

VIL
1.5
Vin
2 2.5 3 3.5

to VIL and VIH are defined
where the gain is –1.
i.e. dVout/dVin = -1
VIH
Noise margins are the difference in what the
nominal output voltage is at a given logic level and
what the input of a similar gate must see to
interpret the level correctly.

Noise Margins are defined as:

NML ≡ VIL-VOL =Max. input for logic 0 – Nominal value of logic 0
NMH ≡ VOH-VIH = Nominal value of logic 1 – Min. value for logic 1

Transistor Review 8/12/03

 13

Small-signal Gain
dc Transfer Curve
VDD
3.5

2.5
Slope of curve
around
Vin Vout 2
threshold

Vout
1.5
voltage
CL 1

0.5

0
0 0.5 1 1.5 2 2.5 3 3.5

For this example:

Vin

Must have voltage gain > 1

dV out 1
g = Av = =
1
= 26 otherwise signals will fall below VTH
dV in VTH 26 after passing through several gates.
Minimum allowable value for
absolute value of voltage gain of a
digital gate is about 2 . Typical
gains are from 2 to 50.
Transistor Review 8/12/03
 14

Calculation of Noise Margins

dc Transfer Curve
VDD
3.5
VOH
3

Vin Vout
2.5

Vout
CL 1.5

0.5

VOL 0
0 0.5 1 1.5 2 2.5 3 3.5
VIL
Vin
VIH

Linearize the transfer curve as shown with

the slope between the transitions equal to the
gain, g, at VTH .

Transistor Review 8/12/03

 15

Calculation of Noise Margins

From the definition of gain and the nominal values of the gate: dc Transfer Curve

VOH − VOL V −0 3.5

g= = − DD VOH
VIL − VIH VIH − VIL 3

From the equation of the slanted line: 2.5

VTH
VIH = VTH − 2

Vout
g 1.5

Therefore combining the top two equations: 1

VDD − VTH
VIL = VTH +
0.5

g VOL 0
0 0.5 1 1.5 2 2.5 3 3.5
VIL
Vin
VIH

VTH
NM H = VOH − VIH = VDD − VTH + ≈ VOH − VTH ≈ VDD − VTH
g for large gain
VDD − VTH
NM L = VIL − VOL = VIL = VTH + ≈ VTH − VOL ≈ VTH
g for large gain

Transistor Review 8/12/03

 16

Calculation of Gain at VTH

Write a nodal equation with the drain currents of each
transistor equal to each other and VGSn = Vin , VDSn = Vout ,
VGSp = Vin – VDD , and VDSp = Vout – VDD .

Next, differentiate Vout with respect to Vin and solve for

dVout/dVin
knVDSsatn (1 + λnVTH ) + k pVDSsatp (1 + λ pVTH − λ pVDD ) 1+ r
g=− ≈
 VDSsatn   VDSsatp   V 
λn knVDSsatn VTH − VTn −  + λ p k pVDSsatp VTH − VDD − VTp −  VTH − VTn − DSsatn (λn − λ p )
 2   2   2 

Channel-length modulation factors, λ, CANNOT be ignored for

this analysis (depletion region at drain-end encroaches on
channel and reduces its effective length thus causing drain
current to increase).

Transistor Review 8/12/03

 Channel-Length Modulation Factor
17

 VDS − VDSsat 
I D = I Dsat (1 + λVDS ) la ln 1 +
V

λ=  E 
  VDS − VDSsat  
VDS  L − la ln 1 + 
la = (0.22cm1 / 6 )d 1j / 2tox
1/ 3
  VE 
dj is the drain junction depth VE is determined empirically and is < 1 V

Y.A. El-Mansy and A.R. Boothroyd, “A simple two-dimensional model for IGFET operation in the
saturation region,” IEEE Trans. ED, vol. 24, pp. 254-262, 1977.

P.K. Po, “Approaches to scaling,” pp. 1-37, Advanced MOS Device Physics, N.G. Einspruch and G.
Gildenblat, eds., VLSI Electronics, vol. 18, Academic Press, New York, 1989.

N.D. Arora, MOSFET Models for VLSI Circuit Simulation-Theory and Practice, Computational
Microelectronics Series, S. Selberherr, ed., Springer-Verlag, New York, 1993.

H.C. de Graaff and F.M. Klaassen, Compact Transistor Modeling for Circuit Design, Springer-Verlag, New
York, 1990.

Transistor Review 8/12/03

 Parasitic Capacitances Influencing
18

CMOS Inverter Pair

VDD
VDD
Cg4
M2
C db2 M4
Vout
Vin Vout2
Cgd12
Cdb1 M3
M1 Cw Cg3

Transistor Review 8/12/03

 Miller Capacitances
19

VDD
VDD C gd 2 = 2CGDOpW p = 2Coxp xdpW p
Cg4
M2 C gd 1 = 2CGDOnWn = 2Coxn xdnWn
C db2 M4
Vout CGDO is the overlap
Vin Vout2
Cgd12
Cdb1
capacitance per unit
M3 width, xd is the extension
M1 Cw Cg3 of the drain implantation
under the gate oxide.

Cgd1 Vout
Vout

→
'V
'V 'V
Vin 'V Vin
2Cgd1
M1 M1

Can replace gate-drain capacitances (Miller caps) with

equivalent at output wrt ground because of ∆V change
at each capacitance terminal.
Transistor Review 8/12/03
 Fan-out Gate Capacitances
20

VDD
VDD
Cg4
M2
C db2 M4
Vout
Vin Vout2
Cgd12
Cdb1 M3
M1 Cw Cg3

Each gate capacitance is made of the oxide capacitance along

the channel plus the overlap capacitance between gate oxide
and source, plus the overlap capacitance between the drain and
gate oxide.
C fan−out = C g 3 + C g 4 = (CGSOnWn + CGDOnWn + CoxnWn Ln ) + (CGSOpW p + CGDOpW p + CoxpW p L p )
= CoxnWn (2 xn + Ln ) + CoxpW p (2 x p + L p )

Transistor Review 8/12/03

 Wiring Capacitance
21

VDD
VDD
Cg4
M2
C db2 M4
Vout
Vin Vout2
Cgd12
Cdb1 M3
M1 Cw Cg3

The wiring capacitance, Cw, depends upon the length

and width of the connecting traces and is a function of
the distance between load gates and driving gates, as
well as the number of load gates.

Transistor Review 8/12/03

 Diffusion Capacitances 22

VDD
between Drain and Body
VDD
Cg4
M2
C db2 M4
Vout
Vin Vout2
Cgd12
Cdb1 M3
M1 Cw Cg3

Cdb is due to the reverse biased pn-junction between the drain and body
AND is the capacitance that is non-linear and voltage dependent.
C j0 Cj0 is the zero-biased junction capacitance per unit area.
Cdb = C j =
 VD 
m VD is the applied body voltage with respect to the drain.
1 −  Vbi is the built-in potential of the junction (typically about
 Vbi  0.64 V).
m is the grading factor (1/2 for abrupt junctions and 1/3 for
qε si  N A N D  linear junctions).
C j0 =  
2Vbi  N A + N D  NA and ND are the acceptor and donor impurity
concentrations, respectively.

Transistor Review 8/12/03

 Approximate Diffusion Capacitance 23

between Drain and Body

Using an approximation for the large-signal swing in
capacitance and in terms of the grading factor gives:

∆Q j Q j (Vhigh ) − Q j (Vlow )
Ceq = = = K eq C j 0
∆VD Vhigh − Vlow

− Vbim
K eq = [(Vbi − Vhigh )1−m − (Vbi − Vlow )1−m ]
(Vhigh − Vlow )(1 − m)

qε si  N A N D 
C j0 =  
2Vbi  N A + N D 

Transistor Review 8/12/03

 Example
24
VDD
VDD
Cg4
M2
C db2 M4
Vout
Vin Vout2
Cgd12
Cdb1 M3
M1 Cw Cg3

The propagation delay is defined by the time between the

50% transitions of the input and output. For a CMOS inverter
this is the time instance where Vout reaches 1.25 V as the
output voltage swing from rail-to-rail is 2.5 V (VDD = 2.5 V).
The drain-body capacitance is linearized over the voltage
intervals of 2.5 V to 1.25 V for high-to-low and 0 V to 1.25 V
for low-to-high transitions of the NMOS (M1). A similar
computation is performed for the PMOS.

Transistor Review 8/12/03

 Example (page 2)
25
VDD
VDD
Cg4
M2
C db2 M4
Vout
Vin Vout2
Cgd12
Cdb1 M3
M1 Cw Cg3

During the high-to-low transition of the output:

For the NMOS: For the PMOS:
Vhigh = -2.5 V Vhigh = -1.25 V
Vlow = -1.25 V Vlow = 0 V

During the low-to-high transition of the output:

For the NMOS: For the PMOS:
Vhigh = -1.25 V Vhigh = -2.5 V
Vlow = 0 V Vlow = -1.25 V

Transistor Review 8/12/03

 Example (page 3)
26
VDD
VDD
Cg4
M2
C db2 M4
Vout
Vin Vout2
Cgd12
Cdb1 M3
M1 Cw Cg3

During both transitions of the output:

For the NMOS:
Bottom plate: m=0.5, Vbi=0.9 V
Side Wall: m=0.44, Vbi=0.9 V

For the PMOS:

Bottom plate: m=0.48, Vbi=0.9 V
Side Wall: m=0.32, Vbi=0.9 V

Transistor Review 8/12/03

 Example (page 4)
27

Keq W/L AD (µm2) PD

(µm)
As (µm2) Ps (µm)

NMOS 0.375/0.25 0.3 1.875 0.3 1.875

NMOS 0.79
Bottom Plate
(L-H) PMOS 1.125/0.25 0.7 2.375 0.7 2.375
NMOS 0.81
Sidewall
(L-H)
PMOS 0.59
Bottom Plate Capacitor Value (fF) Value (fF)
(L-H) High to Low Low to High
PMOS 0.7
Sidewall Cgd1 0.23 0.23
(L-H)
Cgd2 0.61 0.61
NMOS 0.57
Bottom Plate Cdb1 0.66 0.90
(H-L)
Cdb2 1.5 1.15
NMOS 0.61
Sidewall
(H-L) Cg3 0.76 0.76
PMOS 0.79 Cg4 2.28 2.28
Bottom Plate
(H-L) *Cw 0.12 0.12
PMOS 0.86 CL (total) 6.16 6.05
Sidewall
(H-L)

Transistor Review 8/12/03

 Propagation Delay
28

During the high-to-low transition, the PMOS is turning off

and the NMOS is on. Represent the NMOS by its average
equivalent resistance during the load capacitance discharge.
Use similar expressions for the low-to-high transition.
VDD
1 V 3VDD  7λVDD 
VDD / 2 VDD∫ / 2 I Dsat (1 + λV )
Req = dV ≈ 1 − 
4 I Dsat  9 

W  2
VDSsat 
t pHL = 0.69 Reqn C L− HL I Dsat =k '
(V − V )V
 DD t DSsat − 
L  2 
t pLH = 0.69 Reqp C L− LH
Propagation Delay of Inverter is average of the
two values:
t pHL + t pLH
tp = = 0.345( ReqpCL− LH + ReqnCL− HL ) ≈ 0.345CLavg ( Reqp + Reqn )
2
Transistor Review 8/12/03
 Metastability
29

Two inverters cascaded, with a gain in the transition

region >1, has two stable operating points, A and B, and
one metastable operating point, C.
NOTE: Gain near A and B is << 1.

Transistor Review 8/12/03

 Metastability
30

In figure (a) if initial In figure (b) if initial

operating point is C, operating point is
any noise will cause away from C, any
transition to a stable noise will cause
operating point such transition back to a
as A. stable operating point
such as A.
Transistor Review 8/12/03
 SPICE Models
31

ƒ Level 1:
Shichman-Hodges model based on square-
law, long-channel expressions between
current and voltage.
DOES NOT HANDLE SHORT CHANNEL
EFFECTS!
ƒ Level 2
Geometry based model that incorporates
velocity saturation, mobility dependencies,
and drain-induced barrier lowering.

Transistor Review 8/12/03

 SPICE Models (cont.)
32

ƒ Level 3:
Semiempirical model combining analytical and
empirical expressions. Uses measured data for model
parameters.
Works well for channel lengths down to about 1 µm.
ƒ Berkeley Short-channel IGFET Model (BSIM)
Analytically simple with a ‘small’ number of
parameters derived from empirical data.
BSIM3v3 model (Level 49) has over 200 parameters,
most related to modeling 2nd order effects.
Manufacturer provides a set of models valid over a
limited parameter space of L and W (delineated by
LMIN, LMAX, WMIN, and WMAX, called a bin).
http://bwrc.eecs.berkeley.edu/IcBook/
for BSIM and Matlab models
Transistor Review 8/12/03
 SPICE Models-Example File
33

A CMOS Inverter using Level 3 Model for 0.8 um Process

*
.MODEL nch NMOS
+ LEVEL=3 PHI=0.70 TOX=1.0E-08 XJ=0.20U TPG=1
+ VTO=0.8 DELTA=2.5E-01 LD=4.0E-08 KP=1.88E-04
+ UO=545 THETA=2.5E-01 RSH=2.1E+01 GAMMA=0.62
+ NSUB=1.4E+17 NFS=7.1E+11 VMAX=1.9E+05 ETA=2.2E-02
+ KAPPA=9.7E-02 CGDO=3.7E-10 CGSO=3.7E-10 CGBO=4.0E-10
+ CJ=5.4E-04 MJ=0.6 CJSW=1.5E-10 MJSW=0.3 PB=0.99
*
.MODEL pch PMOS
+ LEVEL=3 PHI=0.70 TOX=1.0E-08 XJ=0.20U TPG=-1
+ VTO=-0.9 DELTA=2.5E-01 LD=6.7E-08 KP=4.45E-05
+ UO=130 THETA=1.8E-01 RSH=3.4E+00 GAMMA=0.52
+ NSUB=9.8E+16 NFS=6.5E+11 VMAX=3.1E+05 ETA=1.8E-02
+ KAPPA=6.3E+00 CGDO=3.7E-10 CGSO=3.7E-10 CGBO=4.3E-10
+ CJ=9.3E-04 MJ=0.5 CJSW=1.5E-10 MJSW=0.3 PB=0.95
*
M1 3 2 0 0 nch W=5u L=0.8u AS=7.2p PS=7.6u AD=7.2p PD=7.6u
M2 3 2 1 1 pch W=5u L=0.8u AS=9.9p PS=9.1u AD=9.9p PD=9.1u
CL 3 0 0.05pF
*
VDD 1 0 3.3V
VIN 2 0 PULSE(0 3.3 0 100p 100p 5n 10n)
*
.TRAN 0.05n 10n
*
.DC VIN 0V 3.3V 0.01V
*
.PROBE
*
.END

Transistor Review 8/12/03

 References for CMOS Transistors
34

ƒ Operation and Modeling of the MOS

Transistor, 2nd ed., Y. Tsividis, McGraw-
Hill, Boston, 1999.
ISBN 0-07-065523-5
ƒ Digital Integrated Circuits – A Design
Perspective, 2nd ed., J.M. Rabaey, A.
Chandrakasan, and B. Nikolic’, Prentice
Hall Electronics and VLSI Series, C.G.
Sodini, ed., Upper Saddle, NJ, 2003.
ISBN 0-13-597444-5
Transistor Review 8/12/03