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2.
5.In below timing report write down what does a,b,c,d denotes and also draw the appropriate ckt taking
all the paths into consideration
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6. Find maximum allowable delay for data path to meet setup , given lib tsetup =0.087.7.
7.
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8.
9.Considering Net parasitic as negligible ,find path delay between IN and OUT with proper explaination.
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Slew at IN = 10ps
Load at OUT (Ci) = 2PF
I/P pin capacitance (I1 & I2) = 1 PF
Slew Table :
Slew at A Load at Y
1PF 2PF
10ps 10ps 20ps
20ps 20ps 30ps
Delay Table
Slew at A Load at Y
1PF 2PF
10ps 40ps 50ps
20ps 50ps 60ps
10.Find maximum operating frequency of following ckt
13. Figure 1 is case when we have not touched both data and clock path and at this stage library setup
time of FF is 2 ps , now occe pnR is done we found BUFF in data path and CLKBUFF in clock path what
will be impact on setup time of FF.
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Figure 1
Figure 2
14.
15.
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16.
18.How a cell delay calculated, How tool will calculate delay for a 2 input NAND gate?
20.Can library setup and hold time be –ve. If yes then what does it mean?
21.Explain recovery and removal time and also pulse width check.
25.Can an new clock i.e master clock be defined instead of generated clock?
26.What is path group ,and what is benefit of setting critical range for a path group.
27.
10 | P a g e S T A E V A L U A T I O N T E S T 1
In the above diagram comment on relation between CLK1 & CLK2 and can we do a timing analysis on
this if yes draw the waveform for the same.
28.
What are timing exceptions, what is use of setting max/min delay. Write a command to constraint max
and min delay between two registers REGA and REGB and comment the case when setup and hold may
fail.
29.What is multicycle path and how a tool will do STA on a path that is constrained as multicycle.
For reference set multicycle of 2 and show with waveform where setup/hold will be checked .
31.
11 | P a g e S T A E V A L U A T I O N T E S T 1
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