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1.Estimate the pararasitics of a net whose fanout is 7.

2.

3.What format of netlist can PT accept?

4.As D1 is pin similiarly what we call to a,b,c


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5.In below timing report write down what does a,b,c,d denotes and also draw the appropriate ckt taking
all the paths into consideration
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6. Find maximum allowable delay for data path to meet setup , given lib tsetup =0.087.7.

7.
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8.

1. Which command will give such an output.


2.Which type of timing analysis is reported here.
3.Is there any violataion ? if yes then what is margin by which it is violating
4.What is timing path that is being analysed here.What type of clock is use to constrain this path?

9.Considering Net parasitic as negligible ,find path delay between IN and OUT with proper explaination.
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Slew at IN = 10ps
Load at OUT (Ci) = 2PF
I/P pin capacitance (I1 & I2) = 1 PF

Slew Table :
Slew at A Load at Y

1PF 2PF
10ps 10ps 20ps
20ps 20ps 30ps

Delay Table
Slew at A Load at Y

1PF 2PF
10ps 40ps 50ps
20ps 50ps 60ps
10.Find maximum operating frequency of following ckt

11. Find maximum operating frequency of following ckt


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12. analyze the following ckt for setup/hold check

13. Figure 1 is case when we have not touched both data and clock path and at this stage library setup
time of FF is 2 ps , now occe pnR is done we found BUFF in data path and CLKBUFF in clock path what
will be impact on setup time of FF.
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Figure 1

Figure 2

14.

Analyse the following ckt


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15.
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16.

17.What is a glitch.How to fix if it occurs in your design?

18.How a cell delay calculated, How tool will calculate delay for a 2 input NAND gate?

19.Explain content of .lib in detail.

20.Can library setup and hold time be –ve. If yes then what does it mean?

21.Explain recovery and removal time and also pulse width check.

22.How a net delay calculation differs in synthesiz,pnR and postRoute.

23.What is max tran violation, how to fix it?

24.Write down different ways of fixing setup and hold?

25.Can an new clock i.e master clock be defined instead of generated clock?

26.What is path group ,and what is benefit of setting critical range for a path group.

27.
10 | P a g e S T A E V A L U A T I O N T E S T 1

In the above diagram comment on relation between CLK1 & CLK2 and can we do a timing analysis on
this if yes draw the waveform for the same.

28.

What are timing exceptions, what is use of setting max/min delay. Write a command to constraint max
and min delay between two registers REGA and REGB and comment the case when setup and hold may
fail.

29.What is multicycle path and how a tool will do STA on a path that is constrained as multicycle.

For reference set multicycle of 2 and show with waveform where setup/hold will be checked .

30.Explain the below commands:

1. set_timing_derate -late -cell_delay 1.4 [get_cells inv*]

2. set_timing_derate -late -cell_delay 1.4 [get_cells inv*]

3. set_timing_derate –late –net_delay -1.1

4. set_timing_derate -late -1.1

5. report_timing_derate [get_cells U*]

31.
11 | P a g e S T A E V A L U A T I O N T E S T 1

Write the output of following command : report_timing -delay max

……………………………………………………………………………………………………………………………

……………………………………………………………………………………………………………………………

Complete the whole table

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