Single Chip CMOS RF Transceivers:

wishful thinking or reality

Michiel Steyaert
Katholieke Universiteit Leuven, ESAT-MICAS,
Kardinaal Mercierlaan 94, B-3001 Heverlee, Belgium

Abstract
Since several years the research in the possibilities of CMOS technologies for RF applications is
growing enormously. The trend towards deep sub-micron technologies allows the operation
frequency of CMOS circuits above IGHz, which opens the way to integrated CMOS RF circuits.
Several research groups have developed high performance down-converters, low phase noise
voltage controlled oscillators and dual modulus prescalers in standard CMOS technologies. The
research has already demonstrated filly integrated receivers and VCO circuits with no extenuzl
components, nor tuning or trimming. Further research on low noise amplifiers, up-converters,
synthesisers has recently resulted in fully integrated CMOS RF transceivers for DCS-1800
applications

1. Introduction
A few years ago the world of wireless communications and its applications started to grow
rapidly. The driving force for this is the introduction of digital coding and digital signal processing
in wireless communications. This digital revolution is driven by the development of high
performance, low cost, CMOS technologies which allow for the integration of an enormous amount
of digital functions on a single die. This allows on its turn for the use of sophisticated modulation
schemes, complex demodulation algorithms and high quality error detection and correction systems,
resulting in high performance, lossless digital communication channels. Low cost and a low power
consumption are the driving forces and they make the analog front-ends the bottle neck in future RF
design. Both low cost and low power are closely linked to the trend towards full integration. An
ever further level of integration renders significant space, cost and power reductions. Many
different techniques to obtain a higher degree of integration for receivers, transmitters and
synthesisers have been presented over the past years [1],[2],[3].
Parallel to the trend to further integration, there is the trend to the integration of RF circuitry in
CMOS technologies. The mainstream use for CMOS technologies is the integration of digital
circuitry. The use of these CMOS technologies for high performance analog circuits yields
however, if possible, many benefits. The technology is cheap, if used without any special
adaptations towards analog design. Plain CMOS has the extra advantage that the performance gap
between devices in BiCMOS and NMOS devices in deep sub-micron CMOS, and even NMOS
devices in the same BiCMOS process, is becoming smaller and smaller due to the much higher
investments in the development of CMOS than bipolar. The f,'s of the NMOS devices are nowadays
even higher than the f: s of the NPN devices.
Although some research has been performed in the past on the design of RF in CMOS
technologies [4], it is only since a few years that real attention has been given to its possibilities [5].
Today several research groups at universities and in industry are researching this topic [2-31,[9],
[22.As bipolar devices are inherently better than CMOS devices, RF CMOS is by some seen as a
possibility for only low p e r f o m c e systems, with reduced specification (like ISM) [6],or that the
CMOS processes need adaptations, like substrate etching under inductors. Others feel however that
the benefits of RF CMOS can be much bigger and that it will be possible to use plain deep sub-
micron CMOS for the full integration of transceivers for high performance applications, like GSM,
DECT and DCS 1800 [2],[3]. First some trends, limitations and problems in technologies for high
frequency design are analyzed. Secondly, the down-converter topologies and implementation

111
02001 The Institution of Uectriml Engineers.
Printed and published by the IEE, Savoy Place,London WC2R OBL, UK
defined as the 3dB point of a diode 1 8 --
connected transistor [7]. The f m a is
more important because it reflects the
1 6 --
l 4 --
speed limitation of a transistor in a H 1 2 -.
\1
circuit designs (f-)
improvement is only moderate.
the speed
Finally, in recent integrated CMOS
%,<
practical configuration. As can be seen, S 1 0 --
the ft rapidly increases, but for real = 8
6
..
4 -.
--
* ..

3. Fully Integrated CMOS Down-converters

The heterodyne or IF receiver is the best known and most frequently used receiver topology. In
the IF receiver the wanted signal is down-converted to a relatively high intermediate frequency. A
high quality passive bandpass filter is used to prevent a mirror signal to be folded upon the wanted
signal on the IF frequency. Very high performances can be achieved with the IF receiver topology,
especially when several IF stages are used The main problem of the IF receiver is the poor degree
of integration that can be achieved as every stage requires going off-chip and requires the use of a
discrete bandpass filter. This is both costly (the cost of the discrete filters and the high pin-count for
the receiver chip) and power consuming (oftenthe discrete filters have to be driven by a 50 S2 signal
source). Moreover, in CMOS RF circuit design inputloutputis already becoming a serious problem
above the GHz frequency range.
The homodyne or zero-IF receiver has been introduced as an alternative for the IF receiver that
can achieve a much higher degree of integration. The zero-IF receiver uses a direct, quadratwe,
down-conversion of the wanted signal to the baseband. The wanted signal has itself as mirror signal
and sufficient minor signal suppression can therefore be achieved, even with a limited quadrature
accuracy. Theoretically,there is thus no discrete high frequency bandpass filter required in the zero-
IF receiver, allowing in this way the realisation of a fully integrated receiver, especially if the down-
conversion is performed in a single stage (e.g. direct from 900 MHz to the baseband) [9]. The
problem of the zero-IF receiver is its poor performance compared to IF-receivers. The zero-IF
receiver is intrinsically very sensitive to parasitic baseband signals like DC-offset voltages and
crosstalk products caused by RF and LO self-mixing. These drawbacks have kept the zero-IF
receiver from being used on large scale in new wireless applications. The use of the zero-IF receiver
has therefore been limited to rather low performance applicationslike pagers and ISM in which the
coding can be scrambled so that an high pass filter cm be inserted to avoid the DC offset problems.
An other application is the use as only a second stage in a combined IF - zero-IF receiver topology

112
[10],[11]. It has however been shown that with the use of dynamic non-linear DCcorrection
algorithms, implemented in the DSP, the zero-IF topology can be used for high performance
applications like GSM and DECT [1],[12].
In recent years new receiver topologies like the low-IF receiver [2,24] have been introduced for
the use in high performance applications. The low-IF receiver performs a downconversion from the
antenna frequency directly down to, as the name already indicates, a low IF (i.e. in the range a few
l00kH.z) [2]. Down-conversion is done in quadrature and the mirror signal suppression is
performed at low frequency, after down-conversion, in the DSP. The low-IF is thus closely related
with the zero-IF receiver. It can be fully integrated (it does not require a HF mirror signal
suppression filter) and uses a single stage direct down-conversion. The difference is that the low-IF
does not use baseband operation, resulting in a total immunity to parasitic baseband signals,
resolving in this way the main disadvantage of the zero-IF receiver. The drawback is that the minor
signal is different from the wanted signal in the low-IF receiver topology, but by carefully choosing
the IF frequency an adjacent channel with low signal levels can be selected for which the typical
mirror signal suppression (i.e. a 3" phase accuracy) is sufficient.
Fig. 2 shows the block &agram of a fully integrated quadrature down-converter realised in a
0.7 pm CMOS process [2]. The proposed ---_ ---.-
down-converter does not require any
__I

_- I_. -- - 8

external components, nor does it require

any tuning or trimming. It uses a newly
developed double quadrature structure,
which renders a very high performance
in quadrature accuracy (less than 0.3" in __.__ -.5c

a very large passband). The topology

used for the down-converter is based on
NMOS transistors in the linear region .
-
1.

..
[5],[2]. In combination with capacitors -
,
-_
*e..

-
-?
..-.
on the virtual grounds, only a low
frequency opamp is required. The MOS ."
transistors in the linear region result is Fig. 2 :A double quadrature down-conversion mixer
very high linearity (input IP3 for the
mixers is over 4 5 a m ) for both the RF and the LO input. The advantages of such a high linearity
on both inputs are that the mixer can handle a very high IMFDR3, resulting in no need for any kind
of HF filtering.
4. The Synthesiser
The local oscillator is responsible for the correct frequency selection in the up- and down-
converters. Since the frequency spectrum in modern wireless communication systems must be used
as efficiently as possible, channels are placed very close together. The signal level of the desired
receive channel can be very small, whereas adjacent channels can have very large power levels.
Therefore the phase noise specifications for the LO signal are very.
Meanwhile, mobile communication means low power consumption, low cost and low weight.
This implies that a completely integrated synthesiser is desirable, where integrated means a standard
CMOS technology without any external components or processing steps. Usually, the LO is realised
as a phase-locked loop. The very hard specs are reflected in the design of the Voltage-Controlled
Oscillator (VCO) and the Dual-Madulus Prescaler OW).
For the realisation of a gigahertz VCO in a submicron CMOS technology, two options exist :
ring oscillators or oscillators based on the resonance frequency of an LC-tank. The inductor in this
LC-tankcan be implemented as an active inductor or a passive one. It has been shown that for ring
oscillators as well as active LC-oscillators [13], the phase noise is inversely related to the power
consumption.
-
Ring osc. [21] : L{Ao} kT. with g,=-
R
1

Active-LC [22] : L{Ao} -

 Therefore, the only viable solution to a low-power, low-phase-noise VCO is an LC-oscillator
with a passive inductor. In this case the phase noise changes proportionally with the power
consumption :
Passive-LC [22] : L{Ao} -.kT.R. L)2with
(- g, = R . ( m 2
As could be expected, the limitation in this oscillator is the integrated passive inductor.
Equation (2) shows that for low phase noise, the resistance R (i.e. the equivalent series resistance in
the LC-loop) must be as small as possible. Since the resistance R will be dominated by the
contribution of the inductors' series resistance, the inductor design is critical. Three solutions exist.
Spiral inductors on a silicon substrate usually suffer from high losses in this substrate, which
limit the obtainable Q-factor. Recently, techniques have been developed to etch this substrate away
underneath the spiral coil in a post-processing step [14]. However, since there is an extra etching
step requiredafter normal processing of the IC's, this technique is not allowed for mass production.
For extremely low phase noise requirements, the concept of bondwire inductors has been
investigated. Since a bondwire has a parasitic inductance of approximately 1 nH/mm and a very low
series resistance, very-high-Q inductors can be created. Bondwires are always available in IC
technology, and can therefore be regarded as being standard CMOS components. Two inductors,
fonned by four bondwires, can be combined in a
enhanced LC-tank [13] to allow a noiselpower trade-
off. A microphotograph of the VCO is shown in fig. 4
[16]. The measured phase noise is as low as -
115dBc/Hi at an offset frequency of 200kHz €?om the
1.8-GHz carrier. The power consumption is only 8mA
at 3V supply. Although chip-tochip bonds are used in
mass commercial products, they are not characterized
on yield performance for mass production. Therefore,
the industry is reluctant to this solution.
The most elegant solution is the use of a spiral
coil on a standard silicon substrate, without any
modifications. Bipolar implementations do not suffer
from substrate losses, because they usually have a
high-ohmic substrate [15]. Most sub-micron CMOS
technologies use a highly doped substrate, and have
therefore large induced currents in the substrate, which Fig. 3: Microphotograph of
are responsible for the high losses [8]. The effects the hollow spiral VCO
present in these low-ohmic substrates can be
investigated with finite-element simulations. This analysis leads to an optimised coil design, which
is used in a spiral-inductor LC-oscillator, presented in fig 3. Only two metal layer are available, and
the substrate is highly doped. With a power consumption as low as 6mW, a phase noise of -
116 dBc/Hz at 6OOkHz offset from the 1.8-GHz carrier has been obtained [19].
5. RF CMOS Up-converters
Until now mainly CMOS down-conversion mixers have been reported in the open literatme. It
is only recently that CMOS Up-converters are presented and results are demonstrated [18]. In
classical bipolar transceiver implementations, the up- and down-converter mixers use typically the
same fourquadrant topology. There are, however, some fundamental differences between up- and
downconverters, which can be exploited to derive optimal dedicated mixer topologies.
In a down-conversion topology the two input signals are at a bigh frequency (e.g. 900 MHz for
GSM systems) and the output signal is a low frequency signal of maximum a few MHz for low-IF
or zero-IF receiver systems. This extra degree of freedom has been used in the design of very
successfuldown-converter-only CMOS mixer topology [5].
For up-conversion mixers, the situation is totally different. The bigh frequent local oscillator
(L.O.)and the low frequent baseband (B.B.)input signal are multiplied to form a high frequent
output signal. All M e r signal processing has to be performed at high frequencies, which is very
difficult and power consuming when using c m n t submicron CMOS technologies. Furthermore,
all unwanted signals like the intermodulation products and L.0.-leakage, have to be limited to a
level below e.g. -30dB of the signal level.

114
 Many published CMOS mixer topologies are based on the traditional variable transconductance
multiplier with cross coupled differential modulator stages. Since the operation of the classical
bipolar cross coupled differential modulator stages is based on the translinear behavior of the
bipolar transistor, the MOS counterpart can only be effectively used in the modulator or switching
mode. Large L.0.-signals have to be used to drive the gates and this results in a huge L.0.-
feedthrough. Already in CMOS down-converters this is a problem; in [26] e.g. the output signal
level is -23 dBm with a L.O. feedthrough signal of -30dBm, which represents a suppression of only
-7dB.This gives rise to very severe problems in direct upconversion topologies.
The problems above can be overcome in CMOS by linearly modulating the current of a MOS
mixing transistor biased in its linear region. For a gate voltage of Vl+vbl, a drain voltage of
V2+v&2 and a source voltage of V2-v*/2 the current through the transistors given by :
9 -
iDs= B (vhl vhz) + p ( v ~vT v ~ )
- - vh2 (3)
When the LO signal is connected to the gate and the baseband signal to vW, the current
contains frequency components around the LO due to the first term and components of the
baseband signal due to the second term in equation (3).
Based on this principle a lGHz up-converter has been
demonstrated in a standard CMOS technology E181 (see
fig 4).
All unwanted measured signals are below -30 dBc.
The mixer of figure 6 e.g. is implemented in a 0.7 pm
CMOS technology which achieves an fmaxof only 6 GHz
for a gate overdrive of 1 V or a grdI ratio of only 2.
Typical bipolar technologies used for the implementation
of 900 M H z fully integrated transceivers have cut-off
frequencies of over 20 GHz [lo]. Due to the low gm/I of
present sub-micron technologies for high frequency
operation, the power consumption in CMOS pre-ampWiers
will be up to 20 times higher than in bipolar. However,
thanks to the rapid down-scaling of CMOS technologies,
the present CMOS building block realizations show that
full CMOS transmitters with an acceptable power
consumption are feasible in very deep submicron CMOS,
but some considerable research has still to be performed
6.Full Integrated CMOS Transceivers
Combining all the techniques described above, have result recently in the development of
single chip CMOS transceiver circuits [25]. In fig 5 a microphotograph of the 0.25 pm CMOS
transceiver is presented. The chip does not require a single extemal component, nor does it require
any tuning or trimming. The
objective of this design is to develop
a complete system for wireless
communications at 1.8 GHz that can
be built with a minimum of
surrounding components : only an
antenna, a duplexer, a power
amplifier and a baseband signal
processing chip. The high level of
integration is achieved by using a
low-IF topology for reception, a
direct quadrature up-conversion
topology for transmission and an
oscillator with on-chip integrated
inductor. The presented chip has been designed for the DCS-1800 system but the broadband nature
of the LNA, the downconverter, the upconverter and the output amplifier makes the presented
techniques equally suited for use at other frequencies, e.g. for use in a DCS-1900or a DECT
system. The presented circuit consumes 240 mW from a 2.5 V supply and occupies a die area of
8.6 mm'.
7. Conclusions
The trend towards deep sub-micron technologies has resulted in the exploration by several
research groups of the possible use of CMOS technologies for the design of RF circuits. Especially
the development of new receiver topologies, such as low-IF topologies, in combination with highly
linear downconverters, has opened the way to fully integrated down-converters with no extemal
filters or components. The trends towards deep sub-micron technologies will allow to achieve those
goals as long as the short channel effects will not limit the pedomance concerning linearity and
intermodulation problems.
High performance low phase noise, low power drain,fully integrated VCO circuits have been
demonstrated in CMOS. Starting with difficult post processing techniques research has resulted in
the use of standard CMOS technologies by using bondwires as inductors. Today, even low phase
noise performances with optimised integrated spiral inductors in standard CMOS technologies
without any post-processing, tuning, trimming or external components have been announced. This
opens the way towards fulIy integrated receiver circuits.
Recently CMOS up-converters with moderate output power are presented in open literature.
Again, thanks to the trends towards deep sub-micron this opens the way towards fully integrated
transceiver circuits in standard CMOS technologies.
8. References
[l]J. Sevenhaus, A. Vanwelsenaers, J. Wenin and J. Baro. "Anmtegmed Si bipolar transceiver for a zero IF 900 MHz GSM digital
mobile radio bntend of a hand partable phone,"Proc. CICC, pp.7.7.1-7.7.4.May 1991.
[2] J. Crols and M. Steyaert, "A S m g l 6 p 900 MHz CMOS Receiver Front-End with a High Performance Low-IF Topology,"
IEEE J. of Solid-state Circuits, vo1.30, 130.12,pp.1483-1492, Dec. 1995.
[3] P.R Gray and RG. Meyer, "FutureDirections in Silicon ICs for FW Personal Co"uniCati0ns." Proc. CICC, May 1995.
[4] Bang-SupSong, "CMOSRF Circuits for Data Co"i&ons Applications,"IEEEJSSC, SC-21,n0.2, pp.310-317, April 1986.
[5] J. b l s , MSteyaert, "A 1.5 GHz Highly Linear CMOS DownconversionMixer,"IEEEJSSC, SC30,no.7, pp.736742, July 1995.
[6] C.H. Hull,RR Chu and J.L. Tham, "A Direct-Conversion Receiver for 900 MHZ (ISM Band) Spread-Spectnm~Digital
cordless Telephone,"Roc. ISSCC, pp.344-345, San Francisco,Feb. 1996.
[7]U Steyaert and W.Sa", "Opamp Design towards Maxi" Gain-BandWidtb," ROC. Of the AACD workshop,pp.63-85,
Delft, March 1993.
[8] J. Crols, P. Kinget, J. Craninckx and M. Steyaert, "AnAnalytical Model.of Planar Inductors on Lowly Doped Silicon Substrates
for High Fresuency Analog Design up to 3 G W Proc. VLSZ CircuitsSymposium, June 1996.
[9] D.Rabaey and J. Sevenhans, "The challenges for analog circuit design in Mobile Radio VLSI Chips," Proc. of the AACD
wonkshop, vol. 2, pp.225-236, Lwven, March 1993.
1101 T. Stetzler, I. Post,J. Havens and M. Koyama, "A 2.7V to 4.5V Single-Chip GSM Transceiver RF Integrated Circuit,"Proc.
ZSSCC, pp.15CL151, San Francisco, Feb. 1995.
[ll]C. Marshall et al., "A2.7V GSM Transceiver ICs with &Chip Fdtering,"Proc. ZSSCC, pp.148-149, Feb. 1995.
1121 J. Sevenhans et al., "An Analog Radio front-end Chip Set for a 1.9 GHz Mobile Radio Telephone Application,"Proc. ISSCC,
pp.4445,SanFmncisco, Feb. 1994.
[13] J. craniackx and U Steyaert, "Low-NoiseVoltage Controlled OscillatorsUsing Enhanced LC-tanks", LEEE Tram. on Cirmits
-
and Systems IZ :Analog and Digital Signal Processing, vol. 42. no. 12, pp. 794-804, Dec.1995.
[14] A. Rofourgan, J. Rael, M.Rofourgan, A. Abidi, "A 9OO-MHz CMOS LC-Osdlator with QuarLature Outputs",Proc ZSSCC,
pp. 392-393, Febr. 1996.
[15] N. M.Nguyen and R. G. Meyer, "A I.8-GHz Monoithic U3 Voltage Conmlled Osdatof, LEEE Journal of Solid-stre
Ciracits, voL 27, no. 3, pp. 444-450,March 1992.
[la I. - C ~ X and M. Steyaen "A 1.S-GHZ Low-phase-N~iseV~ltagecontrolled with prescalef,IEEE J O U Of~
Soli~-SZaZeCimcits, VOL 30,110.12, p ~ 1474-1482,
. Dec. 1995.
[17J J. Cranincloc and M. S&yaert, "A 1.75-GHZn-V Dual Modulus Divide-by-128/129 Rescaler in 0.7-um CMOS", Proc.
BSClRC, pp. 254-257, Sept. 1995.
[18] UBOrremans and M.Steyaert, "A 2V. Low Distortion, 1 GHz CMOS Upconversion Mixer", Proc. CZCC, session 24.3, May
1997, pp517-520.
[19] J. cranincla,M. Steyaert. "A l.&GHZLO~-phaSe-NaiseSpiral-Lx:CMOS VCO." Proc. VLSI sy"aJUTE 1996.
1201 RYau et all. "Highperformance 0.1 micron room tempemure Si mosfets", Digest of technicalpapers, 1992 Symposium on
VLSI technology,2 4 June 1992
[21] J.Chen et all. "A high speed SO1technology with 12 pdl8ps gate delay operation at 1.W,proceedings of IEEE h"tionaI
El- Devices Meeting, SF, CA,13-16 k 9 2
m] F . B M et all " HighintegratiOn CMOS RF Transceivers".Proc. of theAACD wor&shop,Lausanne,April 1996.
[U]J.Foumieret all " 2GHz RF Circuits m BiCMOS Process" Proc of theAACD wor&shop.Lawame, April 1996.
1241 MSteyaert et all. "RI?CMOS Design, Some untold pitfalls" Proc. of the AACD workshop,Lausume, April 1996.
USteyaert et all. "A Single Chip CMOS Transceiver for DCS1800 Wireless Communications", Proc. IEEE-IsSCC'98, Feb.
1998, PP
[26JAN. Karanicolas, "A 2.7 V 900M H z CMOS LNA and Mixer," h o c ZSSCC, pp.50-51. San Fmnckco, Feb. 1996.

116