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Digital Circuits
Assignment- Week 4
TYPE OF QUESTION: MCQ
Number of questions: 15 Total mark: 15 X 1 = 15

QUESTION 1:

DeMorgan’s first theorem shows the equivalence of

(A) OR gate and Exclusive OR gate.
(B) NOR gate and Bubbled AND gate.
(C) NOR gate and NAND gate.
(D) NAND gate and NOT gate

Corrected Answer: B

Detailed Solution:

DeMorgan’s first theorem shows the equivalence of NOR gate and Bubbled AND gate. Logic diagrams for
De Morgan’s First Theorem is shown in fig. (a)

Figure (a) Figure (b)

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Question 2:

The logic circuit shown in the figure below can be minimised to

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Corrected Answer: D

Detailed Solution:
As output of the logic circuit is
Y=(X+Y’)’+(X’+(X+Y’)’)’
(X+Y’)’=X’Y [Using DE Morgan’s Low]
Now this is one of input of 2nd gate.
F= (A+X’)’=A’X=*(X’Y)’.X+
= [(X+Y’)X+=X+XY’=X (1+Y’) =X
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Question 3:

How many two input AND gates and two input OR gates are required to realize the expression Y =
BD+CE+AB

(A) 1, 1
(B) 4, 2
(C) 3, 2
(D) 2, 3

Corrected Answer: C

Detailed Solution:
There are three product terms. So three AND gates of two inputs are required. As only two input OR
gates are available. So two OR gates are required to get the logical sum of three product terms.
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Question 4:

Boolean Algebra implemented with (x + y)(x + z) is simplified to

(A) x
(B) x + x(y + z)
(C) x (1 + yz)
(D) x + yz

Corrected Answer: D

Detailed Solution:
(x + y)(x + z)= xx + xz + xy + yz
= x + xz + xy + yz As (xx = x)
= x(1+z) + xy + yz
= x + xy + yz As [(1+z) = 1]
= x(1 + y) + yz
= x + yz As (1+y) = 1
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Question 5:

In the CMOS inverter, when the input is in logic 1, then

(A) nMOS will be OFF
(B) nMOS will be ON
(C) pMOS will be ON
(D) None

Corrected Answer: B

Detailed Solution:
When A=1, the nMOS will be on and the output will be high.

GND
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Question 6:

When the set of input data to an even parity generator is 0111, the output will be
(A) 1
(B) 0
(C) Unpredictable
(D) Depends on the previous input

Corrected Answer: A

Detailed Solution:
Even parity generator must produce a 1 for all the input combinations that contain odd number of 1
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QUESTION 7:

Which one of the following expressions represents exclusive NOR of A and B?

A) AB+A’B’
B) AB’+A’B
C) (AB)+(AB)
D) (A’ +B’) (A +B)

Correct Answer: A

Detailed Solution:
XNOR (A, B) = (XOR (A, B) )’ = ( A’B + AB’)’= (A’B)’ (AB’)’= (A + B’) (A’ +B)= AB + A’B’
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Question 8

The combinational circuit implementation of the following boolean function

F(A,B,C) = Σ(1,2,4,7)

A
a) b)
B

A
b) d)
B

C
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Correct Answer: (a)

A BC
Detailed Solution:
F(A,B,C) = Σ(1,2,4,7)
=(ABC+ABC+ ABC+ABC)
=(AB+AB)C+ (AB+AB)C
=(AB+AB)C+ (AB+AB)C= (AB+AB)  C=A B C
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QUESTION 9:

Which of the following logic expressions represents the logic diagram shown?

A) X=AB’+A’B
B) X=(AB)’+AB
C) X=(AB)’+A’B’
D) X=A’B’+AB

Correct Answer: (D)

Detailed Solution:

A’B’

=A’B’+AB

AB
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QUESTION 10:

Which of the following is correct for full adders?

A) Full adders have the capability of directly adding decimal numbers

B) Full adders are used to make half adders
C) Full adders are limited to two inputs since there are only two binary digits
D) In a parallel full adder, the first stage may be a half adder

Correct Answer: (D)

Detailed Solution:
As carry in=0 in the first stage, the first stage of a Parallel Full adder may be implemented.
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QUESTION 11:

If A and B is the input of a subtractor, then the borrow will be

A) A AND B’
B) A’ AND B
C) A OR B
D) A AND B

Correct Answer: B

Detailed Solution:

The borrow of a subtractor is received through AND gate whose one input is inverted. On that basis the
borrow will be (A’ AND B).

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QUESTION 12:
The flowing CMOS implementation realizes

a) (AB)
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b) (A+B)
c) (AB)
d) (A+B))
Correct Answer: c

Detailed Solution: The truth table of the circuit is given below. It releases the NAND gate ((AB) ).

QUESTION 13:
The delay times are measured between the __________ % voltage levels of the input and
output waveforms.

A) 50
B) 75
C) 25
D) 100

Correct Answer: A

Detailed Solution:
Propagation delay is the time taken by the output to change it’s state when the input changes. The
average of the two propagation delays is given by (t1 + t2)/2, which gives the intermediate value. So, the
delay times are measured between the 50% voltage levels of the input and output waveforms.

QUESTION 14:
7 bit Haming code word received is 1011011 assuming the even parity state and the received code
word is wrong. The correct code word is
A) 1111011
B) 1001011
C) 1011001
D) 1011111
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Correct Answer: (B)

Detailed Solution:
D7 D6 D5 P4 D3 P2 P1
1 0 1 1 0 1 1

P4 = p4 d5 d6 d7 = 1 => 1 0 1 , p4 is 1
P2 = p2 d3 d6 d7 = 0 = > 0 0 1, p2 = 0
P1 = p1 d3 p5 d7 = 1 => 011, P1 = 1
P4 p2 p1 = 101 = 5
Error occurs at 5th bit.
Corrected answer after changing the 5th bit will be : 1001011

QUESTION 15:
The maximum noise voltage that may appear at the input of a logic gate without changing the logical
state of its output is termed as

A) Noise Margin
B) Noise Immunity
C) White Noise
D) Signal to Noise Ratio

Correct Answer: B

Detailed Solution
The maximum noise voltage that may appear at the input of a logic gate without changing the logical
state of its output is termed as noise immunity.

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