1998 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO.

7, JULY 2011

A High-Performance PWM Algorithm for

Common-Mode Voltage Reduction in
Three-Phase Voltage Source Inverters
Ahmet M. Hava, Member, IEEE, and Emre Ün, Student Member, IEEE

Abstract—A high-performance pulsewidth modulation (PWM)

algorithm with reduced common-mode voltage (CMV) and sat-
isfactory overall performance is proposed for three-phase PWM
inverter drives. The algorithm combines the near-state PWM
(NSPWM) method that has superior overall performance char-
acteristics at high modulation index, and MAZSPWM, a mod-
ified form of the active zero-state PWM method (AZSPWM1),
which is suitable for low modulation index range of operation.
Since AZSPWM1 has line-to-line voltage pulse reversals with small
zero-voltage time intervals, in its naive form, it causes overvolt-
ages, in particular in long-cable motor drive applications. Obtained
by reorganizing the duty cycles of the utilized voltage vectors of
AZSPWM1, MAZSPWM has sufficiently long zero-voltage time
intervals between pulse reversals such that during pulse reversals,
overvoltages are avoided. The combined algorithm performs sat-
isfactorily throughout the inverter operating range and the tran-
sition from NSPWM to MAZSPWM and vice versa is seamless.
The performance of the proposed algorithm is proven by theory,
computer simulations, and detailed laboratory experiments. The
paper also shows that the proposed reduced CMV PWM algorithm
is effective in reducing the motor leakage current, and it is most
beneficial when a small common-mode inductor is included in the
drive.
Index Terms—Active zero-state PWM (AZSPWM), algorithm,
common-mode current (CMC), common-mode voltage (CMV),
discontinuous PWM (DPWM), inverter, modulation, long cable,
near-state PWM (NSPWM), overvoltage, space vector, space vec-
tor PWM (SVPWM), pulsewidth modulation (PWM).
I. INTRODUCTION
HREE-PHASE voltage source inverters (VSIs) are widely
T utilized to drive ac motors with high motion control qual-
ity and high energy efficiency. Pulsewidth modulation (PWM)
is the standard approach to operate the inverter switches in or-
der to generate the required output voltages. Conventional con-
tinuous PWM (CPWM) methods such as space vector PWM
(SVPWM) [1] and Discontinuous PWM (DPWM) methods such
as DPWM1 [2] perform satisfactorily in terms of voltage lin-
earity, output current ripple, dc bus current ripple, and average
switching frequency requirements [3], [4]. However, they have
Manuscript received April 22, 2010; revised July 22, 2010, October 3, 2010;
accepted December 1, 2010. Date of current version August 5, 2011. This paper
was presented in part at the PESC 2008, Rhodes Conference. Recommended
for publication by Associate Editor V. Agarwal.
A. M. Hava is with the Department of Electrical and Electronics Engineer-
ing, Middle East Technical University, İnönü Bulvarı, 06531 Ankara, Turkey
(e-mail: hava@metu.edu.tr).
E. Ün is with the Defense Systems Technologies Division, ASELSAN, Inc.,
P. O. Box 1, 06172 Ankara, Turkey (e-mail: emreun@aselsan.com.tr).
Digital Object Identifier 10.1109/TPEL.2010.2100100
0885-8993/$26.00 © 2011 IEEE
Fig. 1. Three-phase inverter drive with diode rectifier front end.
poor common-mode voltage (CMV) characteristics [5]. In the
standard three-phase two-level VSI with diode rectifier front
end (see Fig. 1), the CMV (vn g ) is defined as the potential of
the star point of the load with respect to the power line ground.
With vn g = vn o + vog and vog being much smaller and slowly
varying signal compared to vn o , vog can be neglected. Therefore,
the CMV of the inverter is practically defined as the load star
point to the center of the dc bus of the VSI potential difference
(vn o in Fig. 1) and can be expressed in the following:
vao + vbo + vco
vn o = . (1)
3
Since the VSI cannot provide purely sinusoidal voltages and
has discrete output voltages synthesized from the fixed dc bus
voltage Vdc , the CMV is always different from zero and may
take the values of ±Vdc /6 or ±Vdc /2 depending on the inverter
switch states. This result can be deduced from the fact that
vao , vbo , and vco may each take the values of ±Vdc /2, and by
substituting in (1) for each inverter state, the discussed CMV
values can be obtained. In SVPWM and DPWM1, its max-
imum reaches ±Vdc /2 (for the states of (111) and (000) for
the switches (Sa + , Sb + , and Sc + ) according to Fig. 1). During
switch state changes, the CMV changes by ±Vdc /3 regardless
the changing states (for example, from (100) to (000), the CMV
changes from −Vdc /6 to −Vdc /2, thus decreases by Vdc /3). At
switching frequencies above several kilohertz, switching times
of several hundred nanoseconds, and Vdc levels above several
hundred volts, excessive CMV with sharp edges can result in
high common-mode current (CMC, motor leakage current). In
motor drive applications, this may lead to motor bearing failures,
EMI noise that causes inverter drive nuisance trip, or interfer-
ence with other electronic equipment in the vicinity [6]–[8].
In the application field, recently, such problems have been in-
creasing due to increasing PWM frequencies (aimed for higher
efficiency, control bandwidth, smaller ripple, and filter size) and
CMV reduction methods have been gaining importance.
HAVA AND ÜN: HIGH-PERFORMANCE PWM ALGORITHM FOR CMV REDUCTION IN THREE-PHASE VOLTAGE SOURCE INVERTERS 1999

CMV and the resulting CMC can be passively or actively

reduced. Passive methods involve utilization of magnetic cir-
cuits such as the common-mode inductor (CMI) and common-
mode transformer [9] and may involve additional passive com-
ponents [10]. All passive filters have a size and cost penalty. The
active methods can be classified as CMV cancellation and CMV
reduction methods. In the CMV cancellation methods, the CMV
generated by the inverter is canceled via active circuits involving
transistors, capacitors, and an injection transformer [11]. This
approach is also costly and complex. The active CMV reduction
method involves reducing the CMV from its source by means of
utilizing a multilevel inverter topology, such as the three-level Fig. 2. Illustration of the voltage space vectors and the voltage synthesis for
neutral-point-clamped inverter [12] or by improving the PWM (a) NSPWM in B2 and (b) ASZPWM1 in A1.
pulse pattern of the two-level inverter such that low CMV is
generated. Utilizing a multilevel inverter involves a significant
cost increase, and can only be favored in applications, where the
multilevel inverter brings other advantages such as increased ef-
ficiency. However, in the general-purpose drive applications, this
approach is cost-prohibitive. Thus, CMV can be most econom-
ically reduced by means of improving the PWM pulse pattern
of the VSI, because only software modifications are required
for this enhancement. As a consequence, recent research has
focused on CMV reduction via PWM methods [5], [13]–[20].
Although various reduced CMV PWM (RCMV-PWM) meth-
ods have been reported, of these only the active zero-state
PWM1 (AZSPWM1) [13], [15], [20] and the near-state PWM
(NSPWM) methods [18], which limit the CMV to ±Vdc /6, are Fig. 3. Switch pulse pattern, CMV, and output line-to-line voltages for (left)
feasible. All other reported RCMV-PWM methods require si- NSPWM in B2 and (right) AZSPWM1 in A1.
multaneous switchings in two inverter legs for CMV reduction algorithm is proposed. The overall high performance of the pro-
[5], [14], [16], [17] and as this cannot be guaranteed/realized, posed PWM algorithm is confirmed by detailed simulations and
in practice, the CMV-related problems are further exacerbated experimental results.
in these methods [21]. Curement for these problems is difficult The approach used to determine, evaluate, and compare CMV
and research efforts are ongoing [19]. Further, rapid reversals and CMC of the drive for various PWM methods in the paper is
of the line-to-line voltages result in significant motor terminal involving time-domain waveforms and the peak and RMS value
overvoltages [18], [20], [22]–[24]. Therefore, most of the re- data recordings. As far as the CMC, only conducted emission is
cently developed RCMV-PWM methods cannot be utilized in considered. The microscopic waveforms and detailed behavior
most practical drives and only NSPWM and AZSPWM1 remain analysis regarding the high-frequency components have been
as possible candidates. covered in [5], [18], and [21] and will be omitted for the sake
This paper considers the utilization of AZSPWM1 and of brevity. Also, the detailed conducted and radiated electro-
NSPWM in motor drive applications for the purpose of CMV magnetic compatibility (EMC) performance evaluation of the
reduction. While effectively reducing the CMV, each of these drive with respect to EMC standards (which covers the thorough
methods suffers from a major limitation and cannot be utilized frequency-domain analysis) [25], [26] is left as future work.
alone. This paper combines the two methods in one algorithm
that overcomes these limitations and yields high overall perfor-
mance. NSPWM is employed at high modulation index where its II. NEAR-STATE PWM (NSPWM) METHOD
performance is extraordinary and after a slight modification for NSPWM [18], [22] employs the three active (nonzero) near-
the purpose of overvoltage reduction in long-cable applications, voltage vectors to program the required output voltage. For
AZSPWM1 (termed as modified AZSPWM1 (MAZSPWM), example, as shown in Fig. 2(a), between 30◦ and 90◦ (B2, as
thereafter) is employed at low modulation index, where it has defined in detail in [5]), V1 –V2 –V3 vectors are the near-voltage
the best overall performance among many modulators. vectors and they are utilized in the optimal sequence of V3 –
The paper first reviews NSPWM and AZSPWM1. Following V2 –V1 –V2 –V3 over a PWM cycle. With this choice since no
the review of these PWM methods, the limitations of these meth- zero-voltage vector is utilized, CMV is reduced to ±Vdc /6 and
ods are discussed. First, the voltage linearity limits of NSPWM also the switching count is minimal as one switching at a time
are discussed. Then, the overvoltage problem of AZSPWM1 is occurs. NSPWM also locks one inverter leg as the conventional
discussed and its pulse pattern is modified such that the over- DPWM methods; thus, it has reduced switching losses [27].
voltage problem is avoided. Having each PWM method to per- These arguments are supported with the switch logic signal and
form satisfactorily in its intended operation range, the combined output voltage pulse patterns, as shown in Fig. 3.
2000 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 7, JULY 2011

Fig. 4. Voltage linearity range of (a) NSPWM and (b) AZSPWM1. (White
region) No solution, (gray region) only PWM cycle linearity range, and (dark
gray region) fundamental cycle linearity range.

The main performance limitation of NSPWM involves its

voltage linearity range. As shown in Fig. 4(a), the method has
no solution in the white hexagonal region of the voltage vector
space. Thus, the method is only applicable above modulation in- Fig. 5. Principle for generating the voltage vectors of MAZSPWM by modi-
fication of AZSPWM1 (a) general, (b) at high Mi , and (c) at low Mi .
dex of Mi > 0.61 (Mi = Vm /(2Vdc /π), where Vm is the reference
voltage magnitude) where it has superior overall performance.
NSPWM can easily be implemented with the scalar PWM ap-
shown in Fig. 3, in the AZSPWM1 method, two voltages are
proach, and in that case, using the DPWM1 modulation wave
bipolar.
along with alternating polarity triangular carrier wave, the pulse
The primary performance limitation of AZSPWM1 involves
pattern of Fig. 3 can easily be obtained [18], [28]. In this case, for
its two bipolar line-to-line voltage pulses. Regardless the Mi
Mi > 0.61, the implementation yields the pulse pattern of Fig. 3,
range, the zero-voltage time interval between the bipolar pulses
while for Mi < 0.61, although the voltage linearity is retained,
periodically decreases within a fundamental cycle (in vector
the pulse pattern becomes different from that of NSPWM and
space, as the reference voltage vector approaches one of the
high CMV results. Thus, regardless its implementation tech-
active vectors) to a very small value that the line-to-line volt-
nique (scalar or vector), NSPWM is only feasible for Mi >
age has rapid pulse reversals (transition from Vdc to −Vdc very
0.61, where it generates the pulse pattern of Fig. 3 with low
rapidly or vice versa). When the zero-voltage time interval is
CMV and low ripple on both the ac side and dc side of the
too small and comparable to the inverter switching transient
inverter [18], [22].
times, before a switching transient is completed, another one
Unlike in the conventional CPWM/DPWM methods, in
starts and overvoltages may occur across the motor terminals.
NSPWM, as seen in Fig. 3, one of the line-to-line voltages is
In particular, in long-cable applications, the voltage reflection
bipolar. However, as the zero-voltage time interval of NSPWM
problem is exacerbated [23], [24]. Therefore, AZSPWM1 can-
is large, the bipolar pulse does not cause performance prob-
not be utilized in its naive form [18], [22] and a modification is
lems [18], [22].
necessary. The following section elaborates on this issue.

III. ACTIVE ZERO-STATE PWM1 (AZSPWM1) METHOD IV. MAZSPWM METHOD

AZSPWM1 [13], [15] involves utilizing the two adjacent volt-
age vectors along with two opposing active voltage vectors with
equal duty cycle to provide cancellation and create an effective
zero state. For example, as shown in Fig. 2(b), in A1, the ad-
jacent state voltage vectors V1 and V2 are accompanied by the
active zero pairs of V3 and V6 . Thus, in A1, the optimal sequence
is V3 –V2 –V1 –V6 –V1 –V2 –V3 . As shown in Fig. 3, the CMV is
reduced to ±Vdc /6 since the zero states are avoided. As shown
in Fig. 4(b), the method is linear in the whole inverter hexagon,
unlike NSPWM. Scalar PWM implementation of the method
is straightforward as the modulation wave of SVPWM [1], [3]
and the alternating polarity carrier wave are used to generate
the pulse pattern of the method [28]. Similar to NSPWM, this
method also has bipolar line-to-line voltage pulses. While in
NSPWM, only one line-to-line voltage has bipolar pulses, as
Fig. 3 illustrates that in A1, for Vab , the zero-voltage time
duration is equal to the time of V2 . Likewise for Vb c , the zero-
voltage time duration is equal to the time of V1 . Of the two,
the vector with the smaller time length is more problematic in
terms of pulse reversals and its duration should be increased.
MAZSPWM provides this modification while retaining the re-
quired volt–seconds (thus the average voltage) over the PWM
cycle. As shown in Fig. 5(a), in A1, this is achieved by increas-
ing the duty cycle of the smaller duty cycle vector by 2ε and
decreasing the duty cycle of the larger duty cycle vector by the
same amount. However, this disturbs the vector volt–seconds
balance. This imbalance is compensated via the modification on
the two active zero states V3 and V6 . Their duty cycles, in this
case, are also modified and while the V3 duty cycle is increased
by ε, the V6 duty cycle is decreased by the same amount. Thus,
HAVA AND ÜN: HIGH-PERFORMANCE PWM ALGORITHM FOR CMV REDUCTION IN THREE-PHASE VOLTAGE SOURCE INVERTERS 2001

unlike in AZSPWM1, in MAZSPWM, the active zero-state vec-

tor volt–seconds do not completely cancel each other. Defining θ
as the angle of the reference voltage vector according to Fig. 2 as
in (2), the vector duty cycles can be calculated. The vector duty
cycles of MAZSPWM, for the region A1, are given in (3)–(6),
where ε is the zero-voltage duration duty cycle parameter
θ = ωe t (2)
√
2 3
d1 = Mi sin (60◦ − θ) + 2ε (3)
π
√
2 3
d2 = Mi sin (θ) − 2ε (4)
π
√
1 3
d3 = − Mi sin (60◦ + θ) + ε (5)
2 π
√
1 3
d6 = − Mi sin (60◦ + θ) − ε. (6)
2 π
Note that with different ε values, different solution sets are
obtained. For ε = 0, the solution set√corresponds to AZSPWM1,
where d3 = d6 . If ε = ±[0.5 − ( 3Mi /π) sin (θ + 60◦ )], the
solution set corresponds to NSPWM, where either d3 or d6 is
zero. Between these two extremes, ε may take any value and Fig. 6. PWM pulse pattern of MAZSPWM.
unique performance characteristics can be obtained.
The minimum required zero-voltage interval (tz m in ) between
the polarity reversals of the line-to-line voltages not resulting
in high peak overshoots is drive and cable-parameter-dependent
and it varies in the order of microseconds [18]. Normalizing
tz m in with the PWM period (Ts ), the minimum zero-voltage
interval duty cycle dz m in is obtained and this value defines
the boundary on ε (εcritical = dz m in ). Choosing a larger value
results in unnecessary aggravation of the PWM ripple (discussed
in the next section). The implementation of MAZSPWM is
illustrated in Fig. 6. Note that at the illustrated operating point
(near θ = 60◦ ), in AZSPWM1, d1 is very low (hence, the dz
is very narrow). After the “ε” modification d1 , and hence, dz
are enlarged sufficiently and the CMV waveform is not affected
and still limited at |Vdc /6|. Note that of the two active voltage
vectors, the one with the smaller duty cycle is modified to have
at least 2dz m in value. Although the basic modification scheme
is simple, there are constraints on the algorithm for operation
at very low and high Mi values (the range of which depends on
dz m in ), which will be discussed in the following.
Fig. 7 shows the MAZSPWM algorithm in detail. In A1,
when d1 and d2 > 2dz m in , AZSPWM1 results (ε = 0) and no
modification is required. If this condition is not satisfied, but Fig. 7. Decision flowchart of MAZSPWM.
with ε modification, all the resulting duty cycles are problem-
free (modified d1 and d2 > 2dz m in ), then the ε modification
is made such that the smaller vector duty cycle is completed negative). To avoid this problem, the duty cycle of the active
to dz m in (ε = dz m in −min (d1 ,d2 )/2). Thus, the compensation zero-voltage vector with negative value is bounded to zero
is provided with the smallest possible modification such that (ε = min(d3 ,d6 )). In the second case, which occurs at low
the waveform distortion does not become excessive. When the Mi [see Fig. 5(c)], the active voltage vectors are problematic
duty cycles are not realizable (modified d1 and d2 > 2dz m in ), such that the wider of the two active voltage vectors is not
there are two cases to consider. In the first case, which occurs sufficient to compensate the narrower. In this case, the opti-
at high Mi [see Fig. 5(b)], this modification may result in ac- mal solution is to equalize the duty cycles of both vectors and
tive zero-voltage vectors with negative duty cycles (in Fig. 5(b), this results in ε = |d1 − d2 |/4. If the desired dz m in cannot
the duty cycle of V6 approaches zero value or may become be realized, the consequence will be an additional overvoltage
2002
Fig. 8. Epsilon “ε” modification of the zero-voltage duty cycle.
proportional to the error between ideal and realized dz m in (still,
there will be less overvoltage than AZSPWM1). Considering the
two cases, for each case, there is a limit on how large a dz value
can be programmed. Calculating the extreme dz values, at low
Mi , dz = (3/4π)Mi and at high Mi , dz = (1/2) − (3/2π)Mi
are obtained. These functions meet at Mi = 2π/9 ≈ 0.7 and
dz = 1/6. For a given dz m in , full compensation is possible for
the range of Mi as defined in (7). Outside the boundaries as dz
becomes smaller, the voltage overshoot increases
   
4π 2π
dz m in < Mi < (0.5 − dz m in ). (7)
3 3
In Fig. 8, the zero-voltage duty cycles of AZSPWM1 for var-
ious Mi values are illustrated along with the ε modification
for a required dz m in (as shown for dz m in = 0.05). Near the
A1 region boundaries (0◦ and 60◦ ), the available AZSPWM1
zero-voltage duty cycle becomes insufficient. These problematic
zones, wherein |ε| = dz m in − dz −az s (x/y ) is applied, become
wider as Mi decreases. For dz −az s (x/y ) > dz m in , no modifi-
cation is required. Here, dz −az sx stands for dz near the 60◦
boundary of A1 and dz −az sy for near the 0◦ boundary of A1,
where the pulse reversal problems occur.
The approach described here modifies the PWM pulses such
that the volt–seconds balance is always maintained for every
PWM cycle and the overvoltages are suppressed as much as
possible. Based on the approach defined in this paper, in [20],
the priority has been given to overvoltage suppression, and thus,
intentional disturbance on the volt–seconds balance has been
allowed. While the first approach allows somewhat high over-
voltages in some operating regions, the second approach allows
increase in the low-frequency (subcarrier frequency) ripple in
the output voltage that causes torque ripple and acoustic noise
in motor drives as mentioned in [20]. This paper will mainly
focus on the first approach and report its results to detail.
V. PERFORMANCE CHARACTERISTICS OF MAZSPWM
MAZSPWM carries the main modulator characteristics of
AZSPWM1, which are reported in [5] in detail. The voltage lin-
earity range and switching loss characteristics are the same. The
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 7, JULY 2011
Fig. 9. HDF characteristics of NSPWM, AZSPWM1, and MAZSPWM with
two different dz m in values (fs−ave = constant).
output current ripple and dc link current ripple characteristics are
also basically the same. However, a slightly higher distortion is
created in MAZSPWM due to the choice of nonzero ε value. The
symmetric volt–second balancing mechanism of AZSPWM1 is
disturbed, asymmetric voltage pulses are generated, and this re-
sults in output current ripple degradation. The harmonic distor-
tion factor (HDF), which illustrates the rms ripple current char-
acteristic of a modulator [3], [4], is calculated for MAZSPWM
for dz m in = 7% and 12% (intentionally selected large for the
purpose of illustrating the differences clearly). In Fig. 9, the
HDF curves of MAZSPWM are illustrated together with those
of AZSPWM1 and NSPWM (assuming that the average switch-
ing frequency is the same for all). It is observed that the HDF
of MAZSPWM is nearly identical to that of AZSPWM1 for
practical (small) dz m in values. NSPWM has low HDF in the
targeted operating range of high Mi . For low Mi , operation with
MAZSPWM (as in AZSPWM1) does not pose a significant
drawback in applications involving high switching frequencies
or motors with relatively large leakage inductance [20]. Thus,
most applications permit the utilization of MAZSPWM for low
Mi .
VI. COMBINED PWM ALGORITHM
As summarized in this paper and detailed in [5], [18], and [22],
NSPWM exhibits high overall performance for Mi > 0.61
(which performs better than MAZSPWM in most aspects). How-
ever, it is not feasible for Mi < 0.61. For Mi < 0.61, the only
feasible RCMV-PWM method is MAZSPWM. Therefore, the
combination of the two methods in one algorithm is optimal
and yields the following benefits: voltage linearity throughout
the whole inverter hexagon (thus maximum voltage utilization),
acceptable output ripple current and dc link ripple current, and
most importantly, low CMV throughout. The flowchart of the
optimal algorithm is shown in Fig. 10.
It is a common practice in industrial drives to employ a PWM
algorithm that utilizes SVPWM at low Mi and DPWM1 at high
Mi . The critical Mi for transition is typically Mi cr1 ≈ 0.5–
0.6 [3], [4]. Thus, if CMV reduction is not a requirement, the
optimal PWM path is the right branch of Fig. 10. However,
when CMV reduction is a requirement, the optimal PWM path
HAVA AND ÜN: HIGH-PERFORMANCE PWM ALGORITHM FOR CMV REDUCTION IN THREE-PHASE VOLTAGE SOURCE INVERTERS
Fig. 10. High-performance combined PWM algorithm.
is the left branch of the figure. At low Mi , MAZSPWM and at
high Mi , NSPWM are employed. Note that there is a striking
resemblance between the right branch and left branch paths. The
modulation wave of MAZSPWM and SVPWM is almost the
same (they are only slightly different in the region where the ε
modification is applied, as will be shown in the simulations in the
next section) [28]. Likewise, modulation wave of NSPWM and
DPWM1 is the same [18]. Also, NSPWM and DPWM1 are both
DPWM methods with reduced switching loss characteristics.
As in the fact that SVPWM and DPWM1 complete each other,
MAZSPWM and NSPWM also complete each other (rather than
being competitors).
Unlike the SVPWM to DPWM1 transition point, the
MAZSPWM to NSPWM transition point cannot be arbitrarily
selected since NSPWM is not feasible inside the white area in
Fig. 4(a). Two methods of transition can be considered. The first
method utilizes polygon boundaries and employs MAZSPWM
minimally [only inside the white hexagon of Fig. 4(a)]. In this
method, it is necessary to detect whether the reference voltage
vector is inside the white hexagon or not, and this involves addi-
tional computational effort. Thus, the left branch of the decision
algorithm in Fig. 10 is slightly modified such that the Mi <
Mi cr2 condition is replaced by the white hexagon checking rou-
tine. With this approach, at steady state, for 0.52 < Mi < 0.61,
over a full fundamental cycle, the PWM method alternates six
times between NSPWM and MAZSPWM. The second method
is easier to implement and only considers circular boundaries for
transition. The transition boundary Mi cr2 = 0.61 corresponds to
the inner circle of the dark gray ring in Fig. 4(a). Thus, inside
the Mi cr2 = 0.61 circle, MAZSPWM and outside it, NSPWM
are utilized. Since the method maximally utilizes MAZSPWM,
the switching losses and the current ripple of the algorithm
are consequently higher than the first transition method. In ei-
ther algorithm, the transition between the two PWM methods
is problem-free as at the beginning of every PWM cycle, the
harmonic currents are reset [3], [4].
VII. COMPUTER SIMULATIONS
To illustrate the current waveform characteristics and the
seamless transition between NSPWM and MAZSPWM, a com-
2003
Fig. 11. MAZSPWM phase current and modulation signal (Mi = 0.58).
Fig. 12. AZSPWM1 phase current and modulation signal (Mi = 0.58).
puter simulation study is conducted. A general-purpose 4-kW,
380-V, four-pole induction motor is fed by an inverter with fixed
500 V dc bus voltage. The inverter is controlled in constant V/f
mode (176.7 Vrm s /50 Hz). The drive is tested at no-load, where
the ripple current can be clearly observed. The inverter average
switching frequency, fs−ave is 6.6 kHz (fs−NSPW M = 10 kHz
and fs−M AZSPW M = 6.6 kHz). Fig. 11 shows the modulation
signal and phase current for MAZSPWM at Mi = 0.58 with
dz m in = 0.04 (corresponding to tz m in = 6 μs, a value selected
based on experimental evaluation [18]). The phase current rip-
ple is nearly uniform and approximately 10% of the no-load
peak fundamental component current. For the purpose of com-
parison, AZSPWM1 is simulated for the same condition and
the waveforms are illustrated in Fig. 12. While the modulation
signal of AZSPWM1 is identical to that of SVPWM [3], [28], in
MAZSPWM, there are deviations from this form that are visible
in the waveform occurring at the edge of 60◦ region boundaries
(where the modifications are applied). As the figure shows, the
current ripple of MAZSPWM slightly increases compared to
AZSPWM1 during these intervals. Fig. 13 shows the modula-
tion signal and phase current for NSPWM at Mi = 0.61 [just
above the internal circular boundary of Fig. 4(a)]. The NSPWM
current ripple is not uniform (very small during the 2 × 60◦
clamping intervals) and overall, it is less than MAZSPWM.
In the combined algorithm with the transition based on the
polygon [internal white hexagon of Fig. 4(a)], boundaries and
for the fundamental component corresponding to Mi = 0.58,
the simulation waveforms are shown in Fig. 14. At this oper-
ating point, methods alternate six times per fundamental cycle.
In the segments utilizing NSPWM, the current waveform car-
ries the NSPWM ripple characteristics; otherwise, it shows the
MAZSPWM characteristics. Since NSPWM has lower ripple
2004
Fig. 13. NSPWM phase current and modulation signal (Mi = 0.61).
Fig. 14. Motor phase current and the modulation signal of the combined algo-
rithm illustrating disturbance-free transition between NSPWM and MAZSPWM
(Mi = 0.58, no-load).
Fig. 15. CMV of the combined PWM algorithm (Mi = 0.58) over a small por-
tion (transition region between NSPWM and MAZSPWM) of the fundamental
cycle under no-load.
than MAZSPWM, the combined algorithm results in lower cur-
rent ripple than utilizing only MAZSPWM. As can be seen
from the phase current waveform, the transition is seamless
(no distortion on the current fundamental component during the
transition). The deviations (the increased current ripple) on the
modulation signal of MAZSPWM in Fig. 11 are not visible in
the combined algorithm due to the fact that around the region
boundaries, NSPWM is utilized (for the given operating condi-
tion of Mi = 0.58) and requires no duty cycle modification for
overvoltage suppression.
The CMV of the combined algorithm has the boundaries
of ±Vdc /6 as it consists of either NSPWM or MAZSPWM.
Fig. 15 shows that the CMV of the combined algorithm is con-
fined within ±83.3 V unlike in SVPWM and DPWM1 where
it reaches ±250 V. In the figure, the transition region between
NSPWM and MAZSPWM is covered and in some intervals,
NSPWM and other intervals, MAZSPWM are active. Thus, in
both methods, low CMV is demonstrated.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 7, JULY 2011
Fig. 16. Experimental setup circuit diagram for CMV/CMC measurement.
Fig. 17. Laboratory experimental system photograph.
VIII. EXPERIMENTAL RESULTS
The performance of the proposed algorithm is investigated
experimentally through the setup of which the circuit diagram
is shown in Fig. 16 and the photograph is shown in Fig. 17. The
motor and inverter ratings are the same as in the simulation. With
the neutral point of the transformer secondary isolated from the
primary and connected to the chassis of the motor through a
1-m-long cable (the inductance of which is negligible compared
to the motor equivalent common-mode inductance that measures
in millihenry values), the cable current becomes the CMC. The
CMC is measured via a high-bandwidth (10 MHz) current trans-
ducer. Also, the CMV that is the motor neutral point to the dc bus
midpoint voltage is measured with a high-bandwidth (100 MHz)
differential voltage probe. The inverter is operated in constant
V/f mode (176.7Vrm s /50 Hz) and the induction motor is oper-
ated at no-load. Since both the PWM ripple and CMV/CMC are
practically independent of loading, the no-load test condition
is satisfactory for the study. A DSP is utilized to control the
motor and program the pulse pattern for the considered PWM
methods. Programming the given algorithm with modern DSPs
that have advanced PWM units is an easy task [28]–[30].
First, SVPWM (at Mi = 0.4 corresponding to motor speed
of 741 min−1 ) and DPWM1 (at Mi = 0.8 corresponding to mo-
tor speed of 1510 min−1 ) are tested to establish a reference for
performance. Then, MAZSPWM (at Mi = 0.4) and NSPWM
(at Mi = 0.8) are tested. Both SVPWM and MAZSPWM are
favorable at low Mi ; thus, the Mi = 0.4 operating point is a good
reference point for these methods. Likewise, Mi = 0.8 is a good
HAVA AND ÜN: HIGH-PERFORMANCE PWM ALGORITHM FOR CMV REDUCTION IN THREE-PHASE VOLTAGE SOURCE INVERTERS 2005

Fig. 18. Phase current (top, 2 A/div), CMC (top, 0.5 A/div), CMV (bottom, Fig. 20. Phase current (top, 2 A/div), CMC (top, 0.5 A/div), CMV (bottom,
200 V/div), and modulation signal (bottom, 0.5 V/div) waveforms for SVPWM 200 V/div), and modulation signal (bottom, 0.5 V/div) waveforms for DPWM1
(Mi = 0.4 and fs = 6.6 kHz). (Mi = 0.8 and fs = 10 kHz).

Fig. 21. Phase current (top, 2 A/div), CMC (top, 0.5 A/div), CMV (bottom,
Fig. 19. Phase current (top, 2 A/div), CMC (top, 0.5 A/div), CMV (bot-
200 V/div), and modulation signal (bottom, 0.5 V/div) waveforms for NSPWM
tom, 200 V/div), and modulation signal (bottom, 0.5 V/div) waveforms for
(Mi = 0.8 and fs = 10 kHz).
MAZSPWM (Mi = 0.4 and fs = 6.6 kHz).

reference point for DPWM1 and NSPWM. To maintain constant

average switching frequency, SVPWM and MAZSPWM oper-
ate at 6.6 kHz. DPWM1 and NSPWM operate at 10 kHz. Hence,
switching losses and inverter efficiency are kept approximately
the same for all conditions.
The motor phase current, CMC, CMV, and modulation waves
of SVPWM and MAZSPWM are shown in Figs. 18 and 19,
respectively. Comparing the two methods, it is apparent that
MAZSPWM has higher phase current ripple (approximately
twice), but it has quite smaller CMV than SVPWM (approx-
imately half). There is also a visible reduction in the CMC
peak values in MAZSPWM compared to SVPWM. However, Fig. 22. Phase current (top, 2 A/div), CMC (top, 0.5 A/div), CMV (bottom,
the CMC reduction rate is not at the CMV reduction rate. CMC 200 V/div), and modulation signal (bottom, 0.5 V/div) waveforms for the com-
bined PWM algorithm (Mi = 0.58 and fs = 10 kHz).
is a function of both CMV magnitude (which depends on the
PWM method) and dv/dt (which is independent of the PWM
method). Since dv/dt is an important and unchangeable part, NSPWM combination algorithm gives acceptable current ripple
its contribution could not be suppressed. As a result, a limited and low CMV/CMC characteristics and it can be favored for low
CMC reduction is possible via MAZSPWM. The waveforms for CMV/CMC applications.
DPWM1 and NSPWM are shown in Figs. 20 and 21, respec- Fig. 22 shows the combined MAZSPWM–NSPWM algo-
tively. The phase current ripple of NSPWM is approximately the rithm performance for Mi = 0.58 (1095 min−1 ). The com-
same as DPWM1, while the peak CMV is significantly reduced. bined algorithm has relatively low phase current ripple (as com-
The CMC reduction is also visible. Thus, it is apparent in this pared to MAZSPWM), disturbance-free transitions (between
case that there is no tradeoff and NSPWM is overall better than MAZSPWM and NSPWM), and low CMV overall. In this ex-
DPWM1. This investigation illustrates that the MAZSPWM– periment, the carrier frequency is selected as constant 10 kHz
2006 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 7, JULY 2011

TABLE I
CMV/CMC PERFORMANCE COMPARISONS OF VARIOUS PWM METHODS

Fig. 23. Phase current (top, 2 A/div), CMC (top, 0.5 A/div), CMV (bottom, 200
V/div), and modulation signal (bottom, 0.5 V/div) waveforms for the combined
PWM algorithm and CMI (Mi = 0.58 and fs = 10 kHz).

due to easier implementation. The CMC performance of the

drive is improved with the addition of a small CMI (ferrite
toroidal core with μr = 12 000, Bsat = 380 mT at 25◦ C, OD =
36 mm, ID = 23 mm, H = 15 mm, N = 12 turns, and Lcm =
2.2 mH). As shown in Fig. 23, with the CMI included, the
drive CMC also decreases significantly yielding a drive with
low CMV/CMC and acceptable PWM ripple performance.
The inverter drive experimental CMV/CMC performance
is summarized in Table I. The industry standard SVPWM–
DPWM1 combination is compared to the proposed RCMV solu-
tion of MAZSPWM–NSPWM. The proposed RCMV methods
reduce the CMV significantly (by approximately 50%) and the Fig. 24. Line-to-line voltage pulses of NSPWM (500 V/div) (Mi = 0.8 and
CMC partially (the peak CMC by approximately 25%–30% fs = 10 kHz).
and the rms by 10%–15%). The CMI further decreases the
CMC. Comparing the CMI-included SVPWM–DPWM1 sys-
tem to the CMI-included MAZSPWM–NSPWM system, the
peak CMC decreases by 45% and the rms CMC by 20%. Thus,
the combination of RCMV-PWM methods with CMI yields sig-
nificant overall CMC reduction (80% reduction of peak CMC).
Note that the CMV and CMC peak and rms values obtained in
Table I, corresponding to waveforms in Figs. 18–23, are de-
tailed in [18], [21], and [22], where the microscopic waveforms
are shown and discussed to detail. The detailed frequency spec-
trum study and comprehension of the CMV and CMC for var-
ious PWM methods involves various parameters, models, and
various operating conditions (motor high-frequency model pa-
rameters and tests for various Mi values). Furthermore, PWM
method pulse sequence details should be involved for expla- Fig. 25. Line-to-line voltage pulses of AZSPWM1 (500 V/div) (Mi = 0.4 and
fs = 6.6 kHz).
nation of the obtained frequency spectrum results [31]. Thus,
this task is beyond this paper and will be reported in a future
publication. 500 V dc bus voltage, the peak overvoltage stress is 1020 V
Finally, the improvement of the line-to-line voltage pulse re- that is twice the bus voltage. During every switching transition,
versal characteristics provided with MAZSPWM is illustrated a voltage reflection leads to voltage oscillations that have ap-
with a 70-m cable experiment. In this experiment, the 1-m-long proximately a frequency of 500 kHz (due to skin effect, higher
grounding cable is disconnected. The cable L and C parameters than the parameter calculated value) and decay in 6 μs (three
were measured approximately 4 nF and 40 μH line-to-line (at cycles). Since there is a sufficient zero-voltage time intervals,
1 kHz), yielding 400 kHz resonant frequency (2.5 μs period). there is no additional voltage overshoot. Although only the re-
First, NSPWM is tested. As it has sufficient zero-voltage time sults for NSPWM are shown, the experiments for SVPWM and
interval, it exhibits the same behavior as SVPWM and DPWM1. DPWM1 yielded the same result. Hence, no additional wave-
Fig. 24 shows the NSPWM line-to-line voltage waveform. For forms are necessary. Fig. 25 shows that AZSPWM1 at Mi = 0.4
HAVA AND ÜN: HIGH-PERFORMANCE PWM ALGORITHM FOR CMV REDUCTION IN THREE-PHASE VOLTAGE SOURCE INVERTERS
Fig. 26. Line-to-line voltage pulses of MAZSPWM (500 V/div) (Mi = 0.4
and fs = 6.6 kHz).
exhibits voltage reversals with small zero-voltage time interval,
resulting in significant overvoltages (as high as 1260 V). In or-
der to avoid such overvoltages, the oscillations that take 6 μs
(three cycles) should be elapsed between two switching actions
(in particular, between voltage reversals as the last switching in
Fig. 25). In other words, tz > tz m in = 6 μs (dz m in = 0.06) must
be satisfied. Based on the discussion in Section IV and using (7),
the fully compensable Mi range can be calculated. For this appli-
cation, the range is found as 0.25 <Mi < 0.92. Thus, it appears
that the problems of MAZSPWM for this application occur at
low Mi and can be fully compensated down to Mi value of 0.25.
With this dz m in chosen, as shown in Fig. 26, with MAZSPWM,
the overvoltage is successfully reduced to the normal value ob-
tained in SVPWM/DPWM1/NSPWM, which is a maximum of
1020 V. Note that the resonant and voltage overshoot behavior of
the cable motor system under rectangular PWM waveform has
been investigated in [23] and [24] in detail. In this paper, only
basic experimental investigation involving the PWM methods’
influence is considered.
IX. CONCLUSION
A combined PWM algorithm, which utilizes the proposed
MAZSPWM method at low modulation index and the NSPWM
method at high modulation index, and exhibits seamless tran-
sition between the two methods, is developed. The algorithm
yields low CMV and current, acceptable PWM ripple at the in-
put and output of the inverter, and has no overvoltage problems
unlike AZSPWM1. The performance of the proposed algorithm
is verified via computer simulations and detailed laboratory ex-
periments. Employing the proposed algorithm and including a
small CMI aids in reduction of both the CMV and CMC and
results in a low-noise and reliable inverter drive. The proposed
RCMV methods reduce the CMV significantly (by 50%) and
CMC partially (by 10%–15% rms and 25%–30% peak). A small
CMI further decreases the CMC to negligible levels (by 80%).
Thus, an overall high-performance motor drive with low ripple
and low common-mode noise could be obtained. As future work,
the CMV/CMC frequency spectrum evaluation and comparison
along with the conducted and radiated EMC performance evalu-
ation according to motor drive EMC standards for the proposed
algorithm and various PWM methods will be considered.
2007
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 7, JULY 2011
Ahmet M. Hava (S’91–M’98) was born in Mardin,
Turkey, in 1965. He received the B. S. degree in elec-
trical engineering from Istanbul Technical University,
Istanbul, Turkey, in 1987, and the M. Sc. and Ph.
D. degrees in electrical engineering from the Uni-
versity of Wisconsin, Madison, in 1991 and 1998,
respectively.
In 1995, he was with Rockwell Automation-
Allen Bradley Company, Mequon, WI. From 1997 to
2002, he was with Yaskawa Electric America, Inc.,
Waukegan, IL. Since 2002, he has been with the Elec-
trical and Electronics Engineering Department, Middle East Technical Univer-
sity, Ankara, Turkey, where he is currently an associate professor. His current
research interests include power electronics, motor drives, and power quality.
Emre Ün (S’06) was born in Ankara, Turkey, in 1983.
He received the B. S. and M. S. degrees in electrical
engineering, in 2004 and 2007, respectively, from the
Middle East Technical University, Ankara, Turkey,
where he was a Research Assistant in the Depart-
ment of Electrical and Electronics Engineering from
2004 to 2008.
Since July 2009, he has been with the Defense Sys-
tems Technologies Division, Aselsan, Inc., Ankara,
as a design engineer. His current research interests
include voltage source inverters, pulsewidth modula-
tion (PWM) methods, and common-mode noise and reduction methods in ac
motors.