Itautec A7520 - 6-71-W2400-D03 GP

Preface
Notebook Computer
W241BU/W241BUQ/W240BU/W245BUQ/W248BUQ/
W249BUQ
Service Manual
Preface
I
Schematic Diagrams
Appendix B: Schematic Diagrams

This appendix has circuit diagrams of the W241BU/W241BUQ/W240BU/W245BUQ/W248BUQ/W249BUQ note-
book’s PCB’s. The following table indicates where to find the appropriate schematic diagram.
Diagram - Page Diagram - Page Diagram - Page Table B - 1

System Block Diagram - Page B - 2 HUDSON PCIE/ PCI/ CLOCK/ FCH - Page B - 16 USB/ FAN/ TP/ MULTI CON - Page B - 30 Schematic
Diagrams
ONTARIO MEM & PCIE I/F, AP - Page B - 3 HUDSON GPIO/ USB/ STRAP - Page B - 17 5VS/ 3.3VS/ 1.8VS/ 1.5VS/ 1.1VS - Page B - 31
B.Schematic Diagrams
ONTATIO DISPLAY/ CLK/ MISC - Page B - 4 HUDSON SATA/ DEBUG IO/ SPI - Page B - 18 POWER VDD3/ VDD5 - Page B - 32
ONTARIO POWER & DECOUPLING - Page B - 5 HUDSON POWER DECOUPLING - Page B - 19 Power 1.5V/ 0.75 - Page B - 33
INAGUA DDR3 SO-DIMMS A - Page B - 6 POWERGOOD/ TPM - Page B - 20 Power 1.1V/ 1VS - Page B - 34
INAGUA DDR3 SO-DIMMS B - Page B - 7 LVDS, INVERTER - Page B - 21 Power 1.8VS - Page B - 35
Robson S3 PCIE/ LVDS 1/6 - Page B - 8 HDMI/ CRT - Page B - 22 APU CORE/ NB CORE - Page B - 36

Robson S3 MAIN 2/6 - Page B - 9 CCD/ 3G - Page B - 23 VGA POWER - Page B - 37
Version Note
Robson S3 MEM Interface 3/6 - Page B - 10 Card Reader/ LAN JMC261C - Page B - 24 CHARGER/ DC IN - Page B - 38
The schematic dia-
Robson S3 Straps 4/6 - Page B - 11 MINI PCIE/ SATA HDD/ ODD - Page B - 25 Click Board - Page B - 39 grams in this chapter
Robson S3 Power 5/6 - Page B - 12 AUDIO CODEC ALC261C - Page B - 26 Audio Board/ USB - Page B - 40 are based upon ver-
sion 6-7P-W2405-
Robson S3 Power 6/6 - Page B - 13 USB 3.0 VL800 - Page B - 27 Power Switch & LID Board - Page B - 41 003. If your main-
Robson DDR3 MEM CH-A - Page B - 14 KBC- ITE IT8518 - Page B - 28 EXTERNAL ODD Board - Page B - 42 board (or other
boards) are a later
Robson DDR3 MEM CH-B - Page B - 15 LED/ MDC/ BT - Page B - 29 version, please
check with the Serv-
ice Center for updat-
ed diagrams (if
required).
B - 1
Schematic Diagrams
System Block Diagram

CLICK BOARD
6-71-W2402-D01
W240BU/W250BUQ/W250BAQ System Block Diagram VDD3,VDD5
POWER SWITCH BOARD GPU POWER, VDDC

POWER SWITCH+HOTKEY X 3 A T I RO BS O N AMD FUSION APU MVDDQ,1.8V_REG,1.0V_REG
6-71-E51QS-D02 (S3 TYPE) PCIE*4 Ontario FT1
5V,3V,5VS,3.3VS
AUDIO BOARD 512MB DDR3 41 3-B A LL
1.5VS,1.1VS
USB+EARPHONE+EXT.MIC 19 mm X 19mm B GA
1066MHz
6-71-W2408-D02 S IN GLE C H A NN E L D D R 3
D I SP LA Y P OR T X 2 DDR3 / 1.5V APU_CORE,NB_CORE
EXTERNAL ODD BOARD DDRIII
EXT. ODD D X 11 IGP
SO-DIMM2
6-71-E51QN-D01 4 X 1 P C IE GE N 2 GP P SHEET 6 1.5V,0.75VS(VTT_MEM)
LCD CONNECTOR 1 X 4 U M I-L IN K GE N 1
V GA D A C DDRIII
SO-DIMM1
CRT Connector SHEET 5
1.1V, 1VS
HDMI Conne ctor UMI*4
USB PORT
1.8VS
(USB4) MIC HP
INT SPK R
AMD HUDSON-M1 IN OUT

CHARGER,DC IN
TOUCH PAD SHEET 38
CLICK BOARD 605-BALL
SPI
23mmX23mm BG A
Sheet 1 of 41 32.768 KHz

TPM
(Reserve)
P C IE GE N 1 I/F (4 x 1) Azalia Codec
INT SPKER
EC U SB 2. 0(12) + 1.1 (2) REALTEK

System Block ITE 8518
128pins LQFP LPC
33 MHz S AT AI I (3 P OR TS )
IN T. C LK GE N
ALC269
INT MIC
Diagram 14 *1 4*1 .6m m

BIOS
SPI
A ZA LIA H D AU D I O
GB M A C
24 MHz AZALIA LINK
S PI I/F
INT. K/B LP C I/ F
EC SMBUS
H W M ON ITOR
PCIE 100 MHz
THERMAL SMART SMART
SENSOR BATTERY FAN 32.768KHz
W83L771AWG AC-IN
USB 3.0 3G CARD Mini PCIE JMICRO JMC261C
(Reserve) SOCKET
USB2.0 (USB3) (USB9) (USB2) CARD
LAN
480 Mbps (Optional) WLAN READER 25
MHz
RJ-45 7IN1
SOCKET
USB PORT USB PORT Bluetooth CCD

SATA HDD SATA ODD
(USB0) (USB1) (USB6) (USB5)
SATA I/II 3.0Gb/s
B - 2 System Block Diagram

Schematic Diagrams
ONTARIO MEM & PCIE I/F, AP

ONTARIO MEM & PCIE I/F, AP
5 , 6 M E M_ A D D R [ 1 5 : 0 ] M E M _D A T A [ 6 3 : 0 ] 5 , 6
R 17
U1 E
M EM _A DD R0 M _AD D0 M _D AT A0 B 14 ME M _ DA T A 0
M E M _A DD R1 H1 9 O NT ARI O (2. 0) A 15 ME M _ DA T A 1
M _AD D1 PA RT 1 O F 5 M _D AT A1
M E M _A DD R2 J17 M _AD D2 M _D AT A2 A 17 ME M _ DA T A 2
M E M _A DD R3 H1 8 M _AD D3 M _D AT A3
D 18 ME M _ DA T A 3
M E M _A DD R4 H1 7 A 14 ME M _ DA T A 4
M _AD D4 M _D AT A4
M E M _A DD R5 G1 7 M _AD D5 M _D AT A5
C 14 ME M _ DA T A 5
M E M _A DD R6 H1 5 C 16 ME M _ DA T A 6
M _AD D6 M _D AT A6
M E M _A DD R7 G1 8 D 16 ME M _ DA T A 7
M _AD D7 M _D AT A7
M E M _A DD R8 F1 9 M _AD D8
M E M _A DD R9 E1 9 C 18 ME M _ DA T A 8
M _AD D9 M _D AT A8
M E M _A DD R1 0 T1 9 A 19 ME M _ DA T A 9
M _AD D10 M _D AT A9
M E M _A DD R1 1 F1 7 M _AD D11 M _D ATA 10 B 21 ME M _ DA T A 1 0
M E M _A DD R1 2 E1 8 D 20 ME M _ DA T A 1 1
M _AD D12 M _D ATA 11
M E M _A DD R1 3 W17 M _AD D13 M _D ATA 12 A 18 ME M _ DA T A 1 2
M E M _A DD R1 4 E1 6 B 18 ME M _ DA T A 1 3
M E M _A DD R1 5 G1 5 A 21 ME M _ DA T A 1 4
Sheet 2 of 41
M _D ATA 15 C 20 ME M _ DA T A 1 5
R1 8 M _BA NK0
5 , 6 M E M _B A N K 0 T1 8 C 23
M _BA NK1 M _D ATA 16 ME M _ DA T A 1 6
5 , 6 M E M _B A N K 1 F1 6 D 23 ME M _ DA T A 1 7
M _BA NK2 M _D ATA 17
5 , 6 M E M _B A N K 2 F 23 ME M _ DA T A 1 8
5 , 6 M E M_ D M[ 7 : 0 ] M _D ATA 18 For W250BA Q
ONTARIO MEM &
M EM _D M0 D1 5 M _DM 0 M _D ATA 19
F 22 ME M _ DA T A 1 9
M EM _D M1 B1 9 M _DM 1 M _D ATA 20 C 22 ME M _ DA T A 2 0 U1 A
M EM _D M2 D2 1 M _DM 2 M _D ATA 21 D 22 ME M _ DA T A 2 1 AA6 P _G PP_ RXP 0 P_G PP _TX P0 AB6 C1 * 0. 1u _ 1 0 V _ X7 R _ 04
H2 2 F 20 7 V GA _ R X P 0 Y6 AC6 V G A _ TX P 0 7
M EM _D M3 M _DM 3 M _D ATA 22 ME M _ DA T A 2 2 P _G PP_ RXN 0 P_G PP _TX N0 C2 * 0. 1u _ 1 0 V _ X7 R _ 04 V G A _ TX N 0 7
M EM _D M4 P2 3 F 21 ME M _ DA T A 2 3 7 V GA _ R X N 0
M _DM 4 M _D ATA 23 O N TAR I O ( 2. 0)
PCIE I/F, AP
M EM _D M5 V2 3 AB4 P ART 2O F 5 AB3 C3 * 0. 1u _ 1 0 V _ X7 R _ 04
M _DM 5 7 V GA _ R X P 1 P _G PP_ RXP 1 P_G PP _TX P1 V G A _ TX P 1 7
M EM _D M6 AB2 0 M _DM 6 M _D ATA 24 H 21 ME M _ DA T A 2 4 A C4 P _G PP_ RXN 1 P_G PP _TX N1 AC3 C4 * 0. 1u _ 1 0 V _ X7 R _ 04
7 V GA _ R X N 1 V G A _ TX N 1 7
M EM _D M7 AA1 6 M _DM 7 M _D ATA 25
H 23 ME M _ DA T A 2 5
M _D ATA 26 K 22 ME M _ DA T A 2 6 AA1 P _G PP_ RXP 2 P_G PP _TX P2 Y1 C5 * 0. 1u _ 1 0 V _ X7 R _ 04
7 VG A_ RXP2 VG A_ TXP2 7
A1 6 K 21 ME M _ DA T A 2 7 AA2 Y2 C6 * 0. 1u _ 1 0 V _ X7 R _ 04
PC IE I/F
5 ,6 ME M _ DQ S _ H0 M _DQ S_H 0 M _D ATA 27 7 VG A_ RXN 2 P _G PP_ RXN 2 P_G PP _TX N2 V G A _ T X N2 7
B1 6 M _DQ S_L 0 M _D ATA 28 G 23 ME M _ DA T A 2 8
5 ,6 ME M _ DQ S_ L 0 B2 0 H 20 Y4 V3
ME M _ DA T A 2 9 C7 * 0. 1u _ 1 0 V _ X7 R _ 04
M _DQ S_H 1 M _D ATA 29 P _G PP_ RXP 3 P_G PP _TX P3 VG A_ TXP3 7
5 ,6 ME M _ DQ S _ H1 A2 0 K 20 ME M _ DA T A 3 0 7 VG A_ RXP3 Y3 V4
5 ,6 ME M _ DQ S_ L 1 M _DQ S_L 1 M _D ATA 30 7 VG A_ RXN 3 P _G PP_ RXN 3 P_G PP _TX N3 C8 * 0. 1u _ 1 0 V _ X7 R _ 04 V G A _ T X N3 7
E2 3 K 23 ME M _ DA T A 3 1
5 ,6 ME M _ DQ S _ H2 M _DQ S_H 2 M _D ATA 31
E2 2 M _DQ S_L 2 1 VS ON _Z V D D Y1 4 P _ZV DD _10 P_ ZVS S
AA1 4 ON _ Z V S S R 1 1. 27 K _ 1 % _ 0 4
M EMO RY I/F
5 ,6 ME M _ DQ S_ L 2 J22 N 23 ME M _ DA T A 3 2
5 ,6 ME M _ DQ S _ H3 M _DQ S_H 3 M _D ATA 32
J23 P 21 ME M _ DA T A 3 3 R 2 2 K _ 1% _ 0 4
5 ,6 ME M _ DQ S_ L 3 M _DQ S_L 3 M _D ATA 33
R2 2 M _DQ S_H 4 M _D ATA 34 T2 0 ME M _ DA T A 3 4
5 ,6 ME M _ DQ S _ H4 P2 2 T2 3 ME M _ DA T A 3 5 AA1 2 AB1 2 C9 0 . 1 u _ 10 V _ X 7 R _ 0 4
5 ,6 ME M _ DQ S_ L 4 M _DQ S_L 4 M _D ATA 35 1 5 C _U MI _ P _ R X 0 P _UM I _RX P0 P _UM I _TX P0 C _ U MI _ P _ T X 0 1 5
W22 M _DQ S_H 5 M _D ATA 36 M 20 ME M _ DA T A 3 6 Y1 2 P _UM I _RX N0 P _UM I _TX N0 AC1 2 C1 0 0 . 1 u _ 10 V _ X 7 R _ 0 4
5 ,6 ME M _ DQ S _ H5 1 5 C _U MI _ N _ R X 0 C _ U MI _ N _ TX 0 1 5
V2 2 M _DQ S_L 5 M _D ATA 37 P 20 ME M _ DA T A 3 7
5 ,6 ME M _ DQ S_ L 5
A C2 0 M _DQ S_H 6 M _D ATA 38
R 23 ME M _ DA T A 3 8 AA1 0 P _UM I _RX P1 P _UM I _TX P1
AC1 1 C1 1 0 . 1 u _ 10 V _ X 7 R _ 0 4
5 ,6 ME M _ DQ S _ H6 A C2 1 T2 2 1 5 C _U MI _ P _ R X 1 Y1 0 AB1 1 C _ U MI _ P _ T X 1 1 5
UM I I/F
M _DQ S_L 6 M _D ATA 39 ME M _ DA T A 3 9 P _UM I _RX N1 P _UM I _TX N1 C1 2 0 . 1 u _ 10 V _ X 7 R _ 0 4 C _ U MI _ N _ TX 1 1 5
5 ,6 ME M _ DQ S_ L 6 AB1 6 1 5 C _U MI _ N _ R X 1
5 ,6 ME M _ DQ S _ H7 M _DQ S_H 7
A C1 6 V 20 ME M _ DA T A 4 0 AB1 0 AA8 C1 3 0 . 1 u _ 10 V _ X 7 R _ 0 4
5 ,6 ME M _ DQ S_ L 7 M _DQ S_L 7 M _D ATA 40 1 5 C _U MI _ P _ R X 2 P _UM I _RX P2 P _UM I _TX P2 C _ U MI _ P _ T X 2 1 5
M _D ATA 41
V 21 ME M _ DA T A 4 1 A C1 0 P _UM I _RX N2 P _UM I _TX N2
Y8 C1 4 0 . 1 u _ 10 V _ X 7 R _ 0 4
1 5 C _U MI _ N _ R X 2 C _ U MI _ N _ TX 2 1 5
M1 7 M _C LK_H 0 M _D ATA 42 Y 23 ME M _ DA T A 4 2
5 M E M_ C LK _H 0 M1 6 Y 22 A C7 AB8
M _C LK_L0 M _D ATA 43 ME M _ DA T A 4 3 P _UM I _RX P3 P _UM I _TX P3 C1 5 0 . 1 u _ 10 V _ X 7 R _ 0 4 C _ U MI _ P _ T X 3 1 5
5 M E M_ C LK _L 0 M1 9 T2 1 ME M _ DA T A 4 4 1 5 C _U MI _ P _ R X 3 AB7 AC8
5 M E M_ C LK _H 1 M _C LK_H 1 M _D ATA 44 1 5 C _U MI _ N _ R X 3 P _UM I _RX N3 P _UM I _TX N3 C1 6 0 . 1 u _ 10 V _ X 7 R _ 0 4 C _ U MI _ N _ TX 3 1 5
M1 8 M _C LK_L1 M _D ATA 45 U 23 ME M _ DA T A 4 5
5 M E M_ C LK _L 1 N1 8 W 23
M _C LK_H 2 M _D ATA 46 ME M _ DA T A 4 6 O N T A R I O_ A P U
6 M E M_ C LK _H 2 N1 9 Y 21 ME M _ DA T A 4 7
6 M E M_ C LK _L 2 M _C LK_L2 M _D ATA 47
L18
6 M E M_ C LK _H 3 M _C LK_H 3
L17 Y 20 ME M _ DA T A 4 8
6 M E M_ C LK _L 3
M _C LK_L3 M _D ATA 48
M _D ATA 49
A B2 2 ME M _ DA T A 4 9 ROUTE A- LIN K D IFF PAI R @ 8 5 OHM +/ - 10 %
L23 A C1 9 ME M _ DA T A 5 0
5 , 6 M E M_ R E S E T # M _RE SET _L M _D ATA 50
N1 7 M _EV ENT _L M _D ATA 51 A A1 8 ME M _ DA T A 5 1
5 , 6 M E M_ E V E N T # A A2 3 ME M _ DA T A 5 2 C8 4 2 C 84 3 C 844
M _D ATA 52
M _D ATA 53 A A2 0 ME M _ DA T A 5 3
F1 5 M _CK E0 M _D ATA 54
A B1 9 ME M _ DA T A 5 4 1 0 u_ 6 . 3 V _ X 5 R _ 0 6 0 . 1u _ 1 0 V _ X 7R _ 04
5, 6 ME M _ C K E 0
E1 5 M _CK E1 M _D ATA 55 Y 18 ME M _ DA T A 5 5 1 0 0 0 p_ 5 0 V _ X 7R _ 0 4
5, 6 ME M _ C K E 1
M _D ATA 56 A C1 7 ME M _ DA T A 5 6
Y 16 ME M _ DA T A 5 7
M _D ATA 57
W19 M 0_O DT0 M _D ATA 58 A B1 4 ME M _ DA T A 5 8 1 .5 V
5 D I MM 0 _O D T 0 V1 5 A C1 4 ME M _ DA T A 5 9
5 D I MM 0 _O D T 1 M 0_O DT1 M _D ATA 59
U1 9 M 1_O DT0 M _D ATA 60 A C1 8 ME M _ DA T A 6 0
6 D I MM 1 _O D T 0 W15 A B1 8 ME M _ DA T A 6 1 V T T _M E M
6 D I MM 1 _O D T 1 M 1_O DT1 M _D ATA 61
M _D ATA 62
A B1 5 ME M _ DA T A 6 2 R 67 8 Analog Thermal Sensor
T1 7 M 0_CS _L0 M _D ATA 63 A C1 5 ME M _ DA T A 6 3 1 K _ 1 % _0 4
5 D I MM 0 _C S # 0 W16 3. 3V
5 D I MM 0 _C S # 1 M 0_CS _L1
U1 7 R 67 9 * 0 _0 4 Q1 5
6 D I MM 1 _C S # 0 M 1_CS _L0
V1 6 M 23 R 68 0 0_04 2 1
6 D I MM 1 _C S # 1
M 1_CS _L1 M _V RE F
VC C OU T 1:2 (4mils:8mils) T H E R M _ V OL T 2 7
U1 8 1 .5 V
5, 6 ME M _ R A S # M _RA S_L
V1 9 M _CA S_L R 68 1 C 3 65 3 C3 6 4
5, 6 ME M _ C A S # V1 7 M 2 2 M E M _Z V D D I O R 6 3 9. 2_ 1 % _ 0 4 1 K _ 1 % _0 4 G ND
5, 6 ME M _ W E # M _WE_L M _Z VDD I O_M E M _S
0 . 1 u _ 10 V _ X 5 R _ 0 4 G 7 11 S T 9 U 0 . 1u _ 1 0 V _ X 5R _ 0 4
O N TA R I O _A P U 1
R6 c onnec tion to VD DIO_SU S s hould 3
Not e: Open th e sod lermas k for Vi as on Mem int erfac e
be direc tly t o the pla n e with ou t a long tr ac e
2
PLACE NEAR U1
ONTARIO MEM & PCIE I/F, AP B - 3

Schematic Diagrams
ONTATIO DISPLAY/ CLK/ MISC

1 .8 V S ONTARIO DISPLAY/CLK/MISC
R 11 1 K_ 0 4 C P U_ S V C
R 12 1 K_ 0 4 C P U_ S V D
R 14 3 0 0_ 1 % _ 0 4 APU _ PW R G D
U 1B
ANAL OG/DISPLAY/MISC
A8
H3
3 .3 V TD P1 _TX P0 DP_ ZV SS
ON D P _ C A LR R 21 1 5 0 _ 1% _ 0 4
21 H D M I B _ D 2B P B8
H 2 G2
21 H D M I B _ D 2B N TD P1 _TX N0
R1 5 *1 K _ 0 4 ON _ B L O N R 16 0_04
DPM ISC
DP_ BLO N BL O N 20
R2 2 1K _ 04 APU _ TH E R MT R I P # B9 ON _ D I GO N R 5 98 0_04
21 H D M I B _ D 1B P TD P1 _TX P1 D P_D IG O N N B_ EN AVD D 2 0
APU _ TA L E R T # A9 H1 ON _ V A R Y
DISPL AYPORT 1
R1 7 1K _ 04 TD P1 _TX N1 DP _VA RY _BL
3 .3 V S R1 9 1K _ 04 P RO C HO T # 21 H D M I B _ D 1B N
R2 4 1K _ 04 APU _ SIC D1 0 O N_ BL O N R 5 91 1 0 0 K_ 0 4
21 H D M I B _ D 0B P TD P1 _TX P2
R2 0 1K _ 04 APU _ SID C1 0 TD P1 _TX N2 TD P1_ AU XP
B2 H D MI _ D D C _ C LK O N _ D I GO N R 5 92 1 0 0 K_ 0 4
21 H D M I B _ D 0B N C2 H D MI _ D D C _ D A T A H D MI _ D D C _ C LK 2 1 O N_ VA R Y
TD P1_ AU XN R 5 93 1 0 0 K_ 0 4
A1 0 H D MI _ D D C _ D A T A 2 1
HD M I 2 1 H D MI B _ C L K B P B1 0
TD P1 _TX P3
C1
2 1 H D MI B _ C L K B N TD P1 _TX N3 T DP 1_H PD P OR T C _ H P D 21
R2 5 0_ 0 4 P R OC H OT # B5 LT DP 0_TX P0 LTD P0_ AU XP
A3 LV D S _ D D C _ C LK
1 7 S B _ P RO C HO T # 20 L V D S -L 2P LV D S _ D D C _ C LK 2 0
A5 LT DP 0_TX N0 LTD P0_ AU XN
B3 LV D S _ D D C _ D A T A
20 L V D S -L 2N LV D S _ D D C _ D A T A 2 0
R 60 *1 0 0 K _ 0 4
D 6 D3 5V S
LT DP 0_TX P1 LT DP 0_H PD R 62 *1 0 0 K _ 0 4
20 L V D S -L 1P C 6
DISPL AYPORT 0
20 L V D S -L 1N LT DP 0_TX N1
C1 2
1 .8 V S DAC _R ED D A C_ R E D 21
A6 LT DP 0_TX P2 D AC_ RE DB
D1 3 R2 7 1 5 0_ 1 % _ 0 4
20 L V D S -L 0P B6 A1 2
LT DP 0_TX N2 D AC _G RE EN D A C_ G R E E N 21
20 L V D S -L 0N B1 2 R2 8 1 5 0_ 1 % _ 0 4
DA C_G R EE NB
D 8 A1 3
R 13
LVD S 20 L V D S -L C L K P C 8
LT DP 0_TX P3
LT DP 0_TX N3
D AC _BL UE
DA C_B LU EB
B1 3 R2 9 1 5 0_ 1 % _ 0 4
D A C _ B LU E 2 1
20 L V D S -L C L K N
3 0 0_ 1 % _ 0 4
V2 E1
VGADAC
15 A P U _C L K P C LK N
I _H DA C_H SY NC DA C_ H S Y NC 21
L DT _ R S T # V1 E2
15 A P U _C L K N C LK N
I _L DA C_V SY NC DA C_ V S Y N C 21
Sheet 3 of 41 D 2 F2
CLK
15 DIS P _ CL K P D I SP _CLK I N_H D AC _SC L DA C_ D DC A C L K 2 1
C 84 0 D 1 D4
15 DIS P _ CL K N D I SP _CLK I N_L DAC _S DA DA C _ DD C A DA T A 2 1
0 . 1 u _1 6 V _ Y 5 V _ 0 4 R 30 R 33 0_04 APU _ SIC
J1 D1 2 DA C _ RS E T APU _ SID
ONTATIO 35
35
CP U_ S V C
C PU _ SVD
J2
S VC
SV D
D AC_ ZV SS
T ES T4
R1 A P U _T H E R MD A
4 9 9 _1 % _ 0 4
R3 1 *0 _ 0 4
R 34 0_04
S MD _ C P U _ T H E R M 1 6 ,1 7 ,2 7
SER
A P U _S I C P3 SIC T ES T5
R2 A P U _T H E R MD C R3 2 *0 _ 0 4
DISPLAY/ CLK/
16 A P U_ S IC A P U _S I D P4 R6 S MC _ C P U _ T H E R M 1 6 ,1 7 ,2 7
16 A P U_ S ID SI D T ES T6
T ES T14
T5
L D T R S T_ R L D T_ R S T # R 35 0_04 L DT R ST _ R T3 RE SE T_L T ES T15
E4 A P U _B P 1 _ T S T U P D _ U S C L K 1 R 58 1 K_ 0 4
L D T P W R GD _ R 15 L D T _R S T # A P U_ P W RG D L DT P W RG D_ R T4 K4
R 36 0_04
MISC
PW RO K T ES T16
1 5, 35 A P U _P W R GD L1
T ES T17
P R OC H O T # U 1 L2 APU _T E S T 1 8_ P L L T E S T 1 R3 7 1 K _0 4
CTRL
15 PRO C HO T # PR O CH O T_L T ES T18
C 21 C 22 0_04 A P U _ TH E R MT R I P # U 2 TH ER M TR IP _L T ES T19
M2 APU _T E S T 1 9_ P L L T E S T 0 R3 9 1 K _0 4 1. 8V S
1 6 CP U _ T HE RM T RIP # T2 K1 APU _T E S T 2 5_ H _ B Y P A S S C L K
1 7 ,2 7 AP U_ T A L E R T # R 38 AL ER T_L TE ST 25_H R4 0 5 1 0 _ 1 % _ 04
* 1 50 p F _ N P O _ 50 V _ 0 4 0 2* 1 5 0p F _ N P O _ 50 V _0 4 0 2 K2 APU _T E S T 2 5_ L _ B Y P A S S C L K R4 1 5 1 0 _ 1 % _ 04
TEST
T ES T25_L
A P U _ TD I N 2 L5
TD I TE ST 28_H
A P U _ TD O N 1 TD O T ES T28_L
M5
A P U _ TC K P1 T CK T ES T31
M2 1
A P U _ TM S P2 J1 8 A P U _T E S T 3 3_ H _ M_ C L K T S T _ H C 23 0 . 1 u_ 1 6 V _ Y 5 V _ 0 4 R 42 5 1 _ 04
J TAG
TM S TE ST 33_H
A P U _ TR S T # M4 TR ST _L T ES T33_L
J1 9 A P U _T E S T 3 3_ L _ M _C L K T S T _ L C 24 0 . 1 u_ 1 6 V _ Y 5 V _ 0 4 R 43 5 1 _ 04
DB RD Y M3 DB RD Y TE ST 34_H
U1 5
DB RE Q # M1 DB RE Q _L T ES T34_L
T1 5
H4 A P U _T E S T 3 5 R 44 * 1K _0 4
T ES T35
R 45 *1 0 m i l _s h o rt _ 0 4 V D D C R _ N B _ S E N S E F4 VD DC R_N B_ SE NS E T ES T36
N5 A P U _T E S T 3 6
35 CP U _ V D DN B _ RU N _ F B _ H
3 5 C P U _V D D 0 _ R U N _ F B _ H R 46 *1 0 m i l _s h o rt _ 0 4 V D D C R _ C P U _S E N S E G 1 VD DC R_C PU _S EN SE T ES T37
R5
VD DIO _ S U S _ S E N SE F 3 VD DI O _M EM _S _S ENS E
R 48 *1 0 m i l _s h o rt _ 0 4 V S S _ S E N S E F1 VS S_ SEN SE
3 5 C P U _V D D 0 _ R U N _ F B _ L K3
3 5 C P U _V D D N B _ R U N _ F B _ L R 49 *1 0 m i l _s h o rt _ 0 4 T ES T38
B4 T1 ON _ D MA A C T I V E # R 50 0_04
RS VD _1 D M AA CT V
I E_L A L LO W _ L D T S T P 1 5
W11 RS VD _2
V5 O NT AR IO ( 2. 0)
RS VD _3
1. 8V S PA RT 3 O F 5
ON T A R I O_ A P U R5 1 R5 6 R5 2
5
U4 4 * 74 A H C 1 G0 8 GW 1 .8 V S
L DT _ R S T # 1 1 K_ 0 4 1 K_ 0 4 1 K_ 0 4 1 .8 VS
4 L DT _ R S T # _ B UF R5 3 * 1 K _ 04
2
3
1. 8V S
5
U4 5 * 74 A H C 1 G0 8 GW
A P U _ P W R GD 1
4 A PU _ P W R G D_ B U F R5 4 * 1 K _ 04
2
Reserve
3
1. 8V S 1 .8 V S H DT + H EA D E R / P L A C E O N T O P 1 .8 VS
J1
R 59 1 2 A P U _ T CK R6 1 1 K_ 0 4
3 CP U_ VD DI O C PU _TC K 4 A P U _ T MS R6 3 1 K_ 0 4
5 G ND CP U_T M S 6 A P U _ T DI
1 K_ 0 4 G ND CP U_ TD I
R6 4 1 K_ 0 4
7 8 A P U _ T DO
G ND CP U_T DO
A P U _ T RS T # R 65 * 0 _0 4 H D T _ T R S T # 9 10 A PU _ P W R G D_ B U F
11 CP U_ TR ST_ L CP U_P WRO K _BU F 12
R 66 * 1 0K _ 04 L D T _ R S T # _B U F
13 CP U_ DB RDY 3 C PU _R ST_ L_BU F 14 D B RD Y
R 67 * 1 0K _ 04 CP U_ DB RDY 2 C PU _DB RD Y0
R 68 * 1 0K _ 04 15 16 D B R E Q# R6 9 3 0 0_ 1 % _ 0 4
17 CP U_ DB RDY 1 CP U_D BR EQ _L 18 J 1 08 _ P L L T S T 0 R7 0 *0 _ 0 4 A P U _ T E S T 1 9 _P L LT E S T 0
19 G ND CP U_ PLLT ES T0 20 J 1 08 _ P L L T S T 1 R7 1 *0 _ 0 4 A P U _ T E S T 1 8 _P L LT E S T 1
CP U_ VD DI O CP U_ PLLT ES T1
* H D R 10 X 2 - B LU E - V E R T I C A L P L U G
B - 4 ONTATIO DISPLAY/ CLK/ MISC

Schematic Diagrams
ONTARIO POWER & DECOUPLING

ONTARIO POWER & DECOUPLING
1 .8 V S
V D D C R _C P U
U 1C C 30 C 26 C 27 C 28 C 29 C3 1 U 1D
E5 V DD CR _C PU _1 VD D_1 8_1
U 8 A7 V SS _1 O N TA RI O 2
( .0) VS S_50
N1 3
E6 W 8 10 u _ 6 . 3 V _ X 5 R _ 0 6 1 u _ 6 .3 V _ X 5 R_ 0 4 1 u_ 6 . 3 V _ X 5 R _ 04 B7 N2 0
V DD CR _C PU _2 VD D_1 8_2 V SS _2 P AR T 5 O F 5 VS S_51
F5 U 6 1 u_ 6 . 3 V _ X 5 R _ 04 * 1 u _6 . 3 V _X 5 R _ 0 4 0. 1u _ 1 0 V _ X 5 R _ 0 4 B1 1 N2 2
V DD CR _C PU _3 VD D_1 8_3 V SS _3 VS S_52
F7 V DD CR _C PU _4 VD D_1 8_4 U 9 B1 7 V SS _4 VS S_53 P1 0
G6 V DD CR _C PU _5 VD D_1 8_5
W 6 B2 2 V SS _5 VS S_54
P1 4
G8 T7 C4 R4
V DD CR _C PU _6 VD D_1 8_6 V SS _6 VS S_55
H5 V DD CR _C PU _7 VD D_1 8_7
V 7 C 869 C 87 1 C 870 D5 V SS _7 VS S_56
R7
H7 V DD CR _C PU _8
D7 V SS _8 VS S_57
R2 0
J6 V DD CR _C PU _9 *1 0 u _ 6 . 3 V _ X 5R _ 0 6 *1 0 u _ 6 . 3 V _ X 5R _ 0 6 D9 V SS _9 VS S_58 T6
J8 * 1 0u _ 6 . 3 V _ X 5 R _0 6 D1 1 T9
V DD CR _C PU _10 V SS _10 VS S_59
L7 V DD CR _C PU _11 D1 4 V SS _11 VS S_60 T1 1
M6 V DD CR _C PU _12
B1 5 V SS _12 VS S_61
T1 3
M8 V DD CR _C PU _13 D1 7 V SS _13 VS S_62 U4
N7 D1 9 U5
V DD CR _C PU _14 V SS _14 VS S_63
V D D C R _N B R8 V DD CR _C PU _15 V D DA N _ 1 8 _ DA C E7 V SS _15 VS S_64
U7
1 .8 VS E9 V SS _16 VS S_65
U1 2
E1 2 V SS _17 VS S_66
U2 0
E8 W 9 R 73 0 _0 4 E2 0 U2 2
V DD CR _N B_1 V DD _18_D AC V SS _18 VS S_67
E1 1 V DD CR _N B_2
F8 V SS _19 VS S_68
V8
E1 3 F1 1 V9
V DD CR _N B_3 V SS _20 VS S_69
F9 V DD CR _N B_4
C 872 C 32 C 33 F1 3 V SS _21 VS S_70
V1 1
ON TA RI O ( 2.0 )
F12 G4 V1 3
P AR T 4 O F 5
G1 1 V DD CR _N B_6 1 0 u _ 6 . 3 V _ X 5R _ 0 6 G5 V SS _23 VS S_72
W1
G1 3 V DD CR _N B_7 *1 0 u _ 6 . 3 V _ X 5R _ 0 6 1 u _ 6 .3 V _ X 5 R_ 0 4 G7 V SS _24 VS S_73
W2
H9 V DD CR _N B_8 G9 V SS _25 VS S_74 W4
GR O UN D
H1 2 G1 2 W5
K1 1 V DD CR _N B_10 V DD P L _ 1 0 1V S G2 0 V SS _27 VS S_76 W7
Sheet 4 of 41
K1 3 V DD CR _N B_11
G2 2 V SS _28 VS S_77
W12
L10 U 11 L63 . H6 W20
P OW ER
V DD CR _N B_12 V DD PL _10 V SS _29 VS S_78
L12 H1 1 Y5
L14 V DD CR _N B_14 H C B 1 6 0 8 K F -1 2 1 T 2 5 H1 3 V SS _31 VS S_80
Y7
M1 1
M1 2
M1 3
V DD CR _N B_15
V DD CR _N B_16
V DD CR _N B_17
C 34 C 35
1 0u _ 6 . 3 V _ X 5 R _0 6
C 36
0 .1 u _ 1 0 V_ X 5 R_ 0 4
J4
J5
J7
V SS _32
V SS _33
V SS _34
VS S_81
VS S_82
VS S_83
Y9
Y1 1
Y1 3
ONTARIO POWER
N1 0 1 u _ 6. 3V _ X5 R _ 0 4 J20 Y1 5
& DECOUPLING
N1 2 V DD CR _N B_19
K1 0 V SS _36 VS S_85
Y1 7
N1 4 V DD CR _N B_20 K1 4 V SS _37 VS S_86 Y1 9
1 .5 V P1 1 1 VS L4 AA4
P1 3 V DD CR _N B_22 VD D_1 0_1 U 13 L6 V SS _39 VS S_88 AA2 2
VD D_1 0_2
W 13 L8 V SS _40 VS S_89
AB2
VD D_1 0_3
V 12 L11 V SS _41 VS S_90
AB5
G1 6 T1 2 L13 AB9
V DD I O _M EM _S _1 VD D_1 0_4 V SS _42 VS S_91
G1 9 V DD I O _M EM _S _2 C 37 C 38 C 39 C4 0 C 41 C 42 L20 V SS _43 VS S_92
AB1 3
E1 7 V DD I O _M EM _S _3 L22 V SS _44 VS S_93 AB1 7
J16 V DD I O _M EM _S _4
1 0u _ 6 . 3 V _ X 5 R _0 6 1 u _ 6 .3 V _ X5 R_ 0 4 0 . 1 u _1 0 V _ X 5 R _ 04 M7 V SS _45 VS S_94
AB2 1
L16 1 0 u _ 6 .3 V _ X 5 R_ 0 6 1 u _ 6 .3 V _ X 5 R_ 0 4 0 .1 u _ 1 0 V _ X 5 R_ 0 4 N4 AC 5
V DD I O _M EM _S _5 V SS _46 VS S_95
L19 V DD I O _M EM _S _6
N6 V SS _47 VS S_96
AC 9
N1 6 V DD I O _M EM _S _7
N8 V SS _48 VS S_97
AC 1 3
R1 6 V DD I O _M EM _S _8
N1 1 V SS _49 V SS BG _D AC
A1 1
R1 9 3 .3 V S C8 7 3 C 874 C 875
V DD I O _M EM _S _9
W18 V DD I O _M EM _S _10
U1 6 V DD I O _M EM _S _11 V DD _33
A 4 *1 0 u _ 6 . 3 V _ X 5 R _ 0 6 * 1 0 u _6 . 3 V _X 5 R _ 0 6 O N TA R I O _ A P U
*1 0 u _ 6 . 3 V _ X 5R _ 0 6
O NT A RIO _ A P U C 43
V D D CR _ CP U 1 u _ 6 .3 V _ X 5 R_ 0 4
1 .5 V
C 44 C 45 C4 6 C 47 C 48 C 49 C5 0
1 0 u _ 6 .3 V _ X 5 R_ 0 6 1 0 u _6 . 3 V _X 5 R _ 0 6 1 0 u _ 6 .3 V _ X 5 R_ 0 6 1 0 u _6 . 3 V _X 5 R _ 0 6 C5 1 C 52 C5 3 C 54
1 0 u _ 6 . 3 V _ X 5R _ 0 6 1 0u _ 6 . 3 V _ X 5 R _0 6 1 0 u _ 6 . 3 V _ X 5R _ 0 6
10 u _ 6 . 3 V _ X 5 R _ 0 6 *2 2 u _ 6 . 3 V _ X 5 R _ 0 8
1 0 u _ 6 .3 V _ X 5 R_ 0 6 *2 2 u _ 6 . 3 V _ X 5R _ 0 8
C 55 C 56 C5 7 C 58 C 59 C 60 C6 1 C 62 C 63
1 u _ 6 .3 V _ X5 R_ 0 4 1 u _ 6. 3V _ X5 R _ 0 4 0 . 1 u _ 10 V _X 5 R _ 0 4 C6 4 C 65 C6 6
1 u _ 6 .3 V _ X 5 R_ 0 4
0. 1u _ 1 0 V _ X 5 R _ 0 4
1 u _ 6 .3 V _ X 5 R_ 0 4 0 . 1 u _ 1 0 V _ X 5R _ 0 4
0. 1u _ 1 0 V _ X 5 R _ 0 4
0 . 1 u_ 1 0 V _ X 5 R _0 4
EMC C APS
0 .1 u _ 1 0 V _ X 5 R_ 0 4 * 0 . 1 u _1 0 V _ X 7 R _ 04
1 .5 V V D DC R _ CP U V D D CR _ NB 1. 5V 0 .1 u _ 1 0 V _ X 5 R_ 0 4
V DD C R_ N B
C 67 C 68 C6 9 C 70 C 71 C7 2 C 73 C7 4
1 80 P _5 0 V _ N P O _ 0 4 1 8 0 P _ 5 0V _ N P O _ 0 4 1 8 0 P _ 5 0 V _ N P O_ 0 4 0 .1 u _ 1 0 V _ X 5 R_ 0 4
1 8 0 P _ 5 0 V _ N P O _0 4 1 80 P _5 0 V _ N P O _ 0 4 1 8 0P _ 50 V _N P O _ 0 4 * 0. 1u _ 1 0 V _ X 7 R _ 0 4 C8 0 C 81 C8 2 C 83
C 75 C 76 C7 7 C 78 C 79
1 u _ 6. 3V _ X5 R _ 0 4 1 u _ 6. 3V _ X5 R _ 0 4
1 0 u _ 6 .3 V _ X 5 R_ 0 6 1 0 u _6 . 3 V _X 5 R _ 0 6 1 0 u _ 6 .3 V _ X 5 R_ 0 6 3. 3V S 1 u _6 . 3 V _X 5 R _ 0 4 *1 u _ 6 . 3 V _ X 5 R _ 0 4
1 0 u _ 6 .3 V _ X 5 R_ 0 6 1 0u _ 6 . 3 V _ X 5 R _0 6 1 .8 VS V D DA N_ 1 8 _ DA C 1 VS V D D P L _ 10
C 84 C8 5 C8 6 C8 7 C 88
1 8 0 P _ 5 0 V _ N P O _0 4 1 8 0 P _ 5 0V _ N P O _ 0 4 1 8 0 P _ 5 0V _ N P O _ 0 4 1 8 0 P _ 5 0 V _ N P O_ 0 4 0 .1 u _ 1 0 V _ X5 R_ 0 4
C 89 C 90 C9 1 C 92 C 93 C 94 C9 5 C 96 C 97
1 u _ 6 .3 V _ X5 R_ 0 4 1 u _ 6. 3V _ X5 R _ 0 4 1 u _ 6 .3 V _ X 5 R_ 0 4 0 . 1 u _ 10 V _X 5 R _ 0 4 0. 1u _ 1 0 V _ X 5 R _ 0 4
1 u _ 6 .3 V _ X 5 R_ 0 4 1 u _ 6 .3 V _ X 5 R_ 0 4 0 . 1 u _ 1 0 V _ X 5R _ 0 4 0 . 1 u_ 1 0 V _ X 5 R _0 4
ONTARIO POWER & DECOUPLING B - 5

Schematic Diagrams
INAGUA DDR3 SO-DIMMS A

SO -D IMM A INAGUA DDR3 SO-DIMMS A
2,6 MEM_ADDR[15:0] MEM_DAT

A[63:0] 2,6
JDIMM1A
MEM_
ADDR0 98 5 MEM_DATA0
MEM_
ADDR1 97 A0 DQ0 7 MEM_DATA1
MEM_
MEM_
MEM_
91 A4 DQ4 6
MEM_
ADDR5 MEM_DATA5
MEM_
ADDR6 90 A5 DQ5 16 MEM_DATA6 JDIMM1B
MEM_
MEM_
MEM_
ADDR9 85 A8 DQ8 23 MEM_DATA9 1.5V
MEM_
MEM_
ADDR11 84 A10/AP DQ10 35 MEM_DATA11 75 44
83 A11 DQ11 22 76 VDD1 VSS16 48
MEM_
ADDR12 MEM_DATA12
MEM_
ADDR13 119 A12/BC# DQ12 24 MEM_DATA13 81 VDD2 VSS17 49
MEM_
ADDR14 80 A13 DQ13 34 MEM_DATA14 82 VDD3 VSS18 54
MEM_
ADDR15 78 A14 DQ14 36 MEM_DATA15 87 VDD4 VSS19 55
A15 DQ15 39 MEM_DATA16 88 VDD5 VSS20 60
109 DQ16 41 MEM_DATA17 93 VDD6 VSS21 61
2,6 MEM_BANK0 108 BA0 DQ17 51 94 VDD7 VSS22 65
MEM_DATA18
2,6 MEM_BANK1
79 BA1 DQ18 53 MEM_DATA19 3.3VS 99 VDD8 VSS23 66

2,6 MEM_BANK2 114 BA2 DQ19 40 100 VDD9 VSS24 71
MEM_DATA20
2 DIMM0_CS#0 121 S0# DQ20 42 MEM_DATA21 20mils 105 VDD10 VSS25 72
2 DIMM0_CS#1 101 S1# DQ21 50 MEM_DATA22 106 VDD11 VSS26 12
7
2 M EM_CLK_H0 103 CK0 DQ22 52 MEM_DATA23 111 VDD12 VSS27 12
8
C9
8 C99
2 M EM_CLK_L0 102 CK0# DQ23 57 MEM_DATA24 112 VDD13 VSS28 13
3
2 M EM_CLK_H1 CK1 DQ24 VDD14 VSS29
104 59 MEM_DATA25 1u_6.3V_X5R_04 117 13
4
2 M EM_CLK_L1 73 CK1# DQ25 67 118 VDD15 VSS30 13
8
MEM_DATA26 0.1u_
16V_Y5V_
04
2,6 MEM_CKE0
Sheet 5 of 41
74 CKE0 DQ26 69 MEM_DATA27 123 VDD16 VSS31 13
9
2,6 MEM_CKE1 115 CKE1 DQ27 56 124 VDD17 VSS32 14
4
MEM_DATA28
2,6 MEM_CAS# 110 CAS# DQ28 58 MEM_DATA29 VDD18 VSS33 14
5
2,6 MEM_RAS# 113 RAS# DQ29 68 MEM_DATA30 199 VSS34 15
0
INAGUA DDR3 SO- 2,6 MEM_WE# 197

201
202
WE#
SA0
SA1
DQ30
DQ31
DQ32
70
12
13
9
1
MEM_DATA31
MEM_DATA32
MEM_DATA33
1.5V 77
122
VDDSPD
NC1
VSS35
VSS36
VSS37
15
1
15
5
15
6
6,10,16 SCLK0
DIMMS A
200 SCL DQ33 141 MEM_DATA34 R75 1K_0
4 125 NC2 VSS38 16
1
6,10,16 SDATA0 SDA DQ34 143 NCTEST VSS39 16
2
MEM_DATA35
116 DQ35 130 198 VSS40 16
7
MEM_DATA36
2 DIMM0_ODT0 120 ODT0 DQ36 132 MEM_DATA37 2,6 MEM_EVENT# 30 EVENT# VSS41 16
8
2 DIMM0_ODT1 ODT1 DQ37 140 MEM_DATA38 2,6 MEM_RESET# RESET# VSS42 17
2
2,6 MEM_DM[7:0] MEM_DM0 11 DQ38 142 MEM_DATA39 VSS43 17
3
MEM_DM1 28 DM0 DQ39 147 MEM_DATA40 MVREF_DIMM0 1 VSS44 17
8
MEM_DM2 46 DM1 DQ40 149 MEM_DATA41 126 VREF_DQ VSS45 17
9
MEM_DM3 63 DM2 DQ41 157 MEM_DATA42 VREF_CA VSS46 18
4
136 DM3 DQ42 159 VSS47 18
5
MEM_DM4 MEM_DATA43 C100 C101 C102
MEM_DM5 153 DM4 DQ43 146 MEM_DATA44 2 VSS48 18
9
MEM_DM6 170 DM5 DQ44 148 MEM_DATA45 3 VSS1 VSS49 19
0
1u_6.3V_X5R_04 1000p_50V_X7R_0
4
5
0.1u_10V_X7R_04
DM7 DQ46 160 MEM_DATA47 9 VSS3 VSS51 19
6
12 DQ47 163 MEM_DATA48 13 VSS4 VSS52
2,6 MEM_DQS_H0 29 DQS0 DQ48 165 14 VSS5
MEM_DATA49
MEM_DATA50
2,6 MEM_DQS_H2 64 DQS2 DQ50 177 20 VSS7 VTT_MEM
MEM_DATA51
2,6 MEM_DQS_H3 137 DQS3 DQ51 164 MEM_DATA52 25 VSS8
2,6 MEM_DQS_H4 154 DQS4 DQ52 166 MEM_DATA53 26 VSS9 20
3
2,6 MEM_DQS_H5 171 DQS5 DQ53 174 MEM_DATA54 31 VSS10 VTT1 20
4
2,6 MEM_DQS_H6 DQS6 DQ54 VSS11 VTT2
188 176 MEM_DATA55 32
2,6 MEM_DQS_H7 DQS7 DQ55 VSS12
181 MEM_DATA56 37 GND1
10 DQ56 183 MEM_DATA57 38 VSS13 G1 GND2
2,6 MEM_DQS_L0 27 DQS0# DQ57 191 43 VSS14 G2
MEM_DATA58
2,6 MEM_DQS_L1 45 DQS1# DQ58 193 VSS15
MEM_DATA59
2,6 MEM_DQS_L2 62 DQS2# DQ59 180 MEM_DATA60 DDRRK-20401- TR4B
2,6 MEM_DQS_L3 135 DQS3# DQ60 182 MEM_DATA61
2,6 MEM_DQS_L5 DQS5# DQ62
169 194 MEM_DATA63
2,6 MEM_DQS_L6 186 DQS6# DQ63
2,6 MEM_DQS_L7 DQS7#
DDRRK-2040
1- T
R4B
(REV)4.0mm C LOS E TO S O- DI M M A
1.5V R76 1K_1%_04 MVREF_DIMM0

1.5V
R77 C103
+ C104 C105 C106 C107 C108 C109 C110 C111 C11

2 C113 1
K_1%_04 0.1u_10V_X5R_04
+
*150u_4V_B_A *220u_4V_V_A 10u_
10V_Y5V_
08 10u_
10V_Y5V_
08 1u_6
. 3V_X5R_04 1u_6
. 3V_X5R_04
10u_
10V_Y5V_
08 1u_6
. 3V_X5R_04 1u_6
. 3V_X5R_04 1u_6
. 3V_X5R_04
1.5V VTT_MEM
C114 C115 C116 C117 C118 C119 C120 C121 C122 C123 C124 C125 C126 C127 C128
0.1u_16V_Y5V_04 0.1u_16V_Y5V_04 0.1u_16

V_Y5V_04 0.1u_16
V_Y5V_04 0.1u_16
V_Y5V_0
4 10u_10V_Y5V_08 1u_6.3V_X5R_04 1u_6.3V_X5R_04
0.1u_16V_Y5V_04 0.1u_16
V_Y5V_04 0.1u_16
V_Y5V_04 0.1u_16
V_Y5V_04 0.1u_16
V_Y5V_0
4 1u_6.3V_X5R_04 1u_6.3V_X5R_04
B - 6 INAGUA DDR3 SO-DIMMS A

Schematic Diagrams
INAGUA DDR3 SO-DIMMS B
S O-D IMM B INA GUA DDR3 S O-DIMMS B
2,5 MEM_ADDR[15:0] MEM_DATA[63

: 0] 2,5
JDIMM2A
MEM_ADDR0 98 5 MEM_DATA0
MEM_ADDR1 97 A0 DQ0 7 MEM_DATA1
90 A5 DQ5 16
MEM_ADDR6 MEM_DATA6 JDIMM2
B
MEM_ADDR9 85 A8 DQ8 23 MEM_DATA9 1.5V
MEM_ADDR11 84 A10/AP DQ10 35 MEM_DATA11 75 44
83 A11 DQ11 22 76 VDD1 VSS16 48
MEM_ADDR12 MEM_DATA12
MEM_ADDR13 119 A12/BC# DQ12 24 MEM_DATA13 81 VDD2 VSS17 49
MEM_ADDR14 80 A13 DQ13 34 MEM_DATA14 82 VDD3 VSS18 54
MEM_ADDR15 78 A14 DQ14 36 MEM_DATA15 87 VDD4 VSS19 55
A15 DQ15 39 MEM_DATA16 88 VDD5 VSS20 60
109 DQ16 41 93 VDD6 VSS21 61
MEM_DATA17
2,5 MEM_BANK0 108 BA0 DQ17 51 MEM_DATA18 94 VDD7 VSS22 65
3. 3
VS
2 DIMM1_CS#0 20mils
Sheet 6 of 41
121 S0# DQ20 42 MEM_DATA21 105 VDD10 VSS25 72
2 DIMM1_CS#1 101 S1# DQ21 50 106 VDD11 VSS26 127
MEM_DATA22
2 M EM_CLK_H2 103 CK0 DQ22 52 111 VDD12 VSS27 128
MEM_DATA23 C129 C130
2 M EM_CLK_L2 102 CK0# DQ23 57 MEM_DATA24 112 VDD13 VSS28 133
2 M
2 M
EM
EM
_CLK_H3
_CLK_L3
2,5 MEM_CKE0
104
73
74
CK1
CK1#
CKE0
DQ24
DQ25
DQ26
59
67
69
M
M
M
EM
EM
EM
_DATA25
_DATA26
_DATA27
1u_6.3V_X5R_04
0
. 1u
_16V_Y5V_04
117
118
123
VDD14
VDD15
VDD16
VSS29
VSS30
VSS31
134
138
139
INAGUA DDR3 SO-
2,5 MEM_CKE1
DIMMS B
115 CKE1 DQ27 56 MEM_DATA28 124 VDD17 VSS32 144
2,5 MEM_CAS# 110 CAS# DQ28 58 MEM_DATA29 VDD18 VSS33 145
2,5 MEM_RAS# 113 RAS# DQ29 68 MEM_DATA30 199 VSS34 150
2,5 MEM_WE# R7
8 4.7K_04 197 WE# DQ30 70 MEM_DATA31 VDDSPD VSS35 151
3.3VS 201 SA0 DQ31 129 MEM_DATA32 77 VSS36 155
202 SA1 DQ32 131 MEM_DATA33 122 NC1 VSS37 156
5,10,16 SCLK0 200 SCL DQ33 141 125 NC2 VSS38 161
MEM_DATA34
5,10,16 SDATA0 SDA DQ34 143 MEM_DATA35 NCTEST VSS39 162
116 DQ35 130 MEM_DATA36 198 VSS40 167
2 DIMM1_ODT0 120 ODT0 DQ36 132 MEM_DATA37 2,5 MEM_EVENT
# 30 EVENT# VSS41 168
2 DIMM1_ODT1 ODT1 DQ37 140 2,5 MEM_RESET
# RESET# VSS42 172
MEM_DATA38
2,5 MEM_
DM[7:0] 11 DQ38 142 VSS43 173
MEM_DM0 MEM_DATA39
28 DM0 DQ39 147 1 VSS44 178
MEM_DM1 MEM_DATA40 MVREF_DIMM1
MEM_DM2 46 DM1 DQ40 149 MEM_DATA41 126 VREF_DQ VSS45 179
MEM_DM3 63 DM2 DQ41 157 MEM_DATA42 VREF_CA VSS46 184
MEM_DM4 136 DM3 DQ42 159 MEM_DATA43 C131 C132 C133 VSS47 185
MEM_DM5 153 DM4 DQ43 146 MEM_DATA44 2 VSS48 189
170 DM5 DQ44 148 3 VSS1 VSS49 190
MEM_DM6 MEM_DATA45 1u_6.3V_X5R_04 1000p_
50V_
X7R_04
0.1u_10V_X7R_04
DM7 DQ46 160 MEM_DATA47 9 VSS3 VSS51 196
12 DQ47 163 MEM_DATA48 13 VSS4 VSS52
2,5 MEM_DQS_H0 DQS0 DQ48 VSS5
29 165 MEM_DATA49 14
MEM_DATA50
2,5 MEM_DQS_H2 64 DQS2 DQ50 177 20 VSS7 VT
T_MEM
MEM_DATA51
2,5 MEM_DQS_H3 137 DQS3 DQ51 164 MEM_DATA52 25 VSS8
2,5 MEM_DQS_H4 154 DQS4 DQ52 166 MEM_DATA53 26 VSS9 203
2,5 MEM_DQS_H5 DQS5 DQ53 VSS10 VTT1
171 174 MEM_DATA54 31 204
2,5 MEM_DQS_H6 188 DQS6 DQ54 176 32 VSS11 VTT2
MEM_DATA55
2,5 MEM_DQS_H7 DQS7 DQ55 181 37 VSS12 GND1
MEM_DATA56
10 DQ56 183 MEM_DATA57 38 VSS13 G1 GND2
2,5 MEM_DQS_L0 27 DQS0# DQ57 191 MEM_DATA58 43 VSS14 G2
2,5 MEM_DQS_L1 45 DQS1# DQ58 193 MEM_DATA59 VSS15
2,5 MEM_DQS_L2 DQS2# DQ59
62 180 MEM_DATA60 DDRRK- 20
401-TP8
D
2,5 MEM_DQS_L6 186 DQS6# DQ63
2,5 MEM_DQS_L7 DQS7#
DDRRK-204
01-TP8D
(REV)8.0mm C LO SE TO SO - DI MM B
SN:6-86-24204-XXX
1.5V R79 1
K_1%_
04 MVREF_DIMM1
1.5V
R80 C134
C136 C137 C1
38 C139 C140 C14
1 C142 C143 C144 1K_1%_04 0.1u_1
0V_X
5R_04
C135 + +
*220u_4 V_V_A 10u_10V_Y5
V_08 10u_10V_Y5V_08 1u_6.3V_X5R_04 1u_6.3V_X5R_04
560u
_2.5V_
6. 6
*6.6*5. 9 10u_1
0V_Y5V_08 1u_6.3V_X5R_0
4 1u_
6.3V_X
5R_04 1u_6.3V_X5R_04
1.5V VTT_
MEM
C145 C146 C147 C1

48 C149 C150 C15
1 C152 C153 C154 C155 C156 C157 C158 C1
59
0.1u_1
6V_Y5V_04 0.1u_16V_Y5V_04 0.1u
_16V_Y5V_04 0.1u_16V_Y5V_0
4 0.1u_16V_Y5V_04 10u_10V_Y5V_
08 1u_6.3V_X5R_04 1u_6
. 3V_X5R_04
0
.1u_16V_Y5V_04 0.1u_16
V_Y5V_
04 0.1u_16V_Y5V_04 0.1u_
16V_
Y5V_04 0.1u_16V_Y5
V_04 1u_
6. 3
V_X5
R_04 1u_6.3V_X5R_
04
INAGUA DDR3 SO-DIMMS B B - 7

Schematic Diagrams
Robson S3 PCIE/ LVDS 1/6

Sheet 7 of 41
Robson S3 PCIE/
LVDS 1/6
B - 8 Robson S3 PCIE/ LVDS 1/6

Schematic Diagrams
Robson S3 MAIN 2/6
COMPONENTS SH OWN AR E EXAMPLES ONLY

AND NOT NEC ESSAR ILY QUALIFIED
U4 B
VBIOS FLA SH ROM 3. 3V S _GP U
0. 1"~ 0.5 " R 10 1

A F2
TX C A P_ D PA 3 P A F4 TMD S _T XC P 21 512Kbit
Y1 1 T XC A M_D P A 3N TMD S _T XC N 21
*1 0K _0 4
AE9 D VC L K A G3 GP I O8 R 92 * 33_ 04 R OM_S O
L9 D VC N T L_ 0 T X0 P_ D PA 2 P A G5 TMD S _T X0 P 21 U5
N9 D VC N T L_ 1 TX0 M_D P A 2N TMD S _T X0 N 21 GP I O9 S I / A1 6 5 2
D VC N T L_ 2 D VO DP A R 93 * 33_ 04 D Q
A H3
1 8. V _R E G AE8 T X1 P_ D PA 1 P A H1 TMD S _T X1 P 21 GP I O10 R 94 * 33_ 04 S C K /W E b 6
A D9 D VD A T A_ 12 TX1 M_D P A 1N TMD S _T X1 N 21 C
A C1 0 D VD A T A_ 11 A K3 GP I O22 R 95 * 33_ 04 CSb 1
D VD A T A_ 10 T X2 P_ D PA 0 P TMD S _T X2 P 21 S
A D7 A K1 TMD S _T X2 N 21
R 96 R 97 R9 8 R 99 A C8 D VD A T A_ 9 TX2 M_D P A 0N 7
A C7 D VD A T A_ 8 A K5 H OL D
AB9 D VD A T A_ 7 TX C B P_ D PB 3 P A M3 3
ME M_ I D 0 *1 0K _0 4 *1 0K _ 04 AB8 D VD A T A_ 6 T XC B M_D P B 3N 3. 3 VS _G PU W
AB7 D VD A T A_ 5 A K6 8 4
ME M_ I D 1 *10 K_ 04 *1 0K _0 4 D VD A T A_ 4 T X3 P_ D PB 2 P R 1 02 *0_ 04 VCC VSS
M EM_ I D 3 AB4 A M5 C 1 70
ME M_ I D 2 M EM_ I D 2 AB2 D VD A T A_ 3 DP B TX3 M_D P B 2N DNI R 1 00 *0_ 04 *EN 2 5P 0 5-50 GC P
ME M_ I D 3 M EM_ I D 1 Y8 D VD A T A_ 2 A J7 *0 .1 u_ 10 V_ X5 R _0 4
M EM_ I D 0 Y7 D VD A T A_ 1 T X4 P_ D PB 1 P A H6
D VD A T A_ 0 TX4 M_D P B 1N
For Seymour, A K8
D PC _ V D D 18 T X5 P_ D PB 0 P A L7 1 M bit SERIAL EEPRO M is optiona l for Se ym our GDDR5 Des ign
DPC_PVDD is DPC_VDD18 TX5 M_D P B 0N
1. 8 V_ R E G DPC_PVSS and all DPC_VSSR are DP_VSSR 1 M bit SERIAL EEPRO M is r e quire d for Pa r k /Robson GDDR5 De s ign
(1.8 V@1 50m A DPC_ VDD18 )
L 64 W6 DP C
D PC _ VD D 18 V6 D PC _ P VD D
C 1 71 C 17 2 C 1 73 *H C B 16 08 KF -12 1T 25 D PC _ P VS S V4 N OTE: D es ig ns t ha t do not inc lu de a n EEP RO M m us t still pr ovide
*0 . 1u _10 V _X 5R _0 4 *1u _6 . 3V _X 5R _ 04 A C6 T XC C P _D P C 3 P U5
*1 0u _6 . 3V _X 5R _ 06 1 . 0V _R E G D P C _ VD D 1 8 A C5 D PC _ V D D 18 #1 TX C C M_D P C 3N a cc e s s to the RO M inte r fa c e s igna ls for de bug pur pos e s
D PC _ V D D 18 #2 W3
(1 .0 V@1 1 0m A DPC_ VDD1 0 ) D P C _ VD D 1 0 AA5 TX 0P _D P C 2 P V2
L6 5 AA6 D PC _ V D D 10 #1 T X0 M_D P C 2N
*H C B 16 08 KF -12 1T 25 D PC _ V D D 10 #2 Y4
C 17 4 C 1 75 C 17 6 TX 1P _D P C 1 P W5
*10 u_6 . 3V _X 5R _ 06 *1u _6 .3 V _X 5R _0 4 *0. 1 u_1 0V _ X5R _ 04 U1

W1
U3
D PC _ V SS R # 1
D PC _ V SS R # 2
D PC _ V SS R # 3
T X1 M_D P C 1N
TX 2P _D P C 0 P
T X2 M_D P C 0N
A A3
Y2 Sheet 8 of 41
Y6 J8 R 1 03 *1 50_ 1% _0 4
Access to SCL and SDA is

mandatory on BACO designs
3 . 3V S_ GP U 3. 3V S _GP U
R 1 04 R 10 5
AA1 D PC _ V SS R # 4
D PC _ V SS R # 5
D P C _C A LR
Robson S3 MAIN 2/
3 3. V S_ GP U
R 10 6 *1 0K _ 04 S B _MX M_C L KR E Q#
for debug purposes
20
20
SCL
SDA
*4 . 7K _0 4 *4. 7 K_ 04
SC L
SDA
R1
R3 SC L
SD A
I2 C
6
R 10 7 *1 0K _ 04 GP I O7_ B LON
A M26 R _D A C 1
R 10 8 *1 0K _ 04 GP I O24 _T R ST B G ENE RA L PU RPO SE I /O R A K2 6 R B _D A C 1 R 71 5 *1 50 _1 %_0 4 R _D A C 1 21
R 10 9 *1 0K _ 04 GP I O25 _T D I GP I O0 U6 RB
10 GP I O0 GP I O1 U1 0 GPI O_ 0 A L2 5 G_D A C 1 1. 8 V_ R E G
R 11 0 *1 0K _ 04 GP I O27 _T MS 10 GP I O1 GP I O2 T1 0 GPI O_ 1 G A J2 5 GB _D A C 1 R 71 6 *1 50 _1 %_0 4 G_D A C 1 21
10 GP I O2 U8 GPI O_ 2 GB
10 MX M_S D A TA MX M_S D A TA
MX M_S C L K U7 GPI O_ 3_ SMB D A TA A H 24 B _D A C 1 (1.8V @65m A AVD D) A V DD
GP I O26 _T C K 10 MXM_ S C LK GP I O5 T9 GPI O_ 4_ SMB C L K B A G25 B B_ D A C 1 R 71 7 B_ D A C 1 21
R 11 1 *1 0K _ 04 10 GP I O5 GPI O_ 5_ AC _ B AT T BB *1 50 _1 %_0 4 L 66
GP I O6 T8 DA C1 C 1 77 C 17 8 C 179
S B _MX M_C L KR E Q# GP I O7_ B LON T7 GPI O_ 6 A H 26
R 68 5 *1 0K _ 04 20 GP I O7_ B LON GPI O_ 7_ BL ON H SY N C H S Y N C _ D AC 1 10, 2 1 * H C B1 60 8K F -121 T2 5
GP I O8 P1 0 A J2 7 *1 0u _6. 3 V _X5 R _0 6 *1u _6 .3 V _X5 R _0 4
10 GP I O8 GP I O9 P4 GPI O_ 8_ R OMSO V SY N C V S Y N C _D A C 1 1 0, 21 *0 . 1u _10 V _X 5R _0 4
10 GP I O9 GP I O10 P2 GPI O_ 9_ R OMSI
GP I O11 N6 GPI O_ 10 _R OMS C K A D 22 R 1 12
10 GP I O11 GP I O12 N5 GPI O_ 11 RS E T AV D D *4 99 _1% _0 4
3. 3 VS _ GPU 10 GP I O12 GP I O13 N3 GPI O_ 12 A G24 (1.8V @100 m A VDD1 DI) VD D 1 D I
10 GP I O13 Y9 GPI O_ 13 A VD D A E2 2
HP D2 L 67
R OB S ON _GP I O1 5 N1 GPI O_ 14 _H P D 2 A V S SQ V D D 1D I C 1 80 C 18 1 C 182
36 R OB S ON _GP I O15 R OB S ON _GP I O1 6 M4 GPI O_ 15 _P WR C N TL_ 0 A E2 3
36 R OB S ON _GP I O16 GPI O_ 16 _S S N
I VDD1 DI * H C B1 60 8K F -121 T2 5
GP U _ TA LE R T# R6 A D 23 *1 0u_ 6. 3 V_ X5 R _0 6 *0. 1u _1 0V _X 5R _ 04
10 , 17 GP U _T A LE R T# GP I O18 _H P D 3 W1 0 GPI O_ 17 _T H ER MA L _I N T V SS 1 D I *1 u_ 6. 3V _ X5R _ 04
GP I O_1 9_ C TF M2 GPI O_ 18 _H P D 3
GP I O20 P8 GPI O_ 19 _C T F A M12 R _D A C 2
R 11 3 *1K _0 4 GP O
I 2 8_ TD O GP I O21 P7 GPI O_ 20 _P WR C N TL_ 1 R2 A K1 2 R B _D A C 2 (1.8V @2m A A2 VD DQ) A 2V D D Q
10 GP I O2 1 GP I O22 N8 GPI O_ 21 _B B _E N R2 B L 68
R 11 4 *1K _0 4 GP O
I 2 4_ TR S T B 10 GP I O2 2 S B _MX M_C L KR EQ# N7 GPI O_ 22 _R OMC S B A L1 1 G_D A C 2 C 183 C 1 84 C 185
1 6 S B_ MXM_ C LK R E Q# GPI O_ 23 _C L KR E QB G2 A J1 1 GB _D A C 2 * H C B1 60 8K F -121 T2 5
GP I O24 _T R S TB L6 G2 B *1 0u _6 .3 V _X 5R _0 6 *1u _6 .3 V _X5 R _0 4
GP I O25 _T D I L5 JT AG_ TR S TB A K1 0 B _D A C 2 *0 . 1u _10 V _X 5R _0 4
GP I O26 _T C K L3 JT AG_ TD I B2 A L9 B B_ D A C 2
GP I O27 _T MS L1 JT AG_ TC K B2 B DAC2 i s NC on Se ymo ur
GP I O28 _T D O K4 JT AG_ TMS
T E ST EN K7 JT AG_ TD O A H 12 (1 .8V @1 00 m A V DD2 DI) V D D 2D I
R 115 A F2 4 TE S TE N C A M10 L 69
*5 . 11 K_ 1% _0 6 TE S TE N _L EGA C Y Y A J9 C 186 C 1 87 C 188
C OMP * H C B1 60 8K F -121 T2 5
GE N _ A A B1 3 DA C2 *1 0u _6 .3 V _X 5R _0 6 *1u _6 .3 V _X5 R _0 4
GE N _ B W8 GEN E R I C A A L1 3 *0 . 1u _10 V _X 5R _0 4
W9 GEN E R I C B H 2 SY N C A J1 3 H S Y N C _D A C 2 1 0
10 GE N E R I C C W7 GEN E R I C C V 2 SY N C V SY N C _ D A C 2 10
HP D_ 4 A D1 0 GEN E R I C D
GEN E R I C E _H P D 4 VD D 2D I
A D 19
HP D1 A C1 4 VDD2 DI A C 19 3. 3 VS _ GPU
R 1 16 21 *5. 1 1K _1 %_
H P 06
D1 P X _E N A B1 6 H PD 1 V SS 2 D I R 1 17
Se ym ou r A 2V D D
For PX_EN, refer to t he BACO (3 .3V @1 30 m A A 2 VDD)
PX _E N A 2V D D L 70
reference schem atics for detail A E2 0 *0 _04 C 1 89 C 19 0 C 191
1 . 8V _R E G A 2 VD D A 2V D D Q * H C B1 60 8K F -121 T2 5
A E1 7 *1 0u _6 .3 V _X 5R _0 6 *0. 1u _1 0V _X 5R _ 04
A 2 VD D Q NC o n Seym ou r *1 u_ 6. 3V _ X5R _ 04
PLA CE VREFG DIV IDER A ND CAP
R 1 18 A E1 9
C LOSE TO ASIC A 2V S SQ
*4 99 _1 %_0 4
A C1 6
VR E F G A G13 R 1 19 *71 5_ 1%_ 04
R 2S E T
R 1 20
1. 8 V_ R EG *2 49 _1 %_0 4
(1 .8 V@75 m A DPLL_ PVDD) D PL L_ PV D D C 19 2 DD C/ AU X A E6 D D C 1C L K D D C 1 C LK 2 1
L 71 *0. 1 u_1 0V _ X5R _ 04 D P LL _P V D D PL L/ CLO CK D D C 1C L K A E5 D D C 1D A T A D D C 1 D AT A 2 1
*H C B 1 60 8K F-1 21 T2 5 C 19 3 C 194 C 1 95 A F1 4 D D C 1D A T A
A E1 4 D PL L_ PV D D A D2 A U X1P X TA L IN C 1 96 *2 2p_ 50 V _N P O_0 4
*10 u_ 6. 3V _ X5 R _06 *0 . 1u _10 V _X5 R _0 4 D PL L_ PV S S A U X1 P A D4 A U X1N
AU X 1N
*1u _6 . 3V _X 5R _ 04 A D1 4 A C 11 D D C 2C L K
D PL L_ VD D C D D C 2C L K A C 13 D D C 2D A T A
D D C 2D A T A
1
(1.0 V@1 25m A DPLL_ VDDC) X TA LI N A M2 8 A D 13 A U X2P X2 R 1 21
1. 0 V_ R EG D P LL _V D D C X TA LOU T A K2 8 XT AL I N A U X2 P A D 11 A U X2N
L7 2 XT AL OU T AU X 2N *F SX 8L _2 7MH z *1 M_0 4
A C2 2 A D 20
2
*H C B 1 60 8K F-1 21 T2 5 C 1 97 C 19 8 C 1 99 D D C C LK _ AU X 3P
A B2 2 XO_ IN D D C C L K _A U X3 P A C 20 D D C D A TA _A U X 3N
*10 u_ 6. 3 V_ X5 R _0 6 * 0. 1u _1 0V _X 5R _ 04 XO_ IN 2 D D C D A T A_ AU X 3N
GND Optio n If A E1 6 D D C C LK _ AU X 5P X TA LOU T
D D C C L K _A U X5 P A D 16 D D C D A TA _A U X 5N
*1 u_ 6. 3V _ X5 R _04 XO_IN/XO_IN2 D D C D A T A_ AU X 5N C 2 00 *2 2p_ 50 V _N P O_0 4
3. 3 VS _ GPU not use d
A C1 D D C 6C L K
T4 THE RM AL D D C 6C L K A C3 D D C 6D A T A D D C 6C L K 21
R 16 7 1 0 GP U _D P LU S T2 D PL U S D D C 6D A T A D D C 6D A T A 21 XTAL Opt ion
*2. 2 K_ 04 1 0 GP U _D MI N U S D MI N U S
1. 8 V_ R EG
(1 .8V @2 0m A TSVDD) T SV D D T S_ F D O R5
L 73 A D1 7 TS _F D O
*H C B 1 60 8K F-1 21 T2 5 C 20 1 C 20 2 C 2 03 A C1 7 TS V D D
TS V SS
*10 u_ 6. 3V _ X5 R _06 *0 . 1u _10 V _X5 R _0 4
*1 u_6 . 3V _X 5R _ 04 *R OB S ON XT S3
Robson S3 MAIN 2/6 B - 9

Schematic Diagrams
Robson S3 MEM Interface 3/6
COMPONENTS SHOWN ARE EXAMPLES ONLY DDR3 Memory

AND NOT NECESSARILY QUALIFIED Interface
U4C
13 DQA0_[ 31. .0] G DDR 5/DD R3 GDD R5/D DR3 MAA[12 ..0] 1 3,14
DQA0_ 0 K2 7 K17 MAA0
J2 9 DQ A0 _0/D QA_ 0 MAA0 _0/ MAA_ 0 J2 0
DQA0_ 1 MAA1
DQA0_ 2 H3 0 DQ A0 _1/D QA_ 1 MAA0 _1/ MAA_ 1 H2 3 MAA2
DQA0_ 3 H3 2 DQ A0 _2/D QA_ 2 MAA0 _2/ MAA_ 2 G2 3 MAA3
DQA0_ 4 G2 9 DQ A0 _3/D QA_ 3 MAA0 _3/ MAA_ 3 G2 4 MAA4
F2 8 DQ A0 _4/D QA_ 4 MAA0 _4/ MAA_ 4 H2 4
DQA0_ 5 MAA5
MEMORY INTERFACE
DQA0_ 6 F3 2 DQ A0 _5/D QA_ 5 MAA0 _5/ MAA_ 5 J1 9 MAA6
DQA0_ 7 F3 0 DQ A0 _6/D QA_ 6 MAA0_ 6/MAA0_ 6 K19 MAA7
DQA0_ 8 C3 0 DQ A0 _7/D QA_ 7 MAA0_ 7/MAA0_ 7 J1 4 MAA8
DQA0_ 9 F2 7 DQ A0 _8/D QA_ 8 MAA1 _0/ MAA_ 8 K14 MAA9
DQA0_ 10 A2 8 DQ A0 _9/D QA_ 9 MAA1 _1/ MAA_ 9 J1 1 MAA10
DQA0_ 11 C2 8 DQ A0 _10/ DQA_10 MAA1_ 2/MAA_1 0 J1 3 MAA11
E2 7 DQ A0 _11/ DQA_11 MAA1_ 3/MAA_1 1 H1 1
DQA0_ 12 MAA12
DQA0_ 13 G2 6 DQ A0 _12/ DQA_12 MAA1_ 4/MAA_1 2 G1 1
D2 6 DQ A0 _13/ DQA_13 MAA1_ 5/MAA_13 /BA2 J1 6 A_BA2 13 ,14
DQA0_ 14
DQA0_ 15 F2 5 DQ A0 _14/ DQA_14 MAA1_ 6/MAA_14 /BA0 L1 5 A_BA0 13 ,14
DQA0_ 16 A2 5 DQ A0 _15/ DQA_15 MAA1_ 7/MAA_15 /BA1 A_BA1 13 ,14
DQA0_ 17 C2 5 DQ A0 _16/ DQA_16 E32 DQMA0_ 0 DQ MA0_[3 ..0 ] 13
DQA0_ 18 E2 5 DQ A0 _17/ DQA_17 WCKA0_0 /DQMA_ 0 E30 DQMA0_ 1

DQA0_ 19 D2 4 DQ A0 _18/ DQA_18 W CKA0B_0 /DQMA_ 1 A21 DQMA0_ 2
DQA0_ 20 E2 3 DQ A0 _19/ DQA_19 WCKA0_1 /DQMA_ 2 C2 1 DQMA0_ 3
F2 3 DQ A0 _20/ DQA_20 W CKA0B_1 /DQMA_ 3 E13 DQMA1_ [3. .0] 1 4
DQA0_ 21 DQMA1_ 0
DQA0_ 22 D2 2 DQ A0 _21/ DQA_21 WCKA1_0 /DQMA_ 4 D1 2 DQMA1_ 1
DQA0_ 23 F2 1 DQ A0 _22/ DQA_22 W CKA1B_0 /DQMA_ 5 E3 DQMA1_ 2
DQA0_ 24 E2 1 DQ A0 _23/ DQA_23 WCKA1_1 /DQMA_ 6 F4 DQMA1_ 3
D2 0 DQ A0 _24/ DQA_24 W CKA1B_1 /DQMA_ 7
DQA0_ 25
DQ A0 _25/ DQA_25 QSA0_[ 3.. 0] 13
DQA0_ 26 F1 9 H2 8 QSA0 _0
Sheet 9 of 41 DQA0_ 27
DQA0_ 28
DQA0_ 29
A1 9
D1 8
F1 7
DQ A0 _26/ DQA_26
DQ A0 _27/ DQA_27
DQ A0 _28/ DQA_28
EDCA0_ 0/RD QSA_ 0
EDCA0_ 1/RD QSA_ 1
EDCA0_ 2/RD QSA_ 2
C2 7
A23
E19
QSA0 _1
QSA0 _2
QSA0 _3
DQA0_ 30 A1 7 DQ A0 _29/ DQA_29 EDCA0_ 3/RD QSA_ 3 E15 QSA1 _0 QSA1 _[3 ..0 ] 14
Robson S3 MEM 14 DQA1_[ 31. .0]

DQA0_ 31
DQA1_ 0
DQA1_ 1
C1 7
E1 7
D1 6
DQ A0 _30/ DQA_30
DQ A0 _31/ DQA_31
DQ A1 _0/D QA_ 32
EDCA1_ 0/RD QSA_ 4
EDCA1_ 1/RD QSA_ 5
EDCA1_ 2/RD QSA_ 6
D1 0
D6
G5
QSA1 _1
QSA1 _2
QSA1 _3
F1 5 DQ A1 _1/D QA_ 33 EDCA1_ 3/RD QSA_ 7
InTERFACE 3/6 DQA1_ 2

DQA1_ 3
DQA1_ 4
DQA1_ 5
A1 5
D1 4
F1 3
DQ A1 _2/D QA_ 34
DQ A1 _3/D QA_ 35
DQ A1 _4/D QA_ 36
DDBI A0_ 0/WD QSA_ 0
DDBI A0_ 1/WD QSA_ 1
H2 7
A27
C2 3
QSA0 _0B
QSA0 _1B
QSA0 _2B
QSA0_0 B
QSA0_1 B
13
13
A1 3 DQ A1 _5/D QA_ 37 DDBI A0_ 2/WD QSA_ 2 C1 9 QSA0_2 B 13
DQA1_ 6 QSA0 _3B
DQA1_ 7 C1 3 DQ A1 _6/D QA_ 38 DDBI A0_ 3/WD QSA_ 3 C1 5 QSA1 _0B QSA0_3 B 13
DQA1_ 8 E1 1 DQ A1 _7/D QA_ 39 DDBI A1_ 0/WD QSA_ 4 E9 QSA1 _1B QSA1_0 B 14
DQA1_ 9 A1 1 DQ A1 _8/D QA_ 40 DDBI A1_ 1/WD QSA_ 5 C5 QSA1 _2B QSA1_1 B 14
DQA1_10 C1 1 DQ A1 _9/D QA_ 41 DDBI A1_ 2/WD QSA_ 6 H4 QSA1 _3B QSA1_2 B 14
DQA1_11 F1 1 DQ A1 _10/ DQA_42 DDBI A1_ 3/WD QSA_ 7 QSA1_3 B 14
DQA1_12 A9 DQ A1 _11/ DQA_43 L1 8 ODTA0
C9 DQ A1 _12/ DQA_44 ADBI A0/OD TA0 K16 ODTA0 13
DQA1_13 ODTA1
DQA1_14 F9 DQ A1 _13/ DQA_45 ADBI A1/OD TA1 ODTA1 14
D8 DQ A1 _14/ DQA_46 H2 6
DQA1_15 CLKA0
DQA1_16 E7 DQ A1 _15/ DQA_47 CLKA0 H2 5 CLKA0# C LKA0 13
DQA1_17 A7 DQ A1 _16/ DQA_48 CLKA0B C LKA0 # 13
DQA1_18 C7 DQ A1 _17/ DQA_49 G9 CLKA1
F7 DQ A1 _18/ DQA_50 CLKA1 H9 C LKA1 14
DQA1_19 CLKA1#
DQ A1 _19/ DQA_51 CLKA1B C LKA1 # 14
DQA1_20 A5
DQA1_21 E5 DQ A1 _20/ DQA_52 G2 2 RASA0#
C3 DQ A1 _21/ DQA_53 R ASA0B G1 7 R ASA0# 13
PLACE MVREF DIVIDERS DQA1_22 RASA1#
DQA1_23 E1 DQ A1 _22/ DQA_54 R ASA1B R ASA1# 14
AND CAPS CLOSE TO ASIC DQA1_24 G7 DQ A1 _23/ DQA_55 G1 9 CASA0#
DQ A1 _24/ DQA_56 C ASA0B C ASA0# 13
DQA1_25 G6 G1 6 CASA1#
DQ A1 _25/ DQA_57 C ASA1B C ASA1# 14
MVD DQ DQA1_26 G1
DQA1_27 G3 DQ A1 _26/ DQA_58 H2 2 CSA0 b_0
J6 DQ A1 _27/ DQA_59 CSA0 B_ 0 J2 2 C SA0b _0 13
DQA1_28
DQA1_29 J1 DQ A1 _28/ DQA_60 CSA0 B_ 1
Ra R12 2
DQA1_30 J3 DQ A1 _29/ DQA_61 G1 3 CSA1 b_0
DQ A1 _30/ DQA_62 CSA1 B_ 0 C SA1b _0 14
*40. 2_1%_0 4 DQA1_31 J5 K13
DQ A1 _31/ DQA_63 CSA1 B_ 1
K2 6 K20 CKEA0
MVREFDA CKEA0 CKEA0 13
J2 6 J1 7 CKEA1
MVREFSA CKEA1 CKEA1 14
R12 3 C204 MVDD Q
R12 4 *2 43_1 %_ 04 J2 5 G2 5 WEA0#
MEM_ CAL RN0 WEA0B WEA0# 13
*100 _04 *0 .1u _10V_X5R_0 4 K2 5 H1 0 WEA1#
Rb MEM_ CAL RP0 WEA1B WEA1# 14
MVDDQ R12 5 *2 43_1 %_ 04
G DDR5 /DD R3
G2 0 MAA1 3
Ra R1 26 MAA0_ 8/MAA_1 3 G1 4 MAA1 _8
MAA13 13 ,14
DMEM_ RST L1 0 MAA1_8 _RSVD
*40 .2_1 %_ 04 T9 7
DR AM_ RST
From GPU
K8
L7 CL KTESTA
CL KTESTB 25mm (max) 5mm (max) 25mm (max)
R1 27 C 205 D MEM_RST RSER 1 RSER2
MEM_RST 13, 14
Rb *ROBSON XT S3 *10 _04 1 0.0 *49. 9_1 %_ 04
*0. 1u_ 10V_X5 R_04
*10 0_04 RPD1 CSHUNT1
r oute 50o hms sin gle- ende d/1 00oh ms d iff *4.99 K_ 1%_04
a nd k eep sho rt *040 2_12 0pF_50 V_ 5%
D ebug onl y, for cloc k ob ser vati on, if n ot need ed, DNI
Place all these components very close to GPU (Within

*0.1u _10 V_ X5R_ 04 25mm) and keep all component close to each Other (within
CLKTESTB C2 06 R 128 *5 1.1 _1%_04
DD R3/GD DR 3 Me mory Stu ff Optio n 5mm) except Rser2
C LKTESTA C2 07 R 129 This basi c topo logy s hould be use d for DRAM_ RST fo r DDR3 /GDDR5 .Thes e
*0. 1u_1 0V_X5R _04 *51. 1_1 %_0 4
Capa citor s and Resist or val ues ar e an exampl e only . The Series R an d
GDDR5 DDR3
|| C ap va lues w ill de pend o n the DRAM load a nd wil l have to be
calc ulate d for diffe rent M emory ,DRAM Load and bo ard t o pass Rese t
MVDDQ 1.5V 1.5V/1.8V Sign al Sp ec.
Ra 40.2R 40.2R
Rb 100R 100R
B - 10 Robson S3 MEM Interface 3/6

Schematic Diagrams
Robson S3 Straps 4/6
GPIO21 MUST BE LOW DURING PERSTB WHEN BEING USED TO CONTROL MVDDQ
3.3VS_GPU
P IN S T RAP S W250B AQ RECOMMENDED SETTINGS
R1
30 *1
0K_0
4
8 GPIO0 GP IO0 1 CONFIGU RATION S TR APS-- SEE EAC H DATAB OOK FOR S TR AP DE TAILS 0= DO NOT INSTALL RESI STOR
1 = I NSTALL 3
K RESISTOR
R1
31 *1
0K_0
4
8 GPIO1 GP IO1 1 ALLOW FOR PULLUP PADS FOR THES E S TRAPS AND IF THES E GPI OS ARE US ED, X = DESIGNDEPENDANT
NA = NOT APPLICABLE
8 GPIO2
R1
32 *1
0K_0
4
GP IO2 0 THEY MUS T NOT CONFLICT DURI NG RESET
R1
33 *1
0K_0
4
8 GPIO8 GP IO8 0 STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS
R1
34 *1
0K_0
4
8 GPIO9 GP IO9 0
R1
35 *1
0K_0
4 TX_PWRS_ENB GPI O0 PCIEFULL TXOUTPUT SWING
8 GPIO11 GP IO11 1 X
R1
36 *1
0K_0
4 TX_DEEMPH_EN GPI O1 PCIETRANSMITTER DE-EMPHASIS ENABLED
8 GPIO12 GP IO12 0
X
R1
37 *1
0K_0
4
8 GPIO13 GP IO13 0 RSVD GPI O2 RESERVED 0
R1
38 *1
0K_0
4 RSVD GPI O8 RESERVED 0
8,21 VSYNC_
DAC1 V SY NC_DA C1 1
R1
39 *1
0K_0
4
8,21 HSYNC_DAC1 HSY NC_DA C1 1
BIF_VGADIS GPI O9 VGAENABLED 0
R1
40 *1
0K_0
4
8 GENERICC GE NERICC 1
R1
41 *1
0K_0
4 RSVD GPI O21 RESERVED 0
8 VSYNC_DAC2 V SY NC_DA C2 0
R1
42 *1
0K_0
4
8 HSYNC_DAC2 HSY NC_DA C2 0 BIOS_ROM_EN GPIO_22_ROMCSB EN ABL E EXTER NA L BIO S R OM X
R1
43 *1
0K_0
4
GP IO21 0
8
8
GPIO21
GPIO22
R1
44 *1
0K_0
4
GP IO22 0 ROMIDCFG(2:0) GPIO[1
3: 1
1] SER IAL RO M TYP E O R MEM O RY AP ER TUR E S IZE S EL EC T XXX Sheet 10 of 41
8 GPIO5 R1
45 *1
0K_0
4
GP IO5 1 VIP_DEVICE_STRAP_ENA V2SYNC IGNOREVIP DEVICESTRAPS(Removed on Seymour/Whistler) X Robson S3 Straps
3.3VS_GPU
GPU Thermal Sensor RSVD H2SYNC RESERVED 0
4/6
R146 R147 AUD[1] HSYNC SEE DA TABO OK FO R DE TA IL X
AUD[0] VSYNC SEE DA TABO OK FO R DE TA IL X
*2.2K_04 *2.2K_04 C208
3.3VS_
GPU
*1000p_
50V_X7R_04 RSVD GENERICC RESERVED 0
U6 C209 *2200p_50V_X7R_04
MXM_SCLK R150 *0_0
4 8
SCLK VDD
1 NOTE1: AMD RESERVED C ONF IGURATI ON ST RAPS
MXM_SDAT
A R151 *0_0
4 7 2
SDATA D+ GPU_
DPLUS 8 ALLOW FOR P ULLUP P ADS FOR THESE STRAPS BUT DO NOT I NST ALL RESI STOR. IF THESE GPI OS ARE US ED,
27 SMC_VGA_THERM
R152 *0_04 6
ALERT D-
3
GPU_
DMINUS 8 THEY MUS T KEEP "LOW" AND NOT CONFLICT DURI NG RESET .
R153 *0_04 5 4 R154 *0_04
27 SMD_VGA_THERM GND THERM VGA_ALERT# 27
GPIO21 H2SYNC GENERICC G PIO 8 GPIO2
*W8
3L771AWG R157 *2.2K_0
4
3.3VS_GPU
R155 *0_04
GPU_T
ALERT# 8
,17
3.3VS_GPU
R156 *2.2K_04 SMBus gating circuit
3.3VS_GPU
7 MXM_RST# R158 *0_04

R159
*6.8K_1%_04
R160
G
*6.8K_1%_04 Q4
MX
M_SDATA S D
8 MXM_SDATA SDATA0 5
, 6,16
*MTN70
02ZHS3
G
Q5
MXM_SCLK S D
8 MX
M_SCLK SCLK0 5
, 6,16
*MTN7002ZHS3
Robson S3 Straps 4/6 B - 11

Schematic Diagrams
Robson S3 Power 5/6
U4E
AA27 A3
AB24 PCIE_VSS#1 GND#1 A30
AB32 PCIE_VSS#2 GND#2 AA13
AC24 PCIE_VSS#3 GND#3 AA16
AC26 PCIE_VSS#4 GND#4 AB10
AC27 PCIE_VSS#5 GND#5 AB15
AD25
AD32
AE27
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
G
G
G
ND#6
ND#7
ND#8
AB6
AC9
AD6
PARK/ROBSON- S3 (DP Power)
AF32 PCIE_VSS#9 GND#9 AD8
AG27 PCIE_VSS#10 GND#10 AE7
AH32 PCIE_VSS#11 GND#11 AG12 ( 1.8V@ 300m A DPAB_VDD18 )
K28 PCIE_VSS#12 GND#12 AH10
K32 PCIE_VSS#13 GND#13 AH28 DPAB_VDD18
L27 PCIE_VSS#14 GND#14 B10 U4
G 1.8V_REG
M32 PCIE_VSS#15 GND#15 B12 *1u_6.3V_X5R_
04 L74
N25 PCIE_VSS#16 GND#16 B14 DP E/F POWER DP A/B POWER
PCIE_VSS#17 GND#17 C210 C21
4 C211 *HCB1608KF-121T25
N27 B16 1.8V_REG DPEF_VDD18
P25 PCIE_VSS#18 GND#18 B18 L75 AG1
5 AE1
1 *10u_6.3V_08_H125
*1u_6.3V_X5
R_04 *0.1u_10
V_X
5R_04
P32 PCIE_VSS#19 GND#19 B20 AG1
6 DPE_VDD18#1 DPA_
VDD18#1 AF1
1
*HCB16
08KF-121T
25
R27 PCIE_VSS#20 GND#20 B22 C212 C21
5 C213 DPE_VDD18#2 DPA_
VDD18#2
T25 PCIE_VSS#21 GND#21 B24

T32 PCIE_VSS#22 GND#22 B26 LVDS mode (1.8V@440mA DPEF_VDD18) *0.1u_
10V_X5R_04
*10u_6.3V_08_H125 DPAB_VDD10 ( 1.0 V@220 m A DPAB_VDD1 0)L76 1.0V_REG
U25 PCIE_VSS#23 GND#23 B6 DP mode (1.8V@300mA DPEF_VDD18) AG2
0 AF6
DPEF_VDD1
0
U27 PCIE_VSS#24 GND#24 B8 AG2
1 DPE_VDD10#1 DPA_
VDD10#1 AF7 C216 C217 C218 *HCB1608KF- 12
1T25
V32 PCIE_VSS#25 GND#25 C1 1.0V_REG DPE_VDD10#2 DPA_
VDD10#2
W25 PCIE_VSS#26 GND#26 C32 L77 *0.1u
_10V_X5R_0
4 *10u_
6.3V_
08_H125
W26 PCIE_VSS#27 GND#27 E28 AG1
4 AE1
PCIE_VSS#28 GND#28 *HCB16
08KF-121T
25 DPE_VSSR#1 DPA_VSSR#1
W27 F10 C219 C220 C2
21 AH1
4 AE3 *1u_6.3V_X5R_04
Sheet 11 of 41 Y25
Y32
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31
GND#29
GND#30
GND#31
GND#32
F12
F14
F16
LVDS mode (1.0V@240mA DPEF_VDD10)
DP mode (1.0V@220mA DPEF_VDD10)
*10
u_6.3V_08_H1
25 *0.1u_10V_X5R_04
AM1
4
AM1
6
AM1
8
DPE_VSSR#2
DPE_VSSR#3
DPE_VSSR#4
DPE_VSSR#5
DPA_VSSR#2
DPA_VSSR#3
DPA_VSSR#4
DPA_VSSR#5
AG1
AG6
AH5
F18
Robson S3 Power M6
GND#33
GND#34
GND#35
F2
F20
F22
*1u_6
.3V_X
5R_04
DPEF_VDD18 AF1
6 AE1
3
DPAB_
VDD18
GND#56 GND#36 DPF_VDD18#1 DPB_

VDD18#1
5/6 N11
N12
N13
N16
GND#57
GND#58
GND#59
GND#37
GND#38
GND#39
F24
F26
F6
F8
DPEF_VDD10
AG1
7
DPF_VDD18#2 DPB_
VDD18#2
AF1
3
DPAB_VDD10
N18
N21
GND#60
GND#61
GND#62
GND GND#40
GND#41
GND#42
G10
G27
AF2
2
AG2
2 DPF_VDD10#1
DPF_VDD10#2
DPB_
VDD10#1
DPB_
VDD10#2
AF8
AF9
P6 G31
P9 GND#63 GND#43 G8
R12 GND#64 GND#44 H14 AF2
3 AF1
0
R15 GND#65 GND#45 H17 AG2
3 DPF_VSSR#1 DPB_VSSR#1 AG9
R17 GND#66 GND#46 H2 AM2
0 DPF_VSSR#2 DPB_VSSR#2 AH8
R20 GND#67 GND#47 H20 AM2
2 DPF_VSSR#3 DPB_VSSR#3 AM6
T13 GND#68 GND#48 H6 AM2
4 DPF_VSSR#4 DPB_VSSR#4 AM8
T16 GND#69 GND#49 J27 DPF_VSSR#5 DPB_VSSR#5
T18 GND#70 GND#50 J31
T21 GND#71 GND#51 K11
T6 GND#72 GND#52 K2
U15 GND#73 GND#53 K22 R162 *150
_1%_04
AF1
7 AE1
0 R163 *150_1%_04
U17 GND#74 GND#54 K6 DPEF_CALR DPAB_CALR
U20 GND#75 GND#55
DPEF_
VDD18 DPAB_VDD18
U9 GND#76
V13 GND#77 AG1
8 DP PLL POWER AG8
V16 GND#78 AF1
9 DPE_PVDD DPA_PVDD AG7
V18 GND#79 DPE_PVSS DPA_PVSS
Y10 GND#80
DPEF_VDD18 DPAB_
VDD18
Y15 GND#81
Y17 GND#82 A32 AG1
9 AG10
Y20 GND#83 VSS_MECH#1 AM1 AF2
0 DPF_PVDD DPB_PVDD AG11
R11 GND#84 VSS_MECH#2 AM32 DPF_PVSS DPB_PVSS
T11 GND#85 VSS_MECH#3
GND#86
*ROBSON XT S3
*ROBSON XT S3
B - 12 Robson S3 Power 5/6

Schematic Diagrams
Robson S3 Power 6/6

M VDDQ
MV D D Q 2.8A 210m il
*0 . 1u _ 10 V _X 5R _ 0 4 *0 . 1 u_ 10 V _X 5 R _0 4 * 1u _6 . 3 V_ X 5R _ 0 4
C 22 2 C 2 23 C 22 4 C 22 5 C 2 26 C 22 7 C 2 28 C2 2 9 C 23 0 C 23 1 U 4D
PCIE
_VDDR 1 . 8V _ R E G
* 0. 1 u_ 1 0V _ X5 R _ 04 * 0. 1 u_ 10 V _X 5 R _0 4 *0 . 1 u_ 10 V _X 5 R _0 4 * 0. 1 u_ 1 0V _ X5 R _ 04 *1 u_ 6 . 3V _ X5 R _ 04 MEM I/O PC E
I _ V D D R _ V GA
PCIE 400mA20mil
* 0. 1 u_ 1 0V _ X5 R _ 04 *0. 1 u _1 0V _ X5 R _ 04 H1 3 AB2 3 L78
H1 6 V DDR 1# 1 P CIE _ V DDR# 1 A C2 3
H1 9 V DDR 1# 2 P CIE _ V DDR# 2 A D2 4 *H C B1 6 08 K F- 1 2 1T 25
C 24 0 C2 4 1 C 2 42 C 2 43 C 2 44 C 24 5
C 23 2 C 23 3 C2 3 4 C 2 35 C 2 38 J1 0 V DDR 1# 3 P CIE _ V DDR# 3 AE2 4
J2 3 V DDR 1# 4 P CIE _ V DDR# 4 AE2 5 *0 . 1u _ 10 V _X 5R _0 4 *1 u_ 6. 3 V _X 5R _0 4 * 1u _6 . 3V _ X5 R _ 04 *1 0u _ 6. 3 V _0 8_ H 1 25
*1 u_ 6 . 3V _ X5 R _ 04 *1 u_ 6. 3 V _X 5 R _0 4 *1 u_ 6 .3 V _ X5 R _0 4 J2 4 V DDR 1# 5 P CIE _ V DDR# 5 AE2 6
J9 V DDR 1# 6 P CIE _ V DDR# 6 AF2 5
V DDR 1# 7 P CIE _ V DDR# 7 * 0. 1 u_ 1 0V _ X5 R _ 04 *1u _ 6. 3 V _X 5R _0 4
K1 0 A G2 6 1.0V_REG VD DC
* 1u _6 . 3 V_ X 5R _ 0 4 * 1u _6 . 3V _ X5 R _ 04 K2 3 V DDR 1# 8 P CIE _ V DDR# 8
K2 4 V DDR 1# 9 2A 80mil
1 . 0V _ R E G
K9 V DDR 1# 10 L23
L1 1 V DDR 1# 11 P CIE _ V DDC# 1 L24 C 8 37
L1 2 V DDR 1# 12 P CIE _ V DDC# 2 L25 +
C 24 8 C 24 9 C 25 1 C 25 2 V DDR 1# 13 P CIE _ V DDC# 3 C 2 53 C 25 4 C 2 55 C 2 56 C 25 7 C2 5 8 C2 5 9 C2 6 0
L1 3 L26 * 22 0u _ 4V _ V_ A
* 10 u_ 6. 3 V _0 8 _H 1 2 5 *10 u _6 . 3V _ 08 _ H 12 5 *1 0u _6 . 3V _ 0 8_ H 12 5 L2 0 V DDR 1# 14 P CIE _ V DDC# 4 M 22 * 1u _6 . 3 V_ X 5R _ 0 4 *1 u_ 6. 3 V _X 5R _0 4 *1 u_ 6. 3 V _X 5R _0 4 *1 u_ 6. 3 V _X 5R _0 4 *1 0u _6 . 3 V_ 0 8_ H 1 25
L2 1 V DDR 1# 15 P CIE _ V DDC# 5 N 22
*10 u _6 . 3V _ 08 _H 12 5 L2 2 V DDR 1# 16 P CIE _ V DDC# 6 N 23
V DDR 1# 17 P CIE _ V DDC# 7 N 24
P CIE _ V DDC# 8 *1 u_ 6. 3 V _X 5 R _0 4 *1 u_ 6. 3 V _X 5 R _0 4 * 1u _6 . 3 V_ X 5R _ 0 4
1 . 8V _ R E G R 22
P CIE _ V DDC# 9 T22
P C I E _V D D C #1 0 U 22
V D D C _C T LEVEL
TRANSLATION P C I E _V D D C #1 1 V2 2 VDDC
L7 9 * H C B 1 60 8K F -1 21 T2 5 *1 u_ 6. 3 V _X 5R _0 4 * 0. 1 u_ 10 V _X 5 R _0 4 AA2 0 P C I E _V D D C #1 2
V D D _ C T #1 12.9A 520mil
AA2 1 V DDC
AB2 0 V D D _ C T #2 AA1 5 * 1u _6 . 3 V_ X 5R _ 0 4 *1 u_ 6. 3 V _X 5R _0 4 *1 u_ 6. 3 V _X 5 R _0 4 * 1u _6 . 3 V_ X 5R _ 0 4
C 2 61 C 26 2 C 26 3 C 26 4 C 2 65 V D D _ C T #3 V DDC# 1
AB2 1 CORE N 15
* 10 u_ 6. 3 V _0 8 _H 1 2 5 *1 u _6 . 3V _ X5 R _ 04 V D D _ C T #4 V DDC# 2 N 17 C 2 66 C 26 7 C2 6 8 C 2 69 C 2 70 C 27 1 C 27 2 C 27 3 C 2 74 C 27 5
3. 3 V S _GP U V DDC# 3 R 13
*1 u _6 . 3V _ X5 R _ 04 I/O V DDC# 4 R 16 *1 u_ 6 . 3V _ X5 R _ 04 *1 u_ 6. 3 V _X 5R _0 4
VDDC_CT+VDDR4 * 1u _6 . 3V _ X 5R _ 04 AA1 7 V DDC# 5 R 18
AA1 8 V D D R 3# 1 V DDC# 6 Y 21 *1u _ 6. 3 V_ X 5R _ 0 4 * 1u _6 . 3V _ X5 R _ 04 *1u _6 . 3 V_ X 5R _ 0 4 *1 u_ 6. 3 V _X 5R _0 4
Sheet 12 of 41
187mA 10mil AB1 7 V D D R 3# 2 V DDC# 7 T12
C 27 6 C 27 7 C 27 8 C 2 79 V D D R 3# 3 V DDC# 8
3.3VS_GPU AB1 8 T15
*1 0u _ 6. 3 V _0 8_ H 1 25 *1 u_ 6. 3 V _X 5 R _0 4 V DD R4 V D D R 3# 4 V DDC# 9 T17 C 2 80 C 28 1 C2 8 2 C 2 83 C 2 84 C2 8 7 C 2 88 C 28 9
60mA 4mil V1 2 V D D C #1 0 T20
Y1 2 V D D R 4# 1 V D D C #1 1 U 13 *1 u _6 . 3V _ X5 R _ 04 *1 u_ 6. 3 V _X 5R _0 4 *1 u _6 . 3V _ X5 R _ 04 *1 u_ 6. 3 V _X 5R _0 4
V DDR4
* 1u _6 . 3V _ X 5R _ 04 U1 2
AA1 1
V D D R 4# 2
V D D R 4# 3
N C #1
V D D C #1 2
V D D C #1 3
V D D C #1 4
V D D C #1 5
U 16
U 18
V2 1
*1 u_ 6 . 3V _ X5 R _ 04
*1 u _6 . 3V _ X5 R _ 04 *1u _ 6. 3 V _X 5R _0 4 * 1u _6 . 3V _ X 5R _ 04
Robson S3 Power
AA1 2 V1 5
POWER
6/6
L8 0 * H C B 1 60 8K F -1 21 T2 5
C 2 91 N C #2 V D D C #1 6 V1 7
C 29 0 V1 1 V D D C #1 7 V2 0 C 2 98 C 2 99 C 3 00 C 3 01 C 3 02 C3 0 3
*1 u _6 . 3V _ X5 R _ 04 *0 .1 u _1 0V _ X5 R _ 04 U1 1 N C #3 V D D C #1 8 Y 13
N C #4 V D D C #1 9 Y 16 *1 0u _ 6. 3 V _0 8_ H 1 25 *1 0 u_ 6. 3 V _0 8 _H 1 25 *1 0u _ 6. 3 V _0 8_ H 1 25 *1 0 u_ 6. 3 V _0 8_ H 1 25
V D D C #2 0 Y 18
V D D C #2 1 M 11 *1 0u _ 6. 3 V _0 8_ H 1 25 * 10 u_ 6. 3 V _0 8 _H 1 25
V D D C #2 2 M 12
MEM CLK V D D C #2 3
L1 7
N C _V D D R H A
L1 6
N C _V S S R H A
P C I E _ VD D R _ VG A PLL B IF _ V D D C
A M3 0
Fo r Se ym o u r,PCIE_ PV DD i s PC IE _ VDDR P C I E _ P VD D R 21
See Not e 1
MP V 18 BI F _ V D D C # 1 U 21
L8 BI F _ V D D C # 2
N C _MP V 1 8
C 30 4 C3 0 5
S P V1 8
H7 *1 u _6 . 3V _ X5 R _ 04 *1 u _6 . 3V _ X5 R _ 04
1. 0 V _R E G S P V 18 ISOLATED
L8 1 *10 u _6 . 3V _ 08 _H 12 5 H8 CORE I/O V D D C I # 1 M 13 V DDCI
S P V 10 M 15
* H C B 16 0 8K F -12 1 T2 5 C 30 6 C 3 07 C 30 8 V DDCI# 2 VDDCI V DDC
J7 M 16
N C1 SPVSS V DDCI# 3 M 17 2A80mil
*0 . 1 u_ 10 V _X 5R _0 4
V DDCI# 4 M 18
V DDCI# 5 M 20 *1 u _6 . 3V _ X5 R _ 04 L 82
* 1u _6 . 3V _ X 5R _ 04 V DDCI# 6 M 21
S H OR T SPVSS V DDCI# 7 N 20 *H C B1 6 08 K F -12 1T 25
V DDCI# 8 C 3 09 C 3 10 C 31 1 C 3 12 C3 1 3 C 3 14
0.9-1.12V @2A (DDR3) ??(GDDR5)
*1 u_ 6 . 3V _ X5 R _ 04 *1 u_ 6 .3 V _ X5 R _0 4
Warning:Select the correct Bead to
* 1u _6 . 3 V_ X 5R _ 0 4 *1 u_ 6. 3 V _X 5 R _0 4 *1 u_ 6. 3 V _X 5R _0 4 support expected VDDCI current. See
*R OB S ON X T S3 databook for details.
(Pa r k : 1 .8 V @7 5 m A M PV 1 8 ) MP V 18
L8 3 C 3 15 C 3 16
*H C B 1 60 8 K F-1 2 1T 25 C 31 7 C 3 20 C 3 21
*1 0u _ 6. 3 V _0 8_ H 1 25 *1 0u _ 6. 3 V _0 8_ H 1 25
*1 0u _6 . 3 V_ 0 8_ H 1 25 *1 u _6 . 3V _ X5 R _ 04
N ote 1
* 0. 1 u_ 1 0V _ X5 R _0 4 B FI _ V D D C V DDC
(1 .8 V @7 5 m A SPV 1 8) SP V 1 8 R 16 4 * 10 mi l_ s ho rt
L84
*H C B 1 60 8K F -1 21 T2 5 C 32 2 C 32 3 C 3 24
VDDCI and VDDC share one commo n regulator
1. No BACO Suppo rt:
*1 0u _6 . 3 V_ 0 8_ H 1 25 * 0. 1 u_ 10 V _X 5 R _0 4
BIF_VDDC sho rts with VDDC if
*1u _ 6. 3 V _X 5R _ 0 4 BACO is not su ppor ted
2. BACO Su pport :
SPVSS
Refer to the BACO r eferen ce schem atics/Application
no te for de ta ila bout BIF_VDDC Rail if BACO is
Suppo rted
Robson S3 Power 6/6 B - 13

Schematic Diagrams
Robson DDR3 MEM CH-A

CHANNEL A: 64M X 16 bit X8 DDR3 (RANK0) COMPONENTS SHOWN ARE EXAMPLES ONLY
AND NOT NECESSARILY QUALIFIED
U 7 U8
MV D D Q
V R E F C _U 7 M8 E3 D QA 0_ 11 D QA 0 _[ 1 5. . 8 ] 9 V R E FC _U 8 M8 E3 DQ A0 _ 27 D QA 0_ [ 31 . . 24 ] 9
V RE F CA D QL0 V RE F CA D QL0 C 33 3 C 3 34 C 33 5 C 3 36 C 33 7 C 3 38 C 33 9 C 3 40 C 34 1 C 3 42
V R E F D _U 7 H1 F7 D QA 0_ 9 V R E FD _U 8 H1 F7 DQ A0 _ 28
V RE F DQ D QL1 F2 D QA 0_ 8 V RE F DQ D QL1 F2 DQ A0 _ 25
*1u _ 6. 3 V_ X 5R _0 4
*1 u _6 . 3V _ X5 R _ 04
*1u _ 6. 3 V_ X 5R _0 4
*1 u _6 . 3V _ X5 R _ 04
*1 u_ 6. 3 V _X 5R _0 4
*0 . 1 u_ 10 V _X 5 R _0 4
* 0. 1 u_ 10 V _X 5 R _0 4
* 0. 1 u_ 10 V _X 5 R _0 4
*0 .1 u _1 0V _ X 5R _ 04
*0 . 1u _1 0V _ X 5R _ 04
N3 D QL2 F8 N3 D QL2 F8
MA A 0 D QA 0_ 10 MA A 0 DQ A0 _ 31
MA A 1 P7 A0 D QL3 H3 D QA 0_ 15 MA A 1 P7 A0 D QL3 H3 DQ A0 _ 29
MA A 2 P3 A1 D QL4 H8 D QA 0_ 12 MA A 2 P3 A1 D QL4 H8 DQ A0 _ 30
MA A 3 N2 A2 D QL5 G2 D QA 0_ 14 MA A 3 N2 A2 D QL5 G2 DQ A0 _ 24
9, 1 4 MA A [ 1 3. . 0 ] MA A 4 P8 A3 D QL6 H7 D QA 0_ 13 MA A 4 P8 A3 D QL6 H7 DQ A0 _ 26
MA A 0 MA A 5 P2 A4 D QL7 MA A 5 P2 A4 D QL7
MA A 1 MA A 6 R8 A5 MA A 6 R8 A5
MA A 2 MA A 7 R2 A6 D7 D QA 0_ 23 D QA 0 _[ 2 3. . 1 6] 9 MA A 7 R2 A6 D7 DQ A0 _ 3 D QA 0 _[ 7 . 0. ] 9
MV D D Q
MA A 3 MA A 8 T8 A7 D QU 0 C3 D QA 0_ 22 MA A 8 T8 A7 D QU 0 C3 DQ A0 _ 2
MA A 4 MA A 9 R3 A8 D QU 1 C8 D QA 0_ 18 MA A 9 R3 A8 D QU 1 C8 DQ A0 _ 5 C 35 4 C 3 55 C 35 6 C 3 57 C 35 8 C 3 59 C 36 0 C 3 61 C 36 2 C 3 63
L7 A9 D QU 2 C2 L7 A9 D QU 2 C2
Sheet 13 of 41 MA A 5 MA A1 0
A 10 / A P D QU 3
D QA 0_ 21 MA A 1 0
A 10 / A P D QU 3
DQ A0 _ 0
*1u _ 6. 3 V_ X 5R _0 4
*1 u _6 . 3V _ X5 R _ 04
*1u _ 6. 3 V_ X 5R _0 4
*1 u _6 . 3V _ X5 R _ 04
*1 u_ 6. 3 V _X 5R _0 4
*0 . 1 u_ 10 V _X 5 R _0 4
* 0. 1 u_ 10 V _X 5 R _0 4
* 0. 1 u_ 10 V _X 5 R _0 4
MA A 6 MA A1 1 R7 A7 D QA 0_ 16 MA A 1 1 R7 A7 DQ A0 _ 7
*0 .1 u _1 0V _ X 5R _ 04
*0 . 1u _1 0V _ X 5R _ 04
MA A 7 MA A1 2 N7 A 11 D QU 4 A2 D QA 0_ 19 MA A 1 2 N7 A 11 D QU 4 A2 DQ A0 _ 4
MA A 8 MA A 1 3 T3 A 12 / B C D QU 5 B8 D QA 0_ 17 MA A 13 T3 A 12 / B C D QU 5 B8 DQ A0 _ 6
MA A 9 T7 A 13 D QU 6 A3 D QA 0_ 20 T7 A 13 D QU 6 A3 DQ A0 _ 1
Robson DDR3 MEM M AA 1 0

M AA 1 1
M AA 1 2
M7
M2
A 14
A 15
D QU 7
B2
MV D D Q
M7
M2
A 14
A 15
D QU 7
B2
M VD D Q
MA A 13 9 ,1 4 A_ B A 0 9, 1 4 A_ BA0
CH-A 9 ,1 4
9 ,1 4
A_ B A 1
A_ B A 2
N8
M3
BA0
BA1
BA2
V D D # B2
VD D #D 9
VD D #G7
V D D # K2
D9
G7
K2
K8
9, 1 4
9, 1 4
A_ BA1
A_ BA2
N8
M3
B A0
B A1
B A2
VD D #B 2
V D D #D 9
V D D #G7
VD D #K 2
D9
G7
K2
K8
MV D D Q
C 37 5 C 3 76 C 37 7 C 3 78
V D D # K8 VD D #K 8
*1 0 u_ 6. 3 V _X 5R _0 6
*1 0 u_ 6. 3 V _X 5 R _0 6
N1 N1
*10 u _6 . 3V _ X5 R _ 06
*10 u _6 . 3V _ X5 R _ 06
J7 VD D #N 1 N9 J7 V D D #N 1 N9
9 C LK A 0 K7 CK VD D #N 9 R1 9 C LK A 0 K7 CK V D D #N 9 R1
9 C LK A 0 # K9 CK VD D #R 1 R9 9 C LK A 0# K9 CK V D D #R 1 R9
9 C K E A0 CKE VD D #R 9 9 C KE A 0 CKE V D D #R 9
MV D D Q M VD D Q
9 D QMA 0_ [ 3. . 0 ] OD T A 0 K1 A1 OD T A 0 K1 A1
D QMA 0 _0 L2 OD T V D D Q# A1 A8 L2 OD T V D D Q#A 1 A8
D QMA 0 _1 9 C S A 0b _0 J3 CS V D D Q# A8 C1 9 C S A 0 b_ 0 J3 CS V D D Q#A 8 C1
D QMA 0 _2 9 R A S A0 # K3 RAS V D D Q#C 1 C9 9 R AS A 0 # K3 RAS V D D Q #C 1 C9
D QMA 0 _3 9 C A S A0 # L3 CAS V D D Q#C 9 D2 9 C AS A 0 # L3 CAS V D D Q #C 9 D2
9 W EA 0 # WE V D D Q#D 2 E9 9 W E A 0# WE V D D Q #D 2 E9
V D D Q# E9 F1 V D D Q#E 9 F1
QS A 0 _1 F3 V D D Q# F1 H2 QS A 0_ 3 F3 V D D Q#F 1 H2
QS A 0 _2 C7 D QS L V D D Q#H 2 H9 QS A 0_ 0 C7 D QS L V D D Q #H 2 H9
9 QS A 0_ [ 3. . 0 ] D QS U V D D Q#H 9 D QS U V D D Q #H 9
Q SA 0 _0
Q SA 0 _1 D Q MA 0_ 1 E7 A9 D QMA 0 _3 E7 A9
Q SA 0 _2 D Q MA 0_ 2 D3 D ML V S S # A9 B3 D QMA 0 _0 D3 D ML V S S #A 9 B3
Q SA 0 _3 D MU V S S # B3 E1 D MU V S S #B 3 E1
V S S # E1 G8 V S S #E 1 G8
QS A 0 _1 B G3 V S S #G8 J2 QS A 0 _3 B G3 V S S #G8 J2
QS A 0 _2 B B7 D QS L V SS # J2 J8 QS A 0_ 0B B7 D QS L VS S # J2 J8 M VD D Q
D QS U V SS # J8 M1 D QS U VS S # J8 M1 MV D D Q
V S S #M1 M9 V S S #M1 M9
QS A0 _ 0B V S S #M9 P1 V S S #M9 P1
9 QS A 0_ 0 B QS A0 _ 1B T2 V S S # P1 P9 T2 V S S #P 1 P9 R1 7 0
9 QS A 0_ 1 B QS A0 _ 2B 9, 1 4 ME M_ R S T RESE T V S S # P9 T1 9, 1 4 ME M_R ST RESE T V S S #P 9 T1 R 1 69 * 4. 9 9K _ 1% _0 4
9 QS A 0_ 2 B QS A0 _ 3B L8 V SS # T1 T9 L8 VS S # T1 T9
9 QS A 0_ 3 B ZQ V SS # T9 ZQ VS S # T9 *4 . 99 K _1 %_ 04
V RE F C_ U8
V R E F C _U 7
R 1 65 *24 3_ 1 %_ 04 B1 R 1 66 * 24 3_ 1% _0 4 B1
V S S Q# B1 B9 V S S Q#B 1 B9 R1 7 4 C 3 26
V S S Q# B9 D1 V S S Q#B 9 D1 R 1 73 C 32 5 *0 . 1u _1 0V _ X5 R _ 04
OD T A0 V S S Q#D 1 D8 V SS Q #D 1 D8 * 0. 1 u_ 10 V _X 5R _0 4 * 4. 9 9K _ 1% _0 4
9 OD T A0 V S S Q#D 8 E2 V SS Q #D 8 E2 *4 . 99 K _1 %_ 04
J1 V S S Q# E2 E8 J1 V S S Q#E 2 E8
L1 N C # J1 V S S Q# E8 F9 L1 N C # J1 V S S Q#E 8 F9
J9 N C # L1 V S S Q# F9 G1 J9 N C # L1 V S S Q#F 9 G1
L9 N C # J9 V S S Q#G1 G9 L9 N C # J9 V SS Q #G1 G9
N C # L9 V S S Q#G9 N C # L9 V SS Q #G9 M VD D Q
10 0-B A LL 1 0 0-B A LL MV D D Q
SD R A M D D R 3 S D R AM D D R 3
* K 4W 1G 16 46 G-B C 11 * K4 W 1G1 6 46 G-B C 11 R1 7 8
R 1 77 * 4. 9 9K _ 1% _0 4
*4 . 99 K _1 %_ 04
V RE F D_ U8
V R E F D _U 7
R1 8 2 C 3 30
R 1 81 C 32 9 *0 . 1u _1 0V _ X5 R _ 04
* 0. 1 u_ 10 V _X 5R _0 4 * 4. 9 9K _ 1% _0 4
*4 . 99 K _1 %_ 04
9 C L KA 0
R 18 5
*5 6_ 04
R 18 6
*5 6_ 04 *0 . 0 1u _1 6V _ X7 R _ 04
9 C L KA 0 # C3 5 3
B - 14 Robson DDR3 MEM CH-A

Schematic Diagrams
Robson DDR3 MEM CH-B
C OMPONEN TS SHOWN AR E EXA MPLES ON LY

A ND N OT NE CE SSA RILY QUA LIFIED CHANNEL A: 64M X 16 bit X8 DDR3 (RANK1)
U1 1 U1 2
V R E F C _U 11 M8 E3 D QA 1 _0 D QA 1 _[ 1 5. . 8] 9 V R E F C _U 12 M8 E3 D QA 1 _2 1 D QA 1 _[ 2 3. . 16 ] 9
V R E F D _U 11 H1 V RE F CA D QL0 F7 D QA 1 _2 V R E F D _U 12 H 1 V RE F CA D QL0 F7 D QA 1 _2 2
V RE F DQ D QL1 F2 D QA 1 _7 V RE F DQ D QL1 F2 D QA 1 _1 6
MA A 0 N3 D QL2 F8 D QA1 _ 3 MA A 0 N3 D QL2 F8 D QA 1 _2 3
MA A 1 P7 A0 D QL3 H3 D QA 1 _6 MA A 1 P7 A0 D QL3 H 3 D QA 1 _1 8
MA A 2 P3 A1 D QL4 H8 D QA 1 _4 MA A 2 P3 A1 D QL4 H 8 D QA 1 _2 0
MA A 3 N2 A2 D QL5 G2 D QA 1 _5 MA A 3 N2 A2 D QL5 G 2 D QA 1 _1 9
9 ,1 3 MA A [ 1 3. . 0] P8 A3 D QL6 H7 P8 A3 D QL6 H 7
MA A 4 D QA1 _ 1 MA A 4 D QA 1 _1 7
MA A 0 MA A 5 P2 A4 D QL7 MA A 5 P2 A4 D QL7 MV D D Q
MA A 1
MA A 2
MA A 3
MA A 6
MA A 7
MA A 8
R8
R2
T8
R3
A5
A6
A7
A8
D QU 0
D QU 1
D7
C3
C8
D
D
QA1 _ 11
QA1 _ 12
D QA 1 _[ 7 . .0 ] 9 MA A 6
MA A 7
MA A 8
R8
R2
T8
R3
A5
A6
A7
A8
D QU 0
D QU 1
D 7
C 3
C 8
D QA 1 _2 8
D QA 1 _2 6
D QA 1 _[ 3 1. . 24 ] 9
C3 9 1 C 39 2 C 39 3 C 3 94 C 3 95 C 3 96 C 39 7 C 39 8 C 3 99 C 4 00 Sheet 14 of 41
* 1u _6 . 3V _X 5 R _0 4
*1 u_ 6. 3 V _X 5R _ 0 4
*1 u_ 6. 3 V _X 5 R _0 4
* 0. 1 u_ 10 V_ X 5R _ 04
*0. 1 u_ 10 V _X 5R _0 4
*0. 1 u_ 10 V _X 5 R _0 4
*0 . 1u _1 0V _ X5 R _ 04
*0 . 1u _1 0V _ X 5R _ 04
MA A 4 MA A 9 D QA1 _ 9 MA A 9 D QA 1 _3 1
*1u _6 . 3V _ X5 R _ 04
*1 u_ 6. 3V _ X 5R _ 04
A9 D QU 2 A9 D QU 2
Robson DDR3 MEM

MA A 5 MA A1 0 L7 C2 D QA1 _ 8 MA A1 0 L7 C 2 D QA 1 _2 4
MA A 6 MA A1 1 R7 A 1 0/ A P D QU 3 A7 D QA1 _ 14 MA A1 1 R7 A 1 0/ A P D QU 3 A7 D QA 1 _2 9
MA A 7 MA A1 2 N7 A1 1 D QU 4 A2 D QA1 _ 15 MA A1 2 N7 A1 1 D QU 4 A2 D QA 1 _2 5
MA A 8 MA A 1 3 T3 A 1 2/ B C D QU 5 B8 D QA1 _ 10 MA A 13 T3 A 1 2/ B C D QU 5 B8 D QA 1 _3 0
MA A 9 T7 A1 3 D QU 6 A3 D QA1 _ 13 T7 A1 3 D QU 6 A3 D QA 1 _2 7
MA A1 0
MA A1 1
MA A1 2
MA A 13
M7
M2
A1 4
A1 5
D QU 7
B2
MV D D Q
M7
M2
A1 4
A1 5
D QU 7
B2
MV D D Q
MV D D Q
CH-B
9 , 13 A _B A 0 N8 BA0 V D D # B2 D9 9 , 13 A _B A 0 N8 BA0 V D D #B 2 D 9
9 , 13 A _B A 1 BA1 VD D #D 9 9 , 13 A _B A 1 BA1 VD D #D 9 C4 1 2 C 41 3 C 41 4 C 4 15 C 4 16 C 4 17 C 41 8 C 41 9 C 4 20 C 4 21
M3 G7 M3 G 7
9 , 13 A _B A 2 BA2 VD D #G7 9 , 13 A _B A 2 BA2 VD D #G7
* 1u _6 . 3V _X 5 R _0 4
*1 u_ 6. 3 V _X 5R _ 0 4
*1 u_ 6. 3 V _X 5 R _0 4
K2 K2
* 0. 1 u_ 10 V_ X 5R _ 04
*0. 1 u_ 10 V _X 5R _0 4
*0. 1 u_ 10 V _X 5 R _0 4
*0 . 1u _1 0V _ X5 R _ 04
*0 . 1u _1 0V _ X 5R _ 04
*1u _6 . 3V _ X5 R _ 04
*1 u_ 6. 3V _ X 5R _ 04
9 D Q MA1 _ [3 . . 0] D QMA 1 _0 V D D # K2 K8 V D D #K 2 K8
D QMA 1 _1 V D D # K8 N1 V D D #K 8 N 1
D QMA 1 _2 J7 VD D #N 1 N9 J7 VD D #N 1 N 9
D QMA 1 _3 9 C LK A 1 K7 C K VD D #N 9 R1 9 C LK A 1 K7 C K VD D #N 9 R 1
9 C LK A 1 # K9 C K VD D #R 1 R9 9 C LK A 1 # K9 C K VD D #R 1 R 9
9 C K E A1 C KE VD D #R 9 9 C K EA 1 C KE VD D #R 9
MV D D Q MV D D Q
9 QS A1 _ [3 . . 0] K1 A1 K1 A1
QS A 1_ 0 OD T A 1 OD T A 1 MV D D Q MV D D Q
QS A 1_ 1 L2 O DT V D D Q# A1 A8 L2 O DT V D D Q#A 1 A8
QS A 1_ 2 9 C S A 1b _0 J3 C S V D D Q# A8 C1 9 C S A1 b_ 0 J3 C S V D D Q#A 8 C 1 C4 3 4 C 43 5 C 43 6 C 4 37
QS A 1_ 3 9 R A S A1 # K3 R AS VD D Q#C 1 C9 9 R A SA 1 # K3 R AS V D D Q #C 1 C 9
9 C A S A1 # L3 C AS VD D Q#C 9 D2 9 C A SA 1 # L3 C AS V D D Q #C 9 D 2 +C 83 8
* 10 u_ 6. 3 V_ X 5R _ 06
*10 u_ 6. 3 V _X 5 R _0 6
*1 0u _6 .3 V _X 5 R _0 6
*1 0u _6 . 3V _ X5 R _ 06
9 W EA 1 # WE VD D Q#D 2 E9 9 WE A 1 # WE V D D Q #D 2 E9
QS A 1_ 0B V D D Q# E9 F1 V D D Q#E 9 F1 * 22 0u _4 V _V _A
9 QS A 1_ 0B QS A 1_ 1B QS A 1 _0 F3 V D D Q# F1 H2 QS A 1_ 2 F3 V D D Q#F 1 H 2
9 QS A 1_ 1B QS A 1_ 2B QS A 1 _1 C7 D QS L VD D Q#H 2 H9 QS A 1_ 3 C7 D QSL V D D Q #H 2 H 9
9 QS A 1_ 2B QS A 1_ 3B D QS U VD D Q#H 9 D QSU V D D Q #H 9
9 QS A 1_ 3B
D Q MA 1_ 0 E7 A9 D QMA 1 _2 E7 A9
D Q MA1 _ 1 D3 D ML VS S # A9 B3 D QMA 1 _3 D3 D ML V S S #A 9 B3
D MU VS S # B3 E1 D MU V S S #B 3 E1
VS S # E1 G8 V S S #E 1 G 8
QS A 1 _0 B G3 V S S #G8 J2 QS A 1_ 2B G3 V S S #G8 J2
QS A 1 _1 B B7 D QS L V SS # J2 J8 QS A 1_ 3B B7 D QSL V SS # J2 J8
D QS U V SS # J8 M1 D QSU V SS # J8 M1 MV D D Q MV D D Q
V S S #M1 M9 V S S #M1 M9
V S S #M9 P1 V S S #M9 P1
T2 VS S # P1 P9 T2 V S S #P 1 P9
9 , 13 ME M_ R S T R ES E T VS S # P9 T1 9 , 13 ME M_ R S T R ES E T V S S #P 9 T1
9 O D TA 1 OD T A 1 R 22 4 R 2 25
L8 V SS # T1 T9 L8 V SS # T1 T9 *4. 9 9K _ 1% _0 4 * 4. 99 K _1 %_ 04
ZQ V SS # T9 ZQ V SS # T9
R 20 5 R 20 6 V R E F C _ U 11 V R E F D _U 1 1
*24 3_ 1% _0 4 B1 *24 3_ 1% _0 4 B1
V S S Q# B1 B9 V S S Q#B 1 B9
9 C LK A 1 V S S Q# B9 V S S Q#B 9
D1 D 1 R 23 2 C 3 87 R 2 33 C 38 8
R 23 6 V S S Q#D 1 D8 V S SQ #D 1 D 8 *0 . 1u _1 0V _ X5 R _0 4 *0. 1 u_ 10 V _X 5R _ 04
*56 _0 4 V S S Q#D 8 E2 V S SQ #D 8 E2 *4. 9 9K _ 1% _0 4 * 4. 99 K _1 %_ 04
J1 V S S Q# E2 E8 J1 V S S Q#E 2 E8
L1 N C #J 1 V S S Q# E8 F9 L1 N C #J 1 V S S Q#E 8 F9
R 23 7 C 41 1 J9 N C #L 1 V S S Q# F9 G1 J9 N C #L 1 V S S Q#F 9 G 1
*56 _0 4 *0 .0 1u _ 16 V_ X7 R _ 04 L9 N C #J 9 V S S Q#G1 G9 L9 N C #J 9 V S SQ #G1 G 9
N C #L 9 V S S Q#G9 N C #L 9 V S SQ #G9
9 C LK A 1#
1 00 -BA L L 10 0 -B A L L
S DRA M DDR3 S DRA M DDR3
*K 4 W1 G16 4 6G-B C 1 1 *K 4W 1 G16 46 G-B C 11
MV D D Q MV D D Q
R 22 6 R2 2 7
*4 .9 9 K_ 1% _0 4 * 4. 9 9K _1 %_ 04
VR EF C _ U 12 V R E F D _U 1 2
R 23 4 C 3 89 R2 3 5 C 39 0
*0 . 1u _1 0V _ X5 R _0 4 *0. 1 u_ 10 V _X 5R _ 04
*4 .9 9 K_ 1% _0 4 * 4. 9 9K _1 %_ 04
Robson DDR3 MEM CH-B B - 15

Schematic Diagrams
HUDSON PCIE/ PCI/ CLOCK/ FCH

C4 4 1 1 50 p F _N P O_ 5 0V _ 0 40 2
U 19 E
HU DS ON P CI E/P CI /C LO CK /FC H
HU DS ON -1 PA RT 1 O F 5
P C I E _ R S T # _C P1 W2
P CI E_RS T# P CI CLK0
R2 4 1 33 _ 04 A _ R S T # _C L1 W1 P CI_ CL K 1 _ R R2 4 2 22 _ 0 4
27 E C_ RS T # A _RST # PC IC LK1/ GP O36 W3 PCL K _ K B C 1 6
PC IC LK2/ GP O37
P CI_ CL K 2 _ R R2 4 0 22 _ 0 4 P CI_ CL K 2 1 6
C4 4 4 0. 1 u _1 0 V _ X7 R _ 0 4 U_ RX 0 P _ C A D2 6 W4 P CI_ CL K 3 _ R R2 4 3 22 _ 0 4
2 C_ UM I _ P _R X0 U_ RX 0 N_ C A D2 7 U MI _TX 0P PC IC LK3/ GP O38 Y1 P CI_ CL K 4 _ R P CI_ CL K 3 1 6
2 C_ UM I_ N_ RX 0 C4 4 5 0. 1 u _1 0 V _ X7 R _ 0 4 U MI _TX 0N PC C
I LK4/ 14M _OS C/ GP O39
R2 4 4 22 _ 0 4 P CI_ CL K 4 1 6
C4 4 3 0. 1 u _1 0 V _ X7 R _ 0 4 U_ RX 1 P _ C A C2 8
2 C_ UM I _ P _R X1 U_ RX 1 N_ C A C2 9 U MI _TX 1P P CI C LKS V2 P C I R S T# _ R P C I _R S T#
2 C_ UM I_ N_ RX 1 C4 4 6 0. 1 u _1 0 V _ X7 R _ 0 4 U MI _TX 1N PC IR ST#
R2 4 5 *3 3 _0 4
C4 4 7 0. 1 u _1 0 V _ X7 R _ 0 4 U_ RX 2 P _ C AB2 9
2 C_ UM I _ P _R X2 U MI _TX 2P
C4 4 8 0. 1 u _1 0 V _ X7 R _ 0 4 U_ RX 2 N_ C AB2 8 C4 4 9 *1 50 p F _ N P O_ 5 0V _ 0 4 02 Re se rve
2 C_ UM I_ N_ RX 2 U_ RX 3 P _ C AB2 6 U MI _TX 2N AA1
2 C_ UM I _ P _R X3 C4 5 0 0. 1 u _1 0 V _ X7 R _ 0 4 U MI _TX 3P AD0/ G PI O0
C4 5 1 0. 1 u _1 0 V _ X7 R _ 0 4 U_ RX 3 N_ C AB2 7 AA4
2 C_ UM I_ N_ RX 3 U MI _TX 3N AD1/ G PI O1 AA3
PCI EXP RE SS I /F AD2/ G PI O2
C 7 50
AE2 4 AB1 P CL K _ K B C R 5 13 *1 0 _0 4 P C L K _ K B C _ R
2 C_ U MI _ P _T X 0 U MI _RX 0P AD3/ G PI O3
AE2 3 AA5
2 C_ U MI _ N _ TX 0 A D2 5 U MI _RX 0N AD4/ G PI O4 AB2
U MI _RX 1P AD5/ G PI O5
*1 0 p _5 0 V _N P O_ 0 6
2 C_ U MI _ P _T X 1 A D2 4 AB6
2 C_ U MI _ N _ TX 1 A C2 4 U MI _RX 1N AD6/ G PI O6 AB5
2 C_ U MI _ P _T X 2 A C2 5 U MI _RX 2P AD7/ G PI O7 AA6 B T _ ON 2 4, 2 8
2 C_ U MI _ N _ TX 2 U MI _RX 2N AD8/ G PI O8
AB2 5 A C2 MX M_ P R E S E N T 2# R6 8 6 * 0_ 0 4
2 C_ U MI _ P _T X 3 AB2 4 U MI _RX 3P AD9/ G PI O9 A C3
12/9 U MI _RX 3N AD10/ G PI O10
MX M_ P R E S E N T 1# R2 4 7 2 0 K _0 4 3 . 3V S
2 C_ U MI _ N _ TX 3 A C4
CA L RP A D2 9 AD11/ G PI O11 A C1
1. 1 V S R 24 9 5 90 P CI E_CA LRP AD12/ G PI O12
3 .3 V
R 25 0 2 K _1 % _0 4 CA L RN A D2 8 A D1
P CI E_CA LRN AD13/ G PI O13 A D2
AD14/ G PI O14
U1 7 C4 6 0
AA2 8 A C6
5
C4 5 2 0. 1 u _1 0 V _ X7 R _ 0 4 F C H _G P P T XP 0 G PP _TX0P AD15/ G PI O15
* 74 A H C 1 G0 8G W
2 3 P C I E _ TX P 0 _ JM C C4 5 3 0. 1 u _1 0 V _ X7 R _ 0 4 F C H _G P P T XN 0 AA2 9 AE2 R 80 5 * 0_ 0 4 1 0 . 1u _ 16 V _ Y 5 V _ 04
2 3 P C I E _ TX N 0_ J MC F C H _G P P T XP 1 Y2 9 G PP _TX0N AD16/ G PI O16 AE1 1 6 P C I E _ R S T # _G A T E 4
2 6 P C I E _ N B _ U S B 30 _ TX P C4 5 4 *0 . 1u _ 1 0V _ X 7R _0 4 G PP _TX1P AD17/ G PI O17
R 8 06 *0 _ 0 4 R 2 51 3 3_ 0 4 B U F _ P L T_ R S T # 1 9, 2 3 , 24 , 2 6 , 27
C4 5 5 *0 . 1u _ 1 0V _ X 7R _0 4 F C H _G P P T XN 1 Y2 8 AF8 P C I E _R S T# _ C 2
2 6 P C I E _ N B _ U S B 30 _ TX N Y2 6 G PP _TX1N AD18/ G PI O18 AE3 C 45 7
Y2 7 G PP _TX2P AD19/ G PI O19 AF1

G PP _TX2N AD20/ G PI O20
3
C8 2 2 0. 1 u _1 0 V _ X7 R _ 0 4 F C H _G P P T XP 3 W28 A G1 MX M_ GP I O0 15 0 pF _ N P O_ 50 V _ 04 0 2
24 P C I E _T X P 3_ W L A N F C H _G P P T XN 3 W29 G PP _TX3P AD21/ G PI O21 AF2 M XM _G P I O0 7
C8 2 3 0. 1 u _1 0 V _ X7 R _ 0 4 G PP _TX3N AD22/ G PI O22
R 2 52 0 _0 4
24 P C I E _T X N 3 _ W LA N AE9 3 . 3V S
AA2 2 AD23/ G PI O23 A D9
2 3 P C I E _ R X P 0 _J MC G PP _RX0P AD24/ G PI O24
R6 8 7 * 10 K _ 0 4 P CE
I _ R ST # I S F OR PC I E D E V I C ES ON H U D SON
Y2 1 A C1 1 R6 8 8 * 10 K _ 0 4
2 3 P C I E _ R X N 0 _ JM C G PP _RX0N AD25/ G PI O25
AA2 5 AF6 3 .3 V
2 6 P C I E _ U S B 30 _ N B _ R X P AA2 4 G PP _RX1P AD26/ G PI O26 AF4
2 6 P C I E _ U S B 30 _ N B _ R X N G PP _RX1N AD27/ G PI O27
W23 AF3 U1 8 C4 6 1
Sheet 15 of 41 V2 4 G PP _RX2P AD28/ G PI O28 A H2 M XM _P W R GD 36
5
G PP _RX2N AD29/ G PI O29
* 74 A H C 1 G0 8G W W 250 BAQ ad d R2 53 , R2 54
W24 A G2 GP I O 30 S B _A R S T #_ GA T E 1 0 . 1u _ 16 V _ Y 5 V _ 04
24 P C I E _R X P 3_ W L A N W25 G PP _RX3P AD30/ G PI O30 A H3 GP I O 31 4
24 P C I E _R X N 3 _W L A N G PP _RX3N AD31/ G PI O31
R 2 53 *3 3 _0 4 P CIE _ A RS T # 7
AA8 A _R S T# _ C 2
HUDSON PCIE/
C BE0#
A D5 C 45 9
P CI I/ F C BE1# A D8
C BE2#
3
AA1 0 *1 50 p F _N P O_ 5 0V _ 0 4 02
C BE3# AE8
PCI/ CLOCK/ FCH M2 3

P2 3 P CI E_RC LKP /N B_LNK _CLKP
P CI E_RC LKN /N B_LNK _CLKN
F RAM E#
DEV SEL#
IR DY#
TR DY#
AB9
AJ 3
AE7
R 2 54 *0 _ 04
P C I E _A R S T # I S F O R P C I E D E V I C E S ON F T1
D I S P _ C L K : C P U (no n -s pre a d) A C5
U2 9 P AR AF5
3 D I S P _C LK P U2 8 N B_DI SP _CLK P STO P# AE6
P C I E _ R C L K : (S p re ad , F U S I ON M OD E ) N B_DI SP _CLK N PE RR#
3 D I S P _C LK N AE4
T2 6 SE RR# AE1 1 B OA R D I D
N B_HT _CLK P RE Q0#
3 .3 V S
T2 7 A H5 MX M_ GP I O2 GP I O 31 GP I O 3 0 1 .8 V S
N B_HT _CLK N RE Q1#/ G PI O40 A H4
RE Q2#/ CLK _RE Q8#/ G PI O41
0 0 W 2 4 0B U
V2 1 A C1 2 W 25 0 B U Q
3 A P U _C LK P T2 1 C PU_H T_C LKP RE Q3#/ CLK _RE Q5#/ G PI O42 A D1 2
C PU_H T_C LKN G NT0#
R 2 56 R2 5 5 1 0 W 2 5 0B A Q
3 A P U _C LK N AJ 5 * 20 K _ 04 * 2 0K _ 0 4 R2 5 7
GN T1#/ GP O44
V2 3 A H6 MX M_ GP I O1
7 V GA _ P C I E C L K _P T2 3 S LT_G FX_ CLKP GN T2#/ GP O45 AB1 2 U S B 3 0 _C L K R E Q# MX M_ GP I O 1 7 , 3 6 GP I O3 1
S LT_G FX_ CLKN G NT3#/ CLK _RE Q7#/ G PI O46
2 0 K _0 4
7 V GA _ P C I E C L K _N AB1 1 R 8 12 *2 2 _ 04 GP I O3 0
L2 9 CLKR UN# A D7 P C I _ C L K R U N # 19 L D T _ S TP #
2 3 C LK _ P C I E _J MC L2 8 G PP _CLK0 P LO CK#
G PP _CLK0 N
22 p _ 50 V _ N P O _0 4
2 3 C LK _ P C I E _J MC # AJ 6 S B _ A R S T # _G A TE R 2 59 R2 5 8 C4 6 2
N2 9 IN TE#/ G PI O32 A G6
G PP _CLK1 P IN TF#/ G PI O33
2 0 K _0 4 2 0K _ 0 4
2 4 CL K_ P CIE _ W L A N N2 8 A G4 * MC -1 4 6 _3 2 . 76 8 K H z
2 4 CL K_ P CIE _ W L A N# G PP _CLK1 N I NT G#/ G PI O34 AJ 4
2
1
2
1
IN TH#/ G PI O35
X4
M2 9 X3
G PP _CLK2 P
FC H _GP P D EV I C E C L KR E Q# M2 8
G PP _CLK2 N
R2 6 0 1T J S 1 25 D J 4 A 4 20 P _ 32 . 7 6 8K H z
3
4
3
4
GF X_ C LK MX M G T2 5 3 2K _ X 1 1 0 M_ 0 4
V2 5 G PP _CLK3 P H2 4 L P CCL K _ 0
0 J MC 2 61C 0 G PP _CLK3 N LPC CLK0
R 2 61 2 2 _0 4 L P C _ C L K 0 1 6, 2 7
1 W LA N 1 H2 5 L P CCL K _ 1 R 2 62 2 2 _0 4 3 2K _ X 2 C4 6 3
CLO CK G EN ERA TO R LPC CLK1
L PC_ CL K 1 1 6
2 N A NA L2 4 J 27
3 N A NA L2 3 G PP _CLK4 P LAD0 J 26 L P C _ A D 0 1 9, 2 7
R2 7 1 * 0_ 0 4
Zo= 50O? 5% 22 p _ 50 V _ N P O _0 4
G PP _CLK4 N LAD1 L P C _ A D 1 1 9, 2 7 P C LK _ T P M 1 9
4 N A NA H2 9
P2 5 LP C LAD2 H2 8 L P C _ A D 2 1 9, 2 7
5 N A NA G PP _CLK5 P LAD3 L P C _ A D 3 1 9, 2 7
6 N A NA M2 5 G2 8
G PP _CLK5 N LF RAM E# J 25 LP C _F R A ME # 1 9, 27
7 U S B3 .0 7 LDR Q0#
8 N A NA P2 9 AA1 8
G PP _CLK6 P LDR Q1#/ CLK _RE Q6#/ G PI O49
P2 8 AB1 9 S E RIR Q D4 6 A_ VBAT
G PP _CLK6 N S ER IR Q/ G PI O48 S E RIR Q 1 9, 2 7
20m i ls B A T 54 C W GH
2 6 P C I E _ U S B 3 0 _C LK P
N2 6
G PP _CLK7 P
R 59 5 *1 0K _ 0 4
3 . 3V
VDD 3 R 2 63 1 K _ 04 1 A 20mi ls
N2 7 C 3 C 4 64 1u _ 6 . 3V _ Y 5 V _ 0 4
2 6 P C I E _ U S B 3 0 _C LK N G PP _CLK7 N G2 1 2
A L L OW _ L D T S TP 3 R T C _ V B A T _1 A
ALLO W_LDT STP / DM A_AC TI VE#
R6 8 9 2 2_ 0 4 T2 9 H2 1
2 3 JM C _ 2 5M _I N T2 8 G PP _CLK8 P P RO CHO T# K1 9 P R OC H OT # 3
G PP _CLK8 N LDT_P G A P U _P W R GD 3, 3 5
C4 6 5 22 P _ 50 V _ N P O _0 4 G2 2 L D T _S T P # R 2 65 INT RUD E R_ A L E RT #
C PU LDT_S TP# J 24
L2 5 LDT_R ST# L DT _ RST # 3
C4 6 6 * 1 M_ 04
14M _25M _48M _OS C
* 1u _ 6 . 3V _ X 5R _ 04 R 26 6
C1 32 K _ X1
1
1
32K_X1 J _R TC 2
X5 R 2 67 J _ RT C1 10mi l s 1 K _ 04
F S X 5L _ 2 5M H Z 2 5M _X 1 L2 6 C2 32 K _ X2 J OP E N 1
25M _X1 R TC 32K_X2 1 1
1 M _0 4 *O P E N _ 1 0m i -l 1 M M
2
2
D2 A_ VBAT
RTC CLK B2 2 2
IN TR UDE R_ALE RT#
I NT RUD E R_ AL E RT #
C4 6 7 22 P _ 50 V _ N P O _0 4 2 5M _X 2 L2 7 V B A T_ I N R 2 6 8 5 1 0_ 1 % _0 4 *8 5 20 5 -0 27 0 1 A A A -B A T -02 2 -K 0 1
25M _X2 VD DBT _RTC _G
B 1
H U D S ON M1 A 1 3 C4 6 8
1 u_ 6 . 3V _X 5 R _ 04
B - 16 HUDSON PCIE/ PCI/ CLOCK/ FCH

Schematic Diagrams
HUDSON GPIO/ USB/ STRAP

HUDSON GPIO/USB/AUDIO/STRAP
U1 9 A
HUDSON-1 P AR T 4O F 5
R 6 92 0 _0 4
S W I # R7 3 0 *0 _0 4 J2 A 10
K1 PCI _P ME #/G E VEN T4# U SB CLK/ 14M _25M _48M _O SC
R6 9 0 *0 _ 0 4 3 . 3V
2 0, 2 7 , 2 9 LI D _ S W # D3 RI #/G E VEN T22# G1 9 U S B _ R C OM P
SPI _C S3#/ G BE_S TA T1/ G EVE NT 21# U SB _RC OM P R 2 72 1 1 K _1 % _ 0 4
F1
1 9 , 2 6, 2 7 , 3 0 S U S B # H1 SLP_ S3# U SB M I SC R 2 73 R S MR S T #
2 7 , 3 0, 3 2 S US C # SLP_ S5# * 2 2K _ 0 4
R6 9 1 0_ 0 4 F2
27 P W R _ B TN # H5 PWR _BTN #
19 S B _ P W R GD PWR _GO O D USB 1. 1
R8 1 3 *0 _0 4 S U S _ S T A T # G6 J1 0 C 4 69
19 S 4 _ S T A TE # B3 SUS _ST AT# US B_F SD 1P/ GP I O186 H1 1
R7 4 2 *2 . 2 K _0 4 TES T0 USB _FS D1N R2 7 4
R7 4 3 *2 . 2 K _0 4 C4 * 2 . 2u _ 6 . 3V _X 5 R _ 0 4
3 . 3V F6 TES T1/ TM S H9
R7 4 4 *2 . 2 K _0 4 TES T2 US B_F SD 0P/ GP I O185 *2 0 K _ 04
D
R 2 75 0 _ 04 GE V E N T 0# AD2 1 J8
27 GA 2 0 GE V E N T 1# AE2 1 GA 20I N/ GE VE NT0# USB _FS D0N
R 2 70 0 _ 04 KBR ST #/G E VEN T1# Q6
27 K B C _ R S T# K2 B 12 G *M T N 7 0 02 Z H S 3
27 E C _S C I # J2 9 LPC_ PM E#/ G EVE NT 3# U SB _HS D13P A 12 2 7 R S M R S T _ GA TE #
LPC_ SM I#/ G EV ENT 23# U SB _HS D13N
S
2 6, 2 7 E C _S MI # S W I # R7 3 1 0_ 0 4 H2
27 S W I# J1 GE VE NT5# F 11
S Y S _ R S T# SYS _RE SET #/ GE VE NT19 # U SB _HS D12P
3 . 3V 19 S Y S _ RS T # H6 E 11
2 3 , 2 4, 26 P C I E _ W A K E # F3 WAK E#/ GE VE NT8# U SB _HS D12N
23 J M_ D 3M OD E IR _RX 1/G EV EN T20#
J6 E 14
3 C P U _ T H E R MT R I P # AC1 9 THR M TRI P# S
/ MB ALE RT# /G EV EN T2# U SB _HS D11P E 12
R2 8 2 N B _ P W R GD NB_P WRG D U SB _HS D11N
1 0K _ 0 4
G1 A CPI / WAK E UP E VE NTS J1 2
RS M RS T # RSM R ST# U SB _HS D10P
S Y S _R S T # J1 4
AD1 9 U SB _HS D10N
CLK_ REQ 4#/ SA TA_ IS 0#/G P O
I 64
C4 7 1 AA1 6 A 13 3 . 3V S
AB2 1 CLK_ REQ 3#/ SA TA_ IS 1#/G P O
I 63 USB _HS D9P B 13 U S B _P P 9 22
1 u _6 . 3 V _ Y 5 V _ 0 4 U SB9 3G
1 5 P C I E _ R S T# _ GA T E SM AR TVO LT 1/S AT A_I S2#/ G PI O 50 USB _HS D9N U S B _P N 9 22
AC1 8 R 2 76 2 .2 K_ 0 4 S CL K 0
AF 2 0 CLK_ REQ 0#/ SA TA_ IS 3#/G P O
I 60 D1 3
MX M_ P W R _ E N R 2 77 2 .2 K_ 0 4 S DA T A 0
7 M XM _P W R _ E N AE1 9 SAT A_I S4#/ F ANO U T3/ GP I O55 USB _HS D8P C1 3 N B _ P W R GD
SAT A_I S5#/ F ANI N3 /G PI O 59 USB _HS D8N R 2 78 4 .7 K_ 0 4
AF 1 9 R 2 79 4 .7 K_ 0 4 S US _ S T A T #
25 H DA _ S P K R AD2 2 SPK R/ G PI O 66 G1 2
5 , 6, 10 S CL K 0 AE2 2 SCL0 G
/ PI O 43 USB _HS D7P G1 4
3 .3 V
5 , 6, 10 S DA T A 0 S CL K 1 F5 SDA 0/ GP O
I 47 USB _HS D7N
F4 SCL1 G
/ PI O 227 USB 2. 0 G1 6
S DA T A 1 P LA C E C L O S E T O S O U T H B R I D GE
R 28 0
* 20 K _ 0 4
2 4 W L A N _ C L K R E Q#
AH2 1
AB1 8
E1
SDA 1/ GP O
I 228
CLK_ REQ 2#/ FA NI N4/ G PI O 62
CLK_ REQ 1#/ FA NO UT 4/G P O
IR _LED #/LLB #/ GP O
I 184
I 61
USB _HS D6P
USB _HS D6N
USB _HS D5P

G1 8
D1 6
U S B _P P 6
U S B _P N 6
U S B _P P 5
28
28
22
U SB6 B L U E T O OT H
3 . 3V
Sheet 16 of 41
HUDSON GPIO/
W F _ RA D IO A J2 1 C1 6 U SB5 CC D
H4 SM AR TVO LT 2/S HU TDO WN #/G P O
I 51 USB _HS D5N U S B _P N 5 22 S Y S _ R S T#
DDR 3_RS T#/ G EVE NT 7#
R 2 81 * 2 . 2K _0 4
C4 7 0 D5 B 14 R 2 88 2 .2 K_ 0 4 S CL K 1
W F _ RA D IO D7 GB E_LE D0/ G PI O18 3 USB _HS D4P A 14 U S B _P P 4 29 S DA T A 1
*0 . 1u _ 1 6 V _Y 5 V _0 4 GB E_LE D1/ G EVE NT 9# USB _HS D4N U S B _P N 4 29 U SB4 P OR T 3 R 2 84 2 .2 K_ 0 4
8 S B _ MX M _C L K R E Q #
R 2 96 0 _ 04
G5
K3
AA2 0
GB E_LE D2/ G EVE NT 10#
GB E_S TAT 0/ GE VE NT11#
CLK_ REQ G #/ GP IO 65/ O SC IN
USB _HS D3P
USB _HS D3N
E 18
E 16 R
R
3 10
3 12
1 0 K_ 0 4
1 0 K_ 0 4
9/14
SC L K2
SD ATA2
USB/ STRAP
GP IO
J1 6 R 3 13 * 2 . 2K _0 4 A P U _ S IC
H3 USB _HS D2P J1 8 U S B _ P P 2 24
BLI NK U
/ SB_ OC 7#/G E VEN T18# USB _HS D2N
U SB2 MI N I C A R D R 3 14 * 2 . 2K _0 4 A P U _ S ID
D1 U S B _ P N 2 24
E4 USB _O C6#/ I R_TX 1/ GE VE NT6# B 17
USB _O C5#/ I R_TX 0/ GE VE NT17# USB _HS D1P U S B _P P 1 29 R 2 91 1 0 K_ 0 4 S W I#
D4 A 17 U SB1 P OR T 1
2 4 OD D _ D A # _ F C H E8 USB _O C4#/ I R_RX 0/ GE VE NT16# USB _HS D1N U S B _P N 1 29
USB _O C3#/ AC _PRE S/ TD O /G EV EN T15#
R 2 92 1 0 K_ 0 4 E C_ S C I#
2 4 OD D _ D E T E C T# F7 A 16 R 2 93 1 0 K_ 0 4 E C_ S M I#
E7 USB _O C2#/ TC K/ GE VE NT 14# USB _HS D0P B 16 U S B _P P 0 29
USB _O C1#/ TD I/ G EV ENT 13# USB _HS D0N U S B _P N 0 29 U SB0 P OR T 0
26 , 2 9 U S B _ O C P 0 _ 1# F8
2 6 U S B 3 0 _P W R _ E N USB _O C0#/ TR ST#/ G EV EN T12#
U SB O C
8/18
Closed to SB. R 4 70 3 3 _0 4 M3
HD AUD IO
D2 5 S C LK 2 R 6 93 *0 _ 0 4
25 H D A _B I TC LK N1 AZ_B I TCLK SC L2/ GP I O193 F 23 S MC _C P U _ T H E R M 3, 1 7 , 2 7
R 4 69 3 3 _0 4 SD ATA2 R 6 94 *0 _ 0 4
25 H D A _S D OU T L2 AZ_S DO UT SD A2/ GP I O194 B 26 S MD _C P U _ T H E R M 3, 1 7 , 2 7
25 H D A _S D I N 0 AZ_S DI N0/ G PI O 167 SCL3_ LV/ GP I O195 R 7 28 *0 _ 0 4 A P U_ S IC 3
M2 E 26 R 7 52 *0 _ 0 4
20 S B _ B L ON M1 AZ_S DI N1/ G PI O 168 S DA3_ LV/ GP I O196 F 25 A P U_ S ID 3 A Z_SD O UT P CI _CLK 1 PC _
I C LK2 P CI _CLK 3 PC I_C LK4 L PC_C LK0 L PC_C LK1 MIN I PCI E _SLT3_ EN# MI NI PCI E _SLT2 _EN#
M4 AZ_S DI N2/ G PI O 169 EC_P WM 0/E C_T IM E R0/ GP I O197 E 22 P ULL LO W PO WE R A LLO W Wat chdog U SE non_F usion EC C LKG E N G PI O 200 G PI O 199
N2 AZ_S DI N3/ G PI O 170 EC_P WM 1/E C_T IM E R1/ GP I O198 F 22 M I N I P C I E _ S L T2 _ E N # H IG H MO DE PC IEG en2 Ti mer D EB UG CLO C K MO D E E NA BLE D E NA BLE D H, H = R eser ved
25 H DA _ S Y N C R 4 73 3 3 _0 4 AZ_S YN C EC_P WM 2/E C_T IM E R2/ GP I O199
R 6 95 3 3 _0 4 P2 E 21 M I N I P C I E _ S L T3 _ E N # P ERF O RMAN CE F OR CE Enabl ed S TR AP D EF AU LT H, L = SP I R OM
25 H DA _ RS T # AZ_R ST # EC_P WM 3/E C_T IM E R3/ GP I O200 MO DE P CI E G en1 Wat chdog I G NO RE FU SI O N EC C LKG E N
G2 4 P ULL D EFA ULT D EFA ULT Ti mer D EB UG CLO C K MO D E D I SAB LED D I SAB LED L, H = LPC RO M ( DE FAU LT)
GB E _C OL T1 K SI _0/ GP I O201 G2 5 LO W Di sabled S TR AP DEFAU LT D EF AUL T L, L = FWH R OM

R2 8 5 10 K _ 0 4 GB E_C OL G B E LAN K SI _1/ GP I O202
R2 8 6 10 K _ 0 4 GB E _C R S T4 E 28 DE FAU LT D EF AULT
L6 GB E_C RS K SI _2/ GP I O203 E 29
GB E_M DC K K SI _3/ GP I O204
R 2 83 1 0 K _0 4 L 5 D2 9
3 .3 V T9 GB E_M DI O K SI _4/ GP I O205 D2 8
GB E_R XCLK K SI _5/ GP I O206
U1 C2 9 V D DIO _ A Z 3 .3 V S 3 . 3V
U3 GB E_R XD3 K SI _6/ GP I O207 C2 8
GB E_R XD2 K SI _7/ GP I O208
T2
U2 GB E_R XD1 B 28
GB E_R XD0 K SO _0/ GP I O209
T5 A 27
GB E_R XCT L/ RXD V K SO _1/ GP I O210
R2 8 7 1 0 K _0 4 G B E _ RX E RR V 5 GB E_R XER R K SO _2/ GP I O211
B 27
P5 D2 6 R 3 68 R 3 69 R 3 7 0 R 3 71 R3 7 2 R 3 7 3 R 37 4 R 3 7 5 R 37 6
M5 GB E_T XCLK K SO _3/ GP I O212 A 26
GB E_T XD3 K SO _4/ GP I O213
1 0 K_ 0 4
3 . 3V P9 C2 6
* 1 0K _ 0 4
*1 0 K _ 0 4
*1 0 K _ 0 4
10 K _ 0 4
1 0 K _0 4
*1 0 K _ 04
*1 0 K _ 04
*1 0 K _0 4
T7 GB E_T XD2 K SO _5/ GP I O214 A 24
GB E_T XD1 K SO _6/ GP I O215
P7 B 25
M7 GB E_T XD0 K SO _7/ GP I O216 A 25
R2 8 9 GB E_T XCT L/ TXE N K SO _8/ GP I O217 H D A _ S D OU T R 3 77 10 K _ 0 4
*1 0 K _ 04 P4 D2 4 R 3 78 *1 0K _0 4
M9 GB E_P HY_P D K SO _9/ GP I O218 B 24 15 PC L K_ KBC
3 .3 V GB E_P HY_R ST # K SO _10/ GP I O219 R 3 79 10 K _ 0 4
GB E _P H Y _ I N TR GB E _ P H Y _ I N T R V7 C2 4 15 P C I_ CL K 2
GB E_P HY_I N TR K SO _11/ GP I O220 15 P C I_ CL K 3 R 3 80 10 K _ 0 4
B 23 R 3 81 10 K _ 0 4
K SO _12/ GP I O221 15 P C I_ CL K 4
R2 9 0 E2 3 A 23 R 3 82 10 K _ 0 4
E2 4 PS2_ DAT S
/ DA 4/G P O
I 187 K SO _13/ GP I O222 D2 2 1 5 , 27 L P C _C L K 0
1 0K _ 0 4 R 8 07 R 3 83 *1 0K _0 4
F21 PS2_ CLK/ SC L4/ GP I O188 K SO _14/ GP I O223 C2 2 15 L P C _C L K 1
* 1 0K _0 4 SPI _C S2#/ G BE_S TA T2/ G PI O166 K SO _15/ GP I O224
G2 9 A 22 MI N I P C I E _S L T 3 _ E N # R 3 84 *2 . 2 K _0 4
FC_R ST #/G P O160 K SO _16/ GP I O225 B 22 MI N I P C I E _S L T 2 _ E N #
K SO _17/ GP I O226 R 3 85 2. 2 K _ 0 4
R6 9 6 0_04 S B _ A C _ OK D2 7
F28 PS2K B_D AT G/ PI O 189
F29 PS2K B_C LK/ G PI O1 90 EM BE DDE D CT RL
E2 7 PS2M _D AT/ G PI O 191

D
PS2M _C LK/ G PI O19 2
Q 8 H U D S ON M1 A 1 3 STR AP PINS
G * MT N 70 0 2 Z H S 3
2 7 , 2 9, 3 7 A C _I N #
S
HUDSON GPIO/ USB/ STRAP B - 17

Schematic Diagrams
HUDSON SATA/ DEBUG IO/ SPI

HUDSON SATA/DEB UG IO/SPI
DEBUG ONLY
DNI R652 and R653 for customer board
U19B
AH28
HUDSON-1 PA RT 2O F 5
AG28
AF26
AH9
24 SAT
ATXP0 AJ9 SA TA _TX 0P FC _C LK
SA TA _TX 0N FC _F BC LKO U T
AF28
24 SAT
ATXN0
FC _FB CLK I N
AG29
AJ8
24 SAT
ARXN0 SA TA _RX 0N
AG26
AH8
24 SAT
ARXP0 SA TA _RX 0P FC _O E#/ G P O
I D 145
AF27
AE29
AH10 FC _AV D#/ G P IO D 146
SA TA _TX 1P F C_ WE#/ G P IO D 148
AF29
24 SAT
ATXP1 AJ10
24 SAT
ATXN1 SA TA _TX 1N F C_C E1#/ G P IO D 149
AH27
AG10 F C_C E2#/ G P IO D 150
24 SAT
ARXN1 AF10 SA TA _RX 1N F C_ IN T1/ G P O
I D 144
24 SAT
ARXP1 SA TA _RX 1P F C_ IN T2/ G P O
I D 147
GP IOD
AG12 AJ27
SA TA _TX 2P F C_A DQ 0/ G P O
I D 128
AF12 AJ26
SA TA _TX 2N F C_A DQ 1/ G P O
I D 129 AH25 Debug port
AJ12 F C_A DQ 2/ G P O
I D 130 AH24
AH12 SA TA _RX 2N F C_A DQ 3/ G P O
I D 131 AG23
SA TA _RX 2P F C_A DQ 4/ G P O
I D 132
AH23
F C_A DQ 5/ G P O
I D 133
AH14 AJ22
AJ14 SA TA _TX 3P F C_A DQ 6/ G P O
I D 134 AG21
SA TA _TX 3N F C_A DQ 7/ G P O
I D 135 AF21
AG14 F C_A DQ 8/ G P O
I D 136 AH22
SATAt race should use on
ly 1via o
n the SA TA _RX 3N F C_A DQ 9/ G P O
I D 137
AF14 AJ23
customers can use 2vias with GND via within 150mils of
trace. SA TA _RX 3P F C_A DQ 10/ G P IO D 138
AF23 NOTE: RO UTETEMP_COMM
signal via as lo
ng as they can ensure that their platfor m AG17 F C_A DQ 11/ G P IO D 139 AJ24 ASA10ML I TRACE
AF17 SA TA _TX 4P F C_A DQ 12/ G P IO D 140 AJ25 PL
ACEQ 600 UNDERDIMM
me
et s SATAlogo requireme
nt s. Return loss is exp
ected
SA TA _TX 4N F C_A DQ 13/ G P IO D 141 AG25
to get aff ected with 2 vias. AMD p
latf orms are valid
at e
d F C_A DQ 14/ G P IO D 142
AJ17 AH26
Sheet 17 of 41 with one via only AH17 SA TA _RX 4N F C_A DQ 15/ G P IO D 143
SA TA _RX 4P
AJ18 S ER I AL AT A
AH18 SA TA _TX 5P W5 HUDSON_FANOUT0
HUDSON SATA/ AH19

AJ19
SA TA _TX 5N
SA TA _RX 5N
FA NO UT 0/ G PI O 52
W6
Y9
ODD_PWR
SB_PROCHOT#_C
R330
ODD_PWR 24
*10K_04
3
.3VS
DEBUG IO/ SPI

SA TA _RX 5P W7 HUDSO N_FANTACH0
F AN IN 0/ G PI O 56
AVDD_SATA V9 HDD0_PWR
F AN IN 1/ G PI O 57
R331 1K_1%_04 SATA_CALP AB14 W8 GPI O58
AA14 SA TA _CA LR P F AN IN 2/ G PI O 58
R332 931_1
%_ 04 SATA_CALN
SA TA _CA LR N B6 TEMPIN0 R333 *0_0
4
T EM P IN 0/ G PI O 171 A6 SMD_CPU_THERM 3,16, 27
T EM P IN 1/ G PI O 172
R798 10K_04
AD11 A5 MB_THRMDA_SB
28 SATA_LED# R335 *0_0
4
C
SA TA _AC T# /G P I O6 7 T EM P IN 2/ G PI O 173
B5 SB_TALERT#
TE MP I N3/ T ALE RT #/ G PI O 174 C7 B
C486 C487 Q9
T EM P _C OM M
*2N3904
3.3VS H W M ON I TO R A3 VIN_VDDCR 330p
_50V_X7R_04
E
V IN 0/ G PI O 175
AD16 B4 VIN_VDDNB 330p_50V_
X7R_04
SA TA _X1 V IN 1/ G PI O 176 MB_THRMDC_SB
R576 *10
K_04 A4 VIN_VDDIO_SUS R336 *0_0
4
V IN 2/ G PI O 177 C5 R799 10K_0
4
V IN 3/ G PI O 178 A7 R800 10K_0
4 R337 *0_0
4
V IN 4/ G PI O 179 SMC_CPU_THERM 3,16, 27
V IN 5/ G PI O 180
R801 10K_0
4
R802 10K_0
4 3.3VS
A8B8B7
V IN 6/ G BE _ST AT 3/ G PI O 181
AC16 R803 10K_0
4
SA TA _X2 VI N 7/ G BE _LED 3/ G PI O 182
3.3VS
U2
0
5
*74AHC1G08GW
1
SPI_DATAIN S PI RO M APU_TALERT# 3,27
J5 R697 10K_04 4
SPI_DATAOUT E2 SP I _DI / G PI O 164 NC 2
YG27
SPI_CLK K4 SP I _DO / G PI O 163 NC GPU_TALERT# 8,10
2
SPI_CS#_SEL K9 SP I _CLK / GP I O 162
3
SP I _CS 1#/ G PI O 165
HUDSO N_RO M_RST# G2
RO M _R ST #/ GP I O 161
HUDSON M1 A13
Co
nne
ctC7 a
ndD8,th
engotoGNDdirectly. 1.8VS
R340 *11K_1%_04 VDDCR_CPU
VIN_VDDCR R341 *10K_04

3.3V
C488 R342
10K_04
R73
2 *0_04 *0.1u_
16V_Y5V_04
R346 D22 RB751

V
R3
50 R347 A C SB_PROCHOT#_C 1VS
3 SB_PROCHOT#
*1K_04
*1
0K_0
4 *10K_04 R344 *4.99K_1%_04VDDCR_NB
NEAR U19
U2
1 VIN_VDDNB R345 *4.99K_1%_04
8 5 SPI _
DATAOUT R573 0_04
VDD SI HSPI _
MSI 27
2 SPI _
DATAIN R386 0_04 C490 R349
SO HSPI _
MSO 27
C491 10K_04
3 1 SPI _
CS#_SEL R571 0_04 *0.1u_
16V_Y5V_04
WP# CE# HSPI _
CE# 27
*0.1u_16V_Y5V_04
6 SPI _
CLK R572 0_04
SCK HSPI _
SCLK 27
1.5V
7 4
HOLD# VSS VIN_VDDI O_SUS R351 *10K_04
*25VF032
B
C492 R352
10K_04
*0.1u_16
V_Y5V_04
B - 18 HUDSON SATA/ DEBUG IO/ SPI

Schematic Diagrams
HUDSON POWER DECOUPLING
HUDSON POWER DECOUPLING

U 19 C
3 . 3V S HUDSON-1 PAR T 3 OF 5 1 .1 V S
P O WER U 19 D
1 3 1 mA A H1 N 13 51 0 m A
V DDI O _33_PC I GP VD DC R_11
V6 R 15 HUDSON-1
Y1 9 V DDI O _33_PC I GP VD DC R_11 N 17 PAR T 5 OF 5
C4 9 4 C4 9 5 C 4 96 C 49 3 V DDI O _33_PC I GP VD DC R_11
C4 9 9 C5 0 0 C 50 1 C5 0 2 C 5 03
AE5 U 13 Y 14 A J2
0. 1u _ 1 0V _ X 5 R _ 0 4 AC2 1 V DDI O _33_PC I GP VD DC R_11 U 17 Y 16 V SSI O _SA TA VS S A 28
2 2u _ 6 . 3V _X 5 R _ 0 8 V DDI O _33_PC I GP VD DC R_11
1u _ 6 . 3 V _X 5 R _ 0 4 10 u _ 6. 3 V _ X 5 R _ 0 8 0 . 1u _ 1 0V _ X 5 R _ 0 4 V SSI O _SA TA VS S
0 . 1u _ 1 0V _X 5 R _ 0 4 0 . 1 u _1 0 V _ X 5R _ 04 AA2 V 12 1 u _ 6. 3 V _ X 5 R _ 0 4 0 . 1 u_ 1 0 V _ X5 R _0 4 A B 16 A 2
AB4 V DDI O _33_PC I GP VD DC R_11 V 18 A C 14 V SSI O _SA TA VS S E 5
V DDI O _33_PC I GP VD DC R_11 V SSI O _SA TA VS S
A C8 W 12 A E 12 D 23
AA7 V DDI O _33_PC I GP C OR E S0 VD DC R_11 W 18 A E 14 V SSI O _SA TA VS S E 25
V DDI O _33_PC I GP VD DC R_11 V SSI O _SA TA VS S
AA9 +1 . 1 V _ C K V D D 1. 1 V S AF9 E 6
AF7 V DDI O _33_PC I GP A F 11 V SSI O _SA TA VS S F 24
1. 8 V S V DDI O _33_PC I GP CLK G EN I O
/ V SSI O _SA TA VS S
R3 5 5 0 _ 04 V D D I O_ 1 8_ F C
AA1 9
V DDI O _33_PC I GP VD DA N_11_C LK
K 28
K 29
T B Dm A L85 . H C B 1 0 0 5K F -12 1 T 2 0 A F 13
A F 16 V SSI O _SA TA VS S
N 15
R 13
VD DA N_11_C LK J28 A G8 V SSI O _SA TA VS S R 17
PC /I G PI O I / O C5 0 5 C5 0 7 C 50 8 C5 1 0 C 49 8
VD DA N_11_C LK K 26 A H7 V SSI O _SA TA VS S T1 0
C 50 9 C5 0 4 C 5 06 C 4 97
VD DA N_11_C LK J21 A H 11 V SSI O _SA TA VS S P 10
71m A FLA SH I / O 0 . 1 u _1 0 V _ X 5R _ 04 1 u_ 6 . 3 V _ X5 R _0 4 2 2u _ 6 . 3V _ X 5 R _ 0 8
AF 2 2 VD DA N_11_C LK J20 A H 13 V SSI O _SA TA VS S V 11
4 . 7 u _6 . 3 V _ X 5R _ 06 0 . 1 u _ 10 V _ X 5R _ 04 0. 1 u _ 10 V _ X 5 R _ 0 4 1 u _6 . 3 V _ X 5R _ 04
AE2 5 V DDI O _18_FC VD DA N_11_C LK K 21 A H 16 V SSI O _SA TA VS S U 15
0 . 1u _ 1 0V _X 5 R _ 0 4 * 0 . 1u _ 1 0V _X 7 R _ 0 4 V DDI O _18_FC VD DA N_11_C LK V SSI O _SA TA VS S
AF 2 4 J22 A J7 M 18
AC2 2 V DDI O _18_FC VD DA N_11_C LK A J 11 V SSI O _SA TA VS S V 19
V DDI O _18_FC V SSI O _SA TA VS S
3 . 3V S A J 13 M 11
V 1 A J 16 V SSI O _SA TA VS S L12
VD DR F_G BE _S
R3 5 6 0_ 0 4 V SSI O _SA TA VS S
L86 . H C B 1 0 0 5K F -12 1 T 20 V D D P L _3 . 3 V _ P C I E 43m A
M 10 R 7 7 1 * 10 m i _l s h ort A9 VS S
L18
J7
PCI EX PRE SS V DDI O _33_G BE _S V SSI O _US B VS S
C 5 11 C 51 2 B 10 P 3
AE2 8 K 11 V SSI O _US B VS S V 4
V DDP L_33_PC I E V SSI O _US B VS S
1 u _1 0 V _ Y 5 V _ 0 6 B9 A D6
G BE L AN D 10 V SSI O _US B VS S A D4
0 . 1u _ 1 0V _X 5 R _ 0 4 V SSI O _US B VS S
1 2/9 U2 6 L7 R 77 2 * 10 m i _l s h ort D 12 A B7
1 .1 V S
60 0 m A
V2 2
V2 6
V2 7
V DDA N_11_P CI E
V DDA N_11_P CI E
V DDA N_11_P CI E
V DDA N_11_P CI E
VD DC R_11_G BE _S
VD DC R_11_G BE _S
L9 D 14
D 17
E9
V SSI O _US B
V SSI O _US B
V SSI O _US B
V SSI O _US B
VS S
VS S
VS S
VS S
A C9
V 8
W 9
Sheet 18 of 41
V2 8 M6 R 77 3 * 10 m i _l s h ort F9 W 10
12 /6 D el R8 27 C 51 7 C5 1 8 C 51 9 C5 2 0 C5 2 1
* 1 u_ 6 . 3 V _ X5 R _0 4 0. 1 u _ 10 V _ X 5 R _ 0 4
V2 9
W22
W26
V DDA N_11_P CI E
V DDA N_11_P CI E
V DDA N_11_P CI E
V DDA N_11_P CI E
V DD IO _G BE _S
V DD IO _G BE _S
P 8 F 12
F 14
F 16
V SSI O _US B
V SSI O _US B
V SSI O _US B
V SSI O _US B
VS S
VS S
VS S
VS S
A J2 8
B 29
U 4
HUDSON POWER
2 2u _ 6 . 3V _X 5 R _ 0 8 1 u _ 6. 3V _ X 5 R _ 0 4 0 . 1 u _1 0 V _ X 5R _ 04 C9 Y 18
3. 3V S
93m A AD1 4
SE RI AL AT A
3. 3V_S5 I / O 3 . 3V
G 11
F 18
D9
V SSI O _US B
V SSI O _US B
V SSI O _US B
G R OU ND
VS S
VS S
VS S
Y 10
Y 12
Y 11
DECOUPLING
L8 8 . H C B 10 0 5 K F -1 2 1T 2 0 V D D P L _3 . 3 V _ S A T A
A J2 0
V DDP L_33_SA TA
VD DI O _33_S
A 21
D 21
32m A H 12
H 14
V SSI O _US B
V SSI O _US B
VS S
VS S
A A 11
A A 12
AF 1 8 V DDA N_11_S AT A VD DI O _33_S B 21 H 16 V SSI O _US B VS S G 4
C 5 27 C 52 8 V DDA N_11_S AT A VD DI O _33_S V SSI O _US B VS S
AH2 0 K 10 C5 2 9 C 5 30 C5 3 1 H 18 J4
A G1 9 V DDA N_11_S AT A VD DI O _33_S L10 J 11 V SSI O _US B VS S G 8
* 0 . 1u _ 1 0 V _X 7 R _ 0 4 V DDA N_11_S AT A VD DI O _33_S V SSI O _US B VS S
1u _ 1 0V _ Y 5V _0 6 AE1 8 J9 * 0. 1u _ 1 0V _ X 7 R _ 0 4 1u _ 1 0V _ Y 5V _0 6 J 19 G 9
AD1 8 V DDA N_11_S AT A VD DI O _33_S T6 K 12 V SSI O _US B VS S M 12
V DDA N_11_S AT A VD DI O _33_S
1u _ 1 0V _Y 5 V _0 6 V SSI O _US B VS S
AE1 6 T8 K 14 A F 25
V DDA N_11_S AT A VD DI O _33_S K 16 V SSI O _US B VS S H 7
A V D D _S A TA K 18 V SSI O _US B VS S A H2 9
1 . 1V S 1 . 1V V SSI O _US B VS S
H 19 V 10
L 89 . H C B 1 0 05 K F -1 2 1 T2 0 5 6 7m A
A1 8
US B I O
/
CO RE S 5
VDD CR _11_S
F 26
G 26
1 1 3m A V D D C R _ 1. 1 V R3 6 1 0 _0 4
V SSI O _US B VS S
VS S
P 6
N 4
A1 9 V DDA N_33_U SB _S VDD CR _11_S Y4 VS S L4
C 5 32 C 5 33 C 5 34 C5 3 5 C5 3 6 V DDA N_33_U SB _S
V D D I O_ A Z C 53 7 C5 3 8 E FUS E VS S
A2 0 M8 L8
V DDA N_33_U SB _S V DDI O _AZ _S
T B Dm A VS S
1 u_ 6 . 3 V _ X5 R _0 4 0. 1 u _ 10 V _ X 5 R _ 0 4 B1 8 1u _ 6 . 3V _ X 5 R _ 0 4 D8
V DDA N_33_U SB _S V SSA N_H WM
2 2u _ 6 . 3V _X 5 R _ 0 8 1 u_ 6 . 3 V _ X5 R _0 4 0 . 1 u _1 0 V _ X5 R _0 4 B1 9 A 11 1 9 7m A V D D C R _ 1. 1 _ U S B 1 u _6 . 3 V _ X 5R _ 04
B2 0 V DDA N_33_U SB _S V DDC R_11_ USB _S B 11 M 19 M 20
V DDA N_33_U SB _S V DDC R_11_ USB _S
1 .1 V V SSX L V SS PL_SY S
C1 8
C2 0
D1 8
V DDA N_33_U SB _S
V DDA N_33_U SB _S
M 21 4 7m A
V D D P L _ 3 . 3V L90 . H C B 1 0 0 5K F -12 1 T 20 P 21 H 23
D1 9 V DDA N_33_U SB _S VD DP L_33_SY S P 20 V SSI O _PC I ECLK VS SI O_P CI EC LK H 26
3 .3 V A V D D _U S B V DDA N_33_U SB _S P LL
V D D P L _1 . 1 V C 53 9 C5 4 0 C 5 41 V SSI O _PC I ECLK VS SI O_P CI EC LK
D2 0 L22 62 m A M 22 A A 21
E1 9 V DDA N_33_U SB _S VDD PL_11_ SYS _S M 24 V SSI O _PC I ECLK VS SI O_P CI EC LK A A 23
L 91 . H C B 1 0 05 K F -1 2 1 T2 0 6 5 8m A V DDA N_33_U SB _S
F 19 17 m A
A V D D_ U S B 10 u _ 6. 3 V _ X 5 R _ 0 8 0 . 1u _ 1 0V _ X 5 R _ 0 4
0 . 1 u_ 1 0 V _ X5 R _0 4 M 26
V SSI O _PC I ECLK VS SI O_P CI EC LK
A B 23
VDD PL_33_ USB _S P 22 V SSI O _PC I ECLK VS SI O_P CI EC LK A D2 3
C5 4 2 C 54 3 C 54 4 C5 4 5 C 5 46 V SSI O _PC I ECLK VS SI O_P CI EC LK
0 . 1u _ 1 0V _ X 5 R _ 0 4 C 1 1 V DDA N_11_U SB _S V DDA N_33_H WM _S
D 6 5m A V D D A N _ 3. 3 V _ H W M 3 .3 V P 24
V SSI O _PC I ECLK VS SI O_P CI EC LK
A A 26
1 u _ 6 . 3V _ X 5 R _ 0 4 10 u _ 6 . 3V _ X 5 R _ 0 8 D1 1 P 26 A C2 6
1u _ 6 . 3 V _X 5 R _ 0 4 1 0u _ 6 . 3 V _X 5 R _ 0 8
V DDA N_11_U SB _S
VD DX L_33_S
L20 TB D m A V D D X L_ 3 . 3 V L92 . H C B 1 0 0 5K F -12 1 T 20 T 20
T 22
V SSI O _PC I ECLK
V SSI O _PC I ECLK
VS SI O_P CI EC LK
VS SI O_P CI EC LK
Y 20
W 21
T 24 V SSI O _PC I ECLK VS SI O_P CI EC LK W 20
HU DS O N M 1 A 1 3 C5 4 7 C 54 8 V SSI O _PC I ECLK VS SI O_P CI EC LK
V 20 A E 26
1 .1 V J 23 V SSI O _PC I ECLK VS SI O_P CI EC LK L21
T B Dm A 0. 1 u _ 10 V _ X 5 R _ 0 4 V SSI O _PC I ECLK VS SI O_P CI EC LK
1 u_ 1 0 V _ Y 5 V _ 06 K 20
L93 . H C B 1 0 0 5K F -12 1 T 20 V D D A N _ 1. 1 V _ U S B
H U D S ON M1 A 1 3
VS SI O_P CI EC LK
C 54 9 C5 5 0
0 . 1 u_ 1 0 V _ X5 R _0 4
1 u _ 10 V _ Y 5V _ 0 6
3. 3 V V D D A N _ 3 . 3V _H W M
3 .3 V S V D D P L _ 3. 3V 1. 1 V V D D P L_ 1 . 1 V
L94 . H C B 1 0 05 K F - 12 1 T 20
3 . 3V V D DIO _ A Z C 5 51 C 55 2
1 .5 V
R 36 2 0 _0 4
L95 . H C B 1 0 0 5K F -12 1 T 20 L96 . H C B 1 0 0 5 K F -1 21 T 2 0 1 u _ 10 V _ Y 5V _ 0 6
0. 1 u _ 1 0V _ X 5 R _ 0 4
C 5 53 C 55 4 C5 5 5 C 5 56
R 36 3 *0 _ 0 4
1 u _ 1 0V _ Y 5V _ 0 6 1u _ 1 0V _Y 5 V _0 6
C5 5 7 *0 . 1 u _ 10 V _ X 7R _ 04 *0 . 1 u _1 0 V _ X 7R _ 04
1 u _ 10 V _ Y 5 V _ 0 6
HUDSON POWER DECOUPLING B - 19

Schematic Diagrams
POWERGOOD/ TPM
3 .3 V
U2 2 B
14
7 4 LV C 0 8P W
4
33 1 . 1 V _ P W R G D 6
5
16 S Y S _ R S T#
7
3 .3 V
3 5 P W R G D _ V C OR E
3 .3 V
3 .3 V R 7 74
3 .3 V
U2 2 A U2 2 C 10 K _ 0 4
14
R7 7 5 0_ 0 4 7 4 LV C 0 8P W U 22 D 74 L V C 0 8 P W R3 6 4 0 _0 4 S B _ P W RO K
14
34 1 . 8 V _ P W R G D 9 S B _ P W R GD 16
7 4 LV C 0 8P W
14
12 8 R3 6 5 0 _0 4 S Y S _P W R OK
1 11 10 A L L _ S Y S _ P W R GD 2 0 , 2 7
R7 7 6 *0 _ 04
3 2 , 35 D D R 1. 5 V _ P W R GD 3 13
2 C 84 1 R3 6 7
1 6 , 2 6, 27 , 3 0 S U S B #
7
7
1 u_ 6 . 3 V _Y 5 V _0 4 *1 0 K _ 04
7
ON
Sheet 19 of 41
POWERGOOD/
TPM
TPM 1.2 3 .3 V S
U 50 C8 7 6 C 8 77 C8 7 8 C 87 9
R 8 14 *0 _ 0 4 2 6 10
1 5 ,2 7 L P C_ A D0 L A D0 V DD 1
1 5 ,2 7 L P C_ A D1 R 8 16 *0 _ 0 4 2 3 19 *0 . 1 u _1 6 V _ Y 5 V _ 04 *0 . 1 u_ 1 6 V _Y 5 V _0 4
R 8 17 *0 _ 0 4 2 0 L A D1 V DD 2 24 *0 . 1 u _1 6 V _ Y 5 V _ 04 * 1u _ 1 6V _ X 5 R _ 06
1 5 ,2 7 L P C_ A D2 L A D2 V DD 3
1 5 ,2 7 L P C_ A D3 R 8 15 *0 _ 0 4 1 7
L A D3
21 3 .3 VS
15 P C L K _T P M L CL K TPM
15 , 2 7 LP C _ F R A M E # R 8 18 *0 _ 0 4 2 2 5
R 8 19 *0 _ 0 4 1 6 L F RA M E # VSB
1 5 , 23 , 2 4 , 26 , 2 7 B U F _ P L T _R S T # L R E S E T#
15 , 2 7 S E RIR Q R 8 20 *0 _ 0 4 2 7 C8 8 0
15 S E R IRQ
15 P C I _ C LK R U N # C LK R U N #
*0 . 1 u _1 6 V _ Y 5 V _ 04
28 6 T P M3 0 04
16 S 4 _ S T A TE # L P CP D # G PIO 2 T P M3 0 05
T P M_ B A D D 9 GP I O 2
T E S T B I/B A D D 13 XTAL I
T P M_ P P 7 X T A LI
PP X 12 * 3 2. 7 6 8 K H z
14 XTAL O 4 1
T P M3 0 0 1 1 XT A L O 3 2
T P M3 0 0 2 3 N C_ 1 4
T P M3 0 0 3 1 2 N C_ 2 GN D _ 1 11 X 13 * 3 2. 7 6 8 K H z
N C_ 3 GN D _ 2 18 4 1
8 GN D _ 3 25 3 2
TESTI GN D _ 4
C 8 81 C8 8 2
* S L B 96 3 5 TT *1 8p _ 5 0V _ N P O_ 0 4 *1 8 p_ 5 0 V _N P O_ 0 4
Ass er ted befo re entering S3

LPC reset t iming:
P C L K _ TP M R 8 21 *3 3 _ 04 C 8 83 *1 0 p_ 5 0 V _0 4
LPCP D# inac tive to LRST# inact ive 32~96us
HI: ACCESS 3 .3 V S
TPM_PP L OW: NORMAL ( Int ernal PD) T P M_ P P R 8 22 *1 0 K _ 04
HI: 4E/ 4F H
TPM_BADD L OW: 2E/ 2F H T P M_ B A D D R 8 23 *1 0 K _ 04
R 8 24 *1 0 K _ 04
B - 20 POWERGOOD/ TPM
Schematic Diagrams
LVDS, INVERTER
3 .3 VS
R577, R578 W250BAQ Delete
PANEL CONNECTOR R5 7 7 2. 2 K _ 0 4 J_LC D1 For single channel
R5 7 8 2. 2 K _ 0 4
EDID Mode
J_LC D2 For dual channe l
V IN_ L CD
J _ LC D 1 V IN_ L CD
12/7 8 0mi ls 1 2 LV D S _ D A T A J_ L C D 2
G 2
G1
3 1 2 4 LV D S _ C L K
5 3 4 6 12/ 7 LV D S _ D A T A
5 6 1 2
Gn d 1
G nd 2
7 8 B RIG HT NE S S LV D S _ C L K
9 7 8 10 B R I GH TN E S S 2 7 3 4
11 9 10 12 I N V _ B L ON 3 .3 V 5 6 B RIG HT NE S S
13 11 12 14 7 8
R L V D S -L C LK N 15 13 14 16 R L V D S -L2 N D2 3 9 10 I N V _ B L ON
R L V D S -L C LK P 17 15 16 18 R L V D S -L2 P C 11 12
19 17 18 20 B RIG HT N E S S AC R L V D S -LC L K N 13 14 R L V D S -L 2 N
C 5 66
R L V D S -L 1 N 21 19 20 22 A * 0 . 1u _ 1 6V _ Y 5V _ 0 4 R L V D S -LC L K P 15 16 R L V D S -L 2 P
R L V D S -L 1 P 23 21 22 24 17 18
25 23 24 26 3. 3 V S 19 20
*B A V 99 R E C T I F I E R R L V D S -L1 N
R L V D S -L 0 N 27 25 26 28 R L V D S -L1 P 21 22
29 27 28 30 23 24 3 .3 VS
R L V D S -L 0 P
29 30 R L V D S -L0 N 25 26
C5 6 1
87 2 1 6-3 0 0 6 R L V D S -L0 P 27
29
28
30
PL VD D 2A
0 . 1u _ 1 6V _ Y 5V _0 4
31 32
P LV D D 7 T X CL K _ UN 33 34 T XO U T _ U 2 N 7
7 TX C LK _ U P 35 36 T XO U T _ U 2 P 7
C5 6 2 C 5 63 7 T X OU T_ U 1N T XO U T _ U 0 N 7
37 38
7 TX O U T _U 1 P 39 40 T XO U T _ U 0 P 7
4. 7 u _ 6. 3 V _ X 5 R _ 06 0. 1 u _ 16 V _ Y 5 V _ 0 4
* 87 2 1 6-4 0 0 6
Sheet 20 of 41
12 /7
PANEL POWER LVDS, INVERTER

3. 3 V S
VIN V IN L1 V IN_ L CD
*0 _ 0 6
. 2A
8
Q 46 3 7 3. 3 V C 56 5 C 56 4
2
1
6
5
3A P L V DD
Default UMA
C 5 59
C5 6 0
R5 8 6 P 20 0 3 E V G 0 . 1u _ 1 6V _ Y 5V _ 0 4 *0 . 0 1u _ 1 6V _ X 7 R _ 0 4
R2 3 8 U2 4
1 M_ 0 4 4 1 2A
5 VIN V OU T
4
R 2 28 R LV D S -L 0 N R 6 02 0_04 L V D S -L 0 N
VIN L V D S -L 0 N 3
0 . 01 u _ 50 V _ X 7 R _ 0 4
*1 0 K _0 4
*2 00 _ 1 %_ 0 4 0 . 1 u _5 0 V _ Y 5 V _0 6 R 6 03 * 0 _0 4 T X OU T _ L 0N
E N A V DD 3 2 T XO U T _ L 0N 7
C1 8 1108 3 NB _ E N A V DD R 69 8 0 _ 04
D
EN G ND
6
D D R LV D S -L 0 P R 6 04 0_04 L V D S -L 0 P
L V D S -L 0 P 3
*0 . 1 u _5 0 V _ Y 5 V _ 0 6 7 V GA _D I GO N R 69 9 *0 _ 0 4 R3 8 7 A P L 3 5 12 A
G E N A V DD 2G 5G 1 00 K _ 0 4 R 6 05 * 0 _0 4 T X OU T _ L 0P
T XO U T _ L 0P 7
Q 49 Q 45 A S Q4 5 B S
S
M T N 7 0 02 Z H S 3 *M TD N 7 0 02 Z H S 6 R *MT D N 7 0 02 Z H S 6R R LV D S -L 1 N R 6 06 0_04 L V D S -L 1 N
W250BAQ R698 Off, R699 On L V D S -L 1 N 3
R 6 07 * 0 _0 4 T X OU T _ L 1N
T XO U T _ L 1N 7
R LV D S -L 1 P R 6 08 0_04 L V D S -L 1 P
G5243A 6-02-05243-9C0 L V D S -L 1 P 3
APL3512A 6-02-03512-9C0 R 6 09 * 0 _0 4 T X OU T _ L 1P
T XO U T _ L 1P 7
R LV D S -L 2 N R 6 10 0_04 L V D S -L 2 N
L V D S -L 2 N 3
R 6 11 * 0 _0 4 T X OU T _ L 2N
T XO U T _ L 2N 7
R LV D S -L 2 P R 6 12 0_04 L V D S -L 2 P
L V D S -L 2 P 3
R 6 13 * 0 _0 4 T X OU T _ L 2P
27 B K L_ E N
R3 8 8 *1 0 mi l _ sh o rt _ 04 B K L _ E N_ R INVERTER CONNECTOR R LV D S -L C L K N R 6 14 0_04 LV D S -L C L K N
T XO U T _ L 2P 7
L V D S -L C LK N 3
R 6 15 * 0 _0 4 TX C L K _ L N
T XC L K _L N 7
R 38 9 C5 6 7
3 . 3V 3 .3 V 3. 3 V R LV D S -L C L K P R 6 16 0_04 LV D S -L C L K P
L V D S -L C LK P 3
* 10 0 K _ 04 *0 . 4 7u _ 10 V _ Y 5V _ 0 4
U 2 5A R 6 17 * 0 _0 4 TX C L K _ L P
14
T XC L K _L P 7
7 4 L VC0 8 PW U2 5 B
14
1 74 L V C 0 8 P W C5 6 8
3 Z 12 0 1 4
R 7 00 0_04 2 6 *0 . 1 u _1 6 V _ Y 5 V _ 04 L V D S _D A T A R 6 18 0_04 LV D S _ D D C _ D A T A
3 B L ON 5 L V D S _ D D C _ D A TA 3
R 7 01 * 0_ 0 4 R 6 19 * 0 _0 4 S DA
8 GP I O 7_ B L O N SDA 8
7
R 39 0
7
L V D S _C L K R 6 20 0_04 LV D S _ D D C _ C L K
L V D S _ D D C _ C LK 3
1 0 0K _0 4 U2 5 C
14
7 4 LV C 0 8P W R 6 21 * 0 _0 4 S CL
W250BAQ R700 Off , R701 On 16 S B _ B LO N Z 1 20 2 9 SCL 8
3 .3 V 8 I N V _B LO N
R3 9 1 * 10 0 K _ 0 4 Z 1 20 3 10
U2 5 D
14
74 L V C 0 8 P W R 3 92 C5 6 9
12
7
16 , 2 7 , 29 L I D _S W # 11 * 1 M_ 0 4 0 . 1u _ 1 6V _ Y 5V _ 0 4
13
1 9 , 27 A L L _ S Y S _ P W R GD
7
LVDS, INVERTER B - 21
Schematic Diagrams
HDMI/ CRT
HDMI PORT 5V S _H D MI
RD2
* BA V 99 R EC T I FI E R R D 3
* BA V 99 R EC T I FI E R
L9 8
1_ 04
5V S
RD1 For ESD
C
A
A
* BA V 99 R EC T I FI E R
R H D MI B _ D 2B P C 82 9 0. 1u _1 0V _X 7R _ 04 H D MI B_ D A TA 2P R 3 93
R H D MI B _ D 2B N C 83 0 0. 1u _1 0V _X 7R _ 04 H D MI B_ D A TA 2N 5V S _H D MI
1 _04 5 V S_ H D MI
AC
AC
AC
R H D MI B _ D 1B P C 83 1 0. 1u _1 0V _X 7R _ 04 H D MI B_ D A TA 1P
R H D MI B _ D 1B N C 83 2 0. 1u _1 0V _X 7R _ 04 H D MI B_ D A TA 1N R 579 2. 2 K_ 04 J_ H D MI 1
R 580 2. 2 K_ 04
R H D MI B _ D 0B P C 83 3 0. 1u _1 0V _X 7R _ 04 H D MI B_ D A TA 0P C 5 70 C 5 71
R H D MI B _ D 0B N C 83 4 0. 1u _1 0V _X 7R _ 04 H D MI B_ D A TA 0N
1 0u_ 10 V_ Y 5V _ 08 2 2u_ 6. 3 V_ X5 R _0 8
R H D MI B _ C LK BP C 83 5 0. 1u _1 0V _X 7R _ 04 H D MI B_ C LOC K P 19 H D MI B _E X T1 _H P D
R H D MI B _ C LK BN C 83 6 0. 1u _1 0V _X 7R _ 04 H D MI B_ C LOC K N 18 H OT P L U G D ET E C T
+ 5V 17
16 D D C / C E C GN D
4 99 _1 %_0 4
4 99 _1 %_0 4
4 99 _1 %_0 4
H D MI B _E XT 1_ SD A
499 _1 %_ 04
49 9_ 1% _04
49 9_ 1%_ 04
49 9_ 1% _04
49 9_ 1%_ 04
S DA 15 H D MI B _E X T1 _S C L
FO R EM I 14 S CL FO R EM I
3 . 3V S R E S E R VE D 13 H D MI _ C EC
H D MI B _E XT 1_ SC L H D MIB _ C LOC K N 4 3 12 CEC
L99 T MD S C L OC K -
H D MI B _E XT 1_ SD A 11
H D MI B _E XT 1_ H PD H D MIB _ C LOC K P 1 2 10 C L K S H I E LD
*H D MI 2 012 F 2S F -9 00 T0 4-sh ort T MD S C L OC K + 9 1 L1 00 2 H D MI B _D A T A0 N
S
TMD S D AT A 0-
* LV A R 040 2-2 40 E0 R 05 P-L F

G 8
*L VA R 04 02 -24 0E 0R 0 5P -LF
R 6 48
R 64 9
R 65 0
R 651
R 6 52
R 65 3
R 65 4
R 647
S H I E LD 0 7 4 3 H D MI B_ D AT A 0P
6 TM D S D A TA 0 +
R 39 5
R 4 00
Q2 5 MT N 70 02 ZH S 3 *H D MI 2 01 2F 2S F -90 0T0 4-s ho rt
T MD S D A T A1 - 5
R 3 97
R 39 8
*LV A R 04 02 -2 40 E0 R 05 P -L F
*L VA R 0 40 2-24 0E 0R 0 5P -LF
D
4 SH I E L D 1
T MD S D A T A1 + 3
2 TMD S D AT A 2-
CLOSE TO HD MI CO NN. 3 . 3V S 5V S S H I E LD 2
TM D S D A TA 2 +
1
3 . 3V S
R 65 5 R 656 H D MIB _ D AT A 1N 4 L10 1 3
G
3 .3 V S 4. 7 K _04 Q2 6 2. 2K _ 04 H D MIB _ D AT A 1P 1 2
*H D MI 2 012 F 2S F -9 00 T0 4-sh ort C 1 28 17 -1 19 A5 -L 1 L1 02 2 H D MI B _D A T A2 N
W250BAQ Del R719, Add R718 H D MI _ SC L S D H D MI B _E XT 1_ SC L
* LV A R 040 2-2 40 E0 R 05 P-L F
*L VA R 04 02 -24 0E 0R 0 5P -LF
Sheet 21 of 41
C
Q27 4 3 H D MI B_ D AT A 2P
R 7 18 *0_ 04 B R5 5 20 0K _0 4 H D M IB _ EX T1 _H P D MT N 70 02 ZH S 3 *H D MI2 01 2F 2S F -90 0T 04-s ho rt
R 40 4
R 4 05
8 HPD1
*LV A R 04 02 -2 40 E0 R 05 P -L F
*L VA R 0 40 2-24 0E 0R 0 5P -LF
2N 3 90 4
R 4 06
R 40 7
E
HDMI/ CRT 3 P OR TC _ H P D
R 7 19 0_ 04 R 65 7
*2 00 K _04
3 . 3V S 5V S
R 72 0 R 6 58
*1 00K _ 04 10 K _04 3 . 3V S
R 65 9 R 660
R 721 *0_ 04 4. 7 K _04
G
Q2 8 2. 2K _ 04
H D MI _S D A S D H D MI B _E XT 1_ SD A 3. 3 VS
3 H D MI B_ D 2B P R 6 61 0_ 04 R H D MI B_ D 2B P
MT N 70 02 ZH S 3
8 TMD S _T X2 P R 6 62 *0_ 04
C 57 7 C 5 78
R 6 63 0_ 04 R H D MI B_ D 2B N
3 H D MI B_ D 2B N 0. 1 u_ 16 V_ Y 5V _0 4 *0 . 1u_ 16 V _Y 5V _ 04
8 TMD S _T X2 N R 6 64 *0_ 04
3 H D MI B_ D 1B P R 6 65 0_ 04 R H D MI B_ D 1B P
R 6 66 *0_ 04
Default UMA 8 TMD S _T X1 P
R H D MI B_ D 1B N
3 H D MI B_ D 1B N R 6 67 0_ 04
8 TMD S _T X1 N R 6 68 *0_ 04
8
H D MI B_ D 0B P
TMD S _T X0 P
R 6 69
R 6 70
0_ 04
*0_ 04
R H D MI B_ D 0B P
CRT PORT 6-20-14X30-015 J_ C R T1
10 8A H 15 F ST 04 A1 C C
R 6 71 0_ 04 R H D MI B_ D 0B N RE D 1
3 H D MI B_ D 0B N 9
R 6 73 *0_ 04 R D A C _R E D L 137 FC M 100 5MF -60 0T 01 L 10 4 F C M10 05MF -6 00T 01 2
8 TMD S _T X0 N R D A C _GR E E N
. . GR N 24
10 m il
L 139 . FC M 100 5MF -60 0T 01 L 10 3 . F C M10 05MF -6 00T 01
R 6 72 0_ 04 R H D MI B_ C LK B P R D A C _B LU E L 138 . FC M 100 5MF -60 0T 01 L 10 5 . F C M10 05MF -6 00T 01 B LU E 3
3 H D MI B _C L KB P 11
1 0p _50 V _N P O_0 4
2 2p _50 V _N P O_0 4
1 0p _5 0V _N P O_0 4
10 p_ 50 V_ N P O_0 4
R 6 74 *0_ 04 4
10 p_ 50 V_ N PO _04
10p _5 0V _N P O_ 04
22 p_ 50 V_ N P O_04
22p _5 0V _N P O_ 04
10 p_ 50V _ N PO_ 04
8 TMD S _T XC P
12 D D C D A TA
3 H D MI B _C L KB N R 6 75 0_ 04 R H D MI B_ C LK B N R 4 12 R 41 3 R 4 14 5
13 HS Y NC
R 6 76 *0_ 04 1 50 _1% _0 4 1 50 _1 %_0 4 6
8 TMD S _T XC N 14
15 0_ 1%_ 04 V S YNC
R 6 25 0_ 04 H D MI _S C L 7
3 H D MI _ D D C _C L K 15 DDCL K
R 6 26 *0_ 04 8
8 D D C 1C L K
C 58 5 10 00 p_ 50 V_ X7 R _0 4
C 58 8 10 00 p_5 0V _ X7 R _0 4
C 5 79
C 58 0
C 8 65
C 86 6
C 86 7
C 5 82
C 5 83
C 58 4
220 p_ 50 V_ N P O_0 4
C 5 87 2 20 p_5 0V _N PO_ 04
C 581
R 6 27 0_ 04 H D MI _S D A 3. 3 VS 5 VS
3 H D MI _D D C _ D A TA
GN D 1
GN D 2
8 D D C 1D A TA R 6 28 *0_ 04
1
2
3
4
RN1
2. 2K _ 8P 4R _ 04
8
7
6
5
R 6 29 0_ 04 R D AC _ R E D
C 586
3 D AC _ R E D
8 R _D A C 1 R 6 30 *0_ 04
3 D A C _GR E E N R 6 31 0_ 04 R D AC _ GR E EN U 27
R D AC _ D D C A D A TA 10 9 D D C D AT A
R 6 32 *0_ 04 D D C _ IN 1 D D C _ OU T1
8 G_D A C 1 11 12
R D AC _ D D C A C LK D D C LK
R 6 33 0_ 04 R D AC _ B LU E D D C _ IN 2 D D C _ OU T2
3 D AC _ B LU E R D A C _H S Y N C 13 14 C R T_H SY N C H SY N C
S Y N C _I N 1 SY N C _ OU T1 R 4 15 33 _04
R 6 34 *0_ 04
8 B_ D A C 1 R D A C _V S Y N C 15 16 C R T_V S Y N C R 4 16 33 _04 VS Y N C
Default UMA 3 D A C _H S Y N C R 6 36 0_ 04 R D AC _ H S Y N C S Y N C _I N 2 SY N C _ OU T2
1 3 BL U E
R 6 35 *0_ 04 5V S V C C _S Y N C VI D E O_1
8, 1 0 H S Y N C _D A C 1 2 4
3 . 3V S GR N
R 6 37 0_ 04 R D AC _ V SY N C V C C _V I D E O VI D E O_2
3 D A C _V S Y N C 7 5 R ED
3. 3V S V C C _D D C VI D E O_3
8, 1 0 V SY N C _ D A C 1 R 6 38 *0_ 04
8 6
0. 2 2u_ 10 V_ Y 5V _0 4
0 . 22 u_1 0V _ Y5 V_ 04
R 6 39 0_ 04 R D AC _ D D C A D AT A BYP GN D
0. 2 2u _10 V _Y 5V _0 4
3 D A C _D D C A D A TA TP D 7S 01 9
C 58 9
C 590
8 D D C 6D A TA R 6 40 *0_ 04 I P47 72C Z16 6- 02-4 772 1-B 60
C 5 91
3 D A C _D D C A C LK R 6 41 0_ 04 R D AC _ D D C A C LK T PD7 S01 9 6-0 2-07 019 -B2 0
8 D D C 6C L K R 6 42 *0_ 04
B - 22 HDMI/ CRT
Schematic Diagrams
CCD/ 3G
MINI CARD 3G(Port 6)

Layo ut Sh ow "3.5G( HSDPA)" Note
3 G_ 3 . 3 V Layout?
1
J _3 G 1
2 60 mils 1. SIM? ? ? ? ? ? ? ? (10mil)
W AKE# 3 .3 V A UX _ 0
3
5 C O E X1 1. 5 V _ 0
6
8 U I M_ P W R
2. ? ? ? ? ? ? ? ? GND
C O E X2 U I M_ P W R
7 U I M _D A T A
10
12
U
U
I M_ D A T A
I M_ C L K C5 9 4
C5 9 2
+C 5 9 3 3. SIM hold ? ? ? ? ? GND? ?
11 CL K RE Q # U I M _C L K 14 U I M_ R S T
13 R E F C LK -
R E F C LK +
U I M _R E S E T
U I M _V P P
16 U I M_ V P P 0. 1u _ 16 V _ Y 5 V _ 0 4 0 . 1u _ 1 6V _ Y 5V _ 0 4 2 20 u _ 4V _ V _ B 4. SIM CONN ? ? MINI CARD
9
15 GN D 0
GN D 1 GN D 5
4 CONN
KEY
21 18
27 GN D 2 GN D 6 26
29 GN D 3 GN D 7 34
27 3G _ D E T #
35
23
GN D 4
GN D 1 1
GN D 8
GN D 9
GN D 1 0
40
50 SIM CONN
25 P E T n0 20 R 42 0 *4 . 7K _0 4
31 P E T p0 W _D I S A B L E # 22 3 G _E N 27
33 P E Rn 0 P E RS E T # 30 L106 *W C M2 0 12 F 2 S -1 61 T 0 3-s h o rt
P E Rp 0 S M B _C L K 32 2 1
3 G_ 3 . 3 V 17 S M B _D A T A 36 USB_ P N 9 1 6
J _ S I M1
19 R e s erv e d 0
R e s erv e d 1
USB_ D -
U S B _D +
38 3 4
USB_ P P9 16 LO CK
D avid 8/25
37 R4 2 1 R 4 22
39 GN D 1 2 24 R 41 9 *1 5 m li _ sh o rt _ 06 *1 0 mi l _s h o rt _0 4 *1 0m i l _s h or t _0 4
3. 3 V A U X_ 3 3 .3 V A UX _ 1 3 G_ 3 . 3 V (T OP VI EW )
C5 9 8 C5 9 9
41
43
45
3. 3 V A U X_ 4
GN D 1 3
R e s erv e d 2
1. 5 V _ 1
1. 5 V _ 2
3 .3 V A UX _ 2
28
48
52 60 mil s
3G _ 3. 3 V
C 86 8
U I M _C LK
UIM _ RS T
UIM _ P W R
C3
C2
C1
U I M_ C L K
U I M_ R S T
U I M_ P W R
U I M_ D A T A
U I M_ V P P
U I M_ GN D
C 7
C 6
C 5
UIM _ DA T A
UIM _ V P P Sheet 22 of 41
0 . 1u _ 1 6V _ Y 5V _ 0 4 1 0u _ 1 0V _ Y 5V _ 0 8 47 42 0 . 1 u_ 1 6 V _Y 5 V _0 4 C6 0 5
49
51
R e s erv e d 3
R e s erv e d 4
R e s erv e d 5
L E D_ W W A N #
LE D _ W LA N #
L E D_ W P A N #
44
46 C6 0 0
+ C 6 01
*2 2 p _5 0 V _ N P O_ 0 4 O PEN
C 1 77 0 6 61 -1
C 6 02
*2 2p _ 5 0V _ N P O_ 0 4
C6 0 3
*2 2 p_ 5 0V _N P O_ 0 4
C 60 4
* 22 p _ 50 V _ N P O _0 4
CCD/ 3G
8 89 1 0 -52 0 4 M-0 1 *0 . 1 u _1 6 V _ Y 5 V _ 04 S I ML OC K
22 0 u _4 V _ V _ B
AO3409? ? ?
AO3409( 90mohm) C hange
to AO3 415(45moh m). CCD
3G POWER 5V Q 10
MT P 3 4 03 N 3
5V _ C C D
3 . 3 V _ 3G S D 48 mil
R7 8 9 *0 _ 0 6 3G _3 . 3 V MJ_CCD1
3 .3 V S
Q 32 C 6 10 C6 1 1 R 4 23 C 61 2 C 6 13 C 6 14
G
A O3 41 5 C8 4 6 1
R7 9 0 0 _ 06
3A 120mils S D
3A 120mils 1 u _ 6. 3 V _ Y 5 V _ 0 4 10 0 K _ 04 * 1u _ 6 . 3V _ Y 5V _ 0 4 0 . 1 u _1 6 V _ Y 5 V _ 04 1u _ 6. 3 V _ Y 5 V _ 0 4
3 .3 V
0 . 1 u _1 6 V _ Y 5 V _ 04
1 u_ 6 . 3 V _Y 5 V _0 4 R4 2 4 5
C5 9 6 C 5 95
G
C 8 57 1u _ 6 . 3V _ Y 5V _ 0 4 1 00 K _ 0 4
1 0u _ 10 V _ Y 5 V _ 0 8 0. 1 u _1 6 V _ Y 5 V _ 04 J _ CCD 1
R4 2 6 3 3 0K _ 0 4
1
R7 9 1 R 7 92 16 US B _ P N5
D
2
16 U S B _P P 5 CC D_ DE T # 3
2 0K _ 1 % _0 4 1 0 _ 06 Q1 1 2 7 C C D _D E T #
C CD_ E N G MT N 7 0 0 2Z H S 3 4
27 C C D _E N 5
R7 9 3 1 0 0K _ 0 4
S
3
D 8 5 20 5 -0 50 0 1
From H8 default HI
6
D
5 G Q 3 3B
2 G Q3 3 A S R T 3K 4 4 M
2 7 3G _ P OW E R
4
S R T 3 K 4 4M
1
From SB GPI O P in de fa ul t HI ADDR128,Q2

Pow e r Pla ne : Suspe nd So lut ion F or 1A
U4 7
S3 : Def ine d PDA
4 1
BUG- Wh en V IN V O UT
5
Bat te ry V IN 1A
dis charge to
C C D _E N 3 2
sh utd ow n, EN GN D
th e CMOS *G 52 4 3 A
so me time s
los s.
CCD/ 3G B - 23
Schematic Diagrams
Card Reader/ LAN JMC261C
3 . 3 V _L A N
JMC261 C S D_ CL K
C 6 43 near Pin#41
S D _ CL K R 44 0 0_04
S wit ch in g Reg ul at or
c los e to P IN3 3
LDO t ype ? J MC26 1C ,
L6 2 NC da vid 8 /25
5V
DV DD U 49
L62
3 . 3V S * 1 0p _ 50 V _ N P O_ 0 4 3 . 3 V _ LA N (> 20m il ) C8 5 2 6 5
REG L X DVDD VC NT L VIN 9
. R4 3 7 R4 4 6
3 . 3V _L A N R4 3 6 *4 . 7 K _0 4 S D_ CD # DV D D 1 u_ 1 0 V _Y 5 V _0 6 4 VIN 7
(> 20m il ) VO UT P OK U 31
*S W F 2 52 0 C F -4 R 7 M -M C 6 44 C6 4 5 * 4 . 7K _ 0 4 *4 . 7 K _ 04
R 4 33 1 K_ 0 4 M S_ INS# S D X C _ P OW E R DV D D 3 8 7
S D X C _ P OW E R
VO UT 8 V D D_ IN V CC WP
Fo r J MC 25 1/2 61 o nl y 1 0 u _1 0 V _ Y 5 V _ 08 0. 1 u _ 16 V _ Y 5 V _ 0 4
VCC _ CA R D C 6 46 Pin#33 Pin#33 EN LA N _ S C L 6
LA N _ LE D 0
L A N_ L E D1
2 1 5 S CL 1
C 64 7 C8 5 3
M DIO 1 1
R E GL X
VF B GN D S DA A0 2
S D _D 2
S D_ D1
S D_ D 0
S D _B S
R4 4 4 1 K_ 0 4 SD _ W P * 0 . 1u _ 1 6V _ Y 5V _ 0 4
S D_ D3
2 . 2 u _6 . 3 V _ X5 R _0 6 A1
I S ON
8 2 p _5 0 V _ N P O _0 4 LA N _ S D A 4 3
V DD 3 3 . 3V A X 6 6 10 G ND A2
Card Reader Pull High/Low *A T 2 4C 0 2B N

for AX6610 , Ra( 1. 69K_1% ) , 3 . 3V V D D3
Resistors Vout=0.8(1+Ra/Rb).
Rb( 2.7K_1% )
48
47
46
45
44
43
41
39
37
35
33
42
40
38
36
34
U3 0 R5 8 4 R4 3 4
AP L5603-12B Change AX6610.
IS O N
LX
MD I O1 1
L A N_ L E D0
LA N _ LE D 1
M DIO 5
M D I O4
M DIO 3
M D I O2
M DIO 1
M D I O0
FB1 2
V D DIO
G ND
V DDO
GN D
C R _ C D 1N R 5 8 3 * 0_ 0 4 MS _ I N S # 0 _0 6 *0 _ 06 R4 4 7 R 5 81
U4 3
MD I O1 3 R 5 8 8 0 _ 04 ( >2 0m il) D VDD 1.2 V 5 1 *0 _ 0 6 0_06
M DIO 1 0 49 32 V D DR E G OU T I N 3. 3 V S V D D 3
50 M D I O 10 VD DREG 31
M DIO 9 ( >2 0m il) R4 4 2
M DIO 8 51 M DIO 9 VC C3 V 30 3 .3 VS 3 V D D_ IN
52 M DIO 8 P W RCR 29 V C C_ CA R D Ra 1 . 6 9K _ 1 % _0 4
S HD N#
DVD D VD D TEST
L A N _M D I P 0 53 28 M PD 4 2 MP D R 44 5 10 K _ 0 4
L A N _M D I N 0 54 V I P _1 MP D 27 SET GN D
R 82 8 0_04 L A N _ P C I E _W A K E # 2 7 C6 4 8
55 VIN _ 1 W AKEN 26 L A N _S C L *A P L 5 6 03 -1 2 B I -T R G R 58 9 *4 . 7 K _0 4
DVD D L A N _M D I P 1 56 AV DD1 2 L AN_ L E D2 25 L A N _S D A R5 8 5 1 u_ 6 . 3 V _ Y 5 V _ 04
Rb
L A N _M D I N 1 57
58
V I P _2
VIN _ 2 JMC261 C C R _ LE D
R S TN
24
23
B U F _ P LT _ R S T #
S EE DA T B U F _P L T _ R S T # 15 , 1 9 , 2 4, 2 6 , 2 7
2 . 7 K _1 % _ 04 C6 4 9 0 . 1 u_ 1 6 V _ Y 5 V _ 04
59 G ND CP P E N 22
3 . 3 V _L A N AV DD3 3 GN D G9141
Sheet 23 of 41 C8 0 4
DV D D
L A N _M D I P 2
L A N _M D I N 2
A V D D 12 _ 62
L A N _M D I P 3
60
61
62
63
V I P _3
VIN _ 3
AV DD1 2
( LQFP 64) V DDIO
MD I O6
M D I O1 2
21
20
19
18
SD _ W P
3 . 3 V _ LA N
APL5603-12B(no R201,R198)
R6 7 7 * 0_ 0 4 B U F _P LT _ R S T #
Card Reader/ LAN L A N _M D I N 3 64 V I P _4 M D I O1 4 17 S D _ CD#

VIN _ 4 C R _ C D 0N 3. 3 V S
C R_ CD 1 N
10 u _ 10 V _ Y 5 V _ 0 8
3 . 3V
A VD D1 2
A VD D1 2
M D I O1 3
Pin#59
A V D D 33
(>2 0m il ) (> 20m il )
M DIO 7
VD DR EG
R EXT
X OU T
C LK N
CL K P
JMC261C
RX N
G ND
T XP
T XN
RXP
X IN
PC Ie D iff er en ti al
C6 5 0 C6 5 1 C 65 2 C 8 17
need to close to chip Pa ir s = 1 00 O hm
JM C 2 6 1 C R8 2 5
for D3E C991022
11
13
15
V DD 3 3 .3 V
1
2
3
4
5
6
7
8
9
10
12
14
16
1 0u _ 1 0V _Y 5V _0 8 0 . 1u _ 1 6V _ Y 5V _ 0 4 1 0 u_ 1 0 V _Y 5 V _0 8 0. 1 u _ 16 V _ Y 5 V _ 0 4
1 0K _ 0 4 Pin#32 Pin#32 Pin#31 Pin#31
CR _ CD1 N
L A N X OU T
R 8 26 *0 _ 0 4 R 72 9 *0 _ 06
10/28 Modify value
M D I O 13
LA N X I N
3 . 3V _ L A N
M D I O7
L A N X OU T
JM _D 3 MO D E
JM _ D 3 MO D E 1 6
R4 3 5 R 44 1 *0 _ 06
need to close to chip
D
R4 3 2 * 1M _ 04 L A NXIN R6 0 1 *0 _ 0 4
J M C _ 2 5M _I N 1 5
12 K _ 1 %_ 0 4 Q7 9
X8 6- 22- 25 R0 0-1 B4 SE E DAT G M TN 7 00 2 Z H S 3
2 1 V D D3
6- 22- 25 R0 0-1 B5
S
IS O N
D VDD
D VDD
F S X5 L _ 25 MH Z 3 . 3 V _ LA N R 44 3 0_ 0 4
C 8 02 C8 0 1
need to cl ose to chip
R 43 8 *1 0 K _0 4
27 p _ 50 V _ N P O_ 04 27 p _ 50 V _ N P O _ 04
need to cl ose to chip C 81 1 0. 1 u _ 10 V _ X 7R _ 04
P C I E _ R X P 0 _ JM C 1 5
C 81 9 0. 1 u _ 10 V _ X 7R _ 04
P C I E _ R X N 0_ J MC 15
P C I E _T X N 0 _ JM C 1 5
P C I E _T X P 0 _J MC 1 5
D VDD DV D D DVD D DVD D D V DD

C L K _P C I E _ J MC 15
C LK _ P C I E _ JM C # 1 5 Card Reader
4 IN 1 SOCKET SD/MMC/MS/MS Pro
3. 3 V _ L A N
D4 5 Power J _C A R D -R E V 1
P CIE _ W A K E# A C R5 8 2 1 0 K _ 04 S D_ CD # P1
16 , 2 4 , 26 P C I E _ W A K E # P2 CD_ S D
C8 0 9 C8 0 7 C8 1 6 C 8 54 C 8 10 S D_ D2
LA N _ P C I E _ W A K E # V C C_ CA R D V CC _ CA RD S D_ D3 P3 D A T 2 _S D
0 . 1u _ 1 6V _Y 5V _0 4 0 . 1u _ 1 6V _ Y 5V _ 0 4 0. 1 u _ 16 V _ Y 5 V _ 0 4 0. 1 u _ 16 V _ Y 5 V _ 0 4 * 10 u _ 6. 3V _ X 5 R _ 06 R B 7 5 1V SD_ BS P4 C D / D A T 3_ S D
P5 C MD _ S D
Pin#52 Pin#55 Pin#62 Pin#35 Pin#7
Reserved C 8 39 P6 VSS_ SD
S D_ CL K P7 V D D _S D
R6 4 3 0_04 R6 4 5 0_04 10 u _1 0 V _ Y 5 V _ 0 8 C 80 3 C 80 6 P8 CL K _ S D
S D_ D0 P9 VSS_ SD
M LM X 0-_ R 4 3 M L MX 0 - ML MX 1 -_ R 4 3 ML M X1 - 0 . 1 u_ 1 6 V _ Y 5 V _ 04 S D_ D1 P1 0 D A T 0 _S D
3 .3 V_ L AN *W C M2 0 12 F 2 S -1 6 1T 0 3 *W C M2 0 12 F 2 S -1 6 1T 0 3 * 0. 1 u _ 16 V _ Y 5 V _ 0 4 SD_ W P P1 1 D A T 1 _S D
D VDD DV DD M LM X 0+ _ R 1 2 M L MX 0 + ML MX 1 + _R 1 2 ML M X1 + P1 2 W P_ SD
L 13 1 L 13 2 P1 3 V S S _ MS
P1 4 V C C _M S
R6 4 4 0 _0 4 R6 4 6 0_04 S D_ CL K
C 8 20 C 81 2 V C C_ CA R D C 82 1 C 81 5 S D_ D3 P1 5 S C L K _ MS
MS _ I N S # P1 6 D A T 3 _M S
C 8 08 C 8 13
0 . 1 u _1 6 V _ Y 5 V _ 0 4 * 0. 1 u _ 10 V _ X 7R _ 04 0 . 1 u_ 1 6 V _ Y 5 V _ 04 S D_ D2 P1 7 I N S _ MS
S D_ D0 P1 8 D A T 2 _M S
Pin#43 Pin#43 0. 1 u _ 16 V _ Y 5 V _ 0 4 0 . 1 u _1 6 V _ Y 5 V _ 04 L36 * 0. 1 u _ 16 V _ Y 5 V _ 0 4
Pin#7 Pin#13 R7 3 6 S D_ D1 P1 9 S D I O / D A T 0 _M S
L A N _M D I P 0 7 10 ML M X0 + _ R SD_ BS P2 0 D A T 1 _M S P 22
*7 5_ 1 % _0 4
L A N _M D I N 0 8 T D+ TX+ 9 ML M X0 -_ R J _R J1 P2 1 B S _M S G ND P 23
T D- T X- ML MX 0 + 1 GN D 1 V S S _ MS G ND
D a v di 8 / 2 7
3 . 3 V _ LA N 4 12 ML MX 0 - 2 DA+ s h ei l d GN D 2 MD R 0 1 9-C 0 -10 4 2
5 N C NC 13 ML MX 1 + 3 DA- s h ei l d
N C NC ML MX 1 - 6 DB+
10/21
L A N _M D I P 1 1 16 ML M X1 + _ R DB-
C 81 4 C 80 5 C 8 18 L A N _M D I N 1 2 R D+ RX + 15 ML M X1 -_ R
R D- R X- 4
0 . 1 u _1 6 V _ Y 5 V _ 04 0 . 1 u_ 1 6 V _Y 5 V _0 4 0 . 1 u _1 6 V _ Y 5 V _ 04 R D_ CT 3 14 RX _ CT D C _N P 5 DC+
R D_ CT R X _C T DC- Fo r JM C2 51 C
Pin#59 Pin#2 Pin#21 R4 5 0 T D_ C T 6 11 T X_ CT 7
T D_ C T T X _C T 8 DD+ 3 . 3 V _ LA N
*0 _ 04 D D _N P
DD-
C 48 9 C 61 9 P 30 1 2 R3 3 4 R3 4 8 R 2 69 R 3 43 P J S -0 8S L 3 B C 8 00 C 79 9
Pla ce all cap acito rs clo sed t o ch ip. W240BU 6-21-B4000-008
0 . 0 1u _ 1 6V _ X 7 R _0 4
*0 . 1u _ 1 6V _Y 5V _0 4 *1 0 u_ 1 0 V _ Y 5 V _ 08
*0 . 0 1 u_ 1 6 V _ X 7R _ 04
75 _ 1 %_ 0 4
75 _ 1 %_ 0 4
75 _ 1 %_ 0 4
75 _ 1% _ 0 4
The su bscript in eac h CAP incica tes t he p in W250BUQ 6-21-B4040-008
Pin#2 Pin#2
nu mber of JMC251/JMC261 t hat shou ld b e
clo sed t o. C 6 20
1 0 0 0p _ 2 K V _X 7 R _ 1 2 _H 1 25
B - 24 Card Reader/ LAN JMC261C

Schematic Diagrams
MINI PCIE/ SATA HDD/ ODD
MINI CARD (WLAN,Port 5)

20 mil 3 .3 V
Layo ut Sho w "WLAN( Wimax, 802. 11N) "Not e C 84 7
0 . 1 u _1 6 V _ Y 5 V _ 04
J_ M I N I 1
P CIE _ W A K E # R5 0 9 *0 _ 0 4 1 2
1 6, 2 3 , 2 6 P C I E _ W A K E # 3 W AKE# 3 . 3 V A U X_ 0 6
R 4 51 1 0 K _ 04 5 C OE X 1 1. 5 V _ 0 8 20 mil
3 .3 VS C OE X 2 U I M_ P W R 10 V D D3
R4 5 2 *0 _ 04
W LA N _ C L K R E Q # 7 U I M _D A T A 12 R4 9 6 0 _0 4 B T_ ON 1 5 , 28
1 6 W L A N _ C L K R E Q# 11 C L K RE Q # UIM _ CL K 14 8 0 CL K 27
R7 2 2 1 00 K _ 0 4
15 C LK _ P C I E _ W LA N # 13 R E F C LK - U I M _R E S E T 16 R5 0 8 0 _0 4 3 IN 1
15 C LK _P C I E _ W L A N 9 R E F C LK + UIM _ V P P
15 G ND 0 4
G ND 1 GN D 5
KEY
21 18
27 G ND 2 GN D 6 26
29 G ND 3 GN D 7 34 R4 5 3
G ND 4 GN D 8 40 *1 0 K _0 4 3 .3 V S
35 GN D 9 50
27 W LA N _ D E T # G ND 1 1 GN D 1 0
R 7 23 *1 0 m li _ sh o rt 23
1 5 P C IE _ RX N3 _ W L A N 25 P E Tn 0 20
1 5 P C I E _R X P 3_ W L A N R 7 24 *1 0 m li _ sh o rt W L AN_ E N 2 7 ,2 8
31 P E Tp 0 W _D I S A B L E # 22 B U F _P L T _ R S T #
1 5 P C I E _ T XN 3_ W L A N 33 P ERn 0 P E RS E T # 30 B U F _ P L T _R S T # 1 5 , 1 9, 23 , 2 6 , 27
1 5 P C I E _T X P 3 _ W LA N P ERp 0 S M B _ CL K 32
17 S M B _D A T A 36 B T _D E T # 2 7 , 2 8
R 4 55 *1 0 K _ 04 R 72 5 * 10 m i l_ s ho rt US B _ P N 2 1 6
27 , 2 8
27
B T _E N
3I N 1
3 IN1
R4 5 4
R7 3 8
*0 _0 4
*0 _0 4
3. 3 V
19
37
39
R e se rv e d 0
R e se rv e d 1
G ND 1 2
3 . 3 V A U X_ 3
U S B _D -
U SB _ D+
3 . 3 V A U X_ 1
38
24 3. 3 V A U X _1 20 mil
R 72 6
R7 2 7
* 10 m i l_ s ho rt
0 _ 04
US B _ P P 2 1 6
3. 3 V
Port 2 Sheet 24 of 41
41 28
R4 9 4 * 1 0K _ 0 4
43
45
47
3 . 3 V A U X_ 4
G ND 1 3
R e se rv e d 2
1. 5 V _ 1
1. 5 V _ 2
3 . 3 V A U X_ 2
48
52
42 20 mil 3 .3 V
MINI PCIE/ SATA
V D D3 49 R e se rv e d 3 L ED_ W W AN# 44
1 5, 2 8
2 7, 2 8
B T_ ON
B T _E N
3 .3 V
R4 5 6
R4 5 7
R4 5 8
* 1 0K _ 0 4
* 0 _0 4
0 _0 4
51 R e se rv e d 4
R e se rv e d 5
LE D _ W L A N #
L E D _W P A N #
B E L LW E TH E R 8 0 0 03 -1 0 21
46 W LA N _ LE D # 27 , 2 8
R7 3 9 *0 _0 4
8 0 CL K 27 HDD/ ODD
SATA HDD SATA ODD

J _ HD D1
S1 J _ OD D 1
S2 S A TA _ T X P 0 C6 5 3 0 . 0 1 u_ 1 6 V _ X7 R _ 0 4 S1
S3 S A TA T X P 0 1 7 S2
S A TA _ T X N 0 C6 5 4 0 . 0 1 u_ 1 6 V _ X7 R _ 0 4 S A T A _ TX P 1 C 65 6 0. 0 1 u _1 6 V _ X7 R _0 4
S4 S A TA T X N 0 1 7 S3 S A T A _ TX N 1 C 65 7 0. 0 1 u _1 6 V _ X7 R _0 4 S A T A TX P 1 1 7
S5 S4 S A T A TX N 1 1 7
S A TA _ R XN 0 C6 5 5 0 . 0 1 u_ 1 6 V _ X7 R _ 0 4
S6 S A TA _ R XP 0 C6 5 8 0 . 0 1 u_ 1 6 V _ X7 R _ 0 4 S A TA R X N 0 1 7 S5 S A T A _ R X N 1 C 65 9 0. 0 1 u _1 6 V _ X7 R _0 4
S7 S A TA R X P 0 17 S6 S A T A RX N1 1 7
S A T A _ R X P 1 C 66 0 0. 0 1 u _1 6 V _ X7 R _0 4
3 . 3V S S7 S A T A R X P 1 17
P1
P2
P3 C6 6 1 P1 R7 0 5 0_ 0 4 OD D _ D E T E C T#
P4 P2 O D D _ D E TE C T # 16
C6 6 2
P5 *0 . 0 1 u_ 1 6 V _ X7 R _ 0 4 P3 3 .3 VS
P6 P4 OD D _ 5 V
*1 0 u _1 0 V _ Y 5 V _ 08 5V S
P7 P5
P8 P6 R 70 6 *1 0 K _0 4
P9 5V S OD D _ 5 V
P1 0
2 2 0u _ 6 . 3V _ 6 . 6 *5 . 7
C 1 8 5 53 -1 1 30 5 -L
G
P1 1 H D D _N C 0 P IN G ND 1 ~ 2 = G ND *M TN 70 0 2 Z H S 3 Q 7 R7 0 2 0 _ 06
0 . 1 u_ 1 6 V _Y 5 V _ 0 4
0 . 1 u_ 1 6V _Y 5 V _ 0 4
0 . 1u _ 1 6V _Y 5 V _ 0 4
1 u_ 6 . 3 V _Y 5V _ 0 4
2 2u _ 6. 3V _ X 5 R _ 0 8
22 u _ 6. 3 V _ X 5 R _ 0 8
P1 2
P1 3 H D D _N C 1 S D Q3 0
P1 4 H D D _N C 2 O D D _D A # _F C H 1 6 S D
P1 5 H D D _N C 3
* A O3 4 0 9
A L L T OP -C 16 6 N 5 -1 2 20 5 -L R 70 3 C8 4 5
G
+ * 1M _ 04
A L L T O P -C 1 6 6 N 5 -1 2 2 0 5 -L *1 00 0 p _5 0 V _ X7 R _0 4
C6 7 1
C6 7 2
C6 7 3
C6 7 4
C6 7 5
C6 7 6
C 67 0
W240BU 6-20-43730-122 R 70 4
*1 0 K _0 4
D
W250BUQ 6-20-43750-022
Q 31
R7 0 7 * 1K _0 4 G * MT N 7 0 02 Z H S 3
17 OD D _ P W R
S
5 VS
OD D _ 5 V
C 6 77 C 6 78 C 67 9 12 /6 Re se rve
0. 0 1 u _1 6 V _ X7 R _0 4 0 . 0 1 u_ 1 6 V _X 7 R _ 0 4 0 . 0 1u _ 1 6V _X 7 R _ 0 4
C6 6 3 C 66 4 C6 6 5 C6 6 6 C 66 7 C 66 8 + C6 6 9
0 . 1 u _1 6 V _ Y 5 V _ 04 1 u_ 6 . 3 V _ Y 5 V _ 04 * 22 0 u _6 . 3 V _ 6. 6 * 5. 7
*0 . 1 u _1 6 V _ Y 5 V _ 04 0. 1 u _ 16 V _ Y 5 V _ 0 4 1 0 u _1 0 V _ Y 5 V _ 08 *0 . 1 u _1 6 V _ Y 5 V _ 04
MINI PCIE/ SATA HDD/ ODD B - 25

Schematic Diagrams
AUDIO CODEC ALC261C
5
8
C
o
m
p
o
n
e
n
t
.
AUDIO CODEC
ALC269 VB P V D D1 _ 2 5 VS
Lay out note :
VT1802P For 1 .5 V H DA Link . R 45 9 0 _ 06
GN D a nd AUDG spa c e is EM I Requ ire
1. 5V S R4 6 0 * 0 _0 4 60 mil s ~ 100 mi ls
C 6 80 C 68 1 L 1 091 2 *H C B 1 0 05 K F -1 2 1 T2 0
1 0 u _1 0 V _ Y 5 V _ 0 8 0 . 1 u_ 1 6 V _ Y 5 V _ 04
DV D D_ IO
For 3. 3V HDA Li nk. A UDG
R4 6 1 *1 0 m il _ s ho rt VT1802P J P1 *1 0 mi l _ sh o rt
3 .3 V S _ A UD
L75,C718 ? ? ? AN ALOG DIG ITAL J P2 *1 0 mi l _ sh o rt
C6 8 2 C6 8 3 C 68 4 C6 8 5
1 0 u_ 1 0 V _Y 5 V _ 08 0 . 1 u _1 6 V _ Y 5 V _ 04 * 1 0u _ 1 0V _ Y 5V _ 0 8 *0 . 1 u _1 6 V _ Y 5 V _ 0 4 5 V S _A U D C 68 6 0. 1u _ 1 6V _ Y 5V _ 0 4
3 . 3V S L 11 0 3. 3 V S _ A U D L 11 1 5 VS
PD# Cont rol H C B 1 0 0 5K F -12 1 T 2 0 H C B 1 0 0 5K F -12 1 T 20
1 2 1 2 C 68 7 0. 1u _ 1 6V _ Y 5V _ 0 4
C6 8 8 C6 8 9 C 69 0 C 6 91 C6 9 2 C6 9 3 C 69 4 C6 9 5
AZ_ RST# For 3 .3 V 5 VS
HDA Li nk D e- pop 0 . 1u _ 1 6V _Y 5 V _0 4 10 u _ 10 V _ Y 5 V _ 0 8 0 . 1 u _1 6 V _ Y 5 V _ 04 0 . 1 u _ 16 V _ Y 5 V _ 0 4 1 0 u_ 1 0 V _Y 5 V _ 08 0. 1 u _ 16 V _ Y 5V _ 0 4 1 0 u _1 0 V _ Y 5 V _ 08 1 u_ 6 . 3 V _ Y 5 V _ 04 A UDG
R 4 62
D3 3 A U DG A UD G
39
25
46
38
1
9
B A T 54 A W G H 1 0 K _ 04 U 32
H D A _ R S T# 1 A MI C 2- V R E F O J_INTMIC1
P V DD 2
A V DD 2
DVD D1
P VD D1
A VD D1
D V D D -I O
C 3 P D# 4 13 S E N S E _A R4 6 3 2 0 K _ 1% _ 0 4 MI C _ S E N S E
2 A PD # S en s e A M IC_ S E N S E 2 9
2 1
D
2 7 K B C _M U T E # 14 LI N E 2 _ L R4 6 4 3 9 . 2 K _1 % _ 04 H P _S E N S E R 46 5
40 L I N E 2 -L 15 HP _ S E N S E 2 9 VT1802P
Q 13 S P K O UT L + LI N E 2 _ R
R4 6 6 * 10 0 K _ 04 G * MT N 7 0 0 2Z H S 3 P le a se Le t LC Filt e r S P K O UT L - 41 S P K -L + L I N E 2 -R 2.2K_04 4 . 7 K _ 04
Sheet 25 of 41 5V S
t oge t he r a nd c lose t o S P K -L -
M I C 2 -L
16 MI C 2_ L C6 9 6 4 . 7 u _6 . 3 V _ X5 R _0 6 J _ INT M IC1
S
S P K O UT R- 44 17 MI C 2_ R C6 9 7 4 . 7 u _6 . 3 V _ X5 R _0 6 I N T _ MI C R 4 67 1 K _ 04 I N T _ MI C _ OU T
Q 12 C ode c. IF S pe a k er S P K O UT R+ 45 S P K -R - MI C 2 -R 1
S P K -R + 2
AUDIO CODEC
H D A _ R S T #G 18 S E N S E _B
*B S S 1 3 8 _N L w i re le ngt h is le ss EAPD 47 S en s e -B VT1802P 5.1K_1%_04 VT1802P C 69 8
8 8 2 66 -0 2 00 1
AZ_RST# For 1. 5V t han 80 00m ils It don't S PD IF C2 /E A PD 330P
S
S P DI F O 48 19 JD R E F R4 6 8 2 0 K _ 1% _ 0 4 6 8 0p _ 5 0V _X 7 R _ 0 4 P C B F oo t p ri nt = 8 8 2 66 -2 L
S PD IF O J DR EF 20
HDA Link De -pop ne e d the LC Filt e r. M ON O-O U T
MO N O _O U T C6 9 9 * 10 0 p _5 0 V _ N P O _ 04 A UDG
ALC261C C O D E C _ GP I O 02
C O D E C _ GP I O 13 GP I O0 -D M I C -D A T
GP I O1 -D M I C -C L K M I C 1 -L
MI C 1 -R
21
22
MI C 1_ L _ C
MI C 1_ R _C
C7 0 0
C7 0 1
4 . 7 u _6 . 3 V _ X5 R _0 6
4 . 7 u _6 . 3 V _ X5 R _0 6
1 6 H DA _ S DO UT DIGITAL ANALOG 23 LI N E 1 _ L
C 7 02 22 p _ 50 V _ N P O _ 04 5 L I N E 1 -L 24 LI N E 1 _ R C7 0 3 0 . 1 u _1 6 V _ Y 5 V _ 04
S D A TA - OU T L I N E 1 -R
6 27 C O D E C _V R E F C7 0 4 2 . 2 u _6 . 3 V _ X5 R _0 6
1 6 H DA _ B IT CL K B I T -C L K VR EF
R 4 71 2 2 _0 4 A Z _S D I N 0 _ R 8 28 LD O_ C A P
VT1802P 10u VT1802P 75_1%_04
16 H D A _S D I N 0 S D A TA - I N LD O_ C A P 30 MI C 1- V R E F O -R MI C 1-L M I C 1 -L _ M
C7 0 5 1 0 u_ 1 0 V _ Y 5 V _ 08 R4 7 2 1K _ 0 4 MI C 1 -L M 29
10 M I C 1 -V R E F O-R 29 MI C 2- V R E F O
16 H DA _ SY NC S Y NC MI C 2- V R E F O VT1802P NC PIN MI C 1-R M I C 1 -R _M
R4 7 4 1K _ 0 4 MI C 1-R M 2 9
H D A _ R S T# 11 32 HE A D P HO NE - L
16 H D A _R S T # R E S E T# H P -O U T -L 33 HE A D P HO NE - R H E A D P H ON E -L 29 M I C 1 -V R E F O-R R 4 7 5
A UD G 2. 2 K _ 0 4
B E E P _R 12 H P -OU T -R H E A D P H ON E -R 2 9
MI C 1 -V R E F O -L
PC BEEP PC BEEP
CBN
35 C O D E C _C B N M I C 1 -V R E F O-L R 4 7 6 2. 2 K _ 0 4
D 28 C7 0 6 36 C O D E C _C B P
VT1802P 4.7K_1%_04
PV SS2
DV S S 2
A VSS1
C BP
PVSS1
AVSS2
B A T 5 4 CW G H 34
G ND
1 A OP V E E
1u _ 6 . 3V _Y 5 V _0 4
27 K B C_ B EE P C 3 BEEP R 4 77 4 7 K_ 0 4 B E E P _C C7 0 7 C 7 08
2 A
16 H D A _S P K R 2 . 2 u _6 . 3 V _ X5 R _0 6
42
37
A LC 2 69 Q -V B 6 -GR 2. 2 u _ 6. 3 V _ X 5 R _ 0 6
43
49
26
31
FOR VOLUMN
R4 7 8 C7 0 9
ADJUST 1 2/6 S P K OU T R +
SP K O UT R+ 2 9
4. 7 K _ 0 4 10 0 p _5 0 V _ N P O _ 04 A U DG
S P K OU T R -
SP K O UT R- 2 9
A U DG M I C 1 -V R E F O-L
The rm al Pa d pl ac e 9
Vi a hole .
3 .3V S_AUD L 1 12 Re serve 9/8
* F C M 16 0 8 K -1 21 T 0 6_ s h ort
S P K O UT L + S P K O U T L + _L
5VS C 7 10 C7 1 1 C2 3 6 *1 8 0 p_ 5 0 V _ N P O _0 4
C2 4 6 *1 8 0 p_ 5 0 V _ N P O _0 4
20ms * 1u _ 1 0V _Y 5 V _0 6 *1 8 0 p_ 5 0 V _N P O_ 0 4 A UD G
J _ SPK1
AZ_ RST# S P K OU TL - S P K OU TL -_ L S P K OU T L+ _ L
S P K OU T L-_ L 4
* F C M 16 0 8 K -1 21 T 0 6_ s h ort C7 1 2 J_ S P K L 1 SP K O UT R+ L136 * F C M 1 60 8 K -1 21 T 0 6 _s h o rt S P K OU T R +_ R 3
SP K O UT R- S P K OU T R -_R 2
J_SPK1 L 1 13 L135 * F C M 1 60 8 K -1 21 T 0 6 _s h o rt
PD# *1 8 0 p_ 5 0 V _N P O_ 0 4 1 1
2
2 1 * 85 2 0 4-0 4 0 01
8 5 20 4 -0 20 0 1 PN: 6-20- 43130- 104
Spea k er wi re le ngth l es s tha n 8 00 0mi ls , It don't ne ed LC Fil te r. EMI Require P C B F o o t p rin t = 8 5 20 4 -0 2R
C2 3 7 *1 8 0 p_ 5 0 V _ N P O _0 4
C2 3 9 *1 8 0 p_ 5 0 V _ N P O _0 4
SPKO UTR+, R-, L+, L- Tra ce wi dth A UD G
Spea k er 4 ohm- --- -- > 40 mil s
Spea k er 8 ohm- --- -- > 20 mil s
B - 26 AUDIO CODEC ALC261C

Schematic Diagrams
USB 3.0 VL800
Sheet 26 of 41
USB 3.0 VL800
USB 3.0 VL800 B - 27

Schematic Diagrams
KBC- ITE IT8518

R 50 1 *1 5 m li _ sh o rt _ 06 KB C _ AV DD L 1 17 V DD3
V DD3 H C B 1 0 05 K F -1 2 1T 2 0 U 37
. 8 5 K B C _S P I _S I _ R VD D3
C7 4 1 C7 4 2 C7 4 3 C 74 4 C 74 7 V DD 3 VD D SI 2 K B C _S P I _S O _ R
SO 1 K B C _S P I _C E # _R
C8 5 6 C7 4 5 C 7 46
0. 1 u _ 16 V _ Y 5 V _ 0 4 1 0u _ 10 V _ Y 5 V _ 0 8 0 . 1u _ 1 6V _ Y 5V _ 0 4 0 . 1 u_ 1 6V _Y 5V _ 0 4 0 . 1 u_ 1 6 V _Y 5 V _0 4 CE # 6 K B C _S P I _S C L K _R
K B C _ F LA S H 3 SC K
0. 1 u _ 16 V _ Y 5 V _ 0 4 *0 . 1 u_ 1 6 V _Y 5 V _0 4 * 0 . 1u _ 1 6V _ Y 5 V _ 0 4 R 50 2
W P#
C 74 8 1 0 0K _0 4
L 11 8
H C B 1 00 5 K F -1 21 T 2 0 0 . 1 u_ 1 6 V _Y 5 V _0 4 K B C _ A GN D K B C _ H OL D # 7 4 K B C _W R E S E T #
. EC_ VCC HO L D# VSS
3 .3 VS
* A T 25 F 5 1 2A N C 74 9
FOR J W240BU FOR W250BUQ For 8502E
114
127
_ KB1 J _K B 2 1 u _6 . 3 V _ X5 R _0 4
1 21
26
50
92
11
74
3
U3 8 8 52 0 1 -24 0 5 1 * 8 52 0 1- 24 0 51 U9 U28 Co-layout
V CC
A VCC
VST BY
VSTB Y
VBAT
VSTBY
VSTBY
VSTBY
VSTBY
10 58 K B -S I 0 4 KB -S I 0 4
1 5, 1 9 L P C _A D 0 9 L AD 0 KSI0 /ST B# 59 K B -S I 1 5 KB -S I 1 5 1 J_KB1 24
1 5, 1 9 L P C _A D 1 8 L AD 1 K S I1 /A F D # 60 K B -S I 2 6 KB -S I 2 6
1 5, 1 9 L P C _A D 2 7 L AD 2 K S I 2/ I N I T # 61 K B -S I 3 8 KB -S I 3 8
1 5, 1 9 L P C _A D 3 13 L AD 3 K S I 3/ S L I N # 62 K B -S I 4 11 KB -S I 4 11
15 , 1 6 LP C _ C L K 0 L PC CL K KS I4
R7 8 5 *0 _0 4 6 63 K B -S I 5 12 KB -S I 5 12 EC MODULE CHOOSE (FOR DIFFERENCE K/B TYPE)
1 5 , 19 , 2 3 , 24 , 2 6 B U F _ P L T_ R S T# 1 5 , 19 L P C _ F R A ME # 5 LFR A ME # KS I5 64 K B -S I 6 14 KB -S I 6 14
R7 8 6 0_ 0 4
1 5, 1 9 S E RIR Q 22 SER IRQ LPC K/B MATRIX KS I6 65 K B -S I 7 15 KB -S I 7 15
V ER . RX V OLT AG E M OD EL _ID
15 E C_ RS T # L PC R S T #/ W U I 4 / GP D 2 ( P U ) KS I7
K B C _W R E S E T # 14 36 K B -S O0 1 KB -S O0 1
W R ST # K S O0 / P D 0 37 K B -S O1 2 KB -S O1 2
V 1. 0 R5 03 10 K/ R5 04 X 3.3 V W240BU
G A 20 1 26 K S O1 / P D 1 38 K B -S O2 3 KB -S O2 3
16 GA 2 0 4 G A 2 0/ G P B 5 K S O2 / P D 2 39 K B -S O3 7 KB -S O3 7
V 2. 0 R5 03 X/ R 504 1 0K 0V W250BU
1 6, 2 9 , 3 7 A C _ I N # 16 K B R S T #/ G P B 6 ( P U ) K S O3 / P D 3 40 9 9
K B -S O4 KB -S O4 V 2. 0 R5 03 10 K/ R5 04 10 K 1.6 5V W250BAQ
28 LE D _ A C I N P W U R E Q # / GP C 7( P U ) K S O4 / P D 4
R 7 97 0 _ 04 20 41 K B -S O5 10 KB -S O5 10
3 ,1 7 AP U_ T A L E RT # L 8 0L L A T / GP E 7 ( P U ) K S O5 / P D 5 42 13 13
K B -S O6 KB -S O6
( S MI # ) 23 K S O6 / P D 6 43 K B -S O7 16 KB -S O7 16
1 6, 2 6 E C _ S MI # 15 E C S CI# /G P D3 ( P U ) K S O7 / P D 7 44 K B -S O8 17 KB -S O8 17 MO D E L _ I D
( S CI# ) R5 0 3 1 0 K _ 04
16 E C_ S CI# E C S MI # / G P D 4 ( P U ) K S O8 / A C K # 45 K B -S O9 18 KB -S O9 18 VD D3
K S O 9/ B U S Y 46 K B -S O1 0 19 KB -S O1 0 19
DAC R5 0 4 * 1 0K _ 0 4
W L A N _E N 76 K S O 10 / P E 51 K B -S O1 1 20 KB -S O1 1 20
2 4 , 28 W L A N _E N
25 K B C _ MU T E #
77
78
G
G
PJ 0
PJ 1
K S O1 1 / E R R #
K S O 1 2/ S L C T
52
53
K B -S O1 2 21
22
KB -S O1 2 21
22
RX
M E _W E # K B -S O1 3 KB -S O1 3
Sheet 27 of 41 C PU_ F A N 79 D A C 2 / GP J 2 KSO 1 3 54 K B -S O1 4 23 KB -S O1 4 23

29 C P U _F A N 80 D A C 3 / GP J 3 KSO 1 4 55 24 24
( W EB1 # ) K B -S O1 5 KB -S O1 5
2 9 W E B _E MA I L # V G A _F A N 81 D
D
A C 4 / GP J 4
A C 5 / GP J 5
IT8518 KSO 1 5 V DD3
C8 5 5 V D D3
KBC- ITE IT8518 0 . 1u _ 1 6V _ Y 5V _ 0 4

37
37
B A T _ DET
B A T _ V OL T
BA T _ DE T
B A T _ V OL T
66
67 AD
AD
ADC
C 0 / GP I
C 1 / GP I
0
1
FLASH
F L F R A M E # / GP G 2
F L AD0 /S C E #
100
101
( 3 G_ P W R _ E N )
K B C _ S P I _C E # 3 G_ P OW E R 22
SM D_ BA T R8 0 8
SM C_ BA T R8 0 9
2. 2 K _ 0 4
2. 2 K _ 0 4
3G _D E T # R 50 5 1 0K _ 0 4
( APKEY# ) 68 102 K B C _ S P I _S I CCD _ DE T # R 50 6 1 0K _ 0 4

29 A P _K E Y # AD C 2 / GP I 2 F L A D1 /S I Pin100 ,104&106 EXT ? ? Pu ll hi
69 103 K B C _ S P I _S O
2 TH E R M _V OL T L A N _ P C I E _W A K E # 70 AD C 3 / GP I 3 F L A D2 /SO 104 & Pull L ow .
( V C H G-S E L )
2 3 L A N_ P CIE _ W A K E # 3 G_ D E T# 71 AD C 4 / GP I 4 F LA D 3 / GP G 6 105 KB C_ S P I_ SCL K V C H G _ S E L 37 3 .3 VS
22 3 G_ D E T # C C D _ D E T# 72 AD C 5 / GP I 5 F LC L K / S C K 106
22 CCD _ DE T # AD C 6 / GP I 6 ( P D )F L R S T# / W U I 7/ G P G0 / T M C CD_ E N 22
M OD E L_ I D 73 W L A N_ L E D# R 50 7 *1 0 K _ 04
AD C 7 / GP I 7
GPIO 56
S MC _ B A T 1 10
SMBUS ( P D )K S O1 6 / GP C 3 57 S USB # 1 6 , 1 9, 2 6 , 3 0 B A T _V O L T
37 S MC _B A T S USC # 1 6 , 3 0, 3 2 C 7 5 1 1 u _6 . 3 V _ X5 R _0 4
S MD _ B A T 1 11 SM C L K 0 / GP B 3 ( P D )K S O1 7 / GP C 5
37 S MD _B A T S MC _ V GA _ T H E R M 1 15 SM D A T 0 / GP B 4 93
1 0 S MC _ V GA _ T H E R M 1 16 SM C L K 1 / GP C 1 ( PD )G P H0 /ID 0 94
S MD _ V GA _ T H E R M
1 0 S MD _ V GA _ T H E R M R 70 8 0_04 1 17 SM D A T 1 / GP C 2 ( PD )G P H1 /ID 1 95 B T _E N 2 4 ,2 8
3, 1 6 , 1 7 S M C _ C P U _ TH E R M 1 18 SM C L K 2 / GP F 6 ( P U ) ( PD )G P H2 /ID 2 96 B K L _E N 20
R 70 9 0_04
3, 1 6 , 1 7 S M D _ C P U _ TH E R M H _P E C I R 52 3 * 0 _0 4 SM D A T 2 / GP F 7 ( P U ) ( PD )G P H3 /ID 3 97 H S PI_ CE # 1 7
( PD )G P H4 /ID 4 98 H S P I _ S C LK 1 7
PWM VD D3
L C D _ B R I GH TN E S S 24 ( PD )G P H5 /ID 5 99
H S P I _ MS O 1 7 80PORT
K BC_ BE E P( B E EP ) 25 PW M 0 / GP A 0 ( PU ) ( PD )G P H6 /ID 6 107 H S P I _ MS I 17
J_ 8 0D E B U G 1
25 K B C_ B E E P 28 PW M 1 / GP A 1 ( PU ) ( PD )G P G1 / I D 7 D D _O N 2 9 , 3 0, 3 1
28 L E D _ S C R OL L # 29 PW M 2 / GP A 2 ( PU ) 5 3 IN 1
28 L E D _N U M #
30 PW M 3 / GP A 3 ( PU ) EXT GPIO 82 E GA D 4 8 0 CL K
28 L E D _C A P # 31 PW M 4 / GP A 4 ( PU ) ( P D )E GA D / GP E 1 83 3 80 D E T#
2 8 LE D _ B A T _C H G OC P P E # 26 R 51 4 1 0 K _0 4
32 PW M 5 / GP A 5 ( PU ) ( P D )E G C S # / GP E 2 84 2
2 8 L ED_ BA T _ F UL L 34 PW M 6 / GP A 6 ( PU ) ( P D )E G C L K / GP E 3 ICP P E # 26 1
Pin87 3 IN1 mult i 28 L E D_ P W R PW M 7 / GP A 7 ( PU )
WAKE UP *8 52 0 5 -05 0 0 1 1 2/6 Reve rse
f un ctio n pin 35
8 0 CL K 85 PS/2 ( P D )W U I 5 / GP E 5 17 R S M R S T _ GA T E # 16
24 80 C L K 86 PS2 C LK 0 / G P F 0( PU ) ( P D )L P C P D # / W U I 6 / GP E 6 K B C_ RS T # 1 6
2 4, 2 8 B T_ D E T # 87 PS2 D A T0 / G P F 1( PU ) A L L _S Y S _ P W R G D 1 9 , 20
R 7 87 1 K_ 0 4 8 0 D E T # ( 80 P O R T _D E T # ) PWM/COUNTER
24 3 IN1 ( W EB2 # ) 88 PS2 C LK 1 / G P F 2( PU ) 47
2 9 W E B _W W W # 89 PS2 D A T1 / G P F 3( PU ) ( P D )T A C H 0 / GP D 6 48 C P U _F A N S E N 29 VDD 3
For 8512E
V GA _ F A N S E N C7 5 2 KBC_SPI_*_R = 0.1"~0.5"
29 T P _ CL K 90 PS2 C LK 2 / G P F 4( PU ) ( P D )T A C H 1 / GP D 7 0 . 1 u _1 6 V _ Y 5 V _ 04
29 T P_ DAT A PS2 D A T2 / G P F 5( PU ) 120
( P D )T MR I 0/ W U I 2 / GP C 4 1 2 4 ( P M_ P W R O K ) V C O R E _ ON 35 U 39
1 25
WAKE UP ( P D )T MR I 1/ W U I 3 / GP C 6 8 5 K B C _S P I _S I _R K B C _S P I _ S I
22 3G _E N R 7 10 0_ 0 4 R5 2 6 4 7 _ 04
P W R S W / G P E 4( P U ) VD D SI
18
CIR 119 2 K B C _S P I _S O _ R
30 P W R_ S W # C E L L _C ON TR OL 3 7 ? ? ? R5 2 7 1 5 _ 1% _ 0 4K B C _S P I _ S O
21 R I 1# / W U I 0 / GP D 0( P U ) ( P D )C R X / GP C 0 1 2 3 ( K B C _ P ME # ) P ME # R5 2 8 1 K _ 0 4 SO
16 , 2 0 , 29 L I D _ S W # R I 2# / W U I 1 / GP D 1( P U ) ( P D )C TX / GP B 2 K B C _ F LA S H 3 1 K B C _S P I _C E # _R R5 2 9 1 5 _ 1% _ 0 4K B C _S P I _ C E #
W P# CE#
33
GP INTERRUPT LPC/WAKE UP 19 6 K B C _S P I _S C L K _R K B C _S P I _ S C LK
16 P W R_ B T N# S W I# 16 R5 3 0 4 7 _ 04
G I N T / GP D 5 ( P U ) ( P D )L 80 H L A T / GP E 0 R 5 3 2 4 . 7 K _ 04 SC K
112 K B C _ H O LD # 7 4
( P D )R I N G #/ P W R F A I L # / L P C R S T# / GP B 7 C H G_ E N 37 H OL D # VSS
R 83 0 * 0 _0 4 UART
1 0 V G A _ A L E RT # R 82 9 * 0 _0 4 1 08
2 4, 2 8 W L A N _ L E D # 1 09 R XD / GP B 0 ( P U ) CLOCK 2
U37 U39 Co-layout
CK 3 2 K E P C T 25 V F 0 1 6B -75 -4 I -S 2 A F
AVSS
24 W L A N_ DE T # T X D/G P B1 ( PU ) C K 32 K E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
128 CK 3 2 K
C K 3 2K
WEB1 #- --WEB_EM AIL# R 53 1 *1 0 M_ 0 4
WEB2 #- --WEB_WWW # I T8 5 1 8E
1
12
27
49
91
113
1 22
75
X1 0
R 5 33 *0 _0 4 EC_ VS S R5 3 4 *1 0m i l _s h ort 1 4 C K 3 2K E
0 _04 F OR IT 85 12C X/ EX 2 3
0 .1U _0 4 F OR I TE8 51 2- J(I TE 85 02- J W/ 0 CI R) C 7 53 0 . 1 u_ 1 6 V _Y 5 V _0 4 C7 5 4 C 7 55 C K 3 2K Co -la yo ut X2 , X3
E C C os t D ow n
* 12 p _5 0 V _ N P O _0 4 * 12 p _ 50 V _ N P O _ 04
1 4 X1 1
NC 2 S H OR T 2 3
R5 3 5 * 10 m i _l s h ort _ 0 4L C D _ B R I G H T N E S S * MC -14 6 _3 2 . 7 68 K H z * 1T J S 1 25 D J4 A 4 2 0P _ 3 2 . 76 8 K H z
2 0 B R I GH TN E S S 6 -2 2-3 2R 76 -0B 4
6 -22 -3 2R 76- 0B 2
C7 5 6 *0 . 1 u_ 1 6 V _Y 5 V _0 4 K BC_ AG ND R5 34 F or IT8 518 BX& 6 -22 -3 2R 76- 0B G
IT 85 19 BX On ly.
B - 28 KBC- ITE IT8518

Schematic Diagrams
LED/ MDC/ BT
3V _B T
Bluetooth 3 .3 V
J _ BT 1
1
2
16 US B _ P N 6 3
16 US B _ P P 6 4
R5 3 6
2 4, 2 7 B T _ DE T # BT _ EN# 5
6
47 K _ 0 4
3 .3 V *8 7 21 2 -0 6G 0
1 5, 2 4 B T _ ON R5 3 7 * 0_ 0 4
B T _ DE T #
C7 5 7 R 5 38
* 18 0 p_ 5 0 V _N P O_ 0 4 *1 0K _0 4 3 . 3V 3 V_ BT
R 5 39
50 mi l 5 0mi l
B T _ E N#
D
*1 5 m li _ sh o rt _ 06
Q1 4 C 75 8 C7 5 9
G *MT N 70 0 2Z H S 3
2 4 , 27 BT_ EN
* 18 0 p_ 5 0 V _N P O_ 0 4
*1 0 u_ 1 0 V _Y 5V _0 8
3 .3 VS 3 . 3V S
LED 3 .3 VS 3 .3 V S 3 .3 V S 3 . 3V S
LE D _A C I N 2 7 L E D_ B A T _ CH G 2 7
R 5 49 R5 4 6 R5 4 7 R 5 48
R 5 40
22 0 _0 4
R 54 1
2 2 0 _0 4 Sheet 28 of 41
L ED_ PW R 27 L E D _ B A T _F U L L 2 7
22 0 _ 04 2 20 _ 0 4 2 20 _ 0 4 22 0 _0 4
BT WLAN LED/ MDC/ BT
3
LED 1 3 D1 LED
A
A
HDD/ODD NUM CAPS SCROLL R 5 42 R 54 3 R 54 4 R5 4 5
SG
Y
D2 D 3 D 4 D5 2 4 K P B -3 02 5 Y S G C
LED LOCK LOCK LOCK 2 2 0 _0 4 2 2 0_ 0 4 2 2 0_ 0 4 2 20 _ 04
4
R Y -S P 1 70 Y G 34 -5 M
R Y -S P 1 70 Y G 34 -5 M
R Y -S P 17 0 Y G3 4 -5 M
LED LED LED
R Y - S P 17 0 Y G3 4 -5M
R5 5 0 POWER ON
W LA N _L E D # 2 4 , 2 7 BAT LED
C
C
1
3
LED
C
* 10 m i _l s ho rt _ 0 4 D1 3 D 14
B 2
SG
SG
Y
Y
W L A N _E N 2 4, 2 7 K P B -3 02 5 Y S G C K P B - 30 2 5Y S GC
Q1 6
4
* DT C1 1 4 E UA
S A T A _L E D # 1 7 L E D _ N U M# 2 7 L E D_ CA P # 2 7 L E D _ S C R OL L # 2 7
E
C
6- 52- 52 001 -0 27 6- 52 -52 00 1- 027 6-5 2- 520 01 -02 7 6-5 2- 520 01 -02 7
B
BT _ EN 24 , 2 7
Q1 7
D T C 1 1 4E U A
For W240BU
E
H2 5 H1 4 H1 3
M1 M5 M7 M8 M2 9 9 9
M -MA R K 1 M -MA R K 1 M-MA R K 1 M-M A R K 1 M-M A R K 1 H3 4 H3 5 3 8 3 8 3 8
h t 6 _ 0b 7 _0 d 3 _7 H C 6_ 0 d 3_ 7 4 1 7 4 1 7 4 1 7
5 6 5 6 5 6
C 76 0
MT H 31 5 D 1 1 1 MT H 31 5 D 1 1 1 MT H 3 1 5 D 1 1 1 *0 . 1 u_ 1 6V _Y 5V _ 0 4
V D D3
H2 H1
C 1 10 D 11 0 N P M6 M3 M4 H5 H3 H2 4
C 11 0 D 1 1 0N P M-MA R K 1 M-M A R K 1 M-M A R K 1 9 9 9 GN D
3 8 3 8 3 8 J_ T P 4
4 1 7 4 1 7 4 1 7
5 6 5 6 5 6 1 L E D_ P W R
2 L E D_ A CI N
H 29 H 30 H 31
H 17 H 4_ 7 B 6 _0 D 3 _ 7 H 4_ 7 B 6 _0 D 3_ 7 H 4 _7 B 6 _0 D 3_ 7 MT H 31 5 D 1 1 1 MT H 31 5 D 1 1 1 MT H 3 1 5 D 1 1 1 3 L E D_ B A T _ F UL L
H 18 H 15 * H 4 _7 B 6 _ 0D 3 _7 4 L E D_ B A T _ CHG
5
H 6_ 0 D 3 _ 7 S1 S2 H 4_ 7 B 6 _0 D 3 _ 7
S MD 80 X 8 0 S MD 8 0 X 80 6
H1 1 H7 H2 6
9 9 * 85 2 01 -0 6 05 1
3 3 8 3 8
1
4 1 4 1 7 4 1 7 GN D
5 6 5 6 5 6
1
1 2/9 For W250BUQ

mt h3 1 5d 1 1 1_ 3 MT H 31 5 D 1 1 1 M TH 3 15 D 1 1 1
H1 9 H3 6 H3 2 H 33
H 23 H6 H2 1 H 20 H 4 _ 0B 7 _ 0 D 3 _7 h t 6 _ 0b 7 _0 d 3 _7 H 4 _ 7B 6_ 0 D 3 _ 7 H T 6_ 0 B S 1 D 3 _7 H9 H4
C 67 D 6 7 C6 7 D6 7 C 1 10 D 1 1 0 N P C 11 0 D 1 1 0N P 9 9
3 8 3 8
4 1 7 4 1 7
5 6 5 6
MT H 31 5 D 1 1 1 MT H 3 1 5 D 1 1 1
LED/ MDC/ BT B - 29
Schematic Diagrams
USB/ FAN/ TP/ MULTI CON

USB PORT*2(Port 0,Port1) US B V CC1 R7 4 0 0 _ 06
U S B _V C C 2
60 mil
R7 4 1 * 0_ 0 6
Reserve 9/8
US B V CC0
C 7 40 + + C7 6 9 C7 6 8
FAN CONTROL
V DD 5 US B V C C0
2 2 0u _ 6. 3V _ 6 . 6 *4 . 5 *1 0 0u _ 6 . 3V _ B _ A 0 . 1 u _1 6 V _ Y 5 V _ 04 Port 0 5V S _ F A N 5V S U 41
F ON # 1 8
US B PO RT Charg e 2 FO N GN D 7
17
3 VIN GN D 6
100 mil U 10 100 mil 12 /7
1 12 J _ USB 1 4 V O UT GN D 5
IN O UT 27 C P U _F A N VSET GN D
PPAD
R 7 11 0_ 0 4 1
U S B _P N 0 2 11 U S B _ P N 0 _R V+ A X 9 9 5S A
D M_ O D M _I N U S B _P N 0 _R 4 3 2
U S B _P P 0 3 10 U S B _ P P 0_ R *W C M2 0 1 2F 2 S -1 6 1T 0 3 D A TA _ L G 9 9 0P 1 1 U 6 - 0 2- 9 9 01 1 - B2 0
D P _O D P _I N U S B _P P 0_ R 1 2 3
4 14 L 1 20 D A TA _ H P 2 7 93 A 6- 0 2 - 02 7 9 3- B 2 0
I L I M_ S E L G ND 4
G ND1
GN D 2
G ND3
GN D 4
R 7 49 *1 0 K _0 4 5 16 R7 3 7 * 17 . 8 K _ 1% _ 0 4 R 7 12 0_ 0 4 GN D
V D D5 EN /DSC I L I M0 5 VS 5 VS_ FAN
R 7 50 *1 0 K _0 4 6 15 R7 4 5 * 10 K _ 0 4 U S 0 40 3 6 B C A 0 8 1 J _ F A N1
G ND 1
G ND 3
27 , 3 0 , 31 D D _ ON C TL 1 I L I M1
GN D 2
GN D 4
V DD 5
7 9 1
V DD5 R 7 48 *1 0 K _0 4 W 24 0 B U 6 - 21 - B 49 C 0 -1 0 4 C 7 65
C TL 2 NC C7 6 6 2
A C_ IN 8 13 3
R 7 47 * 10 K _ 0 4 R 7 51 *1 0 K _0 4 R7 4 6 *1 0 K _0 4 V DD3 W 25 0 B UQ 6 -2 1 - B4 4 1 0- 0 0 4 0. 1 u _1 6 V _ Y 5 V _ 04
C TL 3 F A U LT # 1 0u _ 1 0V _ Y 5V _ 0 8 8 52 0 5-0 3 7 01
D
R5 7 4 *0 _ 04 U S B _ O C P 0 _1 #
Q7 6 *T P S 2 5 40
G *M TN 70 0 2 Z H S 3 N/A
1 6 , 27 , 3 7 A C _I N #
16 US B _ P N0 U S B _P N 0 R 1 68 0_ 0 4 US B _ P N0 _ R JFAN
S
2 7 C P U_ F A N S E N
3
U S B _P P 0 R 1 71 0_ 0 4 U S B _ P P 0 _R
16 U S B _P P 0
R 5 51 4. 7 K _ 0 4
3 .3 VS 1
CTL1 CTL2 CTL3: 0 X 1-----> Dedicated Charging Port, Auto-detect

Sheet 29 of 41 CTL1 CTL2 CTL3: 1 1 1-----> Charging Downdtream Port, BC Spec 1.1
CTL1 CTL2 CTL3: X 1 0-----> Standard Downstream Port, USB 2.0 Mode.
USB/ FAN/ TP/
MULTI CON 3 . 3V 3 . 3V US B V CC1 L 13 0
*1 5 mi l _ sh o rt _ 06
U S B _ V CC3
80 mil
R 5 52 R 5 53
1 0 K _ 04 *1 0K _ 0 4 + C 7 72 C 7 73 CLICK CONN FO R CLI CK B OA RD
U S B _O C P 0 _ 1 # R 5 54 *0 _ 04 U S B _F L G # * 10 0 u _6 . 3 V _ B _A 0 . 1 u _1 6 V _ Y 5 V _0 4
1 6, 2 6 U S B _ O C P 0 _ 1#
Port 1 5 VS_ TP
J _ USB 2 R 5 55 * 15 m il _ s ho rt _ 0 6
U 40 1 5V S
5V 5 6 U S B V CC 1 R7 1 3 0 _0 4
U S B _ F L G# V+ C 77 0 C7 7 1
F L G# V O U T 1
100 MIL 4 3 2 R 5 56 R 5 57
2 7 16 U S B _P N 1 DA T A _ L
VIN1 V O UT 2 * W C M 20 1 2 F 2S -1 6 1 T0 3 * 10 u _ 10 V _ Y 5 V _ 08 1 u_ 6 . 3V _Y 5V _ 0 4
1 2 3 J_ T P 1 10 K _ 0 4 10 K _ 0 4
C 76 1 3 8 C 7 62 C 7 63 C 7 64 1 6 US B _ P P 1 DA T A _ H
VIN2 V O UT 3 L1 2 1
1
G ND 2
G ND 4
4
GN D 1
GN D 3
1 0u _ 10 V _ Y 5 V _ 0 8 4 1 T P _D A T A 2 7
0 . 1 u _1 6 V _ Y 5 V _ 04 0. 1 u _1 6 V _ Y 5 V _ 04 *1 0u _ 6 . 3V _ X 5 R _ 06 R7 1 4 0 _0 4 GN D 2
E N# G ND 3 T P _C LK 27
R T9 7 1 5B G S U S 0 40 3 6 B C A 0 81 4 C 7 74 C 7 75
G ND 1
GN D 2
G ND3
GN D 4
8 52 0 1-0 4 0 51
W 24 0 B U 6 - 2 1- B 4 9C 0 - 10 4 47 p _ 50 V _ N P O _0 4 47 p _ 50 V _ N P O _0 4
3 0, 3 2 , 3 3 D D _ ON #
W 25 0 B UQ 6 - 21 - B 44 1 0 -0 0 4
VDD 3 3 .3 VS 3 .3 V
Audio/B CONN.(Port 2) POWER SWITCH CONN. CLOSE TO J_SW1 AP_ KEY #

W E B _W W W #
R8 3 1
R8 3 2
1 0 K _ 04
* 1 0K _ 0 4
W E B _E M A I L # R8 3 3 * 1 0K _ 0 4
AP_ KEY# J_ S W 2
FOR P OW ER S WI TC H BO AR D A P _K E Y # 2 7 2 0m il
1
2 MB T N
US B V CC1 R7 3 3 0 _ 06 R5 5 8 *1 0 m il _ sh o rt _ 04 M_ B T N #
3 . 3V S 3. 3 V 3 W EB_ W W W #
1.1A 60mils 4
D
W E B _ E MA I L #
R7 3 4 *0 _ 0 6 C7 7 8 0 . 0 1 u_ 1 6 V _X 7 R _ 0 4 C7 7 6 C 7 77 Q 18 5 LI D _ S W #
5V 6
G
* MT N 7 0 02 Z H S 3 7 AP_ KEY#
S
J _ A UDIO 1 0 . 01 u _ 16 V _ X 7R _0 4 0. 0 1 u_ 1 6 V _X 7 R _ 0 4 8
12 /10 Dele te R5 59
88 4 8 6-0 8 01
F OR A UD IO B OA RD 2 5 M I C 1 -R M
M I C 1 -R M
M IC1 -L M
1
2 M_ B T N #
J _ SW 1
2 5 M I C 1 -L M 3 20 mi l 30 M_ B T N #
1
R5 6 0 12 /8
H E A D P H O N E -R 4 1
2 5 H E A D P H ON E -R *1 0m i l _s h or t _0 4 P C2 3 0 P R 21 5
H E A D P H O N E -L 5 2 M _B T N #_ R M_ B TN # * 47 K _ 0 4 P V1
2 5 H E A D P H ON E -L M IC_ S E NS E 6 3 W EB_ W W W #
2 5 M IC_ S E N S E W E B _W W W # 2 7 A P _ ON 30 *0 . 1u _ 5 0V _ Y 5V _ 0 6
S P K _H P # 7 4 W E B _ E M A I L# *V 1 5 A V L C 0 4 02
H P _ S ENSE 8 5 L ID_ S W # W E B _E M A I L # 2 7
1
2 5 H P _ S ENSE 9 6 L I D _ S W # 1 6, 2 0 , 2 7
2
U S BN4 _ R
U S B P 4 _R 10 7 A P _ ON PV2
11 8
S P K OU T R + 12 9 *V 1 5 A V L C 0 40 2
2 5 S P K OU T R + 13 10 VIN
2 5 S P K OU T R - S P K O UT R-
14
2
R5 6 1 *1 0 m il _ sh o rt _ 04 U S B N4 _ R 8 5 20 1 -14 0 5 1-0 1 * 5 05 0 0- 01 0 41 -0 0 1L
16 USB _ PN4 1 2/8
R5 6 2 *1 0 m il _ sh o rt _ 04 U S B P 4 _R
16 USB _ PP 4
Ch an ge co nne ct or If system has APON function, uses J_SW1
If system has no APON function, uses J_SW2
B - 30 USB/ FAN/ TP/ MULTI CON

Schematic Diagrams
5VS/ 3.3VS/ 1.8VS/ 1.5VS/ 1.1VS

VI N
VA VIN V IN 1 3 .3 V
V IN 1
R8 1 0 PU 1
1 8 12 /6 PC 6 PC 7 PC 8 C 7 79
V A VA V IN1
*1 2 K _ 06
2 7 R5 6 3 1 K _ 04 0 . 1 u_ 5 0 V _Y 5 V _ 06 0 . 1 u _5 0 V _ Y 5 V _ 0 6 0 . 1 u_ 5 0 V _ Y 5 V _ 0 6 0 . 0 1 u _1 6 V _ X7 R _0 4
V IN V IN D D _ ON _L A T C H D D_ O N 2 7 , 29 , 3 1 ON
DD_ON"L" T O
P R 2 10 1 K_ 0 4 3 6 P R1 8 1 K_ 0 4
29 M_ B T N # M _B T N # P W R_ S W # P W R_ S W # 2 7 "H" FROM EC
P R 2 11 1K _ 0 4 4 5
29 A P _ ON I N S TA N T -ON GN D PR 3 10 0 K _ 0 4 V DD 3
P 2 8 0 8B 0
S Y S 5V S Y S 5V SY S5 V
5V
PR 4 P R5 P R6
1 0 K_ 0 4 1 0 K_ 0 4 10 K _ 0 4 ON
ON S US C
S US C 3 3, 3 5
C 78 0 C7 8 1 C7 8 2 D D _ ON # SU SB
D D_ O N# 2 9 , 3 2 , 33 S US B 3 2 , 3 3 , 34 , 3 6
0 . 0 1 u_ 1 6 V _X 7 R _0 4 0. 0 1 u _1 6 V _ X 7R _ 04 0 . 01 u _ 1 6V _ X 7 R _ 0 4
D
P Q1 A ON P Q1 B P Q2
3
M TD N 7 0 0 2Z H S 6 R D M TD N 7 0 0 2Z H S 6 R D MT N 7 0 0 2 Z H S 3
G P C1 1
2G PC 9 5G PC 1 0 1 6 , 27 , 3 2 S US C #
27 , 2 9 , 3 1 D D _ ON 1 6, 1 9 , 2 6 , 27 S U S B #
3. 3 V S S S * 0 . 1u _ 1 6 V _Y 5 V _ 04
4
* 0. 1 u _ 16 V _ Y 5V _ 0 4 * 0. 1 u _ 16 V _ Y 5V _ 0 4 P R9
PR 7 PR 8
10 0 K _ 04
C7 8 3 C 78 4 1 0 0K _0 4 1 0 0 K _0 4
0. 01 u _ 16 V _ X 7 R _ 0 4 0 . 0 1u _ 1 6V _X 7 R _ 0 4 ON
ON ON
Sheet 30 of 41
5VS/ 3.3VS/ 1.8VS/
5VS NM O S 1.5VS 1.5VS/ 1.1VS
5V S Y S 1 5V V DD 5 PQ 4 A
M TN N 2 0 N 0 3 Q8
5V S S Y S 15 V 1 .5 V N M OS
P Q 5A 1 . 5V S
S Y S 15 V V DD 5 P Q3 A 5V 8 2 *M T N N 20 N 03 Q 8
MT N N 20 N 03 Q 8 7 1 8 2
8 2 P R1 1 P R1 2 7 1
3A 7 1 3A Power Plane
P R1 0 1 M_ 0 4 P C1 2 P C2 2 5 P R 2 06 *1 M_ 0 4
3
PC1 3 P C1 4 P R1 4
3
1M _ 04 P C 22 6 P C 2 27 P R2 0 7 0. 1 u _ 16 V _ Y 5V _ 0 4 1 0u _ 1 0V _Y 5 V _0 8 1 0 0 _1 % _ 04
3
*0 . 1 u _1 6 V _ Y 5 V _ 0 4 *1 0 u_ 1 0 V _ Y 5 V _ 08 * 1 00 _ 1 % _0 4
4
0 . 1 u_ 1 6 V _Y 5 V _ 04 1 0 u _1 0 V _ Y 5 V _ 0 8 10 0 _ 1% _ 0 4 P Q4 B
4
M TN N 2 0 N 0 3 Q8 PQ 6 0 P Q 5B
D
4
P Q3 B P C1 8 M TN 7 00 2 Z H S 3 *M TN N 2 0 N 0 3 Q8 P Q1 3
D
M T N N 20 N 03 Q 8 P Q6 1 5 S US B G P C1 9 * MT N 70 0 2 Z H S 3
P C1 7 MT N 7 0 0 2Z H S 3 4 70 p _ 50 V _ X 7 R _ 0 4 5 S US B G
S
5 D D _O N # G *0 . 1 u_ 1 0 V _ X7 R _0 4
1
10/20
S
6
47 0 p _ 50 V _ X 7 R _ 0 4 PJ 2
6
S
1
6
P J1 4 0 m li
2
SU SB 3 2, 3 3 , 3 4 , 36
4 0m i l
2
ON
ON
1.1VS
NM O S
3.3VS SY S1 5 V 1 . 1V P Q6 A
M T N N 20 N 03 Q 8
1 .1 V S
3.3V NM O S 3. 3 V S PR 1 3
8
7
2
1
S Y S 1 5V V D D3 P Q9 A
MT N N 2 0N 0 3Q 8 1 M_ 0 4
P Q8 A P C1 5 PC 1 6 P R 15
S Y S 15 V V DD 3 3 .3 V 8 2
3
MT N N 20 N 03 Q 8 7 1
3A 8
7
2
1
3A Power Plane P R 17
0 . 1 u _ 16 V _ Y 5 V _ 0 4 1 0 u_ 1 0 V _ Y 5 V _ 0 8 1 0 0_ 1 % _0 4
4
P Q6 B
P R1 6 1 M_ 0 4 P C2 1 P C2 2 PR 1 9
D
M T N N 20 N 03 Q 8 PQ 7
3
PC 2 0 MT N 70 0 2 Z H S 3
1M _ 04 P C 22 8 P C 2 29 P R2 0 8 0. 1 u _ 1 6V _ Y 5V _0 4 1 0 u _1 0 V _ Y 5 V _ 0 8 1 0 0 _1 % _ 04 5 SU SB G
3
0 . 0 1 u_ 1 6 V _ X7 R _0 4
4
S
0 . 1 u_ 1 6 V _Y 5 V _ 04 1 0 u _1 0 V _ Y 5 V _ 0 8 10 0 _ 1% _ 0 4 P Q9 B
MT N N 2 0N 0 3Q 8 D PQ 1 0
6
4
P Q8 B P C 26 M TN 7 00 2 Z H S 3
D
M T N N 20 N 03 Q 8 P Q6 2 5 SU SB G
P C2 5 MT N 7 0 0 2Z H S 3 2 20 0 p _ 50 V _ X 7 R _ 0 4 ON
S
5 D D _ ON # G
6
22 0 0 p _5 0 V _ X 7R _ 04 1 2/8
S
6
ON
5VS/ 3.3VS/ 1.8VS/ 1.5VS/ 1.1VS B - 31

Schematic Diagrams
POWER VDD3/ VDD5

VR EF
P R2 1 * 0 _0 4 P R2 2 0_04
P C2 8
1u _ 1 0 V _ Y 5 V _ 0 6
P R2 3 PR2 4
E N _3 V E N _5 V
PC2 9 1 00 K _ 0 4 10 0 K _ 0 4 PC 3 0
1 0 0 0p _ 5 0 V _ X7 R _ 04
1
10 0 0 p _5 0 V _ X 7 R _ 0 4 PU 2
V F B2
T O N SEL
VR EF
E N2
VF B1
E N1
V IN
7 24
V RE G 3 V O2 V O1
VIN
PR 2 5 *1 0 K _ 04
PC 3 2 P C3 1 8 23 P C 33
L D O3 PO K SY S5 V
P C3 4 PC3 7 PC 3 8
4 . 7 u _2 5 V _ X 5 R _ 0 8 P Q 14 1u _ 1 0 V _ Y 5 V _ 0 6 PC3 6 4 . 7 u_ 2 5 V _ X 5R _ 0 8
P 1 2 0 3B V P C 35 9 22 0 . 1u _ 5 0 V _ Y 5 V _ 0 6 4 . 7 u _ 25 V _ X 5 R _ 0 8
B OO T2 B O OT 1
8
7
6
5
5
6
7
8
4 . 7 u _2 5 V _ X 5 R _ 0 8
4
0 . 1 u _1 0 V _ X 7 R _ 0 4
10
uP6182 21
1 u_ 1 0 V _ Y 5 V _ 0 6
4
PQ 1 5
S YS5 V
U GA TE 2 UG A T E 1 P1 2 0 3 BV
V D D3 S YS3 V PL 1 P L2 V D D5
5A
PJ 4
3
2
1
1
2
3
P J3 T M P C 0 6 0 3H -4 R 7 M -Z 0 1 T MP C 0 60 3 H -4 R 7 M-Z 01
2 1 2 1 11
P HAS E 2 PH ASE1
20 1 2 5A 1 2
* 5 mm P Q 16
Ra *5 m m
22 0 u _ 6. 3V _6 . 6 * 5. 7
12 19
8
7
6
5
5
6
7
8
P 1 2 0 3B V P R 1 46 P R2 6
GN D P A D
L G AT E2 LG A T E 1
S K IPS EL
P R1 5 2 PQ 1 7 5 . 1 _ 06 P C 41
P C3 9 + P R2 7 PC 4 2 5. 1_ 0 6 4 4 P 1 2 0 3B V 3 0 K _ 1 % _0 6
L DO 5
VCL K
G ND
EN0
VIN
0 . 1 u_ 1 6 V _ Y 5 V _ 0 4 1 0 00 p _ 5 0 V _X 7 R _0 4
22 0 u _ 6. 3 V _ 6 . 6 *4 . 5
3
2
1
1
2
3
1 3 K _ 1 % _0 6 P C 1 74
PC 4 0
Sheet 31 of 41
1 0 0p _ 5 0 V _ N P O _ 04
PD 3 PD 4
2 2 00 p _ 5 0V _X 7 R _0 4 Rb
13
25
15
16
17
18
A C C A
14
VR EG 5 V REG 5 + P C4 4
P C2 3 8 PR 3 0 P R2 1 6 P R2 8
POWER VDD3/ 22 0 0 p _ 50 V _ X 7 R _ 0 4 * RB 0 5 4 0 S 2 EN _ AL L * RB 0 5 4 0 S 2 0 . 1 u _ 1 6V _Y 5 V _ 04
P C 45
P R2 9 P R3 1 P R 32 68 0 K _ 1 % _ 06 1 9 . 1 K _ 1 % _0 6
20 K _ 1 % _ 04 * 68 0 K _ 1 % _0 4 0_04 *0 _ 0 4
VDD5 VR EF P R3 4 0 _0 4
P R3 3
2 . 2_ 0 6 P C 46
0 . 01 u _ 5 0V _X 7 R _0 4
P D5
B A T 54 S W GH
A 1
SY S5 V
12 /7
P R3 5 *0 _ 0 4 3 C
VR EG 5 2
A
SY S1 0 V
VIN 1 V RE G 5
P D7 P C 47
PC 4 8 PC 4 9
C A P D6 2 20 0 p _ 50 V _ X 7 R _ 0 4
V IN
4 . 7 u _ 25 V _ X 5 R _ 0 8 1 u _1 0 V _ Y 5V _0 6 P C 50 B A T 54 S W GH
0 . 01 u _ 5 0V _X 7 R _0 4 A 1
R B 0 54 0 S 2 3 C
A 2
SY S1 5 V
P C 51
2 20 0 p _ 50 V _ X 7 R _ 0 4
VR EG 5
P R3 6 *0 _ 0 4 E N_ 3 V
P R 37
Z24 18
P R3 8 0 _ 04 E N_ 5 V
1 0K _0 4
D
P Q1 8
G
MT N 70 0 2 Z H S 3
D
S
PC 5 5
PR3 9
1
G PJ 5
2 7 , 2 9 , 30 D D _ ON
*6 m i l
S
0 . 1 u _1 0 V _ X 7 R _0 4
10 0 K _ 0 4
P Q 19
2
M T N7 0 0 2 Z HS 3
D
G
37 AC IN
S
P Q2 2
*M T N 7 0 0 2Z H S 3
B - 32 POWER VDD3/ VDD5

Schematic Diagrams
Power 1.5V/ 0.75
* 4 . 7 u _2 5 V _ X 5 R _0 8
*0 . 1 u _5 0 V _ Y 5 V _ 0 6
*4 . 7 u _2 5 V _ X 5 R _0 8
V IN
PD 1 2
A C
5V
P C6 8
P C6 6
P C6 7
12 /6 Dis ab le
R B 0 5 40 S 2
PU 4
V D DQ
u P 6 1 63
5
6
7
8
PC 6 9 PQ 2 3
10 u _ 1 0V _ Y 5 V _ 0 8 MD S 2 6 5 9
PC 7 0 0 . 1 u _ 10 V _ X 7 R _0 4 4
23
V L DO IN VBST
22
1.5V
2
3
1
V D DQ
PJ 7 PL 4
2 1 24 21 P R 47 0_06 1 . 0 U H _ 1 0 *1 0 *4 . 5 PJ 8
V TT _ M E M VTT D RV H 1 2 10A 1 2
1 .5 V
* OP E N _ 2 A
1 20 * OP E N _ 8 A
5 6 0 u _2 . 5 V _ 6 . 6 *6 . 6 * 5. 9
*5 6 0 u _ 2. 5 V _ 6 . 6 * 6. 6 * 5 . 9
PC 7 1 PC 7 2 PC 7 3 V T T GN D LL
2 2 0 0p _ 5 0 V _ X 7 R _ 0 6
P C7 4
PC 7 5
P C 77
PR 4 8
1 0 u _ 10 V _Y 5 V _ 0 8 0_06 2 19
C
V T T S NS DR V L
5
6
7
8
1 0 u _ 10 V _ Y 5 V _ 08 PQ 2 4 Z 26 2 1
0 . 1 u _1 6 V _ Y 5 V _ 0 4
0 . 0 1u _ 1 6 V _ X 7 R _ 0 4
* 10 u _ 1 0 V _ Y 5 V _ 0 8 MD S 2 6 5 5 PD 1 3 + +
11/5 3 18 4
P R4 9 0 _ 06 GN D P G ND 17 PR 5 2 0_06 * SK3 4 SA
V D DQ 11 /5 C S _G N D
2
3
1
5V
PC 7 6
P C7 9
A
P R5 3 *0 _ 0 4 4 16 PR 5 4 1 0 K _ 1 % _ 06
5V MO D E C S P R5 0
P R5 5 *0 _ 0 4 P C8 0 0 . 1 u _ 10 V _ X 7 R _ 0 4 15 5 .1 _ 0 6
5 P V C C5 14 P R 56 2 . 2 _0 4
V T T REF V C C5
5V
P R5 8 0_06 6
C O MP P GO OD
13 P C8 1 PC 8 2
3 .3 V
PR 5 7
0_06
Sheet 32 of 41
Power 1.5V/0.75V
1 u _ 10 V _ Y 5 V _ 0 6
1u _ 1 0 V _ Y 5 V _ 0 6
8 11
V D DQ S NS S5
P R5 9
9 10
V D DQ S E T S3
P R6 0
*1 0 _0 4
1 0 0 K_ 0 4
G N D
* 1 00 0 p _ 5 0V _X 7R _ 0 4
PC 8 3
N C
NC
DD R1 .5 V _ P W RG D
PC 8 4
DD R1 .5 V _ P W RG D 1 9 ,3 5
7
12
25
*1 0 0 0p _ 5 0 V _ X 7 R _ 0 4
P R6 2
5V
*1 0 K _ 1 % _ 04
PR 6 3 1 0K _1 % _ 0 6
PR 6 4
1 0 K _ 1 %_ 0 6
P R6 5 4 7K _0 4 1 .5 V E N
5V
D
P Q2 5 P C 85
P R6 6 1 0 0 K _ 04 G MT N 70 0 2 Z H S 3 P Q2 6
G 0 . 1 u_ 1 6 V _ Y 5 V _ 0 4
D
S
2
*M T N 7 0 0 2 Z H S 3
S
P Q 27 PJ 9
G *6 m i l
1 6 ,2 7 ,3 0 S U S C#
M TN 7 0 02 Z H S 3
S
2 9 , 3 0, 33 D D _O N #
PR 6 7 1 0 0K _0 4
5V
P R 68 * 2 2 _0 4 +1 . 5 S _ C P U _ P W R G D PR 6 9 *1 0 0 K _ 0 4 V TT E N
V T T _ ME M
D
P C8 6
PQ 2 8 PQ 2 9
SU SB G S US B G 0. 1u _ 1 6 V _ Y 5 V _ 0 4
3 0 , 3 3 , 3 4, 3 6 S U S B
* MT N 7 00 2 Z H S 3 M TN 7 0 0 2Z H S 3
S
Power 1.5V/ 0.75 B - 33

Schematic Diagrams
Power 1.1V/ 1VS

5V
V IN
5V
PR 7 0
A
E N _ 1 .1 V
OCP=10uA X RILIM / Rdson PD 1 4
D
1 0 0 K _ 1 % _0 4 P C8 8 PC 8 7 P C 90
PQ 3 0 P C 89 R B 0 5 40 S 2
SU SC G
0 .1 u _ 5 0 V _ Y5 V_ 0 6
4 . 7 u _ 25 V _X 5R _ 0 8
*4 . 7 u _ 2 5V _ X 5 R _ 0 8
PR 7 2 * 6 2K _ 1% _ 0 4 P R7 1 10 K _1 % _ 0 4
3 0 , 35 SU SC
C
M TN 7 0 0 2Z H S 3 0 . 1 u_ 1 0 V _ X 7 R _ 0 4
5
6
7
8
PQ 3 1
P R 1 97 6 2 K _ 1 % _ 04 PC 9 1 M D S 2 65 8
29 , 3 0 , 3 2 D D _ O N # 4
0 . 1 u _1 0 V _ X 5 R _ 0 4
2
3
1
PC 9 2
1.1V
1
PJ 2 3 PU5 0 . 1 u _ 10 V _ X 7 R _ 0 4
O P E N -1 mm uP 6 12 7
14
15
13
16
3 .3 V PL 5 V 1 .1 P J1 0 1 .1 V
2
TM P C 0 60 3 H -4 R 7 M -Z 0 1
5A
N .C
D H
I LI M
N.C
12 1 1 2 1 2
EN LX
P R7 3 11 2 5m m
0 . 1u _ 1 6 V _ Y 5 V _ 0 4
PG D BST
5 6 0u _ 2 . 5 V _ 6 . 6 *6 . 6 *5 . 9
5
6
7
8
2 2 0 K _ 1 % _ 04 10 3 P R 51
V O UT VC C 5 . 1 _0 6
9 4 4
19 1.1 V_PWRGD FB DL
P Q3 2 +
G N D
R TN
17
2
3
1
N .C
MD S 2 6 5 8
N.C
PA D
P C9 5
P C 78
P C9 3
P R 74
5
* 0 . 1 u_ 1 0 V _ X 7 R _ 0 4 P C9 6
PC9 4
2 2 00 p _ 5 0 V _ X7 R _ 0 4
1 u_ 1 0 V _ Y 5 V _0 6
* 1 0 m il _ s h ort
Sheet 33 of 41 P C 97
0 . 0 1u _ 1 6 V _ X 7R _ 0 4
PR 7 5
1 0 K _ 1 % _ 04
PC 9 8
* 2 0p _ 5 0 V _ N P O_ 0 4
Power 1.1V/ 1VS 5V

PC 9 9 P C 2 13
PR 7 6
* 2 0p _ 5 0 V _ N P O_ 0 4 1 u _1 0 V _ Y 5 V _ 06
1.1VS_VTT=0.75 X (1+PR101 / PR102) 2 1 K _ 1 % _ 04 P U1 1
0 . 1u _ 1 6 V _ Y 5 V _ 0 4
3A 5 6 V1 S _ R EG PJ 1 8 1 VS
1. 5V 9 V IN V C NT L
P C 2 15 P C2 1 8 1V S _ P W R GD 7 V IN 4 3A 1 2
P OK V O UT
1 0 u_ 6 . 3 V _ X 5 R _ 0 6 3 3m m
E N_ 1 VS 8 V O UT P R 1 96 P C 2 14 P C2 1 6 PC 2 1 9
E N
1 2 Ra 3 . 2 4 K _ 1% _ 0 4 1 0 u _ 6 . 3 V _ X5 R _ 06
G N D V FB 8 2 p _5 0 V _ N P O_ 0 4 1 0 u _6 . 3 V _ X 5 R _0 6
A X 66 1 0
P R 1 95
5V
Rb 1 0 . 2 K _ 1% _ 0 4
VIN
Vout = 0.8V ( 1 + Ra / Rb )
5V
P R7 7
10/22 1.0V=>1.054V
A
E N_ 1 V S
OCP=10uA X RILIM / Rdson P D1 6
10 0 K _ 1 % _ 0 4
D
P C 10 1 P C1 0 3 PC 1 0 2
PQ 3 3 P C 10 0 * R B 05 4 0 S 2
SU SB PR 7 8 62 K _1 % _ 0 4 G M TN 7 0 0 2Z H S 3 PR 7 9 *6 . 8 K _ 1 % _ 0 4
* 4 . 7u _ 2 5 V _ X 5 R _ 0 8
*0 . 1 u _ 5 0V _Y 5V _ 06
*4 . 7 u _2 5 V _ X 5 R _ 08
3 0 , 3 2 , 3 4, 36 S U S B
C
0 . 1 u_ 1 0 V _ X 7 R _ 0 4
S
5
6
7
8
P Q3 4
P C1 0 4 *M D S 26 5 9
4
0 . 1 u _ 1 0V _ X5 R _ 04
2
3
1
PU 6
P C1 0 5
* 0 . 1 u_ 1 0 V _ X 7 R _ 0 4
1VS
*u P 6 1 2 7
13
14
16
15
3 .3 V PL 6 V1 .0 S PJ 1 1 1 VS
*2 . 5 U H _ 6 . 8 *7 . 3 * 3
6.5A
IL IM
N .C
N .C
DH
12 1 1 2 1 2
EN LX
P R8 0 11 2 5 mm
PG D BS T
* 5 60 u _ 2 . 5 V _ 6 . 6 *6 . 6 *5 . 9
10 3
5
6
7
8
2 20 K _ 1 % _ 0 4
V O UT VC C
P Q 35
C
1 V S _P W R GD 9 4 4 *M D S 26 5 5
* 0 . 1 u_ 1 6 V _ Y 5 V _ 0 4
35 1VS_ PWRGD FB D L
PD 1 7 +
R TN
GN D
2
3
1
N .C
17
N.C
* C S O D 14 0 S H
P C1 0 8 P AD
PC1 0 6
PR 8 1
A
*0 . 1 u _ 10 V _ X 7 R _0 4 P C 1 09
P C 1 07
*1 u _ 1 0 V _ Y 5 V _ 0 6
*1 0 m i l_ s h o rt
PC 1 1 0 P R8 2 PC1 1 1
* 0. 01 u _ 1 6 V _ X7 R _ 0 4 *1 . 2 K _ 1 % _0 4 *2 0 p _5 0 V _ N P O_ 0 4
PC1 1 2
P R8 3
*2 0 p _5 0 V _ N P O_ 0 4
*3 K _ 1 % _0 4
B - 34 Power 1.1V/ 1VS

Schematic Diagrams
Power 1.8VS
5V VI N
5V
OCP=10uA X RILIM / Rdson
PR40
A
EN_1.8V PR41 *15K_1%_04
PD10 PC52 PC53 PC54
D
100K_1%_04
*4.7u_25V_X5R_08
*4.7u_25V_X5R_08
*. 1u_50V_Y5V_06
PQ20 PC56 *RB0540S2
1
2
SUSB PR42 10K_ 1%_04 G
C
30, 32,33,36 SUSB
MTN7002ZHS3 *0.1u_10V_X7R_04 PQ21A
S
*AP6901GSM
PC57 8
0.01u_16V_X7R_04 PU3 PC58
7
13
14
15
16
*uP6127
*0. 1u_10V_X7R_04 PL3 V1.8S PJ6 1.8VS
DH
*TMPC0603H- 4R7M-Z01
ILIM
4A
N.C
N.C
12 1 1 2 1 2
EN LX
3.3V 11 2 5mm
5
6
PGD BST
1.8VS
*560u_2.5V_6. 6*6.6*5.9
10 3
VOUT VCC
*0.1u_16V_Y5V_04
PR43 9 4 3
FB DL +
GND
RTN
N.C
N.C
220K_1 %_04 17 PQ21B
4
PAD
*AP6901GSM
PC59
PC60
19 1.8V_PWRGD 1.8V_PWRGD
7
6
5
PR44 PC61
PC62 *1u_10V_Y5V_06
*10mil_short
*0.1u_10V_X7R_04
PC64
PR45 PC63
*14K_1%_04 *20p_50V_NPO_04
Sheet 34 of 41
*0.01u_16V_X7R_04
Power 1.8VS
PR46 PC65
*10K_1%_04 *20p_50V_NPO_04
5V
3.3V 0.1u_16V_Y5V_04
PC224
PC217 PC221
1u_10V_Y5V_06
10u_6.3V_X5R_06 3A PU12
5 6 V1.8 S_REG PJ22 1.8VS
9 VIN VCNTL 3A
1.8V_PWRGD 7 VIN 4 1 2
POK VOUT
3 3mm
EN_1. 8V 8 VOUT
EN PR204 PC222 PC223 PC220
1 2
Ra
12.7K_1%_1/16W_04 10u_6.3V_X5R_06
GND VFB 82p_50V_NPO_04 10u_6.3V_X5R_06
AX6610
PR205
Rb
10K_1%_04
Vout = 0.8V ( 1 + Ra / Rb )
Power 1.8VS B - 35
Schematic Diagrams
APU CORE/ NB CORE
Of fse t &
O FS/V FIX EN Dr oop SV I VF IX
GND O O X V DDCR_ CP U EMI
P R 10 9
+3 .3V X X O 10 _0 4
N B _V D D C R C 78 9 0 . 1u _10 V _X 5R _0 4
+5V X O X
C 79 0 * 0. 01 u_ 16V _ X7 R _04
C PU _ V D D N B_ R U N _F B _H 3
M eta l VI D C ode s
C PU _ V D D N B_ R U N _F B _L 3
SV C SV D O utp ut
V IN C 79 1 0 . 1u _10 V _X 5R _0 4
4 . 7u _2 5V _X 5R _ 08
4. 7 u_ 25 V_ X5 R _0 8
0 0 1 .1
5V S
1
1 00 0p_ 50 V _X 7R _ 04
0 1 1 .0 P C 1 40
P R 11 0 P R 11 1 +
5
6
7
8
P C 13 9
10 _0 6 P C 13 7 S GN D 5 S GN D 5 10 _0 4
PC 1 38
1 0 0 .9
2 2K _ 1%_ 04
*3 30 U _2 5V
2
1 u_1 0V _Y 5V _0 6 U GA T E_ N B 4
1 1 0 .8
P Q42
2
3
1
10 00 p_5 0V _ X7 R _0 4
MD S 26 59
3 3p_ 50 V_ N P O_0 4
P R 11 2 N B _V D D C R P J1 9 VD D C R _N B
*1 0mi l _s hort P L8 T MP C 06 03H -R 6 8M-Z 01 10 A
V FIX EN V ID Cod es P H A S E_ N B 1 2 1 2
SGN D 5
56 0u_ 2. 5 V_ 6. 6 *6. 6* 5. 9
SV C SV D O utp ut P R 21 7 *8 mm
*3 30 u_2 . 5V _V _ A
P R 1 13
P C 14 1
PD 2 0 5 . 1_0 6
V IN
0 0 1 .4 + + P C 1 45
5
6
7
8
*C S OD 140 S H
*1 0mi l _s hort
*10 mi _l sh ort
P R 11 4
0. 1 u_ 50 V_ Y5 V _06
0 1 1 .2 10 _0 6 P Q43 1 0u _6 .3 V _X 5R _0 8
L GA TE _N B 4 MD S 26 55 P C 23 4
P C 14 6
A
P C 14 7
P R 1 16 2 20 0p_ 50 V_ X7 R _0 4
P C 142
1 0 1 .0
2
3
1
P C 14 4
8 . 2K _1 %_0 4
P C 143
1 1 0 .8
SGN D 5
P R 115
Sheet 35 of 41
44 . 2K _1 %_0 4 PC 1 48
P R 11 7
0. 22 u_ 16V _ 06 V IN
P R 118
3. 3V S S GN D 5
P R 11 9 0_0 6 +P C 15 4
48
47
45
42
39
49
46
44
43
41
40
38
37
5 VS
4. 7 u_2 5V _X 5 R _0 8
4 . 7u _2 5V _X 5R _ 08
*4 . 7u_ 25 V_ X 5R _ 08
*4. 7 u_ 25V _ X5 R _0 8
APU CORE/ NB P U9 P C 15 6 P C 14 9 P C 157
5
6
7
8
PR 1 20 *1 5u _2 5V _6 . 3*4 .4 _C
V CC
F B_ N B
F S E T_ N B
V SE N _ N B
R TN _ N B
OC S E T _N B
LGA T E_ N B
P H A SE _ N B
U GA TE _ N B
GN D
VI N
C OMP _N B
P GN D _N B
3 . 3V S P R 12 2 *0_ 06 1_1 %_ 06 *0 .1 u_ 50 V_ Y 5V _0 6 0. 1 u_ 50V _ Y 5V _0 6 *0. 1 u_ 50V _ Y 5V _0 6
4
P C 15 0
P C 15 2
PC 1 51
P C 153
P R 12 1 P Q44
CORE
2
3
1
1 0K _0 4 P R 12 3 *10 K_ 06 1 36 MD S 26 59 C P U _V D D C R V D D C R _ C PU
OF S/ V F I XE N B OOT _N B
PR 125 P C 15 5 P L9 PJ 20
S GN D 5 1_ 1% _0 6 0 2. 2u _1 6V _0 6 T MPC 0 60 3H -R 6 8M-Z 01 1 1A
PR 1 24 *1 0mi l _sh ort 2 35 1 2 1 2
1 9 P WR GD _ VC OR E P GOOD B OOT_0
*8mm
3 34
0. 0 1u _50 V _X 7R _ 04
AP U _ PW R GD _R P R 12 6 * 10m li _s ho rt U GAT E _0 P R 21 8
560 u_ 2. 5 V_ 6. 6* 6. 6*5 . 9
0 . 22u _1 0V _Y 5 V_ 04
C
P WR OK U GA TE _0
5
6
7
8
5 . 1_0 6
10u _6 . 3V _X 5R _ 08
Pin 49 is GND Pi n
P Q45 P D 21 P R 12 8 P R 12 9
P C 16 4 *3 30 u_2 . 5V _V _ A
P R 12 7 * 10m li _s ho rt 4 33 P H A SE _ 0 4 MD S 26 55 *C S OD 1 40S H *1 0m li _s ho rt *1 0m li _s ho rt
3 C PU _ SV D S VD P H A SE _0
P C 15 8
2
3
1
A
P R 13 0 * 10m li _s ho rt 5 32 2 20 0p_ 50 V_ X7 R _0 4
3 C PU _ SV C S VC P GN D _0
EN _ V C OR E P R 13 1 0 _0 6 6
E N AB L E
ISL6265C LGA TE _0
31 LGA TE _0 + +
5 VS
PC 1 61
7 30
P C 16 0
P C 16 2
PC 1 59
R B I AS P V CC
P R 1 34 P C 16 5 S GN D 5 PR 1 33 PR 1 32 P C 163
62 K_ 1%_ 04 54 .9 K _1% _0 4 8 29 2. 2 u_6 . 3V _Y 5 V _06
OC S ET LGA TE _1 I S P _0
2 55 _1 %_0 4 4 70 0p_ 50 V_ X7 R _0 4
9 28
P R 13 5 1 K _1% _0 4 V D I FF _0 P GN D _1
10 27
F B_ 0 P H A SE _1 IS N_ 0
P R 1 36 P C 16 6
11 26
C OMP _0 U GA TE _1
5 4. 9 K_ 1%_ 04 1 00 0p _5 0V _X 7R _0 4
P R 137 6 .8 K _1% _0 4 12 25
V W_ 0 B OOT_1
V SE N _ 0
V SE N _ 1
VD I F F _1
C OMP _1
PC 1 67
RT N_ 1
R TN _ 0
I S N _0
I S P _1
I SN _ 1
18 0p_ 50 V_ N P O_0 4 P C 168 1 00 0p_ 50 V_ X7 R _0 4
I SP _0
F B _1
VW _1
P R 1 39 51 0K _0 4 EN _ V C OR E
13
14
16
19
22
5V
15
17
18
20
21
23
24
I S P _1 PR 1 45
P C 17 2
D
I SP _0 PR 1 38 7. 5 K_ 1% _0 4 I S N _1 10 0K _0 4
27 V C OR E _ON P R 14 4 *0 _0 4 P Q46 0. 1 u_ 10 V_ X7 R _0 4
Z 33 01 G MT N 700 2Z H S 3
C los e to
P R 14 1 P R 1 40 P C 1 69
S
1
10 _0 4 C PU 4 . 02 K_ 1%_ 04 0 . 1u _5 0V _Y 5 V_ 06 P R 14 7 *0 _0 4
D
3 0, 3 3 S US C
*1 0mi l _sh ort
*10 mi _l sh ort
C P U _V D D C R P J1 6
s ock et PQ4 7 OP EN -1 mm
P R 14 2
I SN _ 0 P R 20 9 0 _0 4 G MTN 7 00 2Z H S3
P R 143
2
S
3 C P U _V D D 0_ R U N _F B _H 3. 3 VS P C 17 1
3 C P U _V D D 0 _R U N _ FB _ L U4 6 *0 . 1u _10 V _X7 R _0 4
5
*74 AH C 1 G08 GW
P R 14 9 1
10 _0 4 33 1 VS _ PW R GD 4
2
P R 14 8 1 0K _1 %_ 04 19 , 32 D D R 1 . 5V _P W R GD
1 . 5V
3
1 . 8V S 3. 3V S
R 6 82
1 0K _0 4
G
MTN 7 00 2Z H S 3 Q29
S D AP U _P W R GD _R
3, 1 5 AP U _ PW R GD
B - 36 APU CORE/ NB CORE

Schematic Diagrams
VGA POWER
Table: VDDC_OPT_VID 3 . 3V S _GP U

1.15V 1.05V 1.0V 0.9V
VID0 0 1 0 1
P R9 1 5V VI N
VID1 0 0 1 1
* 10 K_ 04
SE T0 SE T1 SE T2 SET 3
MX M_P W R GD
15 MX M_ PW R GD
? ? VGA default? ? ?
P C 1 18
? ? ? ? ? ? ? ? ? ? ? VGA? ? ? ? ? P C 11 3 P C 11 4 PC 11 5
A
* 10 0p _50 V _N P O_ 04
PD 1 8 *4. 7 u_ 25 V _X 5R _ 08 *4. 7 u_ 25 V _X5 R _ 08
*0 .1 u_ 50 V _Y 5 V _0 6
PC 12 6 *10 00 p_ 50 V _X 7R _ 04 *R B 0 54 0S 2
5
6
7
8
P Q36
C
P R 1 51 * 0_ 04 P R 1 50 * 0_0 4 *ME 4 89 4-G
4
2
3
1
PR 10 3 *10 K _1 %_0 4 PR 1 02 * 14 . 7K _1 %_ 04
PR 10 1 *10 . 2K _1 %_ 04 PR 1 00 * 17 . 4K _1 %_ 04 P U7 P C 11 7
*u P6 12 2
5
4
3
2
1
*0 . 1u _5 0V _Y 5V _0 6
EAP
SS
P OK
B OOT
UG
PR 99 *10 . 2K _1 %_ 04 PR 9 8 * 18 . 7K _1 %_ 04 PL 7 V GA _ VC OR E P J 12 VDDC
6 G ND
21
20
*1. 0 U H _6 . 8* 7. 3* 3. 5 13A 1 2
7 S ET 3 P HA SE 19
PR 97 *10 . 2K _1 %_ 04 PR 9 6 * 21 . 5K _1 %_ 04
8 S ET 2 LG 18 * 8mm
9 S ET 1 V CC 17
P C 11 9
P C 12 1
10 S ET 0 RT 16
5
6
7
8
E N / P SM
PR 95 *0_ 04 P R 92
V GA_COR E
C OM P
FB CSP P Q38 *5. 1 _0 6
VID0
VID1
CS N
C
P R 89 4 *ME 46 26 -G PR 19 3 +
PC 1 27 *3 3K _ 1%_ 04 P D 19
2
3
1
P C 12 3 *12 K _1 %_ 04
11
12
13
14
15
*5 60 u_ 2. 5 V_ 6. 6 *6 .6 *5 . 9
*0 . 1u _1 0V _X 7 R _0 4
*0. 0 1u _5 0V _X 7R _ 04 *C S OD 1 40 SH P C 12 2
*1 u_ 16 V_ X5 R _ 06
Sheet 36 of 41
A
PR 9 3 *22 00 p_ 50 V _X 7R _ 04
*1K _ 1%_ 04 P C 1 24 * 47 p_ 50 V_ N P O_0 4
PR 9 4
*22 _0 4 P R 1 04 P C 1 25
3 . 3V
* 10 0K _1 %_ 04 * 0. 01 u_ 50 V _X 7R _ 04
PC 17 0
1 2/8 Delete PC120 3 . 3V 3 . 3V S _GP U

VGA POWER
*0. 1 u_ 50 V _Y 5 V_ 06
S
Q1
D
300mA
P C 1 73
P R 21 4 * 0. 1u _5 0V _ Y 5V _ 06
*A O3 40 9
*10 K _0 4 P R 19 4 *3K _ 1% _0 4 C 1 68
G
C 1 69
MX M_P W R E N # * 10 u_ 6. 3V _ 08 _H 1 25
D
*2 20 0p _5 0V _ X7 R _0 4
P Q63 R8 3
MXM_ PW R E N G *MT N 70 02 ZH S 3 *1 K _0 4
12/10
P J 24 * 6mi l
S
PR 8 4 * 10 0K _0 4 2 1 3. 3V S
3. 3 V
3. 3 V S_ GP U R8 4 *1 00 K _0 4
P J 25 * 6mi l ON
2 1 P R 88 *1 0K _0 4 R8 8
* 10 K_ 04
D
R OB S ON _ GPI O1 5 P C 1 16 P R 21 2 *0 _0 4 Q2
8 R OB SON _GP I O15 MX M_P W R E N 7
*2 20 0p _5 0V _ X7 R _0 6 G *MT N 70 02 Z H S 3
R OB S ON _ GPI O1 6 P R 21 3 *0 _0 4
S
8 R OB SON _GP I O16 MV D D Q
D
Q3 R9 0
P R8 6 P R8 7
MX M_GP I O1 R 68 4 * 0_ 04 G *M TN 7 00 2Z H S 3 *1 M_0 4
*1 00 K _0 4 *1 00 K _0 4 7 , 15 M XM_ GP IO 1
S
SUS B R 91 * 0_ 04
12/7
NMOS
1. 5 V
Q19
*P 12 03 B V
8 MVD D Q
7 3 1. 8 V _R E G
6 2
S Y S 1 5V 5 1 1 .5 V 5V
NM OS
PC 1 28 PC 1 29 P C 1 30
Q20 A S Y S 15 V 1 . 8V S
4
*MT N N 20 N 03 Q8 *10 u_ 6. 3 V_ X5 R _ 08 *1 u_ 10 V _Y 5 V _0 6
R 5 64 8 2 200MIL PJ 14 2A P Q3 9A
120MIL *0. 1 u_ 16 V_ Y 5V _ 04 P U8
7 1 1 2 * MTN N 2 0N 0 3Q8 P J1 5 5 6 R E G_ 1 . 0V 1 .0 V _ REG
*1 M_0 4 R 5 65 8 2 2A 1 2 9 V IN
V IN
V C N TL
1.5A P J2 1
C 78 5 C 78 6 *OP EN _5 A 7 1 P R 10 5 *10 0K _ 04 1 . 5V _P G 7 4 1 2
*10 u_ 10 V _Y 5 V_ 08 R 56 6 * 1M_ 04 C 7 87 *OP E N _3 A 3. 3 VS P OK V OU T
3
F B V D D Q_P W R _E N *0. 1 u_ 16 V _Y 5 V_ 04 P C 1 31 R 56 7 3 *OP E N _3 A

* 10 0_ 04 *1 0u _1 0V _ Y 5V _0 8 P R 10 6 *10 K _0 4 8 V OU T P R 1 07 P C 1 32 P C 13 3 P C 13 4
5V EN
3
*0 . 1u _1 6V _ Y 5V _0 4 *1 00 _0 4 Ra
4
C 7 88 1 2 *2 . 61 K _1 %_0 4 *1 0u _6 . 3V _X 5R _ 08
D
D
GN D VFB
4
*0 . 02 2u _5 0V _X 7R _ 04 Q 22 P C 1 36 PQ4 0 PC 1 35 *8 2p _5 0V _ N PO _0 4 *1 0u _6 . 3V _X 5R _ 08
D
*MTN 7 00 2Z H S 3 Q23
5 G * 0. 02 2u _5 0V _ X7 R _0 4 *MT N 70 02 Z H S3 G *1U _ 6. 3 V_ Y 5 V_ 04 * AX 66 10
5 G *MTN 7 00 2Z H S 3
S
S
*MTN N 20 N 03 Q8 1021 delete P R 1 08
S
6
Q20 B *M TN N 2 0N 0 3Q8 Rb
6
P Q3 9B *1 0K _ 1% _0 4
Vout = 0.8V ( 1 + Ra / Rb )
ON
P R 19 9 *0 _0 4 MXM_ P WR E N # PR 20 0 *0_ 04 MX M_P W R E N #
PR 19 8 *0_ 04 MX M_P W R E N #
ON P R 20 2 *0 _0 4 SU SB PR 20 3 *0_ 04 S U S B
PR 20 1 *0_ 04 S U S B
S US B 3 0, 3 2, 3 3, 3 4
VGA POWER B - 37
Schematic Diagrams
CHARGER/ DC IN
# Char g e Cur r ent 1.5A
6-20-B3Z40-004 for 30W

CHARGER VA
P Q 48
# Char g e Volt age 1 2.6V
V IN
4
P 2 0 03 E V G
6-20-B3410-003 for 65W 1
2
5
6
J A CK 1 3 7
J D D -5 2 0 48 A S 1 F - 1 65 PL 1 0 VA PQ 5 0 PC2 3 5 8
H C B 4 53 2 K F -8 00 T 6 0 P 2 0 0 3E V G P Q 49 A 0. 1 u _ 50 V _ Y 5 V _ 06
8 PR1 5 3 A P 6 9 01 G S M PR1 5 5 V _B A T
1 7 3 0 . 02 _ 1 %_ 3 2 2 0. 02 _ 1% _ 3 2
2 6 2 1 7 PL 1 1 B C I H P 0 7 30 -6 R 8 M
GN D 1 P C 17 5 P C 17 6 P C 17 7 P R 1 54 5 1
GN D 2
0 . 1 u_ 5 0 V _Y 5 V _ 0 6
0 . 1 u_ 5 0 V _Y 5 V _ 0 6
0 . 1 u_ 5 0 V _Y 5 V _ 0 6
4 . 7 u _2 5 V _X 5 R _0 8
0 . 1 u _5 0 V _Y 5 V _ 0 6
5
6
4 . 7 u _2 5 V _ X 5R _0 8
* 4. 7 u _2 5 V _ X 5R _ 08
4 . 7 u _2 5 V _X 5 R _0 8
4 . 7 u_ 2 5V _ X 5 R _ 0 8
P R1 5 6 1 3 0K _1 % _0 4
*1 u _2 5 V _0 8
4. 7 u _ 25 V _ X 5R _ 08
0. 1 u _ 50 V _ Y 5V _0 6
4. 7u _ 25 V _ X 5 R _ 08
4. 7 u _ 25 V _ X 5R _ 08
0. 1u _ 50 V _ Y 5 V _0 6
4
8
20 0 K _ 1% _ 04
P R 15 7
1 0 K _ 04 3
P R 1 59 P Q 4 9B
4
A P 6 9 0 1G S M
P C1 7 8
P C 1 82
P C1 8 0
P C1 8 3
P C 1 81
P C1 8 4
P C1 8 5
P C 1 86
P C1 8 9
P C 1 87
P C 18 8
P C1 9 0
P C1 7 9 1 0 K _ 1% _ 04
0. 01 u _1 6 V _ X7 R _ 0 4
V_ BAT
P C1 9 1 0 . 1 u _5 0 V _Y 5 V _0 6
0_ 0 4
0_ 0 4
P C 19 2 P C 19 3 PC1 9 4
PC1 9 5
*0 _0 4
0 . 1 u_ 5 0 V _Y 5V _ 0 6 0 . 1 u_ 5 0V _ Y 5V _ 0 6 0 . 1 u _5 0 V _ Y 5 V _0 6 P D 22 1u _ 10 V _ Y 5 V _ 0 6
C A
10 0 K _ 1% _ 0 4
PIN 25th
V IN FOR2S CONNECT TO GND
R B 05 4 0S 2 FOR3S CONNECT N.C.
P R1 6 0
P R1 6 1
FOR4S CONNECT TO VREF PIN
P R1 6 3
P C 19 6 P C 19 7 P C2 0 0 P C 20 1
C E LL S
P R1 6 4
P R1 6 5 *0 _ 04
Sheet 37 of 41 0 . 1u _ 50 V _ Y 5 V _ 0 6 0 . 1 u_ 5 0V _ Y 5V _ 0 6 0 . 1u _ 5 0V _ Y 5 V _ 0 6 0 . 1 u_ 5 0 V _Y 5V _ 0 6 P C 1 98 P C 1 99
VA
* 0. 1 u _5 0 V _ Y 5V _ 0 6
* 0. 1 u _5 0 V _ Y 5V _ 0 6
31
30
29
28
26
VA
32
27
25
CHARGER/ DC IN V DD 3
P U 10
O U T -1
O U T -2
P GN D
CB
LX
VB
C E LL S
C T L2
1 24 P C2 0 2 0 . 1u _ 5 0V _ Y 5 V _ 0 6
2 V CC V IN 23 V DD3
C T L1
3 -I N C 1 CT L 1 22
4 +I N C 1 G ND 21
31 A C IN PR1 6 6 R5 6 8 1 0K _ 0 4
5 A CIN TRERMAL PAD VR EF 20
6 A C OK RT 19 C
10 K _ 0 4
7 -I N E 3 C S 18 V O LT _ S E L P R 1 67 S MC _ B A T AC
O UT C 2
C O MP 2
C OM P 3
0 . 1 u _5 0 V _Y 5 V _ 0 6
OU T C 1
A DJ 1 ADJ 3
AD J 2
8 17 S G ND6 A
-IN E 1
+I N C 2
-INC 2
0 . 1 u_ 5 0V _ Y 5 V _ 06
A C_ IN# 1 6, 2 7 , 2 9 C OM P 1 BATT 33 4 9 . 9 K _1 % _ 04 D2 9
39 . 2 K _ 1% _ 04
D
SG ND *B A V 9 9 R E C TI F I E R
P Q5 1 P R 1 68 MB 39 A 1 32 C
9
10
11
12
13
15
P R1 6 9 1M _ 04 G S G ND6 S MD _ B A T AC
3 . 6 5K _ 1 %_ 0 4
14
16
VA A
P R1 7 0
MT N 7 0 02 Z H S 3 TOTAL 1 0 K _ 1% _ 0 4 P C2 0 3 CHARGE
S
1 0 0p _ 5 0V _ N P O_ 04 P R 17 3 P R 1 72 D3 0
P R 1 71 POWER 1 K _ 1 %_ 0 4 CURRENT *B A V 9 9 R E C TI F I E R
P C 20 5 ADJ P C 2 04 1 0 K _ 1% _ 0 4 ADJ C
2 0 0 K _0 4 B A T _ DE T AC
* 0. 1 u _5 0 V _ Y 5 V _ 06 0 . 0 1 u_ 5 0 V _X 7 R _ 0 4 P C2 0 6 *2 2 p_ 5 0V _ N P O_ 04 A
P C 20 7
P C 2 08
P R1 7 4
P C2 0 9 D3 1
PR17 0 : 1 0K fo r 65 W 1 0 00 p _ 50 V _ X 7R _0 4 P R 17 7 *B A V 9 9 R E C TI F I E R
S G ND6
2 0K _1 % _0 4
C
P R1 7 6
PR17 0 : 3 .65 K f or 3 0W 22 K _ 1 %_ 0 4 S G ND6 S GN D 6 S GN D 6
P Q 52 P R 17 8 P C2 1 0 AC
A O3 4 09 3 0 0K _ 1 % _0 4 1 0 00 p _ 50 V _ X 7R _0 4 P R 17 9 S GN D 6 27 B A T _V O L T A
V_ BAT S D B A T _V O L T D3 2
S GN D 6 1 0 K _1 % _ 04 *B A V 9 9 R E C TI F I E R
G
P R1 8 0
P R 18 1 P C 21 1 P C 2 36 0. 1 u _ 50 V _ Y 5 V _ 06
V_ BAT
0. 5V/ 1A
2 0 0K _ 1 % _0 4 6 0 . 4K _ 1 % _0 4 0 . 1 u_ 5 0 V _Y 5V _ 0 6 TO T A L_ C U R
P R1 8 2 PIN17t h CONNECT W240BU
C H G-C U R R E N T
*1 0m i l _s h ort _0 4 0. 5V/ 1A T OBAT CONN.
CU R_ S E NS E
5
P R 1 83
P L1 2 H C B 10 0 5K F -12 1 T2 0
27 S M C_ B A T 4
D
P Q5 3 1 0 2 K _1 % _ 04 27 S M D_ B A T P L1 3 H C B 10 0 5K F -12 1 T2 0
C E L LS C E P L1 4 H C B 10 0 5K F -12 1 T2 0 3
G P R 18 4 27 B A T _ DE T 2
SY S3 V 1
MT N 7 0 02 Z H S 3 V OL T _S E L
S
P Q5 4 P C 23 1 P C 23 2 P C 23 3 JB A TT A 2
D T A 11 4 E U A P R 1 85 P R 18 6 B T D -05 T I 1G
D
D B
1 0 0 K _0 4 * 17 . 4 K _ 1% _ 04 2 M_ 1 %_ 0 4 3 0p _ 5 0V _ N P O_ 04 3 0p _ 5 0V _ N P O_ 04
SYS3 V SY S3 V P R 1 87 3 0p _ 5 0V _ N P O_ 04
P Q5 5 G
G 7 6 . 8 K _1 % _ 04
V C H G_ S E L 2 7 W250BUQ
S
MT N 70 0 2Z H S 3 P Q5 6 P C2 3 7
5
S
P R 1 88 P R1 8 9 MT N 7 0 0 2Z H S 3 V H= 4.2 V
D
V L= 4.3 V 0. 1u _ 50 V _ Y 5 V _ 06
1 0 0K _0 4 1 0K _ 0 4 P Q5 7 4
G 3
P Q 5 8A C E CL M
C T L1 * MT N 7 0 02 Z H S 3 2
6 3 1
S
MT D N 70 0 2Z H S 6 R
D
D D P C 21 2 PR1 9 0 6- 2 1 -D 3 4 B0 - 1 05 JB A TT A 1
P Q5 8 B P Q 59 * B TD -0 5T C 1 B
G 2 G 5 MT D N 70 0 2 Z H S 6 R G 1. 5 M_ 0 4 P R 19 1 *1 5 m li _ sh o rt _ 06
0 . 0 1u _ 50 V _ X 7 R _ 04
27 C H G_ E N S S 2 7 C E LL _ C O N T R O L
M TN 7 00 2 Z H S 3
S
1 4
1
VH =3 S
P J 17 VL =4 S P R 1 92 S GN D 6
O P E N -1 m m 1 M_ 0 4
F RO M E C: #1 23 /(P D) CTX /G PB2
2
S G ND 6
B - 38 CHARGER/ DC IN
Schematic Diagrams
Click Board
CLICK BOARD
CLED_ACIN CLED_BAT_CHG
CLED_PWR CLED_BAT_FUL L
CR1 CR2 CR3 CR4

CC1 CC2 CC3
0.1u_16V_Y5V_04 *0. 1u_16V_Y5V_04 *0.1u_16V_Y5V_04 *220_04 *220_04 POW ER O N *220_04 *220 _04
C5VS C5VS CVDD3 B AT LED
3
1 LED
CD27 CD26
2
SG
CGND CGND CGND
SG
Y
Y
CJ_TP2 CJ_ TP3
CJ_TP1 *KPB-3025YSGC *KPB-30 25YSGC
2
4
1 CTP_DATA 1 CTP_CLK 1 CLED_PWR
2 2 2
3 CTP_CL K 3 CTP_DATA 3 CLED_ACIN
CTPBUTTON_L CLED_BAT_FULL
4 4 CTPBUTTON_R 4 CLED_BAT_CHG
85201-0 4051 5 5
6 6
CGND 85201- 06051 *85201- 06051 CGND CGND CGND CGND Sheet 38 of 41
6- 20-9 4A50 -104 CGND CGND 6-5 2-55 002 -042 6-52 -550 02-0 42
6- 20-9 4AA0 -104
6- 20-9 4A70 -104 6- 21-9 1A00 -106 6-21 -91A 00-1 06
6-5 2-55 002 -04E 6-52 -550 02-0 4E Click Board
6- 21-9 1A20 -106 6-21 -91A 20-1 06
For W250BUQ
CSW1~4
2 4
1 3
LIF T RIG HT LI FT RI GHT
KEY KE Y KE Y K EY
CSW1 CSW2 CSW3 CSW4
TJG-533-S-T/R TJG-533-S-T/R *TJG- 533-S- T/R *TJG-533-S-T/R
1 2 1 2 1 2 1 2
3 4 CTPBUTTON_L 3 4 CTPBUTTON_R 3 4 CTPBUTTON_L 3 4 CTPBUTTON_R
5
6
5
6
5
6
5
6
CGND CGND CGND CGND
6-53 -30 50B- 041 6-5 3-30 50B- 041 6-5 3-30 50B -041 6-5 3-3 050B -041
CH3 CH1 CH4 CH2 CH5 CH6

2 9 2 9 2 9 2 9 C95D9 5 HO-165X94_5NP
3 8 3 8 3 8 3 8
4 1 7 4 1 7 4 1 7 4 1 7
5 6 5 6 5 6 5 6
MTH237D91 MTH237D91 MTH237D91 MTH237D91

CGND CGND CGND CGND CGND CGND CGND CGND
Click Board B - 39
Schematic Diagrams
Audio Board/ USB
USB PORT
A R7 3 5 0 _0 6
A_ US B V CC AL 1 A_ US B V C C2
H C B 1 60 8 K F -1 2 1T 2 5 60 mil
A _U S B V C C
AU 1 A C1 0 +A C 1 A C2
A_ 5 V 5 6 50m ils * 10 0 u_ 6 . 3 V _ B _A
F L G# V O U T 1 2 2 u _6 . 3 V _ X5 R _0 8 0 . 1u _ 1 6V _ Y 5V _ 0 4
5 0mi ls 2 7
V IN 1 V O UT 2 A C3 A C4 A J _ US B 1
A C5 3 8 A R1 *1 0 mi l _ sh o rt _ 04 A GN D 1
V IN 2 V O UT 3 *0 . 1 u_ 1 6V _Y 5V _ 0 4 0. 1 u _ 16 V _ Y 5 V _ 0 4 AL 1 2 2 V+
1 0u _ 1 0V _ Y 5 V _ 0 8 4 1 A US B _ P N2 4 3 A US B _ P N2 _ R 2
E N# G ND D A TA _ L
* R T 9 71 5 B GS A US B _ P P 2 1 2 A US B _ P P 2 _ R 3
D A TA _ H
A GN D A G ND A GN D A G N D A G ND *W C M2 0 12 F 2 S -1 6 1T 0 3
6-02-09715-920
G ND 1
G ND 3
4
GN D 2
GN D 4
G ND
A R2 *1 0 mi l _ sh o rt _ 04
U S 0 4 03 6 B C A 0 8 1
G ND 3
GN D 1
GN D 2
GN D 4
6-21-B49C0-104
A G ND
Sheet 39 of 41 TO M/B AUDIO JACK EMI Require

Audio Board/ USB
5 A J _ MI C 1
A M IC_ S E N S E 4
A M I C 1 -R A L1 213 2 F C M1 0 05 K F -1 2 1T 0 3 M I C 1 _ OU T _ R 3 R
A M I C 1 -L A L1 214 2 F C M1 0 05 K F -1 2 1T 0 3 M I C 1 _ OU T _ L 2
N C _M I C 1 6 L
1
A C 7 92 A C7 9 3 2S J -T 3 51 -S 2 3
A_ 5 V A J _ A U D I O1
* 1 00 p _5 0 V _ N P O _0 4 *1 00 p _ 50 V _ N P O _ 04 6-20-B2800-106
MIC IN
A M I C 1 -R 1
A M I C 1 -L 2 R esi stor 3 2 or 3 3_0 4 BLACK
3
4
m ee t WLK Te st
A H E A D P H ON E -R VT1802P A _ A UD G
A H E A D P H ON E -L 5
A M IC_ S E N S E 6 33_1%_04 5 A J _ HP1
A S P K _H P # 7 10/28 Modify value A HP _ S E N S E 4
A H P _ S E NS E 8 A H E A D P H O N E -R A R5 6 9 1 8 0_ 1 % _0 4 P H O N E -R A L 1215 2 F C M 1 00 5 K F -1 21 T 0 3 P H O N E _ OU T_ R 3 R
A U S B _ P N2 9
AU SB_ PP2 10 A H E A D P H O N E -L A R5 7 0 1 8 0_ 1 % _0 4 P H O N E -L A L 1216 2 F C M 1 00 5 K F -1 21 T 0 3 P H O N E _ OU T_ L 2
11 A S P K _ HP # 6 L
12 1
A S P K OU T R +
A S P K OU T R - 13 A C 7 94 A C7 9 5 2S J -T 3 51 -S 2 3
14
8 52 0 1 -14 0 5 1-0 1 La y out not e : *1 0 0 p_ 5 0V _N P O_ 0 4 *1 00 p _ 50 V _ N P O _ 04
A _ A U DG A G ND
HEADPHONE
Reverse He adphone ? ? ? ? > 1 0mi ls
? ? phone ja ck ? ? BLACK 6-20-B2800-106
?? ?? ?? ? A _ A UD G
R/L? ? ? ? GND ? ? ? ? 3*? ? EMI Require 2 3
4
1
G ND
A C6 0 . 1 u_ 1 6V _Y 5V _ 0 4 HP -L
3* R/ L? ?
6 5
A C7 0 . 1 u_ 1 6V _Y 5V _ 0 4 HP -R
G ND
A C8 0 . 1 u_ 1 6V _Y 5V _ 0 4
A C9 0 . 1 u_ 1 6V _Y 5V _ 0 4
A L 12 7
*F C M1 6 0 8K -1 2 1 T0 6 _ sh o rt
A S P K OU TR +
A GN D A _ A UDG
A C7 9 6 A C7 9 7
*1 u _1 0 V _ 06 *1 8 0p _ 5 0V _ N P O_ 0 4
A J _ S P K R1
A _A U D G A S P K O UT R+ _ R J_SPK1
1 2 1
A S P K OU TR - A S P K O U T R -_ R
2
*F C M1 6 0 8K -1 2 1 T0 6 _ sh o rt A C7 9 8 85 2 0 4-0 2 0 01
A L 12 8 P C B F o ot p ri n t = 8 5 2 04 -0 2 R
J_SPK1 *1 8 0 p_ 5 0V _N P O_ 0 4
AH 1 A H3
C 59 D 59 C5 9 D5 9 A H2 A H4 2 1 6-20-43150-102
2 9 2 9 A _A U D G
3 8 3 8
6-20-43110-102
4 1 7 4 1 7
5 6 5 6
M TH 2 76 D 1 1 1 MT H 2 7 6 D 1 11
A GN D A GN D A G N D A G ND
B - 40 Audio Board/ USB

Schematic Diagrams
Power Switch & LID Board
POWER SW & LED & HOT KEY
S _ 3. 3 V S S _3 . 3 V
POWER
S _ 3. 3 V S S _ 3 . 3V
SWITCH LID SWITCH IC SD2
LED
C
S R2 *B A V 99 R E C T I F I E R
S _ 3. 3 V S S _ 3 . 3V S _ 3 .3 V
SJ _ SW 1 22 0 _0 4
1
20 mi l S R1 1 0 0 K _0 4 AC
SJ _ SW 2
2
3
S M _B T N #
1
20 mi l 20 mi l 2 0m il Z430 1 S U1
SW EB_ W W W # 1 2 S LI D _ S W #
4 S W E B _ E M A IL # 2 S M _B T N # S C6 VC C OU T
5 3
GN D
A
S L ID_ S W # SW EB_ W W W #
A
6 4 S W E B _ E M A I L# *0 . 1 u_ 1 0 V _X 7 R _ 0 4 SC 2 S C1
7 S A P _ ON S M GN D 5 S L ID_ S W # M H 2 4 8-A LF A -E S O
8 6
3
S D3 SD 1 0 . 1 u_ 1 6 V _Y 5 V _0 4 *1 00 p _ 50 V _ N P O _ 04
9 S M GN D 7 S A P _ ON S MGN D
S _ V IN * H T -1 50 N B -D T S MGN D S M GN D
10 8 H T -1 5 0N B -D T
S M GN D S MG N D
C
* 50 5 0 0-0 1 0 41 -0 01 L 8 8 48 6 -0 80 1 6-52-56001-023
6-52-56001-028 6-52-56001-023 S MGN D
6-20-94K10-108 6-52-56000-020 6-52-56001-028
1 0 p in & 8 pi n co- la y 6-52-56001-022
S MG N D S M GN D
6-52-56000-020
6-52-56001-022
6-02-00248-LC2
6-02-00268-LC1
SU1, SU2
3 Sheet 40 of 41
FOR E5128Q FOR E4120Q/E5120Q
1 2
Power Switch & LID
Board
6-53-3150B-245 6-53-3150B-245 6-53-3150B-245 S _ V IN 6-53-3150B-245

HOT KEY 6-53-3050B-241
6-53-3050B-240
6-53-3050B-241
6-53-3050B-240
6-53-3050B-241
6-53-3050B-240
6-53-3050B-241
6-53-3050B-240
POWER BUTTON WEB_WWW# WEB_EMAIL# SR 3
AP_KEY#
SPW R _ SW 1 S W W W _S W 1 S MA I L _ S W 1 * 10 0 K _ 1% _ 0 4 S A P _S W 1
T J G-5 33 -S -T / R *T J G-5 3 3 -S -T/ R * T JG -5 33 -S -T / R * T JG -53 3 -S -T / R
1 2 S M_ B T N # 1 2 S W E B _W W W # 1 2 S W E B _E M A I L # 1 2 S A P _O N
3 4 3 4 3 4 3 4
SC 4 S C3 S C5 SR 5
5
6
5
6
5
6
5
6
PSW1~8 S R4 * 4 7K _ 0 4
* 0. 1 u _ 16 V _ Y 5 V _ 04 *0 . 1u _ 1 6V _ Y 5V _ 0 4 *0 _ 0 4 * 0 . 1u _ 1 6V _ Y 5V _ 0 4
3 1
4 2
S M GN D S M GN D S M GN D S MG N D S MG N D S MGN D S MGN D
S M GN D
S MG N D
FOR E5120Q
POWER BUTTON
S MH 2 S MH 5 S MH 6 S MH 7
SPW R _ SW 2 H 7 _0 D 2_ 3 H 7 _ 0D 2 _3 T1 5 8B 11 8 X8 7 D 1 1 8 X8 7 T1 5 8 B 91 D 91 SM H1 S MH 3 S MH 4
*T J G-5 3 3 -S -T/ R 2 9 2 9 2 9
1 2 S M_ B T N # 3 8 3 8 3 8
3 4 4 1 7 4 1 7 4 1 7
5 6 5 6 5 6
5
6
PSW1~8 M TH 2 37 D 8 7 M T H 2 37 D 87 MT H 2 3 7D 1 18
3 1 S MG N D S MG N D S M GN D S M GN D
4 2 S MG N D S MG N D
S M GN D
6-53-3150B-245
6-53-3050B-240
6-53-3050B-241
FOR E5128Q
Power Switch & LID Board B - 41

Schematic Diagrams
EXTERNAL ODD Board

QJ_O DD 2 QJ_ODD 1
S1 S1
S2 QJ_SATA_TXP1 S2
S3 QJ_SATA_TXN1 S3
S4 S4
S5 QJ_SATA_RXN 1 S5
S6 QJ_SATA_RXP1 S6
S7 S7
QGND QGN D
P1 QJ_O DD _D ETEC T# P1
P2 P2
P3 Q_5VS Q_5VS P3
P4 QJ_SATA_OD D_D A# P4
P5 P5
P6 P6
1-162-100562 242001-1
PI N P IN
QGND QGN D
GN D1 ~ 2= WGN D GN D1 ~ 3= QG ND
6-21 -140 10-01 3
6- 21-1 3A00 -013 6-21 -140 20-01 3
Sheet 41 of 41 6-21 -140 30-01 3
EXTERNAL ODD
Board Q_5VS
QC1 Q C2
0.1u_16V_Y5V_04 *0. 1u_16V_Y5V_04
QGN D
Q H1 QH4 QH 3 QH 2
C 237D91 C 237D 91 C67D 67 C67D 67
QGN D QG ND
B - 42
BIOS Update
Appendix C:Updating the FLASH ROM BIOS 

BIOS Version
To update the FLASH ROM BIOS you must: Make sure you down-
• Download the BIOS update from the web site. load the latest correct
• Unzip the files onto a bootable CD/DVD/USB Flash Drive. version of the BIOS ap-
propriate for the com-
• Reboot your computer from an external CD/DVD/USB Flash Drive. puter model you are
• Use the flash tools to update the flash BIOS using the commands indicated below. working on.
• Restart the computer booting from the HDD and press F2 at startup enter the BIOS.
You should only
• Load setup defaults from the BIOS and save the default settings and exit the BIOS to restart the computer.
download BIOS ver-
• After rebooting the computer you may restart the computer again and make any required changes to the default BIOS sions that are
settings.
C:BIOS Update
V1.01.XX or higher as
appropriate for your
Download the BIOS computer model.
1. Go to www.clevo.com.tw and point to E-Services and click E-Channel. Note that BIOS versions
2. Use your user ID and password to access the appropriate download area (BIOS), and download the latest BIOS files are not backward com-
(the BIOS file will be contained in a batch file that may be run directly once unzipped) for your computer model patible and therefore
(see sidebar for important information on BIOS versions). you may not down-
grade your BIOS to an
older version after up-
Unzip the downloaded files to a bootable CD/DVD/ or USB Flash drive grading to a later ver-
1. Insert a bootable CD/DVD/USB flash drive into the CD/DVD drive/USB port of the computer containing the sion (e.g if you upgrade
a BIOS to ver 1.01.05,
downloaded files.
you MAY NOT then go
2. Use a tool such as Winzip or Winrar to unzip all the BIOS files and refresh tools to your bootable CD/DVD/USB back and flash the BIOS
flash drive (you may need to create a bootable CD/DVD with the files using a 3rd party software). to ver 1.01.04).
Set the computer to boot from the external drive

1. With the bootable CD/DVD/USB flash drive containing the BIOS files in your CD/DVD drive/USB port, restart the
computer and press F2 (in most cases) to enter the BIOS.
2. Use the arrow keys to highlight the Boot menu.
3. Use the “+” and “-” keys to move boot devices up and down the priority order.
4. Make sure that the CD/DVD drive/USB flash drive is set first in the boot priority of the BIOS.
5. Press F4 to save any changes you have made and exit the BIOS to restart the computer.
C - 1
BIOS Update
Use the flash tools to update the BIOS

1. Make sure you are not loading any memory management programs such as HIMEM by holding the F8 key as you
see the message “Starting MS-DOS”. You will then be prompted to give “Y” or “N” responses to the programs
being loaded by DOS. Choose “N” for any memory management programs.
2. You should now be at the DOS prompt e.g: DISK C:\> (C is the designated drive letter for the CD/DVD drive/USB
flash drive).
3. Type the following command at the DOS prompt:
C:\> Flash.bat
4. The utility will then proceed to flash the BIOS.
5. You should then be prompted to press any key to restart the system or turn the power off, and then on again but
make sure you remove the CD/DVD/USB flash drive from the CD/DVD drive/USB port before the computer
C:BIOS Update
restarts.
Restart the computer (booting from the HDD)

1. With the CD/DVD/USB flash drive removed from the CD/DVD drive/USB port the computer should restart from
the HDD.
2. Press F2 as the computer restarts to enter the BIOS.
3. Use the arrow keys to highlight the Exit menu.
4. Select Load Setup Defaults (or press F3) and select “Yes” to confirm the selection.
5. Press F4 to save any changes you have made and exit the BIOS to restart the computer.
Your computer is now running normally with the updated BIOS

You may now enter the BIOS and make any changes you require to the default settings.
C-2

Itautec A7520 - 6-71-W2400-D03 GP

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Preface

Appendix B: Schematic Diagrams

Diagram - Page Diagram - Page Diagram - Page Table B - 1

System Block Diagram

POWER SWITCH BOARD GPU POWER, VDDC

AMD HUDSON-M1 IN OUT

Sheet 1 of 41 32.768 KHz

EC U SB 2. 0(12) + 1.1 (2) REALTEK

Diagram 14 *1 4*1 .6m m

USB PORT USB PORT Bluetooth CCD

SATA I/II 3.0Gb/s

B - 2 System Block Diagram

ONTARIO MEM & PCIE I/F, AP

ONTARIO MEM & PCIE I/F, AP B - 3

ONTATIO DISPLAY/ CLK/ MISC

B - 4 ONTATIO DISPLAY/ CLK/ MISC

ONTARIO POWER & DECOUPLING

ONTARIO POWER & DECOUPLING B - 5

INAGUA DDR3 SO-DIMMS A

2,6 MEM_ADDR[15:0] MEM_DAT

79 BA1 DQ18 53 MEM_DATA19 3.3VS 99 VDD8 VSS23 66

INAGUA DDR3 SO- 2,6 MEM_WE# 197

1.5V R76 1K_1%_04 MVREF_DIMM0

+ C104 C105 C106 C107 C108 C109 C110 C111 C11

0.1u_16V_Y5V_04 0.1u_16V_Y5V_04 0.1u_16

B - 6 INAGUA DDR3 SO-DIMMS A

INAGUA DDR3 SO-DIMMS B

S O-D IMM B INA GUA DDR3 S O-DIMMS B

2,5 MEM_ADDR[15:0] MEM_DATA[63

C145 C146 C147 C1

INAGUA DDR3 SO-DIMMS B B - 7

Robson S3 PCIE/ LVDS 1/6

B - 8 Robson S3 PCIE/ LVDS 1/6

Robson S3 MAIN 2/6

COMPONENTS SH OWN AR E EXAMPLES ONLY

0. 1"~ 0.5 " R 10 1

*10 u_6 . 3V _X 5R _ 06 *1u _6 .3 V _X 5R _0 4 *0. 1 u_1 0V _ X5R _ 04 U1

Access to SCL and SDA is

Robson S3 MAIN 2/6 B - 9

Robson S3 MEM Interface 3/6

COMPONENTS SHOWN ARE EXAMPLES ONLY DDR3 Memory

DQA0_ 18 E2 5 DQ A0 _17/ DQA_17 WCKA0_0 /DQMA_ 0 E30 DQMA0_ 1

Robson S3 MEM 14 DQA1_[ 31. .0]

InTERFACE 3/6 DQA1_ 2

Place all these components very close to GPU (Within

B - 10 Robson S3 MEM Interface 3/6

Robson S3 Straps 4/6

7 MXM_RST# R158 *0_04

Robson S3 Straps 4/6 B - 11

Robson S3 Power 5/6

T25 PCIE_VSS#21 GND#21 B24

GND#56 GND#36 DPF_VDD18#1 DPB_

B - 12 Robson S3 Power 5/6

Robson S3 Power 6/6

Robson S3 Power 6/6 B - 13

Robson DDR3 MEM CH-A

Robson DDR3 MEM M AA 1 0

B - 14 Robson DDR3 MEM CH-A

Robson DDR3 MEM CH-B

C OMPONEN TS SHOWN AR E EXA MPLES ON LY

Robson DDR3 MEM

Robson DDR3 MEM CH-B B - 15

HUDSON PCIE/ PCI/ CLOCK/ FCH

Diagram 14 1 41 .6m m

10 u_6 . 3V _X 5R _ 06 1u _6 .3 V _X 5R _0 4 *0. 1 u_1 0V _ X5R _ 04 U1

F B V D D Q_P W R _E N 0. 1 u_ 16 V _Y 5 V_ 04 P C 1 31 R 56 7 3 OP E N _3 A