Documente Academic
Documente Profesional
Documente Cultură
1 1
2
IGT30 2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sheet 1 of 47
A B C D E
A B C D E
ZZZ1
Compal confidential
File Name : LA-3451P LEFT SWITCH Board LEDs Board
14W_PCB
1
Mobile Merom 1
LVDS uFCPGA-478 CPU
Connector
page4,5,6 Clock Gen.
Nvidia N8M ICS9LPRS355
page15
H_A#(3..35)
FSB
H_D#(0..63) 667/800MHz
PCI-E X16
DDR2 -667 DDR2-SO-DIMM X2
Intel Crestline GMCH BANK 0, 1, 2, 3 page 13,14
S0 O O O O O
S3
O O O X O
S5 S4/AC
O O X X O
S5 S4/ Battery only
O X X X X
S5 S4/AC & Battery
don't exist X X X X X
O MEANS ON S3 : STR
X MEANS OFF S4 : STD
S5 : SOFT OFF
1 BOM Structure USB PORT LIST 1
MARK FUNCTION
External PCI Devices @ NC FOR ALL PORT DEVICE
Device IDSEL# REQ#/GNT# Interrupts
GIGA@ BCM5787 0 LEFT SIDE
13 94 AD22 0 PIRQG/H
100@ BCM5906 1 WIRELESS
UMA@ Internal 965GM 2 RIGHT SIDE
VGA@ 965PM + Ext VGA 3 CMOS
Address
4 RIGHT SIDE
5 NEW CARD
6
EC SM Bus1 address EC SM Bus2 address 7 BT(HDL20)
Device Address Device Address
8
Smart Battery 0001 011X b ADM1032 1001 100X b
9 3G
EEPROM(24C16/02) 1010 000X b
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 3 of 47
A
5 4 3 2 1
+3VS
XDP Reserve
XDP_DBRESET# 1 2 @ 1K_0402_5%
R157
+VCCP
ADDR GROUP 0
H_A#4 L5 E2 H_BNR#
A[4]# BNR# H_BNR# 7
H_A#5 L4 G5 H_BPRI#
A[5]# BPRI# H_BPRI# 7
H_A#6 K5
H_A#7 A[6]# H_DEFER#
M3 A[7]# DEFER# H5 H_DEFER# 7
H_A#8 N2 F21 H_DRD Y#
A[8]# DRDY# H_DRDY# 7
H_A#9 J1 E1 H_DBSY#
A[9]# DBSY# H_DBSY# 7
H_A#10 N3
H_A#11 A[10]# H_BR0# R92
P5 A[11]# BR0# F1 H_BR0# 7
H_A#12 P2 56_0402_5%
A[12]#
CONTROL
H_A#13 L2 D20 H_IERR# 2 1
H_A#14 A[13]# IERR# H_INIT# +VCCP
P4 A[14]# INIT# B3 H_INIT# 20
H_A#15 P1
H_A#16 A[15]# H_LOCK#
R1 A[16]# LOCK# H4 H_LOCK# 7
H_ADSTB#0 M1
7 H_ADSTB#0 ADSTB[0]#
C1 H_RESET#
RESET# H_RESET# 7
H_REQ#0 K3 F3 H_RS#0
7 H_REQ#0 REQ[0]# RS[0]# H_RS#0 7
H_REQ#1 H2 F4 H_RS#1
7 H_REQ#1 REQ[1]# RS[1]# H_RS#1 7
H_REQ#2 K2 G3 H_RS#2
7 H_REQ#2 REQ[2]# RS[2]# H_RS#2 7
H_REQ#3 J3 G2 H_TRDY#
7 H_REQ#3 REQ[3]# TRDY# H_TRDY# 7
H_REQ#4 L1
7 H_REQ#4 REQ[4]#
G6 H_HIT#
7 H_A#[17..35] HIT# H_HIT# 7
H_A#17 Y2 E4 H_HITM#
C A[17]# HITM# H_HITM# 7 C
H_A#18 U5
H_A#19 A[18]# XDP_BPM#0
R3 A[19]# BPM[0]# AD4 T17 +3VS
ADDR GROUP 1
2
H_A#24 R4 AC1 XDP_BPM#5
A[24]# PREQ# T14
H_A#25 T5 AC5 XDP_TCK 0.1U_0402_16V4Z R445
A[25]# TCK T7
H_A#26 T3 AA6 XDP_TDI U24 10K_0402_5%
A[26]# TDI T9
H_A#27 W2 AB3 XDP_TDO H_THERMDA 2 1
A[27]# TDO T16 D+ VDD1
H_A#28 W5 AB5 XDP_TMS C536
T11
1
H_A#29 A[28]# TMS XDP_TRST# H_THERMDC THERM_SCI#
Y4 A[29]# TRST# AB6 T5 1 2 3 D- ALERT# 6 2 1 EC_THERM# 21,33
H_A#30 U2 C20 XDP_DBRESET# 2200P_0402_50V7K R442 @ 0_0402_5%
A[30]# DBR# XDP_DBRESET# 21
H_A#31 V4 EC_SMB_CK2 8 4 THERM# 2 1 +3VS
A[31]# 33 EC_SMB_CK2 SCLK THERM#
H_A#32 W3 10K_0402_5% R448 Check : to sb
A[32]# H_PROCHOT# 45
H_A#33 AA4 THERMAL H_PROCHOT# 2 1 EC_SMB_DA2 7 5
A[33]# +VCCP 33 EC_SMB_DA2 SDATA GND
H_A#34 AB2 R87 56_0402_5%
H_A#35 A[34]#
AA3 A[35]# PROCHOT# D21
H_ADSTB#1 V1 A24 H_THERMDA G781F_SOP8
7 H_ADSTB#1 ADSTB[1]# THERMDA
B25 H_THERMDC Address:100_1100
H_A20M# THERMDC
20 H_A20M# A6 A20M#
ICH
H_FERR# A5 C7 H_THERMTRIP#
20 H_FERR# FERR# THERMTRIP# H_THERMTRIP# 7,20
H_IGNNE# C4
20 H_IGNNE# IGNNE#
H_STPCLK# D5
20 H_STPCLK# STPCLK#
H_INTR C6 H CLK
20 H_INTR LINT0
H_NMI B4 A22 CLK_CPU_BCLK
20 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 15
H_SMI# A3 A21 CLK_CPU_BCLK#
20 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 15
M4 RSVD[01]
FAN1 Conn
N5 RSVD[02] H_THERMDA, H_THERMDC routing together,
T2 RSVD[03]
B
V3 Trace width / Spacing = 10 / 10 mil +5VS B
RSVD[04] +5VS
B2
RESERVED
RSVD[05]
C3 RSVD[06] 1 2
D2 C528 10U_1206_16V4Z
RSVD[07]
1
D22 RSVD[08]
D3 U23 D17
RSVD[09] @ 1SS355_SOD323
F6 RSVD[10] 1 VEN GND 8
2 VIN GND 7
+VCC_FAN1 3 6 D18
2
EN_FAN1 VO GND @ 1N4148_SOT23
33 EN_FAN1 4 VSET GND 5
Merom Ball-out Rev 1a 1 2
ME@ G993P1UF_SOP8
C532
10U_1206_16V4Z
1 2
+3VS C529
+VCCP 1000P_0402_50V7K
1 2
1
R427
1
10K_0402_5%
R85 40mil JP61
2
@ 56_0402_5% +VCC_FAN1
1
33 FAN_SPEED1
2 2
2
3
B
1
C531 ACES_85205-03001
E
@ Q4
A MMBT3904_SOT23 2 A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom(1/3)-AGTL+/XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 4 of 47
5 4 3 2 1
5 4 3 2 1
+CPU_CORE +CPU_CORE
7 H_D#[0..15] H_D#[32..47] 7
JP1B JP1C
H_D#0 E22 Y22 H_D#32 A7 AB20
H_D#1 D[0]# D[32]# H_D#33 VCC[001] VCC[068]
F24 D[1]# D[33]# AB24 A9 VCC[002] VCC[069] AB7
H_D#2 E26 V24 H_D#34 A10 AC7
H_D#3 D[2]# D[34]# H_D#35 VCC[003] VCC[070]
G22 D[3]# D[35]# V26 A12 VCC[004] VCC[071] AC9
DATA GRP 0
H_D#4 F23 V23 H_D#36 A13 AC12
H_D#5 D[4]# D[36]# H_D#37 VCC[005] VCC[072]
G25 D[5]# D[37]# T22 A15 VCC[006] VCC[073] AC13
H_D#6 E25 U25 H_D#38 A17 AC15
D H_D#7 D[6]# D[38]# H_D#39 VCC[007] VCC[074] D
E23 D[7]# D[39]# U23 A18 VCC[008] VCC[075] AC17
H_D#8 K24 Y25 H_D#40 A20 AC18
DATA GRP 2
H_D#9 D[8]# D[40]# H_D#41 VCC[009] VCC[076]
G24 D[9]# D[41]# W22 B7 VCC[010] VCC[077] AD7
H_D#10 J24 Y23 H_D#42 B9 AD9
H_D#11 D[10]# D[42]# H_D#43 VCC[011] VCC[078]
J23 D[11]# D[43]# W24 B10 VCC[012] VCC[079] AD10
H_D#12 H22 W25 H_D#44 B12 AD12
H_D#13 D[12]# D[44]# H_D#45 VCC[013] VCC[080]
F26 D[13]# D[45]# AA23 B14 VCC[014] VCC[081] AD14
H_D#14 K22 AA24 H_D#46 B15 AD15
H_D#15 D[14]# D[46]# H_D#47 VCC[015] VCC[082]
H23 D[15]# D[47]# AB25 B17 VCC[016] VCC[083] AD17
H_DSTBN#0 J26 Y26 H_DSTBN#2 B18 AD18
7 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 7 VCC[017] VCC[084]
H_DSTBP#0 H26 AA26 H_DSTBP#2 B20 AE9
7 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 7 VCC[018] VCC[085]
H_DINV#0 H25 U22 H_DINV#2 C9 AE10
7 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 7 VCC[019] VCC[086]
7 H_D#[16..31] H_D#[48..63] 7 C10 VCC[020] VCC[087] AE12
C12 VCC[021] VCC[088] AE13
H_D#16 N22 AE24 H_D#48 C13 AE15
H_D#17 D[16]# D[48]# H_D#49 VCC[022] VCC[089]
K25 D[17]# D[49]# AD24 C15 VCC[023] VCC[090] AE17
H_D#18 P26 AA21 H_D#50 C17 AE18
H_D#19 D[18]# D[50]# H_D#51 VCC[024] VCC[091]
R23 D[19]# D[51]# AB22 C18 VCC[025] VCC[092] AE20
H_D#20 L23 AB21 H_D#52 D9 AF9
D[20]# D[52]# VCC[026] VCC[093]
DATA GRP 1
H_D#21 M24 AC26 H_D#53 D10 AF10
H_D#22 D[21]# D[53]# H_D#54 VCC[027] VCC[094]
L22 D[22]# D[54]# AD20 D12 VCC[028] VCC[095] AF12
H_D#23 M23 AE22 H_D#55 D14 AF14
H_D#24 D[23]# D[55]# H_D#56 VCC[029] VCC[096]
P25 D[24]# D[56]# AF23 D15 VCC[030] VCC[097] AF15
H_D#25 P23 AC25 H_D#57 D17 AF17 For testing purpose only
H_D#26 D[25]# D[57]# H_D#58 VCC[031] VCC[098]
P22 AE21 D18 AF18
DATA GRP 3
H_D#27 D[26]# D[58]# H_D#59 VCC[032] VCC[099] +VCCP
T24 D[27]# D[59]# AD21 E7 VCC[033] VCC[100] AF20
H_D#28 R24 AC22 H_D#60 E9 R91 0_0402_5%
H_D#29 D[28]# D[60]# H_D#61 VCC[034]
L25 D[29]# D[61]# AD23 E10 VCC[035] VCCP[01] G21 2 1
H_D#30 T25 AF22 H_D#62 E12 V6 2 1
H_D#31 D[30]# D[62]# H_D#63 VCC[036] VCCP[02] R164 0_0402_5%
N25 D[31]# D[63]# AC23 E13 VCC[037] VCCP[03] J6
H_DSTBN#1 L26 AE25 H_DSTBN#3 E15 K6 1
7 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 7 VCC[038] VCCP[04]
H_DSTBP#1 M26 AF24 H_DSTBP#3 E17 M6
C 7 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 7 VCC[039] VCCP[05] + C
H_DINV#1 N24 AC20 H_DINV#3 E18 J21 C214
7 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 7 VCC[040] VCCP[06]
E20 VCC[041] VCCP[07] K21
+CPU_GTLREF AD26 R26 COMP0 F7 M21 330U_D2E_2.5VM_R7
R94 TEST1 GTLREF COMP[0] COMP1 VCC[042] VCCP[08] 2
1 2 @ 1K_0402_5% C23 TEST1 MISC COMP[1] U26 F9 VCC[043] VCCP[09] N21
R93 1 2 @ 1K_0402_5% TEST2 D25 AA1 COMP2 F10 N6
TEST3 TEST2 COMP[2] COMP3 VCC[044] VCCP[10]
T4 C24 TEST3 COMP[3] Y1 F12 VCC[045] VCCP[11] R21
C237 1 2 @ 0.1U_0402_16V4Z TEST4 AF26 F14 R6
TEST5 TEST4 H_DPRSTP# VCC[046] VCCP[12]
T8 AF1 TEST5 DPRSTP# E5 H_DPRSTP# 7,20,45 F15 VCC[047] VCCP[13] T21
54.9_0402_1%
27.4_0402_1%
54.9_0402_1%
27.4_0402_1%
TEST6 A26 B5 H_DPSLP# F17 T6
T3 TEST6 DPSLP# H_DPSLP# 20 VCC[048] VCCP[14]
1
D24 H_DPWR# F18 V21
DPWR# H_DPWR# 7 VCC[049] VCCP[15]
CPU_BSEL0 B22 D6 H_PW RGOOD F20 W21
15 CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGOOD 20 VCC[050] VCCP[16]
R96
R97
R154
R153
CPU_BSEL1 B23 D7 H_CPUSLP# AA7
15 CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# 7 VCC[051]
CPU_BSEL2 C21 AE6 H_PSI# AA9 B26
15 CPU_BSEL2 BSEL[2] PSI# H_PSI# 45 VCC[052] VCCA[01] +1.5VS
0.01U_0402_16V7K
AA10 C26
2
VCC[053] VCCA[02]
10U_0805_10V4Z
Merom Ball-out Rev 1a AA12
ME@ VCC[054]
AA13 VCC[055] VID[0] AD6 CPU_VID0 45
AA15 VCC[056] VID[1] AF5 CPU_VID1 45 1 1
AA17 VCC[057] VID[2] AE5 CPU_VID2 45
C231
C238
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs Resistor placed within AA18 VCC[058] VID[3] AF4 CPU_VID3 45
AA20 AE3 CPU_VID4 45
0.5" of CPU pin.Trace AB9
VCC[059] VID[4]
AF3
2 2
VCC[060] VID[5] CPU_VID5 45
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 should be at least 25 AC10 VCC[061] VID[6] AE2 CPU_VID6 45
AB10
mils away from any other AB12
VCC[062]
VCC[063]
toggling signal. AB14 VCC[064] VCCSENSE AF7 VCCSENSE VCCSENSE 45
166 0 1 1 COMP[0,2] trace width is AB15 VCC[065] Near pin B26
AB17 VCC[066]
18 mils. COMP[1,3] trace AB18 VCC[067] VSSSENSE AE7 VSSSENSE VSSSENSE 45
width is 4 mils. Merom Ball-out Rev 1a
200 0 1 0
ME@ .
B Length match within 25 mils. B
R89
1K_0402_1%
+CPU_CORE
2
+CPU_GTLREF R483
100_0402_1%
1 2 VCCSENSE
1
R486
R95 100_0402_1%
2K_0402_1% 1 2 VSSSENSE
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom(2/3)-AGTL+/PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 5 of 47
5 4 3 2 1
5 4 3 2 1
+CPU_CORE
D D
1 1 1 1 1 1 1 1
JP1D
A4 P6 Place these capacitors on L8 C546 C551 C268 C289 C564 C287 C545 C322
VSS[001] VSS[082] (North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
A8 VSS[002] VSS[083] P21
2 2 2 2 2 2 2 2
A11 VSS[003] VSS[084] P24
A14 VSS[004] VSS[085] R2
A16 VSS[005] VSS[086] R5
A19 VSS[006] VSS[087] R22
+CPU_CORE
A23 VSS[007] VSS[088] R25
AF2 VSS[008] VSS[089] T1
B6 VSS[009] VSS[090] T4
B8 VSS[010] VSS[091] T23 1 1 1 1 1 1 1 1
B11 VSS[011] VSS[092] T26
B13 U3 Place these capacitors on L8 C549 C328 C558 C297 C542 C327 C286 C559
VSS[012] VSS[093] (North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
B16 VSS[013] VSS[094] U6
2 2 2 2 2 2 2 2
B19 VSS[014] VSS[095] U21
B21 VSS[015] VSS[096] U24
B24 VSS[016] VSS[097] V2
C5 VSS[017] VSS[098] V5
+CPU_CORE
C8 VSS[018] VSS[099] V22
C11 VSS[019] VSS[100] V25
C14 VSS[020] VSS[101] W1
C16 VSS[021] VSS[102] W4 1 1 1 1 1 1 1 1
C19 VSS[022] VSS[103] W23
C2 W26 Place these capacitors on L8 C321 C288 C555 C547 C291 C554 C314 C295
VSS[023] VSS[104] (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
C22 VSS[024] VSS[105] Y3
2 2 2 2 2 2 2 2
C25 VSS[025] VSS[106] Y6
D1 VSS[026] VSS[107] Y21
D4 VSS[027] VSS[108] Y24
D8 VSS[028] VSS[109] AA2
+CPU_CORE
D11 VSS[029] VSS[110] AA5
C C
D13 VSS[030] VSS[111] AA8
D16 VSS[031] VSS[112] AA11
D19 VSS[032] VSS[113] AA14 1 1 1 1 1 1 1 1
D23 VSS[033] VSS[114] AA16
D26 AA19 Place these capacitors on L8 C267 C285 C563 C292 C298 C296 C543 C315
VSS[034] VSS[115] (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
E3 VSS[035] VSS[116] AA22
2 2 2 2 2 2 2 2
E6 VSS[036] VSS[117] AA25
E8 VSS[037] VSS[118] AB1 Mid Frequence Decoupling
E11 VSS[038] VSS[119] AB4
E14 VSS[039] VSS[120] AB8
E16 VSS[040] VSS[121] AB11
E19 VSS[041] VSS[122] AB13
E21 VSS[042] VSS[123] AB16
E24 VSS[043] VSS[124] AB19
F5 VSS[044] VSS[125] AB23
F8 VSS[045] VSS[126] AB26
F11 VSS[046] VSS[127] AC3
F13 VSS[047] VSS[128] AC6
+CPU_CORE
F16 VSS[048] VSS[129] AC8
F19 VSS[049] VSS[130] AC11
F2 VSS[050] VSS[131] AC14
F22 VSS[051] VSS[132] AC16
F25 VSS[052] VSS[133] AC19
G4 AC21
VSS[053] VSS[134]
ESR <= 1.5m ohm
330U_V_2.5VK_R9
330U_V_2.5VK_R9
330U_V_2.5VK_R9
330U_V_2.5VK_R9
330U_V_2.5VK_R9
330U_V_2.5VK_R9
G1 VSS[054] VSS[135] AC24 1 1 1 1 1 1
G23 VSS[055] VSS[136] AD2
Capacitor > 1980uF
C561
C312
C313
C557
C548
C562
G26 AD5 + + + + + + North Side Secondary
VSS[056] VSS[137]
H3 VSS[057] VSS[138] AD8 South Side Secondary
H6 AD11 @ @
VSS[058] VSS[139] 2 2 2 2 2 2
H21 VSS[059] VSS[140] AD13
H24 VSS[060] VSS[141] AD16
J2 VSS[061] VSS[142] AD19
B B
J5 VSS[062] VSS[143] AD22
J22 VSS[063] VSS[144] AD25
J25 VSS[064] VSS[145] AE1
K1 VSS[065] VSS[146] AE4
K4 VSS[066] VSS[147] AE8
K23 VSS[067] VSS[148] AE11
K26 VSS[068] VSS[149] AE14
L3 VSS[069] VSS[150] AE16
L6 VSS[070] VSS[151] AE19
L21 AE23 +VCCP
VSS[071] VSS[152]
L24 VSS[072] VSS[153] AE26
M2 VSS[073] VSS[154] A2
M5 VSS[074] VSS[155] AF6 1
M22 VSS[075] VSS[156] AF8 1 1 1 1 1 1
M25 AF11 C229 + Place these inside
VSS[076] VSS[157] C324 C272 C273 C271 C323 C325 socket cavity on L8
N1 VSS[077] VSS[158] AF13
N4 AF16 220U_D2_4VM 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z (North side
VSS[078] VSS[159] 2 2 2 2 2 2 2 Secondary)
N23 VSS[079] VSS[160] AF19
N26 VSS[080] VSS[161] AF21
P3 VSS[081] VSS[162] A25
VSS[163] AF25
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom(3/3)-GND&Bypass
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 6 of 47
5 4 3 2 1
5 4 3 2 1
2.2U_0603_10V6K
M6 H_D#_3 H_A#_7 C15 AR12 RSVD5 SM_CK_4 AV23 M_CLK_DDR3 14
0.01U_0402_25V7K
H_D#4 H_A#8 +1.8V
H7 H_D#_4 H_A#_8 F16 AR13 RSVD6
H_D#5 H3 L13 H_A#9 AM12 AW30 M_CLK_DDR#0
H_D#_5 H_A#_9 RSVD7 SM_CK#_0 M_CLK_DDR#0 13
H_D#6 G4 G17 H_A#10 2 2 AN13 BA23 M_CLK_DDR#1
H_D#_6 H_A#_10 RSVD8 SM_CK#_1 M_CLK_DDR#1 13
1
H_D#7 F3 C14 H_A#11 J12 AW25 M_CLK_DDR#2
H_D#_7 H_A#_11 RSVD9 SM_CK#_3 M_CLK_DDR#2 14
RSVD
H_D#8 N8 K16 H_A#12 R31 AR37 AW23 M_CLK_DDR#3
H_D#_8 H_A#_12 RSVD10 SM_CK#_4 M_CLK_DDR#3 14
C73
C83
H_D#9 H2 B13 H_A#13 AM36
H_D#10 H_D#_9 H_A#_13 H_A#14 1 1 1K_0402_1% RSVD11 DDR_CKE0_DIMMA
M10 H_D#_10 H_A#_14 L16 AL36 RSVD12 SM_CKE_0 BE29 DDR_CKE0_DIMMA 13
H_D#11 N12 J17 H_A#15 AM37 AY32 DDR_CKE1_DIMMA
DDR_CKE1_DIMMA 13
2
D H_D#12 H_D#_11 H_A#_15 H_A#16 SMRCOMP_VOH RSVD13 SM_CKE_1 DDR_CKE2_DIMMB D
N9 H_D#_12 H_A#_16 B14 D20 RSVD14 SM_CKE_3 BD39 DDR_CKE2_DIMMB 14
H_D#13 H5 K19 H_A#17 BG37 DDR_CKE3_DIMMB
H_D#_13 H_A#_17 SM_CKE_4 DDR_CKE3_DIMMB 14
1
H_D#14 P13 P15 H_A#18
H_D#15 H_D#_14 H_A#_18 H_A#19 R38 DDR_CS0_DIMMA#
K9 H_D#_15 H_A#_19 R17 SM_CS#_0 BG20 DDR_CS0_DIMMA# 13
H_D#16 M2 B16 H_A#20 3.01K_0402_1% BK16 DDR_CS1_DIMMA#
H_D#_16 H_A#_20 SM_CS#_1 DDR_CS1_DIMMA# 13
H_D#17 W10 H20 H_A#21 NA lead free BG16 DDR_CS2_DIMMB#
H_D#_17 H_A#_21 SM_CS#_2 DDR_CS2_DIMMB# 14
H_D#18 Y8 L19 H_A#22 H10 BE13 DDR_CS3_DIMMB#
DDR_CS3_DIMMB# 14
2
H_D#_18 H_A#_22 RSVD20 SM_CS#_3
MUXING
H_D#19 V4 D17 H_A#23 SMRCOMP_VOL B51
H_D#20 H_D#_19 H_A#_23 H_A#24 RSVD21 M_ODT0
M3 H_D#_20 H_A#_24 M17 BJ20 RSVD22 SM_ODT_0 BH18 M_ODT0 13
1
2.2U_0603_10V6K
0.01U_0402_25V7K
H_D#21 J1 N16 H_A#25 BK22 BJ15 M_ODT1 M_ODT1 13
H_D#22 H_D#_21 H_A#_25 H_A#26 R45 RSVD23 SM_ODT_1 M_ODT2 +1.8V
N5 H_D#_22 H_A#_26 J19 1 1 BF19 RSVD24 SM_ODT_2 BJ14 M_ODT2 14
H_D#23 N3 B18 H_A#27 BH20 BE16 M_ODT3 M_ODT3 14
H_D#24 H_D#_23 H_A#_27 H_A#28 1K_0402_1% RSVD25 SM_ODT_3 20_0402_1%
W6 H_D#_24 H_A#_28 E19 BK18 RSVD26
C91
C84
H_D#25 W9 B17 H_A#29 BJ18 BL15 SMRCOMP R23 2 1
2
H_D#26 H_D#_25 H_A#_29 H_A#30 2 2 RSVD27 SM_RCOMP SMRCOMP#
N2 H_D#_26 H_A#_30 B15 BF23 RSVD28 SM_RCOMP# BK14 2 1
H_D#27 Y7 E17 H_A#31 BG23 R22 20_0402_1%
H_D#28 H_D#_27 H_A#_31 H_A#32 RSVD29 SMRCOMP_VOH
Y9 H_D#_28 H_A#_32 C18 BC23 RSVD30 SM_RCOMP_VOH BK31
H_D#29 P4 A19 H_A#33 BD24 BL31 SMRCOMP_VOL
DDR
H_D#30 H_D#_29 H_A#_33 H_A#34 RSVD31 SM_RCOMP_VOL
W3 H_D#_30 H_A#_34 B19 13 DDR_A_MA14 BJ29 RSVD32
H_D#31 N1 N19 H_A#35 BE24 AR49
H_D#_31 H_A#_35 14 DDR_B_MA14 RSVD33 SM_VREF_0
H_D#32 AD12 BH39 AW4 +DDR_MCH_REF
H_D#33 H_D#_32 H_ADS# RSVD34 SM_VREF_1
AE3 H_D#_33 H_ADS# G12 H_ADS# 4 AW20 RSVD35
H_D#34 AD9
HOST H17 H_ADSTB#0 BK20
H_D#_34 H_ADSTB#_0 H_ADSTB#0 4 RSVD36
H_D#35 AC9 G20 H_ADSTB#1 C48
H_D#_35 H_ADSTB#_1 H_ADSTB#1 4 RSVD37
H_D#36 AC7 C8 H_BNR# D47 B42 CLK_MCH_DREFCLK
H_D#_36 H_BNR# H_BNR# 4 RSVD38 DPLL_REF_CLK CLK_MCH_DREFCLK 15
H_D#37 AC14 E8 H_BPRI# B44 C42 CLK_MCH_DREFCLK#
H_D#_37 H_BPRI# H_BPRI# 4 RSVD39 DPLL_REF_CLK# CLK_MCH_DREFCLK# 15
H_D#38 AD11 F12 H_BR0# C44 H48 MCH_SSCDREFCLK
H_D#_38 H_BREQ# H_BR0# 4 RSVD40 DPLL_REF_SSCLK MCH_SSCDREFCLK 15
H_D#39 AC11 D6 H_DEFER# A35 H47 MCH_SSCDREFCLK#
H_D#_39 H_DEFER# H_DEFER# 4 RSVD41 DPLL_REF_SSCLK# MCH_SSCDREFCLK# 15
H_D#40 AB2 C10 H_DBSY# B37
H_D#_40 H_DBSY# H_DBSY# 4 RSVD42
H_D#41 AD7 AM5 CLK_MCH_BCLK B36 K44 CLK_MCH_3GPLL
CLK_MCH_BCLK 15 CLK_MCH_3GPLL 15
CLK
H_D#42 H_D#_41 HPLL_CLK CLK_MCH_BCLK# RSVD43 PEG_CLK CLK_MCH_3GPLL#
AB1 H_D#_42 HPLL_CLK# AM7 CLK_MCH_BCLK# 15 B34 RSVD44 PEG_CLK# K45 CLK_MCH_3GPLL# 15
H_D#43 Y3 H8 H_DPWR# C34
C H_D#_43 H_DPWR# H_DPWR# 5 RSVD45 C
H_D#44 AC6 K7 H_DRD Y#
H_D#_44 H_DRDY# H_DRDY# 4
H_D#45 AE2 E4 H_HIT#
H_D#_45 H_HIT# H_HIT# 4
H_D#46 AC5 C6 H_HITM# AN47 DMI_TXN0
H_D#_46 H_HITM# H_HITM# 4 DMI_RXN_0 DMI_TXN0 21
H_D#47 AG3 G10 H_LOCK# AJ38 DMI_TXN1
H_D#_47 H_LOCK# H_LOCK# 4 DMI_RXN_1 DMI_TXN1 21
H_D#48 AJ9 B7 H_TRDY# AN42 DMI_TXN2
H_D#_48 H_TRDY# H_TRDY# 4 DMI_RXN_2 DMI_TXN2 21
H_D#49 AH8 AN46 DMI_TXN3
H_D#_49 DMI_RXN_3 DMI_TXN3 21
H_D#50 AJ14
H_D#51 H_D#_50 DMI_TXP0
AE9 H_D#_51 DMI_RXP_0 AM47 DMI_TXP0 21
H_D#52 AE11 MCH_CLKSEL0 P27 AJ39 DMI_TXP1
+VCCP H_D#_52 15 MCH_CLKSEL0 CFG_0 DMI_RXP_1 DMI_TXP1 21
H_D#53 AH12 K5 H_DINV#0 MCH_CLKSEL1 N27 AN41 DMI_TXP2
H_D#_53 H_DINV#_0 H_DINV#0 5 15 MCH_CLKSEL1 CFG_1 DMI_RXP_2 DMI_TXP2 21
H_D#54 AJ5 L2 H_DINV#1 MCH_CLKSEL2 N24 AN45 DMI_TXP3
H_D#_54 H_DINV#_1 H_DINV#1 5 15 MCH_CLKSEL2 CFG_2 DMI_RXP_3 DMI_TXP3 21
H_D#55 AH5 AD13 H_DINV#2 C21
H_D#_55 H_DINV#_2 H_DINV#2 5 CFG_3
H_D#56 AJ6 AE13 H_DINV#3 C23 AJ46 DMI_RXN0
H_D#_56 H_DINV#_3 H_DINV#3 5 CFG_4 DMI_TXN_0 DMI_RXN0 21
54.9_0402_1%
54.9_0402_1%
R15
DMI
H_D#_60 H_DSTBN#_2 H_DSTBN#2 5 9 CFG8 CFG_8
CFG
H_D#61 AJ3 AH11 H_DSTBN#3 CFG9 C20 AJ47 DMI_RXP0
H_D#_61 H_DSTBN#_3 H_DSTBN#3 5 9 CFG9 CFG_9 DMI_TXP_0 DMI_RXP0 21
H_D#62 AH2 CFG10 R24 AJ42 DMI_RXP1
CFG10 DMI_RXP1 21
2
GRAPHICS VID
W1 H_SCOMP H_REQ#_1 E13 H_REQ#1 4 M24 CFG_17
H_SCOMP# W2 A11 H_REQ#2 CFG18 L32
H_SCOMP# H_REQ#_2 H_REQ#2 4 CFG18 CFG_18
H13 H_REQ#3 CFG19 N33
H_REQ#_3 H_REQ#3 4 9 CFG19 CFG_19
4 H_RESET# H_RESET# B6 B12 H_REQ#4 CFG20 L35
H_CPURST# H_REQ#_4 H_REQ#4 4 9 CFG20 CFG_20
5 H_CPUSLP# H_CPUSLP# E5 H_CPUSLP# H_RS#0
H_RS#_0 E12 H_RS#0 4
D7 H_RS#1 H_RS#1 4 Check : different from hdl00 E35
B H_RS#_1 H_RS#2 PM_BMBUSY# GFX_VID_0 B
H_RS#_2 D8 H_RS#2 4 21 PM_BMBUSY# G41 PM_BM_BUSY# GFX_VID_1 A39
B9 H_DPRSTP# L39 C38
H_AVREF 5,20,45 H_DPRSTP# PM_DPRSTP# GFX_VID_2
H_VREF A9 PM_EXTTS#0 L36 B39
H_DVREF 13 PM_EXTTS#0 PM_EXT_TS#_0 GFX_VID_3
PM
PM_EXTTS#1 J36 E36
14 PM_EXTTS#1 PM_EXT_TS#_1 GFX_VR_EN
CRESTLINE_1p0 2 1 PM_POK_R PM_POK_R AW49
21,33 ICH_POK PWROK +1.25VS
R436 0_0402_5% PLT_RST#_R AV20
H_THERMTRIP# RSTIN#
21,45 VGATE 2 1 4,20 H_THERMTRIP# N20 THERMTRIP#
R438 @ 0_0402_5% 0309 add 21,45 DPRSLPVR DPRSLPVR G36 For AMT function
DPRSLPVR
1
1 2 PLT_RST#_R
18,19,21,23,24,26,27 PLT_RST#
layout note: R449 100_0402_5% AM49 CL_CLK0 R71
CL_CLK CL_CLK0 21
AK50 CL_DATA0
CL_DATA CL_DATA0 21
Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces BJ51 AT43 1K_0402_1%
NC_1 CL_PWROK M_PWROK 21
+3VS CL_RST#
ME
BK51 AN49 CL_RST# 21
2
NC_2 CL_RST# CL_VREF
BK50 NC_3 CL_VREF AM50
Layout Note: 1 2 PM_EXTTS#0 BL50 NC_4
1
Layout Note: R57 10K_0402_5% BL49 0.1U_0402_16V4Z 1
V_DDR_MCH_REF +1.8V PM_EXTTS#1 NC_5 R75
1 2 BL3
H_RCOMP / H_VREF / H_SWNG trace width and R64 10K_0402_5% BL2
NC_6 C167 392_0402_1%
NC_7
NC
trace width and spacing is 10/20 spacing is 20/20. BK1 NC_8
1
2
BJ1 H35
2
R67 NC_9 SDVO_CTRL_CLK
MISC
E1 NC_10 SDVO_CTRL_DATA K36
1K_0402_1% A5 G39 CLKREQ_3GPLL# CLKREQ_3GPLL# 15
NC_11 CLK_REQ# MCH_ICH_SYNC#
C51 NC_12 ICH_SYNC# G40 MCH_ICH_SYNC# 21
+VCCP B50
2
1 R68
1
R16
CRESTLINE_1p0
R411
C161
2
24.9_0402_1%
0.1U_0402_16V4Z
1
1
100_0402_1%
2K_0402_1%
1 1
C23
R17
C15
R412
R399
2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE(1/6)-AGTL+/DMI/DDR2
within 100 mils from NB Near B3 pin AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 7 of 47
5 4 3 2 1
5 4 3 2 1
D D
13 DDR_A_D[0..63] 14 DDR_B_D[0..63]
U22D U22E
DDR_A_D0 AR43 BB19 DDR_A_BS#0 DDR_B_D0 AP49 AY17 DDR_B_BS#0
SA_DQ_0 SA_BS_0 DDR_A_BS#0 13 SB_DQ_0 SB_BS_0 DDR_B_BS#0 14
DDR_A_D1 AW44 BK19 DDR_A_BS#1 DDR_B_D1 AR51 BG18 DDR_B_BS#1
SA_DQ_1 SA_BS_1 DDR_A_BS#1 13 SB_DQ_1 SB_BS_1 DDR_B_BS#1 14
DDR_A_D2 BA45 BF29 DDR_A_BS#2 DDR_B_D2 AW50 BG36 DDR_B_BS#2
SA_DQ_2 SA_BS_2 DDR_A_BS#2 13 SB_DQ_2 SB_BS_2 DDR_B_BS#2 14
DDR_A_D3 AY46 DDR_B_D3 AW51
DDR_A_D4 SA_DQ_3 DDR_A_CAS# DDR_B_D4 SB_DQ_3 DDR_B_CAS#
AR41 SA_DQ_4 SA_CAS# BL17 DDR_A_CAS# 13 AN51 SB_DQ_4 SB_CAS# BE17 DDR_B_CAS# 14
DDR_A_D5 AR45 DDR_B_D5 AN50
SA_DQ_5 DDR_A_DM[0..7] 13 SB_DQ_5 DDR_B_DM[0..7] 14
DDR_A_D6 AT42 AT45 DDR_A_DM0 DDR_B_D6 AV50 AR50 DDR_B_DM0
DDR_A_D7 SA_DQ_6 SA_DM_0 DDR_A_DM1 DDR_B_D7 SB_DQ_6 SB_DM_0 DDR_B_DM1
AW47 SA_DQ_7 SA_DM_1 BD44 AV49 SB_DQ_7 SB_DM_1 BD49
DDR_A_D8 BB45 BD42 DDR_A_DM2 DDR_B_D8 BA50 BK45 DDR_B_DM2
DDR_A_D9 SA_DQ_8 SA_DM_2 DDR_A_DM3 DDR_B_D9 SB_DQ_8 SB_DM_2 DDR_B_DM3
BF48 SA_DQ_9 SA_DM_3 AW38 BB50 SB_DQ_9 SB_DM_3 BL39
DDR_A_D10 BG47 AW13 DDR_A_DM4 DDR_B_D10 BA49 BH12 DDR_B_DM4
DDR_A_D11 SA_DQ_10 SA_DM_4 DDR_A_DM5 DDR_B_D11 SB_DQ_10 SB_DM_4 DDR_B_DM5
BJ45 SA_DQ_11 SA_DM_5 BG8 BE50 SB_DQ_11 SB_DM_5 BJ7
DDR_A_D12 BB47 AY5 DDR_A_DM6 DDR_B_D12 BA51 BF3 DDR_B_DM6
DDR_A_D13 SA_DQ_12 SA_DM_6 DDR_A_DM7 DDR_B_D13 SB_DQ_12 SB_DM_6 DDR_B_DM7
BG50 SA_DQ_13 SA_DM_7 AN6 AY49 SB_DQ_13 SB_DM_7 AW2
DDR_A_D14 BH49 DDR_A_DQS[0..7] 13 DDR_B_D14 BF50
SA_DQ_14 SB_DQ_14 DDR_B_DQS[0..7] 14
DDR_A_D15 BE45 AT46 DDR_A_DQS0 DDR_B_D15 BF49 AT50 DDR_B_DQS0
A
DDR_A_D16 SA_DQ_15 SA_DQS_0 DDR_A_DQS1 DDR_B_D16 SB_DQ_15 SB_DQS_0 DDR_B_DQS1
AW43 BE48 BJ50 BD50
B
DDR_A_D17 SA_DQ_16 SA_DQS_1 DDR_A_DQS2 DDR_B_D17 SB_DQ_16 SB_DQS_1 DDR_B_DQS2
BE44 SA_DQ_17 SA_DQS_2 BB43 BJ44 SB_DQ_17 SB_DQS_2 BK46
DDR_A_D18 BG42 BC37 DDR_A_DQS3 DDR_B_D18 BJ43 BK39 DDR_B_DQS3
DDR_A_D19 SA_DQ_18 SA_DQS_3 DDR_A_DQS4 DDR_B_D19 SB_DQ_18 SB_DQS_3 DDR_B_DQS4
BE40 SA_DQ_19 SA_DQS_4 BB16 BL43 SB_DQ_19 SB_DQS_4 BJ12
DDR_A_D20 DDR_A_DQS5 DDR_B_D20 DDR_B_DQS5
MEMORY
BF44 SA_DQ_20 SA_DQS_5 BH6 BK47 SB_DQ_20 SB_DQS_5 BL7
DDR_A_D21 DDR_A_DQS6 DDR_B_D21 DDR_B_DQS6
MEMORY
BH45 SA_DQ_21 SA_DQS_6 BB2 BK49 SB_DQ_21 SB_DQS_6 BE2
DDR_A_D22 BG40 AP3 DDR_A_DQS7 DDR_B_D22 BK43 AV2 DDR_B_DQS7
SA_DQ_22 SA_DQS_7 DDR_A_DQS#[0..7] 13 SB_DQ_22 SB_DQS_7 DDR_B_DQS#[0..7] 14
DDR_A_D23 BF40 AT47 DDR_A_DQS#0 DDR_B_D23 BK42 AU50 DDR_B_DQS#0
DDR_A_D24 SA_DQ_23 SA_DQS#_0 DDR_A_DQS#1 DDR_B_D24 SB_DQ_23 SB_DQS#_0 DDR_B_DQS#1
AR40 SA_DQ_24 SA_DQS#_1 BD47 BJ41 SB_DQ_24 SB_DQS#_1 BC50
DDR_A_D25 AW40 BC41 DDR_A_DQS#2 DDR_B_D25 BL41 BL45 DDR_B_DQS#2
DDR_A_D26 SA_DQ_25 SA_DQS#_2 DDR_A_DQS#3 DDR_B_D26 SB_DQ_25 SB_DQS#_2 DDR_B_DQS#3
AT39 SA_DQ_26 SA_DQS#_3 BA37 BJ37 SB_DQ_26 SB_DQS#_3 BK38
DDR_A_D27 AW36 BA16 DDR_A_DQS#4 DDR_B_D27 BJ36 BK12 DDR_B_DQS#4
DDR_A_D28 SA_DQ_27 SA_DQS#_4 DDR_A_DQS#5 DDR_B_D28 SB_DQ_27 SB_DQS#_4 DDR_B_DQS#5
AW41 SA_DQ_28 SA_DQS#_5 BH7 BK41 SB_DQ_28 SB_DQS#_5 BK7
C DDR_A_D29 DDR_A_DQS#6 DDR_B_D29 DDR_B_DQS#6 C
AY41 SA_DQ_29 SA_DQS#_6 BC1 BJ40 SB_DQ_29 SB_DQS#_6 BF2
DDR_A_D30 AV38 AP2 DDR_A_DQS#7 DDR_B_D30 BL35 AV3 DDR_B_DQS#7
SA_DQ_30 SA_DQS#_7 DDR_A_MA[0..13] 13 SB_DQ_30 SB_DQS#_7
DDR_A_D31 AT38 DDR_B_D31 BK37 DDR_B_MA[0..13] 14
DDR_A_D32 SA_DQ_31 DDR_A_MA0 DDR_B_D32 SB_DQ_31 DDR_B_MA0
AV13 SA_DQ_32 SA_MA_0 BJ19 BK13 SB_DQ_32 SB_MA_0 BC18
SYSTEM
SYSTEM
DDR_A_D34 AW11 BK27 DDR_A_MA2 DDR_B_D34 BK11 BG25 DDR_B_MA2
DDR_A_D35 SA_DQ_34 SA_MA_2 DDR_A_MA3 DDR_B_D35 SB_DQ_34 SB_MA_2 DDR_B_MA3
AV11 SA_DQ_35 SA_MA_3 BH28 BC11 SB_DQ_35 SB_MA_3 AW17
DDR_A_D36 AU15 BL24 DDR_A_MA4 DDR_B_D36 BC13 BF25 DDR_B_MA4
DDR_A_D37 SA_DQ_36 SA_MA_4 DDR_A_MA5 DDR_B_D37 SB_DQ_36 SB_MA_4 DDR_B_MA5
AT11 SA_DQ_37 SA_MA_5 BK28 BE12 SB_DQ_37 SB_MA_5 BE25
DDR_A_D38 BA13 BJ27 DDR_A_MA6 DDR_B_D38 BC12 BA29 DDR_B_MA6
DDR_A_D39 SA_DQ_38 SA_MA_6 DDR_A_MA7 DDR_B_D39 SB_DQ_38 SB_MA_6 DDR_B_MA7
BA11 SA_DQ_39 SA_MA_7 BJ25 BG12 SB_DQ_39 SB_MA_7 BC28
DDR_A_D40 BE10 BL28 DDR_A_MA8 DDR_B_D40 BJ10 AY28 DDR_B_MA8
DDR_A_D41 SA_DQ_40 SA_MA_8 DDR_A_MA9 DDR_B_D41 SB_DQ_40 SB_MA_8 DDR_B_MA9
BD10 SA_DQ_41 SA_MA_9 BA28 BL9 SB_DQ_41 SB_MA_9 BD37
DDR_A_D42 BD8 BC19 DDR_A_MA10 DDR_B_D42 BK5 BG17 DDR_B_MA10
DDR_A_D43 SA_DQ_42 SA_MA_10 DDR_A_MA11 DDR_B_D43 SB_DQ_42 SB_MA_10 DDR_B_MA11
AY9 SA_DQ_43 SA_MA_11 BE28 BL5 SB_DQ_43 SB_MA_11 BE37
DDR_A_D44 BG10 BG30 DDR_A_MA12 DDR_B_D44 BK9 BA39 DDR_B_MA12
DDR_A_D45 SA_DQ_44 SA_MA_12 DDR_A_MA13 DDR_B_D45 SB_DQ_44 SB_MA_12 DDR_B_MA13
AW9 SA_DQ_45 SA_MA_13 BJ16 BK10 SB_DQ_45 SB_MA_13 BG13
DDR
DDR
DDR_A_D47 BB9 DDR_B_D47 BJ6 AV16 DDR_B_RAS#
SA_DQ_47 SB_DQ_47 SB_RAS# DDR_B_RAS# 14
DDR_A_D48 BB5 BE18 DDR_A_RAS# DDR_B_D48 BF4 AY18 SB_RCVEN#
SA_DQ_48 SA_RAS# DDR_A_RAS# 13 SB_DQ_48 SB_RCVEN#
DDR_A_D49 AY7 AY20 SA_RCVEN# DDR_B_D49 BH5 T1
DDR_A_D50 SA_DQ_49 SA_RCVEN# T2 DDR_B_D50 SB_DQ_49 DDR_B_WE#
AT5 SA_DQ_50 BG1 SB_DQ_50 SB_WE# BC17 DDR_B_WE# 14
DDR_A_D51 AT7 BA19 DDR_A_WE# DDR_A_WE# 13 DDR_B_D51 BC2
DDR_A_D52 SA_DQ_51 SA_WE# DDR_B_D52 SB_DQ_51
AY6 SA_DQ_52 BK3 SB_DQ_52
DDR_A_D53 BB7 DDR_B_D53 BE4
DDR_A_D54 SA_DQ_53 DDR_B_D54 SB_DQ_53
AR5 SA_DQ_54 BD3 SB_DQ_54
DDR_A_D55 AR8 DDR_B_D55 BJ2
DDR_A_D56 SA_DQ_55 DDR_B_D56 SB_DQ_55
AR9 SA_DQ_56 BA3 SB_DQ_56
DDR_A_D57 AN3 DDR_B_D57 BB3
DDR_A_D58 SA_DQ_57 DDR_B_D58 SB_DQ_57
AM8 SA_DQ_58 AR1 SB_DQ_58
DDR_A_D59 AN10 DDR_B_D59 AT3
DDR_A_D60 SA_DQ_59 DDR_B_D60 SB_DQ_59
AT9 SA_DQ_60 AY2 SB_DQ_60
B DDR_A_D61 DDR_B_D61 B
AN9 SA_DQ_61 AY3 SB_DQ_61
DDR_A_D62 AM9 DDR_B_D62 AU2
DDR_A_D63 SA_DQ_62 DDR_B_D63 SB_DQ_62
AN11 SA_DQ_63 AT2 SB_DQ_63
CRESTLINE_1p0 CRESTLINE_1p0
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE((2/6)-DDR2 A/B CH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 8 of 47
5 4 3 2 1
5 4 3 2 1
+3VS
Strap Pin Table
1
R59 R56 010 = FSB 800MHz
2.2K_0402_5% 2.2K_0402_5%
UMA@ UMA@ CFG[2:0] FSB Freq select 011 = FSB 667MHz
2
EDID_CLK_LCD Others = Reserved
37 EDID_CLK_LCD
EDID_DAT_LCD
37 EDID_DAT_LCD
PEGCOMP trace width
0 = DMI x 2
U22C and spacing is 20/25 mils. CFG5 (DMI select)
D D
1 = DMI x 4
16 GMCH_ENBKL GMCH_ENBKL
J40
H39
L_BKLT_CTRL
N43
R66 +VCC_PEG
24.9_0402_1%
*
R425 1 L_BKLT_EN PEG_COMPI
+3VS 2 10K_0402_5% E39 L_CTRL_CLK PEG_COMPO M43 PEGCOMP 1 2 CFG6 Reserved
R429 1 2 10K_0402_5% E40 L_CTRL_DATA PEG_RXN[0..15] 18
EDID_CLK_LCD C37
EDID_DAT_LCD L_DDC_CLK PEG_RXN0
D35 L_DDC_DATA PEG_RX#_0 J51 CFG7 (CPU Strap) 0 = Reserved
16 GMCH_LVDDEN GMCH_LVDDEN K40 L51 PEG_RXN1
L_VDD_EN PEG_RX#_1 PEG_RXN2
N47 1 = Mobile CPU
R62
2 1
2.4K_0402_1%
L41
L43
LVDS_IBG
PEG_RX#_2
PEG_RX#_3 T45
T50
PEG_RXN3
PEG_RXN4
*
LVDS_VBG PEG_RX#_4 PEG_RXN5
N41 LVDS_VREFH PEG_RX#_5 U40 0 = Normal mode
N40 Y44 PEG_RXN6 CFG8 (Low power PCIE)
LVDSAC- LVDS_VREFL PEG_RX#_6 PEG_RXN7
For Crestline:2.4kohm D46 Y40 1 = Low Power mode
For Calero: 1.5Kohm
37
37
LVDSAC-
LVDSAC+
LVDSAC+
LVDSBC-
C45
D44
LVDSA_CLK#
LVDSA_CLK
PEG_RX#_7
PEG_RX#_8 AB51
W49
PEG_RXN8
PEG_RXN9
*
37 LVDSBC- LVDSBC+ LVDSB_CLK# PEG_RX#_9 PEG_RXN10
37 LVDSBC+ E42 LVDSB_CLK PEG_RX#_10 AD44 CFG9 0 = Reverse Lane
LVDS
AD40 PEG_RXN11
LVDSA0- PEG_RX#_11 PEG_RXN12
G51 AG46 (PCIE Graphics Lane Reversal) 1 = Normal Operation
37
37
LVDSA0-
LVDSA1-
LVDSA1-
LVDSA2-
E51
F49
LVDSA_DATA#_0
LVDSA_DATA#_1
PEG_RX#_12
PEG_RX#_13 AH49
AG45
PEG_RXN13
PEG_RXN14
*
37 LVDSA2- LVDSA_DATA#_2 PEG_RX#_14
AG41 PEG_RXN15
PEG_RX#_15 PEG_RXP[0..15] 18
CFG[11:10] Reserved
GRAPHICS
37 LVDSA0+ LVDSA0+ G50 J50 PEG_RXP0
LVDSA1+ LVDSA_DATA_0 PEG_RX_0 PEG_RXP1
E50 L50
37 LVDSA1+
LVDSA2+ F48
LVDSA_DATA_1 PEG_RX_1
M47 PEG_RXP2 00 = Reserved
37 LVDSA2+ LVDSA_DATA_2 PEG_RX_2 01 = XOR Mode Enabled
U44 PEG_RXP3 CFG[13:12] (XOR/ALLZ)
PEG_RX_3
PEG_RX_4 T49 PEG_RXP4 10 = All Z Mode Enabled
LVDSB0- G44 T41 PEG_RXP5 11 = Normal Operation (Default)
37
37
LVDSB0-
LVDSB1-
LVDSB1-
LVDSB2-
B47
B45
LVDSB_DATA#_0
LVDSB_DATA#_1
PEG_RX_5
PEG_RX_6 W45
W41
PEG_RXP6
PEG_RXP7
*
37 LVDSB2- LVDSB_DATA#_2 PEG_RX_7 PEG_RXP8
C PEG_RX_8 AB50 CFG[15:14] Reserved C
Y48 PEG_RXP9
LVDSB0+ PEG_RX_9 PEG_RXP10
37 LVDSB0+ E44 LVDSB_DATA_0 PEG_RX_10 AC45
LVDSB1+ A47 AC41 PEG_RXP11 CFG16 (FSB Dynamic ODT) 0 = Disabled
37 LVDSB1+ LVDSB_DATA_1 PEG_RX_11
LVDSB2+ A45 AH47 PEG_RXP12
37 LVDSB2+ LVDSB_DATA_2 PEG_RX_12 PEG_RXP13
AG49 1 = Enabled
PCI-EXPRESS
PEG_RX_13
PEG_RX_14 AH45
AG42
PEG_RXP14
PEG_RXP15 PEG_M_TXN[0..15] 18
*
TV_COMPS PEG_RX_15
2 1 CFG[18:17] Reserved
R414 UMA@ 150_0603_1% 17 TV_COMPS TV_COMPS E27 N45 PEG_TXN0 C277 VGA@ 0.1U_0402_16V4Z PEG_M_TXN0
TV_LUMA TV_LUMA TVA_DAC PEG_TX#_0 PEG_TXN1 C234 VGA@ 0.1U_0402_16V4Z PEG_M_TXN1
2 1 17 TV_LUMA G27 TVB_DAC PEG_TX#_1 U39
R415 UMA@ 150_0603_1% TV_CRMA K27 U47 PEG_TXN2 C259 VGA@ 0.1U_0402_16V4Z PEG_M_TXN2 0 = No SDVO Device Present
2
R416
1 TV_CRMA
UMA@ 150_0603_1%
17 TV_CRMA
F27
TVC_DAC
TV PEG_TX#_2
PEG_TX#_3 N51
R50
PEG_TXN3
PEG_TXN4
C218
C279
VGA@
VGA@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_M_TXN3
PEG_M_TXN4
SDVO_CTRLDATA
1 = SDVO Device Present
*
TVA_RTN PEG_TX#_4 PEG_TXN5 C236 VGA@ 0.1U_0402_16V4Z PEG_M_TXN5
J27 TVB_RTN PEG_TX#_5 T42
L27 Y43 PEG_TXN6 C264 VGA@ 0.1U_0402_16V4Z PEG_M_TXN6
TVC_RTN PEG_TX#_6 PEG_TXN7 C221 VGA@ 0.1U_0402_16V4Z PEG_M_TXN7
W46 0 = Normal Operation
+3VS 1 2
M35
P33
TV_DCONSEL_0
PEG_TX#_7
PEG_TX#_8 W38
AD39
PEG_TXN8
PEG_TXN9
C282
C242
VGA@
VGA@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_M_TXN8
PEG_M_TXN9
CFG19 (DMI Lane Reversal) (Lane number in Order) *
R52 2.2K_0402_5% TV_DCONSEL_1 PEG_TX#_9 PEG_TXN10 C257 VGA@ 0.1U_0402_16V4Z PEG_M_TXN10
PEG_TX#_10 AC46 1 = Reverse Lane
AC49 PEG_TXN11 C223 VGA@ 0.1U_0402_16V4Z PEG_M_TXN11
PEG_TX#_11 PEG_TXN12 C284 VGA@ 0.1U_0402_16V4Z PEG_M_TXN12
PEG_TX#_12 AC42
AH39 PEG_TXN13 C239 VGA@ 0.1U_0402_16V4Z PEG_M_TXN13 0 = Only PCIE or SDVO is operational.
PEG_TX#_13
PEG_TX#_14 AE49
AH44
PEG_TXN14
PEG_TXN15
C262
C225
VGA@
VGA@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_M_TXN14
PEG_M_TXN15 PEG_M_TXP[0..15] 18
CFG20 (PCIE/SDVO concurrent)
1 = PCIE/SDVO are operating simu.
*
PEG_TX#_15
2 1 CRT_R CRT_B H32 M45 PEG_TXP0 C276 VGA@ 0.1U_0402_16V4Z PEG_M_TXP0
17 CRT_B CRT_BLUE PEG_TX_0
R421 UMA@ 150_0603_1% G32 T38 PEG_TXP1 C233 VGA@ 0.1U_0402_16V4Z PEG_M_TXP1
CRT_G CRT_G CRT_BLUE# PEG_TX_1 PEG_TXP2 C258 VGA@ 0.1U_0402_16V4Z PEG_M_TXP2
2 1 17 CRT_G K29 CRT_GREEN PEG_TX_2 T46
R419 UMA@ 150_0603_1% J29 N50 PEG_TXP3 C217 VGA@ 0.1U_0402_16V4Z PEG_M_TXP3
CRT_B CRT_R CRT_GREEN# PEG_TX_3 PEG_TXP4 C278 VGA@ 0.1U_0402_16V4Z PEG_M_TXP4
2 1 17 CRT_R F29 CRT_RED PEG_TX_4 R51
VGA
R418 UMA@ 150_0603_1% E29 U43 PEG_TXP5 C235 VGA@ 0.1U_0402_16V4Z PEG_M_TXP5 R32 @ 4.02K_0402_1%
CRT_RED# PEG_TX_5 PEG_TXP6 C263 VGA@ 0.1U_0402_16V4Z PEG_M_TXP6
PEG_TX_6 W42 7 CFG5 1 2
B PEG_TXP7 C219 VGA@ 0.1U_0402_16V4Z PEG_M_TXP7 B
PEG_TX_7 Y47
3VDDCCL K33 Y39 PEG_TXP8 C281 VGA@ 0.1U_0402_16V4Z PEG_M_TXP8 R33 @ 4.02K_0402_1%
17 3VDDCCL CRT_DDC_CLK PEG_TX_8
3VDDCDA G35 AC38 PEG_TXP9 C241 VGA@ 0.1U_0402_16V4Z PEG_M_TXP9 1 2
17 3VDDCDA CRT_DDC_DATA PEG_TX_9 7 CFG7
17 CRT_HSYNC CRT_HSYNC 1 2 HSYNC_R F33 AD47 PEG_TXP10 C256 VGA@ 0.1U_0402_16V4Z PEG_M_TXP10
R424 39_0402_1% CRT_HSYNC PEG_TX_10 PEG_TXP11 C222 VGA@ 0.1U_0402_16V4Z PEG_M_TXP11 R26 @ 4.02K_0402_1%
C32 CRT_TVO_IREF PEG_TX_11 AC50
17 CRT_VSYNC CRT_VSYNC 1 2 VSYNC_R E33 AD43 PEG_TXP12 C283 VGA@ 0.1U_0402_16V4Z PEG_M_TXP12 1 2
CRT_VSYNC PEG_TX_12 7 CFG8
R422 39_0402_1% AG39 PEG_TXP13 C243 VGA@ 0.1U_0402_16V4Z PEG_M_TXP13
PEG_TX_13
1
R29 @ 4.02K_0402_1%
7 CFG13 1 2
R27 @ 4.02K_0402_1%
For Crestline:1.3kohm 7 CFG16 1 2
For Calero: 255ohm
+3VS
R55 @ 4.02K_0402_1%
7 CFG19 1 2
R58 @ 4.02K_0402_1%
A A
7 CFG20 1 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE((3/6)-VGA/LVDS/TV
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 9 of 47
5 4 3 2 1
5 4 3 2 1
+3VS VCCSYNC
+3VS +3VS_DAC_BG R51
2 1
1R39 2 0_0603_5%
0.022U_0402_16V7K
0.1U_0402_16V4Z
0_0603_5% 1
+1.25VS_DPLLB +1.25VS
0.1U_0402_16V4Z
4.7U_0805_10V4Z
UMA@ C94 +V1.25VS_AXF
+VCCP R433
1 1 1
1 2 +1.25VS 1 2
2
C92
C96
C97
0.1U_0402_16V4Z
10U_0805_10V4Z
1U_0603_10V4Z
UMA@ UMA@ U22H
10U_0805_10V4Z
10U_FLC-453232-100K_0.25A_10% R24
2 2 2 330U_D2E_2.5VM_R7 0_0603_5%
J32 VCCSYNC VTT_1 U13 1 1 1 1
4.7U_0805_10V4Z
C164
C36
C38
VTT_2 U12
C534
A33 VCCA_CRT_DAC_1 VTT_3 U11 1 1
+3VS_DAC_CRT B33 VCCA_CRT_DAC_2 VTT_4 U9
2 2 2 2
C24
U8 C198 +
VTT_5
CRT
U7 0316 add
VTT_6 2
D
+3VS_DAC_CRT +3VS_DAC_BG A30 VCCA_DAC_BG VTT_7 U5 D
+3VS U3 2
R54 VTT_8 0316 add
B32 VSSA_DAC_BG VTT_9 U2
1 2 VTT_10 U1
0.022U_0402_16V7K
0_0603_5% T13
VTT_11 +1.25VS_DMI +1.8V_SM_CK
0.1U_0402_16V4Z
VTT
UMA@ +1.25VS_DPLLA B49 T11 +1.25VS +1.8V
VCCA_DPLLA VTT_12
0.47U_0603_10V7K
4.7U_0805_10V4Z
2.2U_0805_16V4Z
1 1 T10 R28
VTT_13
+1.25VS_DPLLB H49 VCCA_DPLLB VTT_14 T9 1 1 1 1 2 1 2
C117
C116
22U_0805_6.3V4Z
22U_0805_6.3V4Z
0.1U_0402_16V4Z
UMA@ UMA@ T7 0_0805_5%
VTT_15
C135
C129
C138
PLL
0.1U_0402_16V4Z
+1.25VS_HPLL AL2 T6 R73 1 1
2 2 VCCA_HPLL VTT_16 0_0603_5%
VTT_17 T5 1
2 2 2
C47
C49
C43
+1.25VS_MPLL AM2 VCCA_MPLL VTT_18 T3 1
C166
VTT_19 T2
2 2
VTT_20 R3
2
A LVDS
+1.8V_TXLVDS 1000P_0402_50V7K A41 R2
VCCA_LVDS VTT_21 2
1 VTT_22 R1
C154 +1.25VS_AXD
B41 VSSA_LVDS R34
+3VS_PEG_BG
VCC_AXD_1 AT23 1 2 +1.25VS
R72 2 0_0805_5%
VCC_AXD_2 AU28
1U_0603_10V4Z
10U_0805_10V6K
+3VS 2 1 K50 VCCA_PEG_BG VCC_AXD_3 AU24 1 1
+1.25VS_PEGPLL
C68
C87
AXD
0_0603_5% AT29 +1.25VS
VCC_AXD_4 L4 +1.5VS_TVDAC +1.5VS
1 K49 VSSA_PEG_BG VCC_AXD_5 AT25
A PEG
0.1U_0402_16V4Z AT30 BLM18PG121SN1D_0603 R41
VCC_AXD_6 2 2
2 1 1 2
0.022U_0402_16V7K
0.1U_0402_16V4Z
C165
2 +1.25VS_PEGPLL 20 mils U51 VCCA_PEG_PLL VCC_AXD_NCTF AR29 0_0805_5%
0.1U_0402_16V4Z
10U_0805_10V4Z
1 1 1 1
C168
C162
AW18 VCCA_SM_1 VCC_AXF_1 B23 +V1.25VS_AXF
C78
C79
AV19 B21
VCCA_SM_2
POWER VCC_AXF_2
AXF
AU19 VCCA_SM_3 VCC_AXF_3 A21
AU18 2 2 2 2
+1.25VS_A_SM VCCA_SM_4
AU17 VCCA_SM_5 VCC_DMI AJ50 +1.25VS_DMI
R21 0317 change value
A SM
C +1.25VS 1 2 AT22 VCCA_SM_7 C
1 0_0805_5% AT21 BK24 +1.8V_SM_CK
VCCA_SM_8 VCC_SM_CK_1
SM CK
1 1 1 AT19 VCCA_SM_9 VCC_SM_CK_2 BK23
C8 + C28 C29 C34 AT18 BJ24
VCCA_SM_10 VCC_SM_CK_3
AT17 VCCA_SM_11 VCC_SM_CK_4 BJ23
150U_D_6.3VM 22U_0805_6.3V4Z 4.7U_0805_6.3V6K AR17 +1.25VS_HPLL
2 2 2 2 VCCA_SM_NCTF_1 +1.25VS_DPLLA R398 +1.25VS
AR16 VCCA_SM_NCTF_2 R431
1U_0603_10V4Z
R37 +1.25VS_A_SM_CK
VCC_TX_LVDS A43 +1.8V_TXLVDS 1 2 +1.25VS 2 1
0.1U_0402_16V4Z
10U_0805_10V6K
A CK
2 1 BC29 MBK2012121YZF_0805
VCCA_SM_CK_1 +3VS_HV
1U_0402_6.3V4Z
22U_0805_6.3V4Z
1U_0603_10V4Z
0.1U_0402_16V4Z
C163
C533
1 1 1 1 +3VS_TVDACA C25 B40 C13 C525
VCCA_TVA_DAC_1 VCC_HV_2
C75
C55
C77
C82
HV
B25 VCCA_TVA_DAC_2
0.1U_0402_16V4Z
+3VS_TVDACB C27 0.1U_0402_16V4Z 10U_0805_10V4Z
VCCA_TVB_DAC_1 2 2 2 2
B27 VCCA_TVB_DAC_2 VCC_PEG_1 AD51 +VCC_PEG 1
2 2 2 2
TV
C139
0316 add B28 W50
+3VS_TVDACC VCCA_TVC_DAC_1 VCC_PEG_2
PEG
A28 W51 0316 add
VCCA_TVC_DAC_2 VCC_PEG_3
VCC_PEG_4 V49
0317 change value 2
VCC_PEG_5 V50
D TV/CRT
M32 VCCD_CRT
+1.5VS_TVDAC L29 VCCD_TVDAC
VCC_RXR_DMI_1 AH50 +VCCP +1.25VS_MPLL
DMI
10U_0805_10V4Z
VTTLF3 AH1 1 1
220U_D2_4VM
220U_D2_4VM
J41 VCCD_LVDS_1 0.47U_0603_10V7K 1 +1.25VS 1 1
0.47U_0603_10V7K
0.47U_0603_10V7K
C199
C181
C179
LVDS
C12
C21
2 1 0.1U_0402_16V4Z 10U_0805_10V4Z
2 2 2 0_0805_5% 2 2
+3VS_TVDACC +3VS CRESTLINE_1p0
B
R49 2 2 2 0316 add 04/10 no stuff B
2 1
0.022U_0402_16V7K
0_0603_5%
0.1U_0402_16V4Z
UMA@
1 1
C76
C64
+VCCP_D
2 2
2 1 0_0603_5%
0.022U_0402_16V7K
0.1U_0402_16V4Z
0_0603_5% UMA@
+1.8V_TXLVDS
0.1U_0402_16V4Z
UMA@ 1 1 40 mils
1 1 R74
C58
C46
C54
1000P_0402_50V7K 2 1 +1.8V
2 2 0_0603_5%
2 2 UMA@
1
1 220U_D2_4VM_R15
UMA@ UMA@ C158 + C156
UMA@ UMA@ UMA@ UMA@ PM 0_0402_5% 0_0402_5% 0_0402_5% 0_0603_5%
VGA@ VGA@ VGA@ VGA@ VGA@
2 2 C54 C65 C96 C117
+1.8V_LVDS
A +3VS_TVDACB +3VS A
R36 R69
2 1 2 1 +1.8V 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%
0.022U_0402_16V7K
10U_0805_10V6K
1U_0603_10V4Z
UMA@ 1 1 UMA@
C155
C152
1 1
C66
C65
2 2
2 2
UMA@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title
UMA@
UMA@ UMA@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE(4/6)-PWR
Size Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 10 of 47
5 4 3 2 1
5 4 3 2 1
+VCCP
U22G +VCCGFX
C33
AJ31 T23 C39
+VCCP VCC_7 VCC_AXG_NCTF_6
AJ28 VCC_8 VCC_AXG_NCTF_7 T25
D U22F D
AH32 VCC_9 VCC_AXG_NCTF_8 U15
2 2 2
VCC CORE
AH31 VCC_10 VCC_AXG_NCTF_9 U16
AB33 VCC_NCTF_1 AH29 VCC_11 VCC_AXG_NCTF_10 U17
AB36 AF32 U19 0.22U_0402_10V4Z
VCC_NCTF_2 VCC_12 VCC_AXG_NCTF_11
AB37 VCC_NCTF_3 VCC_AXG_NCTF_12 U20
AC33 VCC_NCTF_4 VSS_NCTF_1 T27 VCC_AXG_NCTF_13 U21
AC35 T37 R53 U23
VCC_NCTF_5 VSS_NCTF_2 VCC_AXG_NCTF_14
AC36 VCC_NCTF_6 VSS_NCTF_3 U24 1 2 R30 VCC_13 VCC_AXG_NCTF_15 U26
AD35 U28 0_0603_5% V16
VCC_NCTF_7 VSS_NCTF_4 VCC_AXG_NCTF_16
AD36 VCC_NCTF_8 VSS_NCTF_5 V31 VCC_AXG_NCTF_17 V17
AF33 VCC_NCTF_9 VSS_NCTF_6 V35 VCC_AXG_NCTF_18 V19
AF36 VCC_NCTF_10 VSS_NCTF_7 AA19 VCC_AXG_NCTF_19 V20
220U_D2_4VM_R15
22U_0805_6.3V4Z
0.22U_0402_10V4Z
0.22U_0402_10V4Z
0.1U_0402_16V4Z
VSS NCTF
1 AH35 VCC_NCTF_12 VSS_NCTF_9 AB35 VCC_AXG_NCTF_21 V23
1 1 1 1 AH36 VCC_NCTF_13 VSS_NCTF_10 AD19 VCC_AXG_NCTF_22 V24
C211
C151
C111
C16
C17
2 2 2 2 2
AJ33
AJ35
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
AF17
AF35
POWER VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
Y16
Y17
AK33 VCC_NCTF_17 VSS_NCTF_14 AK17 AU32 VCC_SM_1 VCC_AXG_NCTF_26 Y19
AK35 AM17 330U_D2E_2.5VM_R7 AU33 Y20
VCC_NCTF_18 VSS_NCTF_15 VCC_SM_2 VCC_AXG_NCTF_27
AK36 VCC_NCTF_19 VSS_NCTF_16 AM24 +1.8V AU35 VCC_SM_3 VCC_AXG_NCTF_28 Y21
AK37 VCC_NCTF_20 VSS_NCTF_17 AP26 AV33 VCC_SM_4 VCC_AXG_NCTF_29 Y23
0.01U_0402_16V7K
AD33 VCC_NCTF_21 VSS_NCTF_18 AP28 AW33 VCC_SM_5 VCC_AXG_NCTF_30 Y24
22U_0805_6.3V4Z
22U_0805_6.3V4Z
AJ36 VCC_NCTF_22 VSS_NCTF_19 AR15 1 AW35 VCC_SM_6 VCC_AXG_NCTF_31 Y26
VCC NCTF
AM35 VCC_NCTF_23 VSS_NCTF_20 AR19 1 1 2 AY35 VCC_SM_7 VCC_AXG_NCTF_32 Y28
C114
C143
C99
AL33 AR28 C125 + BA32 Y29
VCC_NCTF_24 VSS_NCTF_21 VCC_SM_8 VCC_AXG_NCTF_33
AL35 VCC_NCTF_25 BA33 VCC_SM_9 VCC_AXG_NCTF_34 AA16
AA33 VCC_NCTF_26 BA35 VCC_SM_10 VCC_AXG_NCTF_35 AA17
2 2 2 1
AA35 VCC_NCTF_27 BB33 VCC_SM_11 VCC_AXG_NCTF_36 AB16
AA36 VCC_NCTF_28 BC32 VCC_SM_12 VCC_AXG_NCTF_37 AB19
AP35 VCC_NCTF_29 BC33 VCC_SM_13 VCC_AXG_NCTF_38 AC16
AP36 VCC_NCTF_30 BC35 VCC_SM_14 VCC_AXG_NCTF_39 AC17
VCC SM
C C
AR35 VCC_NCTF_31 BD32 VCC_SM_15 VCC_AXG_NCTF_40 AC19
AR36 VCC_NCTF_32 BD35 VCC_SM_16 VCC_AXG_NCTF_41 AD15
Y32 VCC_NCTF_33 BE32 VCC_SM_17 VCC_AXG_NCTF_42 AD16
Y33 BE33 AD17
VCC_NCTF_34
POWER VCC_SM_18 VCC_AXG_NCTF_43
10U_0805_10V4Z
C45
VCC GFX
AL29 VCC_AXM_NCTF_14 AC21 VCC_AXG_14 VCC_AXG_NCTF_79 AR26
AL31 330U_D2E_2.5VM_R7 10U_0805_10V4Z AC23 V26
VCC_AXM_NCTF_15 VCC_AXG_15 VCC_AXG_NCTF_80
AL32 VCC_AXM_NCTF_16 AC24 VCC_AXG_16 VCC_AXG_NCTF_81 V28
AR31 VCC_AXM_NCTF_17 AC26 VCC_AXG_17 VCC_AXG_NCTF_82 V29
AR32 VCC_AXM_NCTF_18 AC28 VCC_AXG_18 VCC_AXG_NCTF_83 Y31
0.22U_0402_10V4Z
0.22U_0402_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C53
C86
C52
AD23 VCC_AXG_21
AD24 VCC_AXG_22 VCC_SM_LF1 AW45 VCCSM_LF1
AD28 VCC_AXG_23 VCC_SM_LF2 BC39 VCCSM_LF2
2 2 2 2 2
VCC SM LF
CRESTLINE_1p0 AF21 BE39 VCCSM_LF3
VCC_AXG_24 VCC_SM_LF3
AF26 VCC_AXG_25 VCC_SM_LF4 BD17 VCCSM_LF4
AA31 VCC_AXG_26 VCC_SM_LF5 BD4 VCCSM_LF5
AH20 VCC_AXG_27 VCC_SM_LF6 AW8 VCCSM_LF6
AH21 VCC_AXG_28 VCC_SM_LF7 AT6 VCCSM_LF7
C133 0.47U_0402_6.3V6K
C145 1U_0603_10V4Z
C159 1U_0603_10V4Z
C19
C22
C18
C35
AH23 VCC_AXG_29 1 1 1 1 1 1 1
AH24 VCC_AXG_30
AH26 VCC_AXG_31
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.22U_0603_10V7K
0.22U_0603_10V7K
AD31 VCC_AXG_32 2 2 2 2 2 2 2
AJ20 VCC_AXG_33
AN14 VCC_AXG_34
A A
CRESTLINE_1p0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE((5/6)-PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 11 of 47
5 4 3 2 1
5 4 3 2 1
U22I
CRESTLINE_1p0
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE((6/6)-PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 12 of 47
5 4 3 2 1
5 4 3 2 1
2.2U_0805_16V4Z
0.1U_0402_16V4Z
1 VREF VSS 2
3 4 DDR_A_D6 1 1
8 DDR_A_DM[0..7] +1.8V VSS DQ4
C253
C251
DDR_A_D4 5 6 DDR_A_D0
DDR_A_D1 DQ0 DQ5
8 DDR_A_DQS[0..7] 7 DQ1 VSS 8
9 10 DDR_A_DM0
VSS DM0
1
DDR_A_DQS#0 2 2
8 DDR_A_MA[0..13] 11 DQS0# VSS 12
R113 DDR_A_DQS0 13 14 DDR_A_D5
DQS0 DQ6 DDR_A_D7
15 VSS DQ7 16
100_0402_1% DDR_A_D2 17 18
D DDR_A_D3 DQ2 VSS DDR_A_D13 D
19 20
2
+DDR_MCH_REF1 DQ3 DQ12 DDR_A_D12
14 +DDR_MCH_REF1 21 VSS DQ13 22
0.1U_0402_16V4Z
DDR_A_D8 23 24
DQ8 VSS
1
Layout Note: DDR_A_D14 25 26 DDR_A_DM1
R112 DQ9 DM1
1 27 VSS VSS 28
Place near JP41 DDR_A_DQS#1 29 30 M_CLK_DDR0
M_CLK_DDR0 7
DQS1# CK0
C254
100_0402_1% DDR_A_DQS1 31 32 M_CLK_DDR#0
DQS1 CK0# M_CLK_DDR#0 7
33 34
2
2 DDR_A_D9 VSS VSS DDR_A_D11
35 DQ10 DQ14 36
DDR_A_D15 37 38 DDR_A_D10
DQ11 DQ15
39 VSS VSS 40
+1.8V 41 42
DDR_A_D16 VSS VSS DDR_A_D20
43 DQ16 DQ20 44
DDR_A_D17 45 46 DDR_A_D21
DQ17 DQ21
47 VSS VSS 48
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 DDR_A_DQS#2 49 50
DQS2# NC PM_EXTTS#0 7
1 1 1 1 1 1 1 1 1 DDR_A_DQS2 51 52 DDR_A_DM2
DQS2 DM2
C148
C144
C153
C146
C141
C42
C41
C98
C67
+ C25 53 54
470U_D2_2.5VM_R15 DDR_A_D18 VSS VSS DDR_A_D23
55 DQ18 DQ22 56
DDR_A_D19 57 58 DDR_A_D22
2 2 2 2 2 2 2 2 2 2 DQ19 DQ23
59 VSS VSS 60
DDR_A_D29 61 62 DDR_A_D28
DDR_A_D24 DQ24 DQ28 DDR_A_D25
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
14,33 EC_TX_P80_DATA 69 NC DQS3 70
71 VSS VSS 72
DDR_A_D26 73 74 DDR_A_D31
DDR_A_D27 DQ26 DQ30 DDR_A_D30
75 DQ27 DQ31 76
77 VSS VSS 78
C DDR_CKE0_DIMMA DDR_CKE1_DIMMA C
7 DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA 7
81 VDD VDD 82
14,33 EC_RX_P80_CLK 83 NC NC/A15 84
DDR_A_BS#2 85 86 DDR_A_MA14
8 DDR_A_BS#2 BA2 NC/A14 DDR_A_MA14 7
Layout Note: DDR_A_MA12
87 VDD VDD 88
DDR_A_MA11
89 A12 A11 90
Place one cap close to every 2 pullup DDR_A_MA9 91 92 DDR_A_MA7
DDR_A_MA8 A9 A7 DDR_A_MA6
resistors terminated to +0.9VS 93 A8 A6 94
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS#1
A10/AP BA1 DDR_A_BS#1 8
DDR_A_BS#0 107 108 DDR_A_RAS#
8 DDR_A_BS#0 BA0 RAS# DDR_A_RAS# 8
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
+0.9VS 8 DDR_A_WE# WE# S0# DDR_CS0_DIMMA# 7
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0
8 DDR_A_CAS# CAS# ODT0 M_ODT0 7
DDR_CS1_DIMMA# 115 116 DDR_A_MA13
7 DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C119
C112
C134
C115
C132
C123
C85
C59
C71
C93
C74
C63
1
10K_0402_5%
10K_0402_5%
DDR_A_MA8 1 8 8 1 DDR_CKE1_DIMMA 1
C6 FOX_ASOA426-M2RN-7F
R14
R13
A 56_0804_8P4R_5% 56_0804_8P4R_5% A
ME@
0.1U_0402_16V4Z
RP11 2
SO-DIMM A
2
DDR_A_MA9 4 5
DDR_A_MA12 3 6
DDR_A_BS#2 2 7
DDR_CKE0_DIMMA 1 8 Top side
56_0804_8P4R_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 13 of 47
5 4 3 2 1
5 4 3 2 1
+1.8V +1.8V
8 DDR_B_DQS#[0..7]
8 DDR_B_D[0..63]
+DDR_MCH_REF1
+DDR_MCH_REF1 13
8 DDR_B_DM[0..7] JP4
2.2U_0805_16V4Z
0.1U_0402_16V4Z
8 DDR_B_DQS[0..7] 1 VREF VSS 2
3 4 DDR_B_D4 1 1
DDR_B_D0 VSS DQ4 DDR_B_D5
8 DDR_B_MA[0..13] 5 DQ0 DQ5 6
C255
C249
DDR_B_D1 7 8
DQ1 VSS DDR_B_DM0
9 VSS DM0 10
DDR_B_DQS#0 2 2
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D7
15 VSS DQ7 16
D DDR_B_D2 D
17 DQ2 VSS 18
Layout Note: DDR_B_D3 19 20 DDR_B_D12
DQ3 DQ12 DDR_B_D13
21 VSS DQ13 22
Place near JP42 DDR_B_D8 23 24
DDR_B_D9 DQ8 VSS DDR_B_DM1
25 DQ9 DM1 26
27 VSS VSS 28
DDR_B_DQS#1 29 30 M_CLK_DDR3
DQS1# CK0 M_CLK_DDR3 7
DDR_B_DQS1 31 32 M_CLK_DDR#3
DQS1 CK0# M_CLK_DDR#3 7
33 VSS VSS 34
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 DQ11 DQ15 38
+1.8V 39 40
VSS VSS
41 VSS VSS 42
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 DDR_B_D17 43 44 DDR_B_D21
DDR_B_D20 DQ16 DQ20 DDR_B_D16
1 1 1 1 1 1 1 1 1 45 DQ17 DQ21 46
C44
C32
C149
C157
C31
C121
C128
C147
C57
+ C81 47 48
470U_D2_2.5VM_R15 DDR_B_DQS#2 VSS VSS
49 DQS2# NC 50 PM_EXTTS#1 7
DDR_B_DQS2 51 52 DDR_B_DM2
2 2 2 2 2 2 2 2 2 2 DQS2 DM2
53 VSS VSS 54
DDR_B_D18 55 56 DDR_B_D22
DDR_B_D19 DQ18 DQ22 DDR_B_D23
57 DQ19 DQ23 58
59 VSS VSS 60
DDR_B_D25 61 62 DDR_B_D26
DDR_B_D28 DQ24 DQ28 DDR_B_D24
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
13,33 EC_TX_P80_DATA 69 NC DQS3 70
71 VSS VSS 72
DDR_B_D30 73 74 DDR_B_D29
DDR_B_D31 DQ26 DQ30 DDR_B_D27
75 DQ27 DQ31 76
C C
77 VSS VSS 78
DDR_CKE2_DIMMB 79 80 DDR_CKE3_DIMMB
7 DDR_CKE2_DIMMB CKE0 NC/CKE1 DDR_CKE3_DIMMB 7
81 VDD VDD 82
Layout Note: 13,33 EC_RX_P80_CLK
DDR_B_BS#2
83 NC NC/A15 84
DDR_B_MA14
8 DDR_B_BS#2 85 BA2 NC/A14 86 DDR_B_MA14 7
Place one cap close to every 2 pullup 87 88
DDR_B_MA12 VDD VDD DDR_B_MA11
resistors terminated to +0.9VS 89 A12 A11 90
DDR_B_MA9 91 92 DDR_B_MA7
DDR_B_MA8 A9 A7 DDR_B_MA6
93 A8 A6 94
95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
DDR_B_MA1 101 102 DDR_B_MA0
A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS#1
+0.9VS A10/AP BA1 DDR_B_BS#1 8
DDR_B_BS#0 107 108 DDR_B_RAS#
8 DDR_B_BS#0 BA0 RAS# DDR_B_RAS# 8
DDR_B_WE# 109 110 DDR_CS2_DIMMB#
8 DDR_B_WE# WE# S0# DDR_CS2_DIMMB# 7
111 VDD VDD 112
DDR_B_CAS# 113 114 M_ODT2
8 DDR_B_CAS# CAS# ODT0 M_ODT2 7
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C136
C131
C137
C113
C142
C118
C61
C72
C95
C89
C69
C62
1
10K_0402_5%
DDR_B_MA3 6 3 3 6 DDR_B_MA11 1 10K_0402_5%
R396
A DDR_B_MA5 DDR_B_MA6 C7 FOX_AS0A426-MARG-7F A
7 2 2 7
DDR_B_MA9 8 1 1 8 DDR_CKE3_DIMMB
0.1U_0402_16V4Z
56_0804_8P4R_5% 56_0804_8P4R_5% 2 SO-DIMM B
2
RP13
DDR_CKE2_DIMMB 8 1
DDR_B_BS#2 7 2
DDR_B_MA12
DDR_B_MA8
6 3
Security Classification Compal Secret Data Compal Electronics, Inc.
5 4 Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title
56_0804_8P4R_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 14 of 47
5 4 3 2 1
5 4 3 2 1
+3VS_CK505
FSLC FSLB FSLA CPU SRC PCI
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz +3VS 1
R149
2
0_1206_5% 1 1 1 1 1 1 1
C329 C331 C335 C333 C342 C344 C343
0 1 0 200 100 33.3
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS
2 2 2 2 2 2 2
0 1 1 166 100 33.3
R165 R152
+1.25VS_CK505
FSB Frequency Selet: 2.2K_0402_5% 2.2K_0402_5%
+1.25VS 1 2 Q12
D R125 0_1206_5% 2N7002_SOT23 D
CPU Driven Stuff R919 R940 R956 1 1 1 1 1 1
C319 C332 C341 C326 C334 C339 CLK_SMBDATA
S
21,26,27 ICH_SMBDATA 1 3
R914 R921 R930 R943 R949 R954 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
*(Default) No Stuff 2 2 2 2 2 2
G
2
Stuff R959 R930 R914 +3VS
2
G
667MHz
No Stuff R919 R940 R956
21,26,27 ICH_SMBCLK 1 3 CLK_SMBCLK
R949 R943 R921
S
2N7002_SOT23
Stuff Q9
R959 R930 R921
+3VS_CK505 U3
800MHz
No Stuff R919 R940 R956 2 VDD_PCI NC 48
9 VDD48
R949 R943 R914 16 VDDPLL3
61 VDDREF
64 CLK_SMBCLK
+VCCP SCLK CLK_SMBDATA CLK_SMBCLK 13,14
39 VDDSRC SDATA 63
55 CLK_SMBDATA 13,14
VDDCPU
2
PCI_STOP# 38
@ R472 37 H_STP_PCI# 21
56_0402_5% CPU_STOP# H_STP_CPU# 21
+1.25VS_CK505 12 VDD96_IO
R467 20
2.2K_0402_5% VDDPLL3_IO R179
26
1
51 R_MCH_BCLK 1 2 0_0402_5%
CPU1_F CLK_MCH_BCLK 7
R469 50 R_MCH_BCLK# 1 2 0_0402_5%
CPU1#_F CLK_MCH_BCLK# 7
R181
@ 1K_0402_5% R177
47 R_CPU_XDP 1 2 0_0402_5%
CLK_PCIE_MCARD1 27
2
CLK_XTAL_IN 60 R143
R481 X1
@ 0_0402_5% CLK_XTAL_OUT 59 1 2 +3VS
X2 R185 @ 10K_0402_5%
SRC7/CR#_F 44
43 CLKREQ_LAN#R 2 1 475_0402_1%
CLKREQ_LAN# 24
2
SRC7#/CR#_E R184
1 2
R515 10K_0402_5%
R175
B +VCCP 41 R_PCIE_LAN 1 2 0_0402_5% B
SRC6 CLK_PCIE_LAN 24
33_0402_5% 1 2 R137 FSA 10 40 R_PCIE_LAN# 1 2 0_0402_5%
21 CLK_48M_ICH USB_48MHZ/FSLA SRC6# CLK_PCIE_LAN# 24
R174
2
A @ 58 2 1 CK_PWRGD 21 A
VGA@ GNDREF +3VS_CK505
Y1 R487 @ 10K_0402_5%
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Routing the trace at least 10mil AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 15 of 47
5 4 3 2 1
A B C D E F G H
+LCDVDD
1 1
2
R886 +3VS
+LCDVDD 0_0805_5%
Q3
S
1 3
R446 AO3413_SOT23
100_0402_1% +5VALW UMA@
UMA@ 1 1 1
G
2
C212 C213 C232
1+LCDVDD_R 2
2
0.1U_0402_16V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z
R452 UMA@ UMA@ UMA@
100K_0402_5% 2 2 2
UMA@
1
D UMA@
2N7002_SOT23 2 1 2
Q27 G R849 10K_0402_5%
UMA@ S 1
3
C215
0.047U_0402_16V4Z
1
UMA@
Q28 2
DTC124EK_SC59
UMA@
9 GMCH_LVDDEN 2 R437 1 2
UMA@ 0_0402_5%
2
2 R434 2
3
100K_0402_5%
UMA@
1
0.1U_0603_50V4Z
B+ INVPWR_B+ +3VS
C526
L14 1 2 0_0805_5% 2 1
2
R116
@ L13 1 2 0_0805_5% 2 1
C527 4.7K_0402_5%
68P_0402_50V8K D2
1
CH751H-40_SC76
JP40 1 2 DISPOFF#
33 BKOFF#
1
2 33 ENBKL
D3
33 INVT_PWM 3
DISPOFF# @ CH751H-40_SC76
4
33 DAC_BRIG 5 9 GMCH_ENBKL 2 R117 1 1 2
3 UMA@ 0_0402_5% 3
INVPWR_B+ 6
7
2
MOLEX_53780-0790 18 G7X_ENBKL 2 R118 1 R669 R119
VGA@ 0_0402_5% 2.2K_0402_5% 100K_0402_5%
VGA@ UMA@
1
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 16 of 47
A B C D E F G H
A B C D E
TV-OUT Conn.
L52
18 CARD_LUMA 2 1 1 2 LUMA
R88 VGA@ 0_0402_5% FLM1608081R8K_0603
L53
2 1 1 2
18 CARD_CRMA
R86 VGA@ 0_0402_5% FLM1608081R8K_0603
L54
@
CRMA
VGA I/O PORT Connector
18 CARD_COMP 2 1 1 2 COMP
R98 @ 0_0402_5% FLM1608081R8K_0603
1
150_0402_1%
150_0402_1%
150_0402_1%
82P_0402_50V8J
82P_0402_50V8J
82P_0402_50V8J
82P_0402_50V8J
82P_0402_50V8J
82P_0402_50V8J
R6
R5
R7
2 1 1 1 1
1 9 TV_LUMA
R455 UMA@ 0_0402_5% @ 1 1 1 S-VIDEO 1
C845
C846
C847
2 1 @
9 TV_CRMA
C848
C849
C850
R454 UMA@ 0_0402_5% @
2
2 2 2 JP71
9 TV_COMPS 2 1
R456 @ 0_0402_5% 2 2 2
1 1 G1 7
CRMA 2 2
3 3
Pop when with internal graphics LUMA 4 4
5 5
COMP 6 8
6 G2
CRT Conn. MOLEX_53780-0670
ME@
L55
VGA@ BK1608LL121-T 0603
2 1 R 1 2
18 CARD_VGA_R RED
R82 0_0402_5% L56
VGA@ BK1608LL121-T 0603
2 1 G 1 2
18 CARD_VGA_G GREEN
R83 0_0402_5% L57
VGA@ BK1608LL121-T 0603
2 1 B 1 2
18 CARD_VGA_B BLUE
R84 0_0402_5% +CRT_VCC
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
1 1 1 1 1 1
DSUB
1
1
150_0402_1%
150_0402_1%
150_0402_1%
C851
C852
C853
R2
R3
R4
C3
C1
C2
UMA@ JP72
2 2 2 2 2 2
9 CRT_R 2 1 1 1
R447 0_0402_5% @ @ @ +5VS +CRT_VCC RED 2
2
UMA@ 2
3 3
2 1 D31 GREEN 4
9 CRT_G 4
2
2 R451 0_0402_5% 2
5 5
UMA@ BLUE 6 6
9 CRT_B 2 1 7 7 15 15
R453 0_0402_5% JVGA_VS 8 16
RB751V_SOD323 8 16
9
1
JVGA_HS 9
Pop when with internal graphics 10 10
11 11
VGA_DDC_DAT 12
VGA_DDC_CLK 12
MSEMS# 13 13
1 14 14
PIN4
C800 1 ACES_87213-1400
0.01U_0402_25V4Z C801 ME@
+CRT_VCC +CRT_VCC 2
2 0.1U_0402_16V4Z
+3VS +3VS
2
2.2K_0402_5%
2.2K_0402_5%
PIN ASSIGMENT
R850
R851
1
1
R12 R8
2.2K_0402_5% 2.2K_0402_5% PIN D-SUB FUNCTION PIN SVIDEO FUNCTION
2
G
Q2
1 9 +CRT_VCC 1 1 NC
2
2 VGA@1 3 1 2N7002_SOT23
18 CARD_DDCDATA VGA_DDC_DAT
R77 10_0402_5%
S
18 CARD_DDCCLK 2
2
G
3 UMA@ 3
Q1
1 2N7002_SOT23
2 1 RED 2 4 CRMA 3
DDCDA VGA_DDC_CLK
S
1 2
9 3VDDCDA
R441
UMA@
0_0402_5% 3 6 GND 3 2 GND
1 2 DDC CL +CRT_VCC +CRT_VCC +CRT_VCC
9 3VDDCCL
R444 0_0402_5% 4 2 GREEN 4 3 LUMA
5 7 GND 5 5 GND
1
1
1
1K_0402_5%
1K_0402_5%
0.1U_0402_16V4Z R1
1K_0402_5% R852
6 3 BLUE 6 6 CVBS
R853
C4
2
2
2
5
U1
VGA@ L58 CHB1608B121_0603 7 8 GND
P
OE#
2 1 HSYNC 2 4 1 2
18 CARD_HSYNC A Y JVGA_HS
R78 0_0402_5%
8 14 VSYNC
G
VGA@
2 1 VSYNC +CRT_VCC 74AHCT1G125GW_SOT353-5
18 CARD_VSYNC
3
R81 0_0402_5%
9 10 GND
0.1U_0402_16V4Z
1
1 UMA@ 2
9 CRT_HSYNC
R439 39_0402_5%
C5
10 13 HSYNC
5
2
1 UMA@ 2 U2
9 CRT_VSYNC
R443 39_0402_5% 11 11 SENSE
P
OE#
2 A Y 4 1 2 JVGA_VS
Pop when with internal graphics
12 12 SM_DAT
G
L59 CHB1608B121_0603
74AHCT1G125GW_SOT353-5
3
4
13 15 SM_CLK 4
14 4 PIN4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT & TVout Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 17 of 47
A B C D E
5 4 3 2 1
D D
MAX. 4.06A @ 1.8V
MAX. 130mA @ 2.5V
MAX. 655mA @ 3.3V
PEG_M_TXP[0..15]
PEG_M_TXP[0..15] 9
PEG_M_TXN[0..15]
PEG_M_TXN[0..15] 9
PEG_RXP[0..15]
PEG_RXP[0:15] 9
JP7 JP8
1 41 1 41 PEG_RXN[0..15]
1 41 1 41 PEG_RXN[0:15] 9
PEG_M_TXP1 2 42 PEG_RXP1 PEG_M_TXP0 2 42 PEG_RXP0
PEG_M_TXN1 2 42 PEG_RXN1 PEG_M_TXN0 2 42 PEG_RXN0
3 3 43 43 3 3 43 43
4 4 44 44 4 4 44 44
PEG_M_TXP3 5 45 PEG_RXP3 PEG_M_TXP2 5 45 PEG_RXP2
PEG_M_TXN3 5 45 PEG_RXN3 PEG_M_TXN2 5 45 PEG_RXN2
6 6 46 46 6 6 46 46
7 7 47 47 7 7 47 47
PEG_M_TXP5 8 48 PEG_RXP5 PEG_M_TXP4 8 48 PEG_RXP4
PEG_M_TXN5 8 48 PEG_RXN5 PEG_M_TXN4 8 48 PEG_RXN4
9 9 49 49 9 9 49 49
10 10 50 50 10 10 50 50
PEG_M_TXP7 11 51 PEG_RXP7 PEG_M_TXP6 11 51 PEG_RXP6
PEG_M_TXN7 11 51 PEG_RXN7 PEG_M_TXN6 11 51 PEG_RXN6
12 12 52 52 12 12 52 52
13 13 53 53 13 13 53 53
C PEG_M_TXP9 PEG_RXP9 PEG_M_TXP8 PEG_RXP8 C
14 14 54 54 14 14 54 54
PEG_M_TXN9 15 55 PEG_RXN9 PEG_M_TXN8 15 55 PEG_RXN8
15 55 15 55
16 16 56 56 16 16 56 56
PEG_M_TXP11 17 57 PEG_RXP11 PEG_M_TXP10 17 57 PEG_RXP10 +5VS +2.5VS
PEG_M_TXN11 17 57 PEG_RXN11 PEG_M_TXN10 17 57 PEG_RXN10
18 18 58 58 18 18 58 58
19 19 59 59 19 19 59 59
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_M_TXP13 20 60 PEG_RXP13 PEG_M_TXP12 20 60 PEG_RXP12
PEG_M_TXN13 20 60 PEG_RXN13 PEG_M_TXN12 20 60 PEG_RXN12
21 21 61 61 21 21 61 61
22 22 62 62 22 22 62 62 2 2 2 2
C252
C248
C228
C216
PEG_M_TXP15 23 63 PEG_RXP15 PEG_M_TXP14 23 63 PEG_RXP14
PEG_M_TXN15 23 63 PEG_RXN15 PEG_M_TXN14 23 63 PEG_RXN14
24 24 64 64 24 24 64 64
25 25 65 65 25 25 65 65
+1.8VS SUSP# 1 1 1 1
+3VS 26 26 66 66 +5VS 15 CLK_PCIE_VGA 26 26 66 66 SUSP# 23,26,28,29,33,35,42,43,44
+1.5VS 27 67 27 67 G7X_THER_ALERT#
27 67 15 CLK_PCIE_VGA# 27 67 VGA_THER_ALERT# 21
28 68 28 68 VGA@ VGA@ VGA@ VGA@
28 68 28 68
29 29 69 69 17 CARD_DDCCLK 29 29 69 69
+2.5VS 30 70 30 70
30 70 17 CARD_DDCDATA 30 70 G7X_ENBKL 16
31 31 71 71 31 31 71 71 PLT_RST# 7,19,21,23,24,26,27
32 32 72 72 17 CARD_VSYNC 32 32 72 72 CLK_27M_VGA 15
33 73 B+ 33 73
33 73 33 73 CLK_27M_VGA# 15
34 34 74 74 17 CARD_HSYNC 34 34 74 74
35 35 75 75 35 35 75 75
36 76 36 76 +3VS
36 76 17 CARD_VGA_R 36 76 CARD_COMP 17
37 37 77 77 37 37 77 77
38 38 78 78 17 CARD_VGA_G 38 38 78 78 CARD_LUMA 17
0.047U_0402_16V4Z
0.047U_0402_16V4Z
39 39 79 79 39 39 79 79
40 40 80 80 17 CARD_VGA_B 40 40 80 80 CARD_CRMA 17
ACES_88363-08001 ACES_88363-08001 1 1
C227
C226
B 2 2 B
VGA@ VGA@
A A
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number
VGA/B connector Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.1
Custom IGT30 LA-3571P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Monday, December 25, 2006 Sheet 18 of 47
5 4 3 2 1
5 4 3 2 1
+3VS
1 2 PCI_DEVSEL# 28 PCI_AD[0..31]
R253 8.2K_0402_5% U28B
1 2 PCI_STOP# PCI_AD0 D20 A4 PCI_REQ0#
AD0 REQ0# PCI_REQ0# 28
R254 8.2K_0402_5% PCI_AD1 PCI_GNT0#
D
1 2 PCI_TRDY# PCI_AD2
E19
D19
AD1 PCI GNT0# D7
E18 PCI_REQ1#
PCI_GNT0# 28 D
R219 8.2K_0402_5% PCI_AD3 AD2 REQ1#/GPIO50 PCI_GNT1#
A20 AD3 GNT1#/GPIO51 C18
1 2 PCI_FRAME# PCI_AD4 D17 B19 PCI_REQ2#
R585 8.2K_0402_5% PCI_AD5 AD4 REQ2#/GPIO52 PCI_GNT2#
A21 AD5 GNT2#/GPIO53 F18
PCI_AD6 A19 A11 PCI_REQ3#
PCI_PLOCK# PCI_AD7 AD6 REQ3#/GPIO54 PCI_GNT3#
1 2 C19 AD7 GNT3#/GPIO55 C10
R536 8.2K_0402_5% PCI_AD8 A18
PCI _IRDY# PCI_AD9 AD8 PCI_CBE#0
1 2 B16 AD9 C/BE0# C17 PCI_CBE#0 28
R216 8.2K_0402_5% PCI_AD10 A12 E15 PCI_CBE#1
AD10 C/BE1# PCI_CBE#1 28
1 2 PCI_SERR# PCI_AD11 E16 F16 PCI_CBE#2
AD11 C/BE2# PCI_CBE#2 28
R233 8.2K_0402_5% PCI_AD12 A14 E17 PCI_CBE#3
AD12 C/BE3# PCI_CBE#3 24,28
1 2 PCI_PERR# PCI_AD13 G16
R539 8.2K_0402_5% PCI_AD14 AD13 PCI _IRDY#
A15 AD14 IRDY# C8 PCI_IRDY# 28
PCI_AD15 B6 D9 PCI_PAR
AD15 PAR PCI_PAR 28
PCI_AD16 C11 G6 PCI_PCIRST#
PCI_AD17 AD16 PCIRST# PCI_DEVSEL#
A9 AD17 DEVSEL# D16 PCI_DEVSEL# 28
PCI_AD18 D11 A7 PCI_PERR#
AD18 PERR# PCI_PERR# 28
PCI_AD19 B12 B7 PCI_PLOCK#
PCI_AD20 AD19 PLOCK# PCI_SERR#
C12 AD20 SERR# F10 PCI_SERR# 28
+3VS PCI_AD21 D10 C16 PCI_STOP#
AD21 STOP# PCI_STOP# 28
PCI_AD22 C7 C9 PCI_TRDY#
AD22 TRDY# PCI_TRDY# 28
PCI_AD23 F13 A17 PCI_FRAME#
AD23 FRAME# PCI_FRAME# 28
1 2 PCI_PIRQA# PCI_AD24 E11
R226 8.2K_0402_5% PCI_AD25 AD24 PCI_PLTRST#
E13 AD25 PLTRST# AG24
1 2 PCI_PIRQB# PCI_AD26 E12 B10 CLK_PCI_ICH
AD26 PCICLK CLK_PCI_ICH 15
R532 8.2K_0402_5% PCI_AD27 D8 G7 PCI_PME#
AD27 PME# PCI_PME# 33
1 2 PCI_PIRQC# PCI_AD28 A6
R199 8.2K_0402_5% PCI_AD29 AD28 @
E8 AD29 1 2 +3VALW
1 2 PCI_PIRQD# PCI_AD30 D6 R195 8.2K_0402_5%
R544 8.2K_0402_5% PCI_AD31 AD30
A3 AD31
1 2 PCI_PIRQE#
R217 8.2K_0402_5%
C
1 2 PCI_PIRQF# PCI_PIRQA# F9
Interrupt I/F F8 PCI_PIRQE# C
R235 8.2K_0402_5% PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF#
B5 PIRQB# PIRQF#/GPIO3 G11
1 2 PCI_PIRQG# PCI_PIRQC# C5 F12 PCI_PIRQG#
PIRQC# PIRQG#/GPIO4 PCI_PIRQG# 28
R244 8.2K_0402_5% PCI_PIRQD# A10 B3 PCI_PIRQH#
PIRQD# PIRQH#/GPIO5 PCI_PIRQH# 28
1 2 PCI_PIRQH#
R524 8.2K_0402_5% ICH8M REV 1.0
1 2 PCI_REQ0#
R528 8.2K_0402_5%
1 2 PCI_REQ1#
R272 8.2K_0402_5%
1 2 PCI_REQ2#
R592 8.2K_0402_5%
1 2 PCI_REQ3#
R549 8.2K_0402_5%
PCI_GNT3#
1
R234
@
1K_0402_5%
Boot BIOS Strap
2
B B
+3V_SB
5
U5
PCI_PCIRST# 1
P
B PCI_RST#
4
0 1 SPI 2 A
Y PCI_RST# 28,32,33
1
A16 swap override Strap @ TC7SH08FU_SSOP5 R188
3
R189
Low= A16 swap override Enble 1 0 PCI 0_0402_5%
100K_0402_5%
2 1
PCI_GNT3# High= Default *
2
1 1 LPC * +3V_SB
5
U11
PCI_GNT0# SB_SPI_CS#1 PCI_PLTRST# 1
P
21 SB_SPI_CS#1 B
4 PLT_RST#
Y PLT_RST# 7,18,21,23,24,26,27
Place closely pin B10 2 A
1
1
R286 @ TC7SH08FU_SSOP5 R283
3
CLK_PCI_ICH R214 @ 1K_0402_5% 100K_0402_5%
@ 1K_0402_5% R289
2
0_0402_5%
2
2
R225 2 1
@ 10_0402_5%
1
A A
1
C383
@ 8.2P_0402_50V
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8(1/4)-PCI/INT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 19 of 47
5 4 3 2 1
5 4 3 2 1
R247
KB_RST# 2 1
1
R287 330K_0402_1% Y3
1 2 LAN100_SLP 2 NC IN 1 R614 +VCCP
32.768KHZ_12.5P_1TJS125BJ2A251 10M_0402_5% R299
R295 1M_0402_5% 3 4 H_FERR# 2 1
NC OUT
1 2 SM_INTRUDER# LPC_AD[0..3] 32,33
2
U28A 56_0402_5%
R319 330K_0402_1% AG25 E5 LPC_AD0 R331 @
RTCX1 FWH0/LAD0
1 2 ICH_INTVRMEN C651 15P_0402_50V8J ICH_RTCX2 AF24 RTCX2 FWH1/LAD1 F5 LPC_AD1 H_DPRSTP# 2 1
G8 LPC_AD2
ICH_RTCRST# FWH2/LAD2 LPC_AD3 56_0402_5%
+RTCVCC 1 2 AF23 RTCRST# FWH3/LAD3 F6
R576 20K_0402_5% R324 @
2
SM_INTRUDER# AD22 C4 LPC_FRAME# H_DPSLP# 2 1
INTRUDER# FWH4/LFRAME# LPC_FRAME# 32,33
2 CLRP1
RTC
LPC
C623 2MM ICH_INTVRMEN AF25 G9 LPC_DRQ0# 56_0402_5%
INTVRMEN LDRQ0# LPC_DRQ#0 32
LAN100_SLP AD21 E6
1U_0603_10V4Z LAN100_SLP LDRQ1#/GPIO23
1 GATEA20
B24 AF13 GATEA20 33
1
GLAN_CLK A20GATE H_A20M#
A20M# AG26 H_A20M# 4
D22 LAN_RSTSYNC
AF26 H_DPRSTP_R# 2 1 H_DPRSTP#
DPRSTP# H_DPRSTP# 5,7,45
C21 AE26 R327 0_0402_5%
LAN_RXD0 DPSLP#
B21 LAN_RXD1 H_DPSLP# 5
C22 AD24 H_FERR#
LAN_RXD2 FERR# H_FERR# 4
LAN / GLAN
D21 AG29 H_PW RGOOD
LAN_TXD0 CPUPWRGD/GPIO49 H_PWRGOOD 5
E20 LAN_TXD1
C20 AF27 H_IGNNE#
LAN_TXD2 IGNNE# H_IGNNE# 4
within 2" from R1557
AH21 AE24 H_INIT#
GLAN_DOCK#/GPIO13 INIT# H_INIT# 4 +VCCP
AC20 H_INTR
INTR H_INTR 4
CPU
C R616 1 GLAN_COMP KB_RST# C
+1.5VS 2 24.9_0402_1% D25 GLAN_COMPI RCIN# AH14 KB_RST# 33
C25 GLAN_COMPO
1
AD23 H_NMI
NMI H_NMI 4
R565 1 2 33_0402_5% HDA_BITCLK_R AJ16 AG28 H_SMI# R328
27 HDA_BITCLK_MDC HDA_BIT_CLK SMI# H_SMI# 4
R556 1 2 33_0402_5% H DA_SYNC_R AJ15
27 HDA_SYNC_MDC HDA_SYNC
AA24 H_STPCLK# 56_0402_5%
STPCLK# H_STPCLK# 4
R552 1 2 33_0402_5% HDA_RST_R# AE14
27 HDA_RST_MDC#
2
HDA_RST# THRMTRIP_ICH# R329 24_0402_1%
THRMTRIP# AE27 1 2 H_THERMTRIP# 4,7
ICH_AC_SDIN0 AJ17
29 HDA_SDIN0 HDA_SDIN0
ICH_AC_SDIN1 AH17 AA23
27 HDA_SDIN1 HDA_SDIN1 TP8 PD_D[0..15] 23
AH15 HDA_SDIN2
IHDA
AD13 V1 PD_D0 placed within 2" from ICH8M
HDA_SDIN3 DD0 PD_D1
DD1 U2
R547 1 2 33_0402_5% HDA_SDOUT_R AE13 V3 PD_D2
27 HDA_SDOUT_MDC HDA_SDOUT DD2
T1 PD_D3
KILL_MDC# DD3 PD_D4
27 KILL_MDC# AE10 HDA_DOCK_EN#/GPIO33 DD4 V4
+3VS IDERST_CD# AG14 T5 PD_D5
23 IDERST_CD# HDA_DOCK_RST#/GPIO34 DD5
AB2 PD_D6
10K_0402_5% SATA_LED# SATA_LED# DD6 PD_D7
2 1 R227 36 SATA_LED# AF10 SATALED# DD7 T6
T3 PD_D8
PSATA_IRX_DTX_N0_C DD8 PD_D9
23 PSATA_IRX_DTX_N0_C AF6 SATA0RXN DD9 R2
PSATA_IRX_DTX_P0_C AF5 T4 PD_D10
23 PSATA_IRX_DTX_P0_C SATA0RXP DD10
PSATA_ITX_DRX_N0_C AH5 V6 PD_D11
PSATA_ITX_DRX_P0_C SATA0TXN DD11 PD_D12
AH6 SATA0TXP DD12 V5
U1 PD_D13
DD13 PD_D14 +3VS
AG3 SATA1RXN DD14 V2
PSATA_ITX_DRX_N0 1 2 PSATA_ITX_DRX_N0_C AG4 U6 PD_D15
23 PSATA_ITX_DRX_N0 SATA1RXP DD15
IDE
C582 3900P_0402_50V7K AJ4 SATA1TXN PD_A0
AJ3 SATA1TXP DA0 AA4 PD_A0 23
PSATA_ITX_DRX_P0 1 2 PSATA_ITX_DRX_P0_C AA1 PD_A1 PD _IORDY R192 1 2 4.7K_0402_5%
23 PSATA_ITX_DRX_P0 DA1 PD_A1 23
SATA
C584 3900P_0402_50V7K AF2 AB3 PD_A2 PD_IRQ R196 1 2 8.2K_0402_5%
SATA2RXN DA2 PD_A2 23
AF1 SATA2RXP
B PD_CS#1 B
AE4 SATA2TXN DCS1# Y6 PD_CS#1 23
AE3 Y5 PD_CS#3
SATA2TXP DCS3# PD_CS#3 23
CLK_PCIE_SATA# AB7 W4 PD_IOR#
15 CLK_PCIE_SATA# SATA_CLKN DIOR# PD_IOR# 23
CLK_PCIE_SATA AC6 W3 PD_IOW#
15 CLK_PCIE_SATA SATA_CLKP DIOW# PD_IOW# 23
Y2 PD_DACK#
DDACK# PD_DACK# 23
R517 AG1 Y3 PD_IRQ
SATARBIAS# IDEIRQ PD_IRQ 23
1 2 AG2 Y1 PD _IORDY
SATARBIAS IORDY PD_IORDY 23
W5 PD_DREQ
DDREQ PD_DREQ 23
24.9_0402_1%
Within 500 mils ICH8M REV 1.0
BATT1.1
XOR CHAIN ENTRANCE STRAP:RSVD Close to ICH
+RTCVCC
+3VS
R543 2 1 HDA_SDOUT_AUDIO
@ 1K_0402_5%
29 HDA_SDOUT_AUDIO 1
R548
2 HDA_SDOUT_R
33_0402_5% R249
+ BATT1 -
1 2 1 2
W=20mils
29 HDA_SYNC_AUDIO 1 2 H DA_SYNC_R 2 100_0603_1%
D8
R557 33_0402_5% C396
1 2 +CHGRTC ML1220T13RE
0.1U_0402_16V4Z 45@
A 1 A
29 HDA_RST_AUDIO# 1 2 HDA_RST_R# RB751V_SOD323
R553 33_0402_5%
29 HDA_BITCLK_AUDIO 1 2 HDA_BITCLK_R
1 R564 33_0402_5%
@ C394
2
27P_0402_50V8J Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8(2/4)_LAN,HD,IDE,LPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 20 of 47
5 4 3 2 1
5 4 3 2 1
2 SIRQ +3V_SB
+3VS
R245
1
10K_0402_5% +3VS Place closely pin G5 Place closely pin AG9
2
R242 8.2K_0402_5% 0316 change design
R322 R269 R236
1
1 2 VGA_THER_ALERT# 8.2K_0402_5%
2
R243 10K_0402_5% 2.2K_0402_5% 2.2K_0402_5% R193 R228
R274 R264 U28C
1
@ 1 2 EC_THERM# V 10K_0402_5% 10K_0402_5% ICH_SMB_CLK AJ26 AJ12 @ 10_0402_5% @ 10_0402_5%
15,26,27 ICH_SMBCLK SMBCLK SATA0GP/GPIO21
R237 8.2K_0402_5% 15,26,27 ICH_SMBDATA ICH_SMB_DATA AD19 AJ10
2
LINKALERT# SMBDATA SATA1GP/GPIO19
AG21 AF11
GPIO
SATA
1
1
LINKALERT# SATA2GP/GPIO36
SMB
1 2 CLKSATAREQ# ME__EC_CLK1 AC17 SMLINK0 SATA3GP/GPIO37 AG11 1 1
R252 10K_0402_5% ME__EC_DATA1 AE19 C349 C385
SMLINK1 CLK_14M_ICH
CLK14 AG9 CLK_14M_ICH 15
D OCP# 0320 add I CH_RI# CLK_48M_ICH @ 4.7P_0402_50V8C @ 4.7P_0402_50V8C D
1 2 AF17 G5
Clocks
RI# CLK48 CLK_48M_ICH 15 2 2
R229 10K_0402_5% +3VS
F4 D3 ICH_SUSCLK T18 PAD
WOL_EN XDP_DBRESET# AD15 SUS_STAT#/LPCPD# SUSCLK
1 2 4 XDP_DBRESET# SYS_RESET#
2
R273 10K_0402_5% AG23 SLP_S3#
SLP_S3# SLP_S3# 33
R583 @ R278 PM_BMBUSY# AG12 AF21 SLP_S4# SLP_S4# 33
7 PM_BMBUSY# BMBUSY#/GPIO0 SLP_S4#
10K_0402_5% 10K_0402_5% AD18 SLP_S5# SLP_S5# 33
SLP_S5#
33 EC_LID_OUT# 1 2 AG22
R323 0_0402_5% SMBALERT#/GPIO11 AH27 R884 100_0402_5%
1
S4_STATE#/GPIO26
GPIO
1 2 GPIO39 H_STP_PCI# AE20 STP_PCI#/GPIO15 1 2 M_PWROK
15 H_STP_PCI#
SYS
R542 10K_0402_5% 2 1 R_STP_CPU# AG18 STP_CPU#/GPIO25 AE23 ICH_POK
15 H_STP_CPU# PWROK ICH_POK 7,33
@ R584 0_0402_5% 1 2 R292
1 2 GPIO48 PCI_CLKRUN# AH11 AJ14 DPRSLPVR 10K_0402_5%
28,33 PCI_CLKRUN# CLKRUN#/GPIO32 DPRSLPVR/GPIO16 DPRSLPVR 7,45
Power MGT
R232 10K_0402_5%
ICH_PCIE_WAKE# AE17 AE21 ICH_LOW_BAT#
24,26,27 ICH_PCIE_WAKE# WAKE# BATLOW#
+3V_SB 1 2 LINKALERT# 28,32,33 SIRQ
SIRQ AF12 SERIRQ
R284 10K_0402_5% EC_THERM# AC13 C2 PBTN_OUT#
4,33 EC_THERM# THRM# PWRBTN# PBTN_OUT# 33
1 2CL_RST# 7,45 VGATE 1 2 VRMPWRGD AJ20 VRMPWRGD LAN_RST# AH20 1 2 PLT_RST# 7,18,19,23,24,26,27
R432 10K_0402_5% R589 0_0402_5% R277 0_0402_5%
PAD T31 SST_CTL AJ22 AG27 EC_RSMRST#R EC_RSMRST#R 1 2
TP7 RSMRST#
1 2XDP_DBRESET# R325 10K_0402_5%
R257 10K_0402_5% OCP# AJ8 E1 CK_PWRGD_R 1 2 CK_PW RGD
4 OCP# TACH1/GPIO1 CK_PWRGD CK_PWRGD 15
AJ9 R511 0_0402_5%
I CH_RI# TACH2/GPIO6 M_PWROK
1 2 AH9 TACH3/GPIO7 CLPWROK E3 M_PWROK 7
R265 10K_0402_5% EC_SMI# AE16
33 EC_SMI# GPIO8
EC_SCI# AC19 AJ25
33 EC_SCI# GPIO12 SLP_M#
1 2ICH_PCIE_WAKE# AG8 TACH0/GPIO17
R271 1K_0402_5% AH12 F23 CL_CLK0
GPIO18 CL_CLK0 CL_CLK0 7
AE11 AE18 0.1U_0402_16V4Z 1 2 +3VS
GPIO20 CL_CLK1
GPIO
Controller Link
2 1ICH_LOW_BAT# AG10 SCLOCK/GPIO22
R313 @ 3.24K_0402_1%
1
R291 8.2K_0402_5% AH25 F22 CL_DATA0 1
C SB_INT_FLASH_SEL# QRT_STATE0/GPIO27 CL_DATA0 CL_DATA0 7 C
PAD T24 AD16 AF19 C419 R314
+3VS QRT_STATE1/GPIO28 CL_DATA1
1 2 DPRSLPVR 15 CLKSATAREQ#
CLKSATAREQ# AG13 SATACLKREQ#/GPIO35
@ 453_0402_1%
R246 100K_0402_5% AF9 D24 CL_VREF0_ICH @
18 VGA_THER_ALERT# SLOAD/GPIO38 CL_VREF0 2
GPIO39 AJ11 AH23 CL_VREF1_ICH
2
SDATAOUT0/GPIO39 CL_VREF1
2
MISC
MCH_ICH_SYNC#AJ13 AJ24 1 2 0.1U_0402_16V4Z 1 2 +3V_SB
7 MCH_ICH_SYNC# ACIN 33,39
1
MCH_SYNC# ME_EC_ALERT/GPIO10
1 2 VRMPWRGD EC_ME_ALERT/GPIO14 AF22 R318 @ 0_0402_5% R593 @ 3.24K_0402_1%
1
R588 @ 0_0402_5% ICH_RSVD AJ21 AG19 WOL_EN 1
TP3 WOL_EN/GPIO9 WOL_EN
1
D C644 R594
2 Q32 ICH8M REV 1.0 453_0402_1%
45 CLK_ENABLE#
G @ RHU002N06_SOT323 low-->default @ @
2
S +3VS 1 2 SB_SPKR
3
2
R222 @ 10K_0402_5% High -->No boot
U28D
27 PCIE_RXN1
PCIE_RXN1 P27 PERN1 DMI0RXN V27 DMI_RXN0 DMI_RXN0 7 RSMRST circuit
PCIE_RXP1 P26 V26 DMI_RXP0 DMI_RXP0 7 R621
27 PCIE_RXP1 PERP1 DMI0RXP
TV TUNER 27 PCIE_TXN1 0.1U_0402_16V7K C672 PCIE_C_TXN1 N29 U29 DMI_TXN0 DMI_TXN0 7
0.1U_0402_16V7K C673 PCIE_C_TXP1 PETN1 DMI0TXN DMI_TXP0 0_0402_5%
N28 U28
C
27 PCIE_TXN2 L29 PETN2 DMI1TXN W29 DMI_TXN1 7 33 EC_RSMRST# 3 1
0.1U_0402_16V7K C675 PCIE_C_TXP2 DMI_TXP1
E
27 PCIE_TXP2 L28 PETP2 DMI1TXP W28 DMI_TXP1 7
BAV99DW-7_SOT363 @ MMBT3906_SOT23
PCI-Express
PCIE_RXN3 DMI_RXN2
B
26 PCIE_RXN3 K27 AB26 DMI_RXN2 7 1 2 +3V_SB
1 2
PCIE_RXP3 PERN3 DMI2RXN DMI_RXP2 R624 @ 4.7K_0402_5%
26 PCIE_RXP3 K26 PERP3 DMI2RXP AB25 DMI_RXP2 7
2
NEW CARD 26 PCIE_TXN3 0.1U_0402_16V7K C676 PCIE_C_TXN3 J29 AA29 DMI_TXN2 DMI_TXN2 7
B 0.1U_0402_16V7K C677 PCIE_C_TXP3 PETN3 DMI2TXN DMI_TXP2 R626 D23B D23A B
26 PCIE_TXP3 J28 PETP3 DMI2TXP AA28 DMI_TXP2 7
@ 2.2K_0402_5% BAV99DW-7_SOT363
PCIE_RXN4 H27 AD27 DMI_RXN3 DMI_RXN3 7
24 PCIE_RXN4 PERN4 DMI3RXN
PCIE_RXP4 H26 AD26 DMI_RXP3 DMI_RXP3 7
24 PCIE_RXP4
1
0.1U_0402_16V7K C678 PCIE_C_TXN4 PERP4 DMI3RXP DMI_TXN3
LAN 24 PCIE_TXN4 G29 AC29 DMI_TXN3 7 R628
6
0.1U_0402_16V7K C679 PCIE_C_TXP4 PETN4 DMI3TXN DMI_TXP3
24 PCIE_TXP4 G28 PETP4 DMI3TXP AC28 DMI_TXP3 7 1 2
RP14 USB20_P3
+3V_SB 8 1 USB_OC#6 D23
USBP3P J2
K5 USB20_N4
USB20_P3
USB20_N4
36
37
1 WIRELESS
CPUSB# SPI_MOSI USBP4N USB20_P4
7
6
2
3 USB_OC#2
F21 SPI_MISO USBP4P K4
K2 USB20_N5
USB20_P4
USB20_N5
37
26
2 RIGHT SIDE
USB_OC#4 USB_OC#0 USBP5N USB20_P5
5 4 31
26
USB_OC#0
CPUSB# CPUSB#
AJ19
AG16
OC0# USBP5P K1
L3 USB20_N6
USB20_P5
USB20_N6
26 3 CMOS
10K_1206_8P4R_5% USB_OC#2 OC1#/GPIO40 USBP6N USB20_P6
37 USB_OC#2
USB_OC#3
AG15
AE15
OC2#/GPIO41 USB USBP6P L2
M5 USB20_N7
USB20_P6
USB20_N7 27
4 RIGHT SIDE
RP16 USB_OC#4 OC3#/GPIO42 USBP7N USB20_P7
5 4 USB_OC#5
37 USB_OC#4
USB_OC#5
AF15
AG17
OC4#/GPIO43 USBP7P M4
M2 USB20_N8
USB20_P7
USB20_N8
27 5 NEW CARD
USB_OC#7 USB_OC#6 OC5#/GPIO29 USBP8N USB20_P8
6
7
3
2 USB_OC#9
USB_OC#6
USB_OC#7
AD12
AJ18
OC6#/GPIO30 USBP8P M1
N3 USB20_N9
USB20_P8
USB20_N9 27
6
A USB_OC#0 USB_OC#8 OC7#/GPIO31 USBP9N USB20_P9 A
8 1 USB_OC#8
USB_OC#9
AD14
AH18
OC8# USBP9P N2 USB20_P9 27 7 BT(HDL20)
10K_1206_8P4R_5% OC9# USBRBIAS
USBRBIAS# F2
F3
1 2
8
USBRBIAS
1 USB_OC#8 R499 22.6_0402_1%
2
R248 10K_0402_5% ICH8M REV 1.0 Within 500 mils
9 3G
2 1 USB_OC#3
R258 10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8(3/4)_PM,USB,GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 21 of 47
5 4 3 2 1
5 4 3 2 1
+RTCVCC U28E
20 mils A23 VSS[001] VSS[099] K7
A5 VSS[002] VSS[100] L1
1 1 AA2 VSS[003] VSS[101] L13
C423 C424 AA7 L15
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VCCP VSS[004] VSS[102]
A25 VSS[005] VSS[103] L26
AB1 VSS[006] VSS[104] L27
2 2
AB24 VSS[007] VSS[105] L4
U28F 0.1U_0402_16V7K AC11 L5
VSS[008] VSS[106]
AD25 VCCRTC VCC1_05[01] A13 AC14 VSS[009] VSS[107] M12
VCC1_05[02] B13 AC25 VSS[010] VSS[108] M13
ICH_V5REF_RUN A16 C13 1 1 AC26 M14
V5REF[1] VCC1_05[03] C412 C386 0.1U_0402_16V4Z VSS[011] VSS[109]
T7 V5REF[2] VCC1_05[04] C14 AC27 VSS[012] VSS[110] M15
VCC1_05[05] D14 AD17 VSS[013] VSS[111] M16
R293 ICH_V5REF_SUS G4 E14 AD20 M17
D 10U_0805_6.3V6M V5REF_SUS VCC1_05[06] 2 2 VSS[014] VSS[112] D
+1.5VS 1 2 40 mils VCC1_05[07] F14 AD28 VSS[015] VSS[113] M23
1 AA25 VCC1_5_B[01] VCC1_05[08] G14 AD29 VSS[016] VSS[114] M28
CHB1608U301_0603 1 1 1 AA26 L11 AD3 M29
+ C428 C418 C426 VCC1_5_B[02] VCC1_05[09] VSS[017] VSS[115]
AA27 VCC1_5_B[03] VCC1_05[10] L12 AD4 VSS[018] VSS[116] M3
C429 AB27 L14 AD6 N1
220U_D2_4VM VCC1_5_B[04] VCC1_05[11] VSS[019] VSS[117]
AB28 VCC1_5_B[05] VCC1_05[12] L16 AE1 VSS[020] VSS[118] N11
2 2 2 2
AB29 VCC1_5_B[06] VCC1_05[13] L17 AE12 VSS[021] VSS[119] N12
+5VS +3VS D28 L18 R332 AE2 N13
10U_0805_6.3V6M 2.2U_0603_6.3V4Z VCC1_5_B[07] VCC1_05[14] 0.01U_0402_16V7K VSS[022] VSS[120]
D29 VCC1_5_B[08] VCC1_05[15] M11 1 2 +1.5VS AE22 VSS[023] VSS[121] N14
CORE
E25 M18 CHB1608U301_0603 AD1 N15
VCC1_5_B[09] VCC1_05[16] VSS[024] VSS[122]
1
VCCA3GP
L25 VCC1_5_B[23] VCCDMIPLL R29 AH16 VSS[038] VSS[136] P17
2
M24 VCC1_5_B[24] AH19 VSS[039] VSS[137] P23
M25 VCC1_5_B[25] VCC_DMI[1] AE28 AH2 VSS[040] VSS[138] P28
N23 AE29 +VCCP AF28 P29
+5VALW +3VALW VCC1_5_B[26] VCC_DMI[2] VSS[041] VSS[139]
N24 VCC1_5_B[27] AH22 VSS[042] VSS[140] R11
N25 VCC1_5_B[28] V_CPU_IO[1] AC23 AH24 VSS[043] VSS[141] R12
P24 VCC1_5_B[29] V_CPU_IO[2] AC24 AH26 VSS[044] VSS[142] R13
1
4.7U_0603_6.3V6M
P25 VCC1_5_B[30] AH3 VSS[045] VSS[143] R14
R187 D4 R24 AF29 +3VS 1 1 1 AH4 R15
VCC1_5_B[31] VCC3_3[01] VSS[046] VSS[144]
C399
0.1U_0402_16V4Z
C421
0.1U_0402_16V4Z
C411
C (DMI) C
R25 VCC1_5_B[32] 1 AH8 VSS[047] VSS[145] R16
10_0402_5% CH751H-40_SC76 R26 AD2 +3VS C434 AJ5 R17
VCC1_5_B[33] VCC3_3[02] (SATA) VSS[048] VSS[146]
R27 1 B11 R18
2
VCCP_CORE
VCC1_5_B[36] VCC3_3[04] VSS[051] VSS[149]
1 T27 VCC1_5_B[37] VCC3_3[05] AE8 B2 VSS[052] VSS[150] T12
C354 +3VS 2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
T28 VCC1_5_B[38] VCC3_3[06] AF8 B20 VSS[053] VSS[151] T13
T29 VCC1_5_B[39] B22 VSS[054] VSS[152] T14
0.1U_0402_16V4Z U24 AA3 B8 T15
2 VCC1_5_B[40] VCC3_3[07] VSS[055] VSS[153]
U25 VCC1_5_B[41] VCC3_3[08] U7 1 C24 VSS[056] VSS[154] T16
V23 V7 C357 C26 T17
VCC1_5_B[42] VCC3_3[09] 0.1U_0402_16V4Z VSS[057] VSS[155]
V24 VCC1_5_B[43] VCC3_3[10] W1 C27 VSS[058] VSS[156] T2
V25 W6 C6 U12
IDE
VCC1_5_B[44] VCC3_3[11] 2 +3VS VSS[059] VSS[157]
W25 VCC1_5_B[45] VCC3_3[12] W7 D12 VSS[060] VSS[158] U13
Y25 VCC1_5_B[46] VCC3_3[13] Y7 D15 VSS[061] VSS[159] U14
R218 D18 U15
VSS[062] VSS[160]
+1.5VS 1 2 AJ6 VCCSATAPLL VCC3_3[14] A8 D2 VSS[063] VSS[161] U16
1U_0603_10V4Z
C362
ARX
CHB1608U301_0603
1 1 +1.5VS 1 2 A26 G22 VCCCL1_05_ICH
VCCGLAN1_5[1] VCCCL1_05 T27
1 A27 VCCGLAN1_5[2]
C655 C653 CHB1608U301_0603 B26 A22 1
A C663 VCCGLAN1_5[3] VCCCL1_5 C645 A
B27 VCCGLAN1_5[4]
2 2 @ 1U_0603_10V4Z
B28 VCCGLAN1_5[5] VCCCL3_3[1] F20 +3VS
2
VCCCL3_3[2] G21
2
+3VS B25 VCCGLAN3_3
10U_0805_6.3V6M
ICH8M REV 1.0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8(4/4)_POWER&GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 22 of 47
5 4 3 2 1
5 4 3 2 1
1
+3VS
R771 +5VS PCMRST# SWDJ@ R772
33 PCMRST#
1000P_0402_50V7K
22U_1206_6.3V6M
@ 0.1U_0402_16V4Z SWDJ@ 10K_0402_5%
0.1U_0402_16V4Z
10K_0402_5%
14
5
1
1 1 1 1 1 U74 U55ASWDJ@
2
C441
C445
C446
1
OE#
20 IDERST_CD# B
C444 C449 4 SD_IDERST# 2 3 SIDE_RST# SIDE_RST#
PLT_RST# Y I O
2 A
G
2 2 2 2 2
2
@ 1U_0603_10V4Z TC7SH08FU_SSOP5
7
@ @ SWDJ@ SN74LVC125APWLE_TSSOP14
Pleace near HD CONN @
D R773 D
10K_0402_5%
1
NOSWDJ@
@ 1 2
JP9 R837 0_0402_5%
1 2
R857 0_0402_5%
1 GND
PSATA_ITX_DRX_P0 2
20 PSATA_ITX_DRX_P0 A+
PSATA_ITX_DRX_N0 3
20 PSATA_ITX_DRX_N0 A-
4 GND
2 1 PSATA_IRX_DTX_N0 5 1 2
20 PSATA_IRX_DTX_N0_C B-
C432 3900P_0402_50V7K 6 R843 0_0402_5%
B+ NOSWDJ@
7 GND
2 1 PSATA_IRX_DTX_P0 +5VCD
20 PSATA_IRX_DTX_P0_C
C435 3900P_0402_50V7K
+3VS_SATA 8 V33
1
9 +3VALW
V33 R782
+3VS 1 2 10 V33
R341 @ 0_0805_5% 11 VCC= +3VALW 10K_0402_5%
GND
4
12 U55B SWDJ@
GND R783
13
OE#
2
+5VS_SATA GND 10K_0402_5% SW_IDE_SDCS1#
+5VS 1 2 14 V5 20 PD_CS#1 5 I O 6 SW_IDE_SDCS1#
R355 0_0805_5% 15 SWDJ@
NOSWDJ@ V5
16
2
V5 SWDJ@
17 GND
18 G_PCI_RST# SN74LVC125APWLE_TSSOP14
Reserved +5VCD
19 GND
1
D
20 V12
+5VS +5VS_SATA 21 PLT_RST# 2 Q87
V12 7,18,19,21,24,26,27 PLT_RST#
1
SWDJ@ 22 G 2N7002_SOT23
V12 R785
S SWDJ@
3
D
C 10K_0402_5% C
6
S
ALLTO_C16616-122A3-L_NR
VCC= +3VALW SW DJ@
13
5 4
2 Q90 U55D SWDJ@
2
1
OE#
+VSB
0.1U_0402_16V4Z
20 PD_CS#3 I O SW_IDE_SDCS3#
1000P_0402_50V7K
1U_0603_10V4Z
1 1
3
C463
22U_1206_6.3V6M
1 1 1 SN74LVC125APWLE_TSSOP14
1
C472
C467
C462
0.1U_0402_16V4Z
C461
R896 NOSWDJ@
2 2 10K_0402_5% 1 2
2 2 2 SWDJ@ R844 0_0402_5%
2
1
80 mil 1 2 80 mil
+5VS
R838 0_0805_5%
NOSWDJ@ +5VCD
Q80
Q92 2 SWDJ@
CD_PLAY 29,33
S
DTC124EK_SC59
D
+5VALW 3 1
SWDJ@
SI2301BDS_SOT23
G
1
3
2
1 1
SWDJ@ C840 SWDJ@ SWDJ@
10U_0805_10V4Z C841 C842
2 10U_0805_10V4Z 0.1U_0402_16V4Z
JP10 2 2
29,31 INT_CD_L 1 1 2 2 INT_CD_R 29,31
29 CD_AGND 3 3 4 4
SIDE_RST# 5 6 PD_D8 SWDJ@
PD_D7 5 6 PD_D9
7 7 8 8 +5VALW 1 2
B PD_D6 9 10 PD_D10 R774 240K_0402_5% B
9 10 PLAY_MODE 30
PD_D5 11 12 PD_D11
PD_D4 11 12 PD_D12 C843
13 13 14 14
PD_D3 15 16 PD_D13 1 2 PLAY_MODE
PD_D2 15 16 PD_D14
17 17 18 18
1
+3VS PD_D1 19 20 PD_D15 1U_0603_10V4Z
19 20
1
PD_D0 21 22 PD_DREQ SWDJ@
21 22 PD_DREQ 20
23 23 24 24 ODD_IOR#
1
PD_IOW# 25 26
20 PD_IOW# 25 26
PD _IORDY 27 28 PD_DACK# SUSP# 2 Q85
20 PD_IORDY 27 28 PD_DACK# 20 18,26,28,29,33,35,42,43,44 SUSP#
R466 PD_IRQ 29 30 DTC124EK_SC59 2 Q86
20 PD_IRQ 29 30
10K_0402_5% PD_A1 31 32 PDIAG# 1 2 SWDJ@ DTC124EK_SC59
PD_A0 31 32 PD_A2 R463 100K_0402_5% +5VCD SWDJ@
33 34
2
33 34
SW_IDE_SDCS1# 35 36 SW_IDE_SDCS3#
3
ODD_LED# 35 36
36 ODD_LED# 37 38
3
37 38
39 39 40 40
41 42 CD_PLAY
+5VCD 41 42 +5VCD 29,33 CD_PLAY
43 43 44 44 2 1
45 46 C553 0.1U_0402_16V4Z
PRI_CSEL 45 46 +3VALW +3VS
47 47 48 48
49 49 50 50
2
0.1U_0402_16V4Z
SWDJ@
OCTEK_CDR-50DY1G
C844
R457 ME@
470_0402_5% R839
8.2K_0402_5%
1
1
U70 NOSWDJ@
R845
SWDJ@
OE#
SWDJ@
10
20 PD_IOR# 2 I O 4 ODD_IOR#
U55C
G
33_0402_5%
OE#
9 8 74LVC1G125GW_SOT3535
3
A I O A
SWDJ@
PD_D[0..15]
PD_D[0..15] 20
NOSWDJ@
+5VCD PD_A[0..2] SN74LVC125APWLE_TSSOP14 1 2
PD_A[0..2] 20
R840 0_0402_5%
1 1
C552 C556
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title
1U_0603_10V4Z 10U_0805_10V4Z
2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & CDROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 23 of 47
5 4 3 2 1
5 4 3 2 1
Layout Notice : Filter place as close L23 @ Layout Notice : Place as close
FBM-L11-321611-260-LMT_1206 Layout Notice : 1.2V filter. Place as close
chip as possible. chip as possible.
1 2 chip as possible.
+2.5V_LAN +3VALW +3V_LAN U31 R587
D
L15 6 +1.2V_LAN
S
2 1 +XTALVDD 5 4
FBM-L11-160808-601LMT_0603 2 +VSB Q34 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
4.7U_0805_6.3V6K
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C589 SI3456BDV-T1-E3_TSOP6 2 2 2 2 2
G
1
C661
0.1U_0402_16V4Z BCM5787MKML_QFN68 1K_0402_1% 2 2 2 2 2 2 2
3
1
C575
C583
C591
C611
R902
C568
C619
C576
C585
C597
C577
C572
21.5 33K_0402_5% GIGA@ 100@
L18 1 1 1 1 1
D 1 1 1 1 1 1 1 D
2 1 +LAN_AVDD
2
FBM-L11-160808-601LMT_0603 2 2 2
C632 C625 C634 1
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z D C877
1 1
0.1U_0402_16V4Z 1 EN_WOL 2 0.1U_0603_25V7K
33 EN_WOL
G
Q93 S 2
3
L22 2N7002_SOT23
2 1 +LAN_BIASVDD
FBM-L11-160808-601LMT_0603 1 U31
C628
41 LAN_TX0-
TRD0_N LAN_TX0- 25
0.1U_0402_16V4Z 28 40 LAN_TX0+
2 15 CLK_PCIE_LAN# PCIE_REFCLK_N TRD0_P LAN_TX0+ 25
42 LAN_RX1-
TRD1_N LAN_RX1- 25
29 43 LAN_RX1+
15 CLK_PCIE_LAN PCIE_REFCLK_P TRD1_P LAN_RX1+ 25
48 LAN_TX2-
TRD2_N LAN_TX2- 25
11 47 LAN_TX2+
15 CLKREQ_LAN# CLKREQ TRD2_P LAN_TX2+ 25
49 LAN_TX3-
TRD3_N LAN_TX3- 25
50 LAN_TX3+
TRD3_P LAN_TX3+ 25
+1.2V_LAN
1 2 3 +3V_LAN
+3VS LOW PWR
2 1 +AVDDL (CLKREQ#) and (ENERGY_DET) are R514 @ 0_0402_5%
L17 FBM-L11-160808-601LMT_0603
2 2 +3VS 1 2 53 2 R521 1 2 0_0402_5% LINKLED# 25 C654 1 2 0.1U_0402_16V4Z
only supported in BCM5787M R567 1K_0402_5% VMAIN_PRSNT LINKLED
1 R522 1 2 @ 0_0402_5%
C636 C633 SPD100LED
+3V_LAN 1 2 54 VAUX_PRSNT SPD1000LED 67 R516 1 2 @ 0_0402_5% C656 1 2 4.7U_0805_10V4Z
4.7U_0805_6.3V6K 0.1U_0402_16V4Z R566 1K_0402_5% 66 ACTIVITY# 25
TRAFFICLED
3
1 1 Q33
2
4
C635 C631 CS
21 PCIE_TXN4 32 PCIE_RXD_N
4.7U_0805_6.3V6K 0.1U_0402_16V4Z 1
1 1 C648
21 PCIE_TXP4 31 PCIE_RXD_P
14 CTL12
0.1U_0402_16V7K PCIE_MRX_C_LTX_N4 REGCTL12 CTL25 10U_0805_10V4Z
21 PCIE_RXN4 25 PCIE_TXD_N REGCTL25 18
C596 2
2 1 +PCIE_PLLVDD RDAC 37 2 1
L19 FBM-L11-160808-601LMT_0603
2 2 21 PCIE_RXP4 0.1U_0402_16V7K PCIE_MRX_C_LTX_P4 26 R587 1.24K_0402_1%
C598 PCIE_TXD_P
GIGA@
C613
C624 0.1U_0402_16V4Z 23 +XTALVDD
4.7U_0805_6.3V6K 1 1 XTALVDD
7,18,19,21,23,26,27 PLT_RST# 10 PERST VDDIO 6 +3V_LAN
VDDIO 15
21,26,27 ICH_PCIE_WAKE# 12 WAKE VDDIO 19
2 1 +PCIE_VDD VDDIO 56
L21 FBM-L11-160808-601LMT_0603
1 2 61
VDDIO +3V_LAN
C629 C617 +3V_LAN 1 2 58 17
SMB_CLK VDDP +2.5V_LAN
4.7U_0805_6.3V6K 0.1U_0402_16V4Z R546 @ 47K_0402_5% 68
2 1 VDDP
+3V_LAN 1 2 57 SMB_DATA
R551 @ 47K_0402_5% 5 +1.2V_LAN
VDDC
4
13 Q31
VDDC MBT35200MT1G_TSOP6
VDDC 20
1 2 4 GPIO_0(SERIAL_DO) VDDC 34
R513 0_0402_5% 55 CTL25 3
LAN_WP VDDC
1 2 7 GPIO_1(SERIAL_DI) VDDC 60
R519 @ 4.7K_0402_5%
1 2 GPIO2 8 36 +LAN_BIASVDD
1
2
5
6
R518 @ 4.7K_0402_5% GPIO_2 BIASVDD
Layout Notice : Place as close PCIE_PLLVDD 30 +PCIE_PLLVDD
chip as possible. +3V_LAN 1 2 9 UART_MODE PCIE_VDD 27 +PCIE_VDD
R512 @ 0_0402_5% 33
PCIE_VDD
B +2.5V_LAN 38 B
AVDD +LAN_AVDD
XTALI 21 45
XTALI AVDD
AVDD 52
XTALO 22 XTALO
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2 1 XTALO 39
AVDDL +AVDDL +2.5V_LAN
10U_0805_10V4Z
2 2 2 R538 200_0603_1% 44
AVDDL
C641
C642
C639
XTALI 16 46
Y2 REG_GND AVDDL
51 Notice : 4.7u 6.3V capactor Thickness 1.25mm
GND
21.5 AVDDL
27P_0402_50V8J
27P_0402_50V8J
1 2 24 PCIE_GND
1 1 1
2 25MHZ_16P_XSL025000FK1H 2 Layout Notice : Filter place as close
69
C612
C581
100@
chip as possible.
1 1
+3V_LAN
1 2
1
C567
0.1U_0402_16V4Z
R489 R488
4.7K_0402_5% 4.7K_0402_5%
2
U27
8 VCC A0 1
LAN_WP 7 2
LAN_CLK WP A1
6 SCL NC 3
LAN_DATA 5 4
SDA GND
AT24C02_SO8
A LAN_CLK A
1 2
R526 4.7K_0402_5%
SI 2 1
R533 GIGA@ 4.7K_0402_5%
CS# 1 2
R534 GIGA@ 4.7K_0402_5%
D D
RJ11+RJ45 CONN
+2.5V_LAN
JP73
+3V_LAN 11 VDD
R910
2 330_0402_5%
1
220P_0402_25V8J 24 LINKLED# 2 1 12
R523 C882 GND
FBM-L11-160808-601LMT_0603
1 MDO0+
MDO0+ 1 TX1+
MDO0- 2
MDO0-
2
TX1-
MDO1+ 3
MDO1+ RX1+
U29
MDO2+ 4
MDO2+ TX2+
LAN_TX3- 12 13 MDO3- MDO2- 5
24 LAN_TX3- TD4- MX4- MDO2- TX2-
LAN_TX3+ 11 14 MDO3+
24 LAN_TX3+ TD4+ MX4+
1 2 0.1U_0402_16V4Z TCT 10 15 MCT0 2 1 R575 RJ45_PR MDO1- 6
TCT4 MCT4 MDO1- RX1-
C578 GIGA@ 75_0402_5%
LAN_TX2- 9 16 MDO2- MDO3+ 7
24 LAN_TX2- TD3- MX3- MDO3+ RX2+
LAN_TX2+ 8 17 MDO2+
24 LAN_TX2+ TD3+ MX3+
1 2 0.1U_0402_16V4Z 7 TCT3 MCT3 18 MCT1 2 1 R569 MDO3-
MDO3- 8 RX2-
C622 GIGA@ 75_0402_5%
LAN_RX1- 6 19 MDO1-
C 24 LAN_RX1- TD2- MX2- C
LAN_RX1+ 5 20 MDO1+ RJ45
24 LAN_RX1+ TD2+ MX2+
1 2 0.1U_0402_16V4Z 4 TCT2 MCT2 21 2 1 R529
C587 GIGA@ 75_0402_5% GIGA@ +3V_LAN 13
LAN_TX0- MDO0- VDD
24 LAN_TX0- 3 TD1- MX1- 22 1 R909
LAN_TX0+ 2 23 MDO0+ 330_0402_5%
24 LAN_TX0+ TD1+ MX1+
1 2 0.1U_0402_16V4Z 1 TCT1 MCT1 24 2 1 R525 C881
24 ACTIVITY# 2 1 14 GND
C599 GIGA@ 75_0402_5% GIGA@ 220P_0402_25V8J
2 R786 FBMA-L11-160808-181LMA15T
GIGA@ 0.5u_24HST1041A-2 RJ_TIP 2 1 9 RJ11_1
RJ11
R J_RING 2 1 10 RJ11_2
R787
U32 RJ45_PR 1 FBMA-L11-160808-181LMA15T
2 15
RJ45_PR SGND1
C803 16
LAN_RX1- MDO1- 1000P_1206_2KV7K SGND2
8 TD- TX- 9
LAN_RX1+ 7 10 MDO1+ 1 1
TD+ TX+
2 1 0.01U_0402_16V7K 6 CT CT 11 MCT0 C802 ALLTO_C100B6-110A4-L
C571 100@
C804
TCT MCT1 2 2
2 1 0.01U_0402_16V7K 3 CT CT 14 4.7U_0805_10V4Z
C573 100@ LAN_TX0- 2 15 MDO0-
LAN_TX0+ RD- RX- MDO0+
1 RD+ RX+ 16
0.1U_0402_16V4Z
NS0013_16P
100@
B B
LAN_TX3- 2 1
R581 @ 49.9_0402_1% 2 1
LAN_TX3+ 2 1 C637 @ 0.01U_0402_16V7K
R579 @ 49.9_0402_1%
LAN_TX2- 2 1
R568 @ 49.9_0402_1% 2 1
LAN_TX2+ 2
R558
1
@ 49.9_0402_1%
C615 @ 0.01U_0402_16V7K
MDC CONN
JP74
RJ_TIP
LAN_RX1- 2 100@ R J_RING 1
1 2
R545 100@ 49.9_0402_1% 2 1
LAN_RX1+ 2 1 C592 0.01U_0402_16V7K EDL71_MDC
R541 100@ 49.9_0402_1%
LAN_TX0- 2 1 100@
A R531 100@ 49.9_0402_1% A
2 1
LAN_TX0+ 2 1 C579 0.01U_0402_16V7K
R527 100@ 49.9_0402_1%
near LAN controller Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN CONTROLLER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 25 of 47
5 4 3 2 1
A B C D E
+1.5VS_PEC
4.7U_0805_10V4Z
1
Express Card Power Switch 1 1 1
C373 C365
+1.5VS 0.1U_0402_16V4Z
U8 +1.5VS_PEC 2 2
2 1 12 1.5Vin 1.5Vout 11
C378 0.1U_0402_16V4Z 14 13
1.5Vin 1.5Vout
+3VS +3VS_PEC
2 1 2 3.3Vin 3.3Vout 3
C375 0.1U_0402_16V4Z 4 5 +3V_PEC
3.3Vin 3.3Vout +3V_PEC
+3VALW
2 1 17 AUX_IN AUX_OUT 15
C389 0.1U_0402_16V4Z
PLT_RST# 6 19 1 1
7,18,19,21,23,24,27 PLT_RST# SYSRST# OC#
SYSON 20 8 PERST# C384 C392
33,35,42 SYSON SHDN# PERST# 0.1U_0402_16V4Z 4.7U_0805_10V4Z
SUSP# 2 2
18,23,28,29,33,35,42,43,44 SUSP# 1 STBY# NC 16
CPUSB# 9 +3VS_PEC
21 CPUSB# CPUSB# 4.7U_0805_10V4Z
18 RCLKEN
R5538_QFN20 1 1
C371 C361
2 0.1U_0402_16V4Z 2
2 2
JP53
0_0402_5% 1
USB20_N5 R259 USB5- GND
21 USB20_N5 1 2 2 USB_D-
USB20_P5 R266 1 2 USB5+ 3
21 USB20_P5 USB_D+
CPUSB# 4
0_0402_5% CPUSB#
5 RSV
6 RSV
ICH_SMBCLK 7
15,21,27 ICH_SMBCLK SMB_CLK
ICH_SMBDATA 8
15,21,27 ICH_SMBDATA SMB_DATA
+1.5VS_PEC 9 +1.5V
+1.5VS_PEC 10 +1.5V
21,24,27 ICH_PCIE_WAKE# R315 1 2 PCIE_PME#_R 11
0_0402_5% WAKE#
+3V_PEC 12 +3.3VAUX
PERST# 13 PERST#
+3VS_PEC 14 +3.3V
15 +3.3V
CLKREQ_NC1# 16
15 CLKREQ_NC1# CLKREQ#
21 CPUSB# CPUSB# 17
CLK_PCIE_NC1# CPPE#
15 CLK_PCIE_NC1# 18 REFCLK-
CLK_PCIE_NC1 19
15 CLK_PCIE_NC1 REFCLK+
20 GND
PCIE_RXN3 21
3 21 PCIE_RXN3 PERn0 3
PCIE_RXP3 22
21 PCIE_RXP3 PERp0
23 GND
21 PCIE_TXN3 PCIE_TXN3 24
PCIE_TXP3 PETn0
21 PCIE_TXP3 25 PETp0
26 GND
27 GND
28 GND
FOX_1CH4110C
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CardBus Socket
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 26 of 47
A B C D E
A B C D E
1
Mini-Express Card(Slot 1-WLAN) Mini-Express Card(Slot 2-3G) 1
21,24,26 ICH_PCIE_WAKE#
JP54 JP55
21,24,26 ICH_PCIE_WAKE# 1 1 2 2 +3VS 1 1 2 2 +3VS
BT_AVTIVE R635 2 1 @ 0_0402_5% 3 4 BT_AVTIVE R555 2 1@ 0_0402_5% 3 4
WLAN_AVTIVE R636 2 @ 0_0402_5% 3 4 WLAN_AVTIVE R561 2 3 4
1 5 5 6 6 +1.5VS 1@ 0_0402_5% 5 5 6 6 +1.5VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
15 CLKREQ_MCARD# 7 7 8 8 CLKREQ_MCARD1# 7 7 8 8
0.1U_0402_16V4Z
0.1U_0402_16V4Z
9 9 10 10 1 9 9 10 10 1
C683
C682
CLK_PCIE_MCARD# 11 12 1 CLK_PCIE_MCARD1# 11 12 1
15 CLK_PCIE_MCARD# 11 12 15 CLK_PCIE_MCARD1# 11 12
C684
C669
CLK_PCIE_MCARD 13 14 CLK_PCIE_MCARD1 13 14
15 CLK_PCIE_MCARD 13 14 15 CLK_PCIE_MCARD1 13 14
15 15 16 16 15 15 16 16
2 2
17 17 18 18 17 17 18 18
2 2
19 19 20 20 RF_OFF# 33 19 19 20 20 RF_OFF# 33
21 22 PLT_RST# 21 22 PLT_RST#
21 22 PLT_RST# 7,18,19,21,23,24,26 21 22 PLT_RST# 7,18,19,21,23,24,26
23 24 2 1 +3VALW PCIE_RXN1 23 24 +3VALW
21 PCIE_RXN2 23 24 21 PCIE_RXN1 23 24
25 26 R595 2 1 0_0402_5% +3VS PCIE_RXP1 25 26
21 PCIE_RXP2 25 26 21 PCIE_RXP1 25 26
27 28 R598 @ 0_0402_5% 27 28
27 28 ICH_SMBCLK 27 28 ICH_SMBCLK
29 29 30 30 ICH_SMBCLK 15,21,26 29 29 30 30 ICH_SMBCLK 15,21,26
31 32 ICH_SMBDATA ICH_SMBDATA 15,21,26 21 PCIE_TXN1 PCIE_TXN1 31 32 ICH_SMBDATA ICH_SMBDATA 15,21,26
21 PCIE_TXN2 31 32 31 32
33 34 21 PCIE_TXP1 PCIE_TXP1 33 34
21 PCIE_TXP2 33 34 33 34
35 35 36 36 USB20_N1 21 35 35 36 36 USB20_N9 21
R899
37 37 38 38 USB20_P1 21 37 37 38 38 USB20_P9 21
39 39 40 40 +3VS 2 1 39 39 40 40
41 42 0_0603_5% 41 42 3G_LED# 36
41 42 41 42
43 43 44 44 WIRELESS_LED# 36 43 43 44 44
45 45 46 46 45 45 46 46
47 47 48 48 47 47 48 48
49 49 50 50 49 49 50 50
51 51 52 52 51 51 52 52
2 2
53 GND1 GND2 54 53 GND1 GND2 54
FOX_AS0B226-S56N-7F FOX_AS0B226-S56N-7F
+5VS
BT MODULE CONN.
1
3 3
+3VALW
MDC CONN. C586
R171
10K_0402_1%
1
1 2
1 2 RF_OFF2
R496 JP17
10K_0402_1%
1U_0805_25V4Z
1 2
2
1 2
20 HDA_SDOUT_MDC 3 3 4 4
5 6 +3V_SB 2 Q13
5 6 33 BT_OFF#
AZ _SYNC 7 8 DTC124EK_SC59
20 HDA_SYNC_MDC 7 8
R497 1 2 AZ_SDIN3 9 10
20 HDA_SDIN1 9 10
20 HDA_RST_MDC# R498 2 133_0402_5% 11 12 +3VS Q8 +3VS_BT2
@ 0_0402_5% 11 12 HDA_BITCLK_MDC 20 C337
3
1
D
D21 3 1 2 1
2 AO3413_SOT23
1 R535 0.1U_0402_16V4Z
13
14
15
16
17
18
19
20
G
20 KILL_MDC# 3 36 BTONLED
2
ME@
13
14
15
16
17
18
19
20
DAP202U_SOT323 1 JP56
1
1 1
C588 2
@ 10P_0402_50V8J USB20_N7 2
21 USB20_N7 3 3
2 USB20_P7
21 USB20_P7 4 4
Q11 2 BTON_LED2 5
DTC124EK_SC59 BT_AVTIVE 5
6 6
WLAN_AVTIVE 7 7
1
8 8
9
3
R151 GND1
10 GND2
10K_0402_5%
4 MOLEX_53780-0870 4
2
ME@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini Card / MDC CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 27 of 47
A B C D E
5 4 3 2 1
+3VS
SD,MMC,MS,XD muti-function pin define
MDIO SD Card MMC Card MS Card XD Card
U18
19 PCI_AD[0..31] PIN Name PIN Name PIN Name PIN Name PIN Name
10U_0805_4VAM
0.01U_0402_16V7K
PCI_AD31 125 10 1 1
PCI_AD30 AD31 VCC_PCI3V
126 AD30 VCC_PCI3V 20 MDIO00 SDCD# MMCCD# XDCD0#
C482
C469
PCI_AD29 127 27
PCI_AD28 AD29 VCC_PCI3V
1 32 MDIO01 MSCD# XDCD1#
PCI_AD27
PCI_AD26
2
3
AD28
AD27 R5C832 VCC_PCI3V
VCC_PCI3V 41
128
2 2 +3VS
MDIO02 XDCE#
PCI_AD25 AD26 VCC_PCI3V
5 AD25
PCI_AD24 6 61 MDIO03 SDWP# XDR/B#
PCI_AD23 AD24 VCC_RIN
9 AD23
0.1U_0402_16V4Z
10U_0805_4VAM
0.01U_0402_16V7K
0.01U_0402_16V7K
PCI_AD22 11 16 MDIO04 SDPWR0 MMCPWR MSWR XDPWR
PCI_AD21 AD22 VCC_ROUT
12 AD21 VCC_ROUT 34 1 1 1 1
D PCI_AD20 D
14 AD20 VCC_ROUT 64 MDIO05 SDPWR1 XDWP#
C451
C455
C452
C448
0.47U_0603_16V4Z
0.47U_0603_16V4Z
0.01U_0402_16V7K
0.01U_0402_16V7K
PCI_AD19 15 114 1 1 1 1
PCI_AD18 AD19 VCC_ROUT
17 AD18 VCC_ROUT 120
2 2 2 2
MDIO06 SDLED# MMCLED# MSLED# XDLED#
C477
C487
C492
C447
PCI_AD17 18
PCI_AD16 AD17
19 AD16 VCC_3V 67 +3VS 2 2 2 2
MDIO07 MSEXTCK
PCI_AD15 36 AD15
10U_0805_4VAM
0.01U_0402_16V7K
PCI_AD14 37 86 1 1 MDIO08 SDCCMD MMCCMD MSBS XDWE#
PCI_AD13 AD14 VCC_MD3V
38 AD13
C481
C657
PCI_AD12 39 98 +3V_PHY MDIO09 SDCCLK MMCCLK MSCCLK XDRE#
PCI_AD11 AD12 AVCC_PHY3V
40 AD11 AVCC_PHY3V 106
PCI_AD10 2 2
42 AD10 AVCC_PHY3V 110 MDIO10 SDCDAT0 MMCDAT MSCDAT0 XDCDAT0
PCI_AD9 43 112
PCI_AD8 AD9 AVCC_PHY3V
44 AD8 MDIO11 SDCDAT1 MSCDAT1 XDCDAT1
PCI_AD7 46 113 IEEE1394_TPBIAS0
PCI_AD6 AD7 TPBIAS0 +3V_PHY
47 AD6 MDIO12 SDCDAT2 MSCDAT2 XDCDAT2
PCI_AD5 48 109 IEEE1394_TPAP0 L25
PCI_AD4 AD5 TPAP0 IEEE1394_TPAN0
49 AD4 TPAN0 108 +3VS 1 2 MDIO13 SDCDAT3 MSCDAT3 XDCDAT3
PCI_AD3 50 AD3
0.1U_0402_16V4Z
0.1U_0402_16V4Z
22U_0805_6.3V6M
1000P_0402_50V7K
1000P_0402_50V7K
PCI_AD2 51 105 IEEE1394_TPBP0 BLM21A601SPT_0805 MDIO14 XDCDAT4
PCI_AD1 AD2 TPBP0 IEEE1394_TPBN0
52 AD1 TPBN0 104
PCI_AD0 53 1 1 1 1 1 MDIO15 XDCDAT5
AD0 SDCD#_XDCD0#
MDIO00 80 SDCD#_XDCD0# 37
C714
C699
C711
C713
C712
79 MSCD#_XDCD1 MDIO16 XDCDAT6
MDIO01 MSCD#_XDCD1 37
PCI_CBE#3 7 78 XD_CE#
19,24 PCI_CBE#3 C/BE3# MDIO02 XD_CE# 37 2 2 2 2 2
PCI_CBE#2 21 77 SDWP#_XDRB# MDIO17 XDCDAT7
19 PCI_CBE#2 C/BE2# MDIO03 SDWP#_XDRB# 37
PCI_CBE#1 35 76 SDPWR0_MSPWR_XDPWR
19 PCI_CBE#1 C/BE1# MDIO04
PCI_CBE#0 45 75 XDWP# MDIO18 XDCLE
19 PCI_CBE#0 C/BE0# MDIO05 XDWP# 37
74 3IN1_LED#
MDIO06 3IN1_LED#
73 TP_MSEXTCK MDIO19 XDALE
PCI_PAR MDIO07 SDCMD_MSBS
19 PCI_PAR 33 PAR MDIO08 88 SDCMD_MSBS 37
PCI_FRAME# 23 84 SDCLK_MSCLK
19 PCI_FRAME# FRAME# MDIO09 SDCLK_MSCLK 37
PCI_TRDY# 25 82 SDDATA0_MSDATA0
C 19 PCI_TRDY#
PCI_IR DY# 24
TRDY# MDIO10
81 SDDATA1_MSDATA1
SDDATA0_MSDATA0 37 Function set pin define C
19 PCI_IRDY# IRDY# MDIO11 SDDATA1_MSDATA1 37
PCI_STOP# 29 93 SDDATA2_MSDATA2 UDIO3 UDIO4 MSEN XDEN Function
19 PCI_STOP# STOP# MDIO12 SDDATA2_MSDATA2 37
PCI_DEVSEL# 26 90 SDDATA3_MSDATA3
19 PCI_DEVSEL# DEVSEL# MDIO13 SDDATA3_MSDATA3 37
PCI_AD22 1 2 CBS_IDSEL 8 91 XDD4 Pull-up Pull-up Pull-up Pull-up Enable
IDSEL MDIO14 XDD4 37
R363 100_0402_5% PCI_PERR# 30 89 XDD5 SD,XD,MS,MMC Card
19 PCI_PERR# PERR# MDIO15 XDD5 37
PCI_SERR# 31 92 XDD6
19 PCI_SERR# SERR# MDIO16 XDD6 37
87 XDD7
MDIO17 XDD7 37 +3VS
85 XDCLE
MDIO18 XDCLE 37
PCI_REQ0# 124 83 XDALE
19 PCI_REQ0# REQ# MDIO19 XDALE 37
PCI_GNT0# 123
19 PCI_GNT0# GNT#
58 MSEN MSEN R343 1 2 10K_0402_5%
MSEN XDEN U DIO3 R347 10K_0402_5%
55 Layout Note: Place close to R5C832 Layout Note: Place close to R5C832 1 2
XDEN U DIO4 R342 10K_0402_5%
15 CLK_PCI_1394 121 PCICLK and Shield GND for SDCLK_MSCLK and Shield GND for SD_CLK 1 2
119 94 R5C832XI U DIO5 R344 1 2 100K_0402_5%
19,32,33 PCI_RST# PCIRST# XI
CBS_GRST# 71 95 R5C832XO 1 2
R659 1 GBRST# XO XDEN
2@ 10K_0402_5% 117 CLKRUN#
C489 R345 1 2 10K_0402_5%
70 96 0.01U_0402_16V7K
R658 1 PME# FIL0
21,33 PCI_CLKRUN# 2 0_0402_5% REXT 101 C485
R5_PME# 100 1 2 R5C832XI
33 R5_PME# VREF
10K_0603_1%
0.01U_0402_16V7K
19 PCI_PIRQG# 115 INTA#
2
116 72 SIRQ 2 15P_0603_50V8J
19 PCI_PIRQH# INTB# UDIO0/SERIRQ# SIRQ 21,32,33
2
R656
60 TP_UDIO1 X2 Solve MS Duo Adaptor short problem
UDIO1 PAD T28
C493
56 TP_UDIO2
UDIO2 PAD T29
1 2 69 65 U DIO3 24.576MHz_16P_1BG24576CKIA
+3VS HWSPND# UDIO3 1
R351 10K_0402_5% 66 59 U DIO4 C488
1
TEST UDIO4 U DIO5 R5C832XO R637 2
UDIO5 57 1 2 1 0_0402_5%
18,23,26,29,33,35,42,43,44 SUSP# 1 2
R349 @ 0_0402_5% 111 4 15P_0603_50V8J @ Q42
AGND GND SDDATA1_MSDATA1 SD_MSDATA1
3 2N7002_SOT23
S
107 AGND GND 13 1 SD_MSDATA1 37
103 22 R629 2 1 0_0402_5%
AGND GND
102 AGND GND 28
99 54 Layout Note: Shield GND for @ Q39
G
2
B AGND GND SDDATA2_MSDATA2 B
32N7002_SOT23 SD_MSDATA2
S
GND 62 CBS_CCLK_INTERNAL and CBS_CCLK 1 SD_MSDATA2 37
GND 63 1 2
97 68 R631 0_0805_5%
NC GND +VCC_4IN1
118
G
2
GND
S
GND 122 1 3 +VCC_4IN1_XD
+5VS @ Q38
R5C832_TQFP128~D 2N7002_SOT23
40mil 1 2
G
2
R627 @ 10K_0402_5%
1 2
Layout Note: Place close to R5C832 +3VS U38 +VCC_4IN1 R634 @ 10K_0402_5%
1
+VCC_4IN1 D D
3 1 SDCD#_XDCD0# 2 XDCD# 2
SDPWR0_MSPWR_XDPWR VIN VOUT
270P_0402_50V7K
4 5 G G
VIN/CE VOUT
1
5.1K_0402_1%
1U_0603_10V4Z
150K_0402_5%
0.1U_0402_16V4Z
10U_1206_6.3V6M
1 S S
3
C496
1
0.1U_0402_16V4Z
2 1 1 1 @ Q36 @ Q41
GND
R381
C664
R619
2N7002_SOT23 2N7002_SOT23
C668
C671
1 RT9701CB_SOT25
2
2
2 2 2
C665
CLK_PCI_1394 2
Z3008
1
2
56.2_0402_1%
56.2_0402_1%
4.7P_0402_50V8C10_0402_5%
R365
R366
+3VS
R367
@ D24
100K_0402_5%
MSCD#_XDCD1 2
2
1
1
1 XDCD#
XDCD# 37
R353
JP13 SDCD#_XDCD0# 3
2 IEEE1394_TPBN0 1 5
A IEEE1394_TPBP0 TPB- GND DAN202U_SC70 A
2 TPB+ GND 6
C495
IEEE1394_TPAN0 3 7
2
ME@
2
2
56.2_0402_1%
56.2_0402_1%
1
Layout Note: Shield GND for
2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
C494
C499
R375
R374
1 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
IEEE1394_TPBIAS0 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 28 of 47
5 4 3 2 1
A B C D E
+VDDA
AC97 Codec
1
28.7K for Module Design (VDDA = 4.702)
R358
10K_0402_1% +5VS
U42
(output = 250 mA)
60mil 40mil
2
2 1C473 L31 1 2 4 VIN VOUT 5 +VDDA
KC FBM-L11-201209-221LMAT_0805
2
1U_0603_10V4Z +VDDA L29 1 2 2 DELAY SENSE or ADJ 6 1 4.85V
C685 1 KC FBM-L11-201209-221LMAT_0805 1
R357 1 2 470P_0402_50V8J C734 C724 7 1 R655 C692
10K_0402_1% ERROR CNOISE 150K_0603_1% 10U_0805_10V4Z
1
C689 1U_0603_10V4Z 10U_0805_10V4Z 10U_1206_10V4Z 2
8 3 1
1
2 2 SD GND
1 2MONO_IN1 2 1 MONO_IN C716
R642 20K_0402_5% R648 SI9182DH-AD_MSOP8
1
1 1 2 10K_0402_1% 1
R646 20K_0402_5% 2
2
1
C454 R352 C C694 680P_0402_50V7K LINE_OUTL R654
33 BEEP# 2 1 1 2 2 Q26 0.1U_0402_16V4Z 51K_0603_1%
B 2SC2411K_SC59 C695 680P_0402_50V7K LINE_OUTR +5VS
1
2
1
C453 560_0402_5% E
3
1U_0603_10V4Z NOSWDJ@
1
@ 0.1U_0402_16V4Z R645
2 10K_0402_1%
C459 +5VS 1 2
1
D R905
R348
2
21 SB_SPKR 2 1 1 2 EAPD 2 Q43 10K_0402_1% R900 100_0402_5%
G 2N7002_SOT23 SWDJ@
2
1
1
560_0402_5% D11 S SUB WOOFER SUPPORT
3
1U_0603_10V4Z R356
@ 10K_0402_5% RB751V_SOD323
ALC262
2
1
D
2 Q96
23,33 CD_PLAY 2N7002_SOT23
G ALC861D
S SWDJ@
3
PC Beep for DOS mode
SWDJ
DIRECT PLAY PATH
SWDJ@ +5VALW
C805 +VDDC
1U_0603_10V4Z SWDJ@ R638
14
+3VS
+5VAMP 2 1 1 2 AMP_LEFT
A B AMP_LEFT 30
R788
1
2 2
1M_0402_5% 1 1 1
SWDJ@ R789 SN74HCT4066PW_TSSOP14 L26 C687 C688 C686
7
13
1M_0402_5% CHB1608U301_0603
SWDJ@ 1 2 0.1U_0402_16V4Z 10U_0805_10V4Z
+VDDA 2 2 2
1 1 1
2
25
38
1 2
9
SWDJ@ 2 2 2 U41 C726 @ 1000P_0402_50V7K
C806 +5VALW 0.1U_0402_16V4Z
AVDD1
AVDD2
DVDD1
DVDD2
1U_0603_10V4Z
INT_CD_R1
14
2
U71B SWDJ@
1 2 14 35 C_LINE_OUTL 1 2 LINE_OUTL
P
12
23 LINE1_L HP_OUT_R 41
24 LINE1_R
EC_IDERST1 R792 2 1 20K_0402_5% CD_R_L 6 R644 1 2 HDA_BITCLK_AUDIO
31 EC_IDERST1 23,31 INT_CD_L BIT_CLK HDA_BITCLK_AUDIO 20
R793 2 1 20K_0402_5% C808 1 2 1U_0402_6.3V4Z CD_RC_L 18 22_0402_5%
R794 20K_0402_5% CD_L 250_SDIN R643 1 HDA_SDIN0
2 1 SDATA_IN 8 2 HDA_SDIN0 20
R795 2 1 20K_0402_5% CD_R_R C809 1 2 1U_0402_6.3V4Z CD_RC_R 20 33_0402_5%
23,31 INT_CD_R CD_R
GPIO2 2
SWDJ@ CD_GNA C810 1 2 1U_0603_10V4Z CD_GNDA 19 R354 1 2 C458 1 2
+5VALW CD_GNA CD_GND
C811 POWER ON PATH @ 22_0402_5% @ 22P_0402_50V8J
0.1U_0402_16V4Z MIC 1 2 C_MIC 21
30 MIC MIC1_L
2 1 SWDJ@ C698 2.2U_0603_6.3V6K
14
U71C 1 2 22 3
R796 MIC1_R GPIO3
3 C715 2.2U_0603_6.3V6K 3
P
1M_0402_5% MONO_IN 12 30
PC_BEEP MIC2_VREFO +MIC2_VREFO
SWDJ@ R797 SN74HCT4066PW_TSSOP14
10mil
7
SENSE B 34 1 JACK_PLUG_CODEC 37
U71D EAPD 1 2 47 43 C812 1 2 861@ 1U_0603_10V4Z 39.2K_0402_1%
R799 33 EAPD SPDIFI/EAPD GPIO0
SWDJ@ L24 @ CHB1608U301_0603 44
P
GPIO1 LFE_OUT 31
+5VAMP 2 1 LINE_OUTR 8 9 AMP_RIGHT R800 1 2 48 C813 1 2 861@ 1U_0603_10V4Z
A B 37 SPDIF SPDIFO
10_0402_5% 40
LFILT
1
2
R801 SN74HCT4066PW_TSSOP14 7 42
7
NOSWDJ@
1
R657 1 2 0_0402_5%
EC_IDERST CD_AGND R848 2 1 CD_GNA
33 EC_IDERST 23 CD_AGND
10K_0402_5%
1
+5VALW 10K_0402_5%
R373 1 2 0_0402_5% 1
10mil 1 1
10mil 1 1
10mil 1
2
4 4
@ @ @
2
EC_IDERST1
Q81 SWDJ@
1
D 2N7002_SOT23
2 1 R804 2 @ EC_IDERST
0_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
G
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title
S
ALC861 VD Codec
3
1 2 SUSP#
SUSP# 18,23,26,28,33,35,42,43,44 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
R805 0_0402_5% Size Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
SWDJ@ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 29 of 47
A B C D E
A B C D E
+5VAMP
Window mode
DOS mode DOS mode Driver initial
2
DOS mode
R368 +5VAMP W=40mil
10K_0402_5% ACPI
SWDJ@ NOSWDJ@ 0.1U_0402_16V4Z +3VALW
RST
1 1
31,33 VOLUME 1
R868
2
0_0402_5%
1
C474
1 RST
2
R369 C483
1.5K_0402_1% 4.7U_0805_10V4Z R362
2 2
NOSWDJ@ 10K_0402_5%
@
(0.65V -> 10dB)
2
U19
1
1 MUTE_AMP R371 1 10K_0402_5% 1
10 VDD MUTE 1 2
15 2 AMP_OFF# R372 1 2 0_0402_5% EC_MUTE#
VDD SHUTDOWN#
9 SPKL- L7 1 2 0_0603_5% SPKL-O
VOL_AMP LOUT-
7 VOLUME SPKR- L8 2 0_0603_5% SPKR-O
VOLMAX ROUT- 16 1
EC_MUTE 12sec
NOSWDJ@
1
R377
2
0_0402_5%
8 VOLMAX
LOUT+ 11 SPKL+ L11 1 2 0_0603_5% SPKL+O SPKL+O 31
EC_MUTE 12sec
1 2 BTL# 13
R359 0_0402_5% SE/BTL# SPKR+ L9
ROUT+ 14 1 2 0_0603_5% SPKR+O SPKR+O 31
R376 1 2 10K_0402_5% L IN 6
29 AMP_LEFT LIN-
3 JP20
R378 1 RIN RIN- SPKL+O
29 AMP_RIGHT 2 10K_0402_5% GND 5 1 1
4 12 SPKL-O 2
BYPASS GND SPKR+O 2
1 3 3
+5VAMP APA2068KAI-TRL_SOP16 SPKR-O 4
C491 4
5 G1
2
4.7U_0805_10V4Z 1 1 1 1 6
R914 2 C247 C246 C245 C244 G1
10K_0402_5% E&T_3802-E04N-01R
SWDJ@ @ 47P_0402_50V8J @ 47P_0402_50V8J @ 47P_0402_50V8J
2 2 2 2
1
BTL# @ 47P_0402_50V8J
BTL# 31
1
D
2 Q99
33 JACKCTL
G 2N7002_SOT23
SWDJ@
S
INT MIC
3
1
Q89
1
R664 R854
SI3445DV_TSOP6 3K_0402_5% 3K_0402_5%
R667
D
2
3K_0402_5%
S
6
4 5 L12
2
2 1 2 FBM-11-160808-601-T_0603
29 MIC EXT_MIC 37 INT_MIC_L 29,36 INT_MIC_R 29,36
1 1
G
1 2
C865 1 1 1
3
PLAY_MODE
PLAY_MODE 23
31 HP_L_SWDJ
3 3
31 HP_R_SWDJ
+3VS
JACK_PLUG
JACK_PLUG 33,37
R652 1 2 NOSWDJ@ R662 47_0402_5%
19
10
SVDD
1
EC_MUTE# 1 2 14 11 HP_OUTR R666 R665 1 1
31,33 EC_MUTE# SHDNR# OUTR C731 C729
D39 RB751V_SOD323 18 9 HP_OUTL 47P_0402_50V8J 47P_0402_50V8J
SHDNL# OUTL 1K_0402_5% 1K_0402_5%
SWDJ@ 2 2
2
NC-4 4
29 HP_R 15 INR
NC-6 6
29 HP_L 13 INL
NC-8 8
NC-12 12
1 C1P NC-16 16
4 4
1
PGND
SGND
3 20
PVss
SVss
17
1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title
C478
2
1U_0603_10V4Z
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMP & Audio Jack
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 26, 2006 Sheet 30 of 47
A B C D E
SWDJ SUBWOOFER (Reserved for C38)
SWDJ@ WOOFER@ +AUD_VREF_LF +5VAMP
C860
1U_0603_10V4Z DIRECT PLAY PATH C814 1U_0603_10V4Z C815 1U_0603_10V4Z
1 2 +5VALW 1 2 +AUD_VREF_LF 1 2
23,29 INT_CD_L
C861
1U_0603_10V4Z SWDJ@ SWDJ@ C816 1 2 0.1U_0603_50V4Z
14
1 2 U75A 1 2 U72A +5VAMP
23,29 INT_CD_R
8
0_0402_5% SWDJ@ C817 TLV2462CDR_SO8
8
2 1 1 LFE_OUT 0.1U_0402_16V4Z
B 2 R9171 2 3 R806 R807
P
+5VAMP A LFE_OUT 29 + C819
R858 1 2 1 2 1 5
P
O +
C
1M_0402_5% LFE_OUT R808 1 2 1 2 C818 2 7 2 1 MIX_OUT
29 LFE_OUT - O
G
SWDJ@ R859 SN74HCT4066PW_TSSOP14 560_0402_5% 560_0402_5% 6
13
-
G
1M_0402_5% 100K_0402_5% 1U_0603_10V4Z U72B 0.22U_0603_10V7K
4
SWDJ@ 2 TLV2462CDR_SO8
4
R809 C820
10mil
2
2 1 100K_0402_5%
+5VAMP 0.1U_0603_50V4Z
C821 1 100P_0402_50V8J 1
2
EC_IDERST1
Gain = 3.1dB
1
@
R810
+5VALW
100K_0402_5% Fc(LPF)= 1.5KHz
20mil
2
14
+AUD_VREF_LF
U75B SWDJ@
P
2 +5VAMP
1
11 10 C822
A B R811
G
2
C
100K_0402_5%
SN74HCT4066PW_TSSOP14 1U_0603_10V4Z 1 R869 +5VAMP W=40mil
7
12
10K_0402_5%
(0.65V -> 10dB)
2
NOSWDJ@ 0.1U_0402_16V4Z +3VALW
1 1
30,33 VOLUME 1 2 1 1
R870 0_0402_5% C868
2
SWDJ@ SWDJ@ R871 C869
SWDJ@ +5VALW POWER ON PATH 1.5K_0402_1% 4.7U_0805_10V4Z R872
C862 2 2
C863 0.1U_0402_16V4Z NOSWDJ@ 10K_0402_5%
1U_0603_10V4Z SWDJ@ @
14
2 1
2
1 2 U75C C870 SWDJ@ U76
30 SPKL+O
1
0_0402_5% SWDJ@ 1U_0603_10V4Z 10 1 MUTE_AMP_1 R874 1 2 10K_0402_5%
P
2
C
1M_0402_5% 9
R861 SN74HCT4066PW_TSSOP14 R876 VOL_AMP LOUT-
SWDJ@ 30 BTL# 7
7
VOLUME WOOF-
1M_0402_5% @ 0_0402_5% ROUT- 16 L60 1 2 0_0603_5% W OOFER-
SWDJ@ 1 R862 2 @ 0_0402_5% 1 2 VOLMAX 8 VOLMAX
NOSWDJ@ R877 0_0402_5% 11
2
1
BTL# LOUT+
1 2 13 SE/BTL#
R878 0_0402_5% @ 14 WOFF+ L61 1 2 0_0603_5% WOOFER+
MIX_OUT R879 1 W IN1 ROUT+
2 10K_0402_5% 6 LIN-
SWDJ@ 3
C864 +5VALW MIX_OUT R880 1 W IN2 RIN-
2 0_0402_5% GND 5
1U_0603_10V4Z 4 12
SWDJ@ SWDJ@ BYPASS GND
14
30 SPKR+O 1 2 1
U75D C871 APA2068KAI-TRL_SOP16
R863
0_0402_5% SWDJ@ 1U_0603_10V4Z C872
P
+5VAMP 2 1 8 9 1 2 1 2 4.7U_0805_10V4Z
A B HP_R_SWDJ 30 2
R881
1
2
C
SWDJ@
1M_0402_5% R864 SN74HCT4066PW_TSSOP14 R882
SubWoofer Conn.
7
1M_0402_5% @ 0_0402_5%
SWDJ@ 1 R865 2 @ 0_0402_5%
30mil
2
FBMA-L11-160808-700LMT_0603 JP75
W OOFER- L51 1 2 WO- 1
EC_IDERST1 WOOFER+ L50 WO+ 1
29 EC_IDERST1 1 2 2 2
FBMA-L11-160808-700LMT_0603
3 GND
4 GND
MOLEX_53780-0270
ME@
+USB_VCCA
1000P_0402_50V7K
1
USB Port C565 + C266
1 1
C275
150U_D_6.3VM
2 2 2
0.1U_0402_16V4Z
+5VALW
ME@
+USB_VCCA SUYIN_020173MR004S558ZL
U4 1 1
1 GND OUT 8 21 USB20_N0 2 2
C338 0.1U_0402_16V4Z 2 7 3
IN OUT 21 USB20_P0 3
2 1 3 IN OUT 6 4 4
2
33,37 USB_ON USB_ON 4 5 5
EN# FLG USB_OC#0 21 D1 GND
6 GND
G545C1P1U_SO8 @ PSOT24C_SOT23 7 GND
8 GND
1
C336 JP21
1
@ 1000P_0402_50V7K For EMI
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Bluetooth & USB CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 26, 2006 Sheet 31 of 47
5 4 3 2 1
SW2
1 3
Power BTN
2 4
6
5
D D
SW1
+3VALW
1 3
1
2 4
KSI[0..7] KSI1 @ C186 1 2 100P_0402_50V8J R255
KSI[0..7] 33,36
SMT1-05_4P 100K_0402_5%
6
5
KSI7 @ C182 1 2 100P_0402_50V8J
KSO[0..15]
KSO[0..15] 33
2
KSI6 @ C169 1 2 100P_0402_50V8J D7
2 ON/OFF ON/OFF# 33
KSO9 @ C171 1 2 100P_0402_50V8J ON/OFFBTN# 1
36 ON/OFFBTN#
3 51ON# 51ON# 36,39
KSI4 @ C172 1 2 100P_0402_50V8J
+3VALW DAN202U_SC70
KSI5 @ C183 1 2 100P_0402_50V8J Q18
JP26
1
KSI1 1 KSO0 @ C184 1 2 100P_0402_50V8J DTC124EK_SC59 1
1
1
KSI7 2 R256 D6
KSI6 2 KSI2 @ C185 1
3 3 2 100P_0402_50V8J 4.7K_0402_5% RLZ20A_LL34
KSO9 4
KSI4 4 KSI3 @ C176 1 2 C379
5 2 100P_0402_50V8J
2
KSI5 5 EC_ON 1000P_0402_50V7K
6 6 33,40 EC_ON 1 2 2
KSO0 7 KSO5 @ C177 1 2 100P_0402_50V8J R261 33K_0402_5%
KSI2 7
8 8
KSI3 9 KSO1 @ C178 1 2 100P_0402_50V8J
KSO5 9
10
3
KSO1 10 KSI0 @ C187 1
11 11 2 100P_0402_50V8J
KSI0 12 12
1
KSO2 KSO2 @ C188 1 D
13 13 2 100P_0402_50V8J
KSO4 14 2
KSO7 14 KSO4 @ C189 1
15 15 2 100P_0402_50V8J G
C KSO8 Q19 C
16 S
3
KSO6 16 KSO7 @ C173 1
17 17 2 100P_0402_50V8J 2N7002_SOT23
KSO3 18
KSO12 18 KSO8 @ C174 1
19 19 2 100P_0402_50V8J
KSO13 20
KSO14 20 KSO6 @ C175 1
21 21 2 100P_0402_50V8J
KSO11 22
KSO10 22 KSO3 @ C191 1
23 23 2 100P_0402_50V8J
KSO15 24 24 KSO12 @ C192 1 2 100P_0402_50V8J
ACES_85202-2405
KSO13 @ C193 1 2 100P_0402_50V8J
1BS003-1211L_3P
B B
+3VALW
2
JP58 R888
1
1
2 2
+5VS FOR LPC SIO DEBUG PORT 100_0603_5%
NOTV@
3 +3VS
1
3
4 4
5 R819 TV@
5 RCIRRX
6 6 CLK_14M_SIO 15 33 RCIRRX 1 2
7 LPC_AD0 LPC_AD[0..3]
7 LPC_AD[0..3] 20,33
8 LPC_AD1 33_0402_5% 1
8 LPC_AD2
9 9
10 LPC_AD3 C827 TV@
10 LPC_FRAME#
11 11 LPC_FRAME# 20,33 22P_0402_50V8J
LPC_DRQ#0 R622 2
12 12 LPC_DRQ#0 20
13 PCI_RST# 10K_0402_5% +5VALW
13 PCI_RST# 19,28,33
14 2 1 TV@ IR1
14
15 15 CLK_PCI_DB 15 1 2 1 Vout
16 SIRQ +5VS R817 100_0603_5%
16 SIRQ 21,28,33
17 17 1 2 2 VCC
18 R818 100_0603_5%
1
18 @ C826
19 19 3 GND
20 20
4.7U_0805_10V4Z 4
ACES_85201-2005 2 GND
ME@ IRM-V538/TR1_3P
A TV@ A
CIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KBD,ON/OFF,T/P,LED/B,DEBUG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 32 of 47
5 4 3 2 1
5 4 3 2 1
+3VALW
Analog Board ID definition,
L5
1 2 Please see page 3.
+3VALW +EC_AVCC
FBM-11-160808-601-T_0603 2 1
C397 +3VALW +3VALW
C398
0.1U_0402_16V4Z 1 1 1 1 1 1
+EC_AVCC
0.1U_0402_16V4Z
C382
0.1U_0402_16V4Z
C431
0.1U_0402_16V4Z
C437
0.1U_0402_16V4Z
C439
1000P_0402_50V7K
C425
1000P_0402_50V7K
C413
1000P_0402_50V7K
2
1 ECAGND 2
1 2 ECAGND
L6 FBM-11-160808-601-T_0603 R574 R915 UMA@
2 2 2 2 2 2 100K_0402_1% 100K_0402_1%
1
111
125
22
33
96
67
U20
9
BRD_ID C HIP_ID
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
2
D D
1
BATT_TEMP 2 1 ECAGND R578 C621 R916
56K_0402_5%
C381 0.01U_0402_16V7K 10K_0402_5%
0.1U_0402_16V4Z
RB751V_SOD323 1 21 INVT_PWM VGA@
20 GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM 16 2
2 1 KB_RST#R 2 23 BEEP#
20 KB_RST# BEEP# 29
1
D9 KBRST#/GPIO01 BEEP#/PWM2/GPIO10 ENLAN1 R898
21,28,32 SIRQ 3 SERIRQ# FANPWM1/GPIO12 26 1 2 EN_WOL 24
4 27 ACOFF 0_0402_5%
20,32 LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF 39,40
LPC_AD3 5
20,32 LPC_AD3 LAD3
LPC_AD2 7 PWM Output
20,32 LPC_AD2 LAD2
LPC_AD1 8 63 BATT_TEMP
20,32 LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP 46
LPC_AD0 BATT_OVP
20,32 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64 BATT_OVP 40
15 CLK_PCI_LPC ADP_I/AD2/GPIO3A 65 ADP_I 40
12 AD Input 66 BRD_ID
PCICLK AD3/GPIO3B BRD_ID
2 1 2 1 13 75
R312@ 10_0402_5%
EC_RST#
+3VALW 1 2
19,28,32 PCI_RST#
EC_RST# 37
PCIRST#/GPIO05
ECRST#
AD4/GPIO42
SELIO2#/AD5/GPIO43 76 C HIP_ID ID BRD ID R578(Rb) Vab
C422 R224 47K_0402_5% EC_SCI# 20
21 EC_SCI# SCI#/GPIO0E
@ 22P_0402_50V8J 0 R01 (EVT)
21,28 PCI_CLKRUN# 1
R223
2
@ 0_0402_5%
38 CLKRUN#/GPIO1D
68 DAC_BRIG
0 0V
DAC_BRIG/DA0/GPIO3C DAC_BRIG 16
EN_FAN1 1 R02 (DVT)
36 MODE_LED#
DA Output
EN_DFAN1/DA1/GPIO3D 70
71 IR EF
EN_FAN1 4 8.2K 0.25V
2 IREF/DA2/GPIO3E IREF 40
C377 KSI0 2 R03 (PVT)
KSI1
55
56
KSI0/GPIO30 DA3/GPIO3F 72 VOLUME 30,31
0_0402_5%
18K 0.50V
0.1U_0402_16V4Z KSI1/GPIO31
KSI2 2 @ 3 R10A (MP)
1 KSI3
57
58
KSI2/GPIO32
83
1
R294
EN_WOL 24 33K 0.82V
KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE# 30,31
KSI4 4
KSI5
59
60
KSI4/GPIO34 PSDAT1/GPIO4B 84
85
USB_ON 31,37 56K 1.19V
KSI5/GPIO35 PSCLK2/GPIO4C TP_LOCK_LED# 36
KSI6 PS2 Interface 5
KSI7
61
62
KSI6/GPIO36 PSDAT2/GPIO4D 86
87 TP_CLK
CMOS_OFF# 36 100K 1.65V
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK 37
KSO0 TP_DATA 6
KSO1
39
40
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA 37 200K 2.20V
KSO2 KSO1/GPIO21
KSO3
41 KSO2/GPIO22 SPI_PULLDOWN R3361
7 NC 3.30V
ISP MODE SUPPOR 42 KSO3/GPIO23 SDICS#/GPXOA00 97 2 4.7K_0402_5%
C KSO4 C
KSO3 KSO5
43 KSO4/GPIO24 SDICLK/GPXOA01 98 BT_OFF# 27 R119(Ra)=100K Ohm
+3VALW
2
R231
1
@ 4.7K_0402_5% KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99 CD_PLAY 23,29
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 MODE# 36
KSO7 +3VS
46 KSO7/GPIO27 SPI Device Interface
KSO8 47 KSO8/GPIO28
2
R288 4.7K_0402_5% 1 1
GND
GND
GND
GND
GND
C417 C415
XCLKO 1 R338 2 XCLKI
@ 100P_0402_50V8J @ 100P_0402_50V8J KB926QFA1_LQFP128 @ 20M_0603_5%
11
24
35
94
113
69
2 2
ECAGND
ECAGND
C443 C442
4
15P_0402_50V8J
15P_0402_50V8J
IN
OUT
EC DEBUG PORT
JP59
NC
NC
+3VALW 1 1
A EC_TX_P80_DATA A
2
3
EC_RX_P80_CLK 2
3 3
4 4
ACES_85205-0400 X1
ME@
32.768KHZ_12.5P_1TJS125BJ2A251
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ENE-KB925
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 26, 2006 Sheet 33 of 47
5 4 3 2 1
C658
+3VALW SPI Flash (8Mb*1)
1 2
2
0.1U_0402_16V4Z
20mils
U36
R885 8 4
10K_0402_5% VCC VSS
1
3 W
7 HOLD
FSEL#SPICS# 2 1 SPI_CS# 1
33 FSEL#SPICS# S
R670 15_0402_5%
SPI_CLK 2 1 SPI_CLK_R 6
33 SPI_CLK C
R617 15_0402_5%
FWR#SPI_SI 2 1 SPI_SI 5 2 SPI_SO 2 1
33 FWR#SPI_SI D Q FRD#SPI_SO 33
R611 15_0402_5% R613
SST25LF080A_SO8-200mil 15_0402_5%
R908 2 1 SPI_CLK_R
33_0402_5%
22P_0402_50V8J
1 JP11
C879 SPI_CS# 1 2 +3VALW
SPI_SO 1 2
3 3 4 4
2 SPI_CLK_R
+3VALW 5 5 6 6
7 8 SPI_SI
7 8
E&T_2941-G08N-00E~D
ME@
+5VALW
+5VALW
1
C364
1 2 0.1U_0402_16V4Z R215
100K_0402_1%
U7
2
8 VCC A0 1
7 WP A1 2
33,46 EC_SMB_CK1 6 SCL A2 3
33,46 EC_SMB_DA1 5 SDA GND 4
AT24C16AN-10SU-2.7_SO8
1
R221
100K_0402_1%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & EC I/O Port
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 34 of 47
A B C D E F G H I J
+5VALW
1
J1
+3VALW PAD-OPEN 3x3m R339
1 2 +3V_SB
+5VALW to +5VS Transfer
1 47K_0402_5% 1
2
U77 +5VALW +5VS SYSON#
SYSON#
8 D S 1
1
7 2 U16 0.1U_0402_16V4Z
D S
6 D S 3 1 1 8 D S 1
+VSB 5 4 C876 C465 7 2 Q24
D G 1 D S
C874 +VSB 10U_0805_10V4Z 6 3
D S 1 1
SI4800DY_SO8 5 4 2
D G 26,33,42 SYSON
1
@ 2 2 0.1U_0402_16V4Z C468 C471
1
R903 10U_0805_10V4Z 2 SI4800DY_SO8 10U_0805_10V4Z
@ 33K_0402_5% R346 2 2
22K_0402_5% DTC124EK_SC59
3
2
2
RUNON
2 1 2
1
D @ C875 1
1
STB_SB# 0.1U_0603_25V7K D C457
33 STB_SB# 2
G SUSP 2 0.1U_0603_25V7K +5VALW RTCVREF
Q94 S 2 G
3
2N7002_SOT23 @ Q25 S 2
1
2N7002_SOT23
R183 R856
@
10K_0402_5% 10K_0402_5%
2
SUSP
43 SUSP
1
Q14
3 3
18,23,26,28,29,33,42,43,44 SUSP# 2
DTC124EK_SC59
3
+3VALW to +3VS Transfer
+3VALW
+3VS
U37 0.1U_0402_16V4Z
8 D S 1
1 7 D S 2
+VSB C667 6 3 +1.8VS +0.9VS
D S 1 1
10U_0805_10V4Z 5 4 C662 C652 +5VS
4 D G 4
1
2 SI4800DY_SO8 10U_0805_10V4Z
R625 2 2
1
33K_0402_5%
R191 R99 R186
2
R623 1 2 RUNON 470_0402_5% 470_0402_5% 470_0402_5%
@ 0_0402_5% VGA@
1 2
1 2
1 2
1
1
D C666 D D D
SUSP 2 0.1U_0603_25V7K 2 SUSP 2 SUSP 2 SUSP
G G G G
Q37 S 2 S Q15 S Q5 S Q16
3
2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23
VGA@
5 5
1
R111 R326 R495
+1.8V to +1.8VS Transfer 470_0402_5% 470_0402_5% 470_0402_5%
1 2
1 2
1 2
+1.8V
+1.8VS VGA@ D D D
U25 0.1U_0402_16V4Z 2 SYSON 2 SUSP 2 SUSP
8 1 G G G
D S Q6 Q22 Q29
6 1 7 2 S S S 6
3
+VSB C539 D S 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23
6 D S 3 1 1
VGA@ 5 4 C537 C538
10U_0805_10V4Z D G VGA@
2
2 SI4800DY_SO8 10U_0805_10V4Z
R115 VGA@ 2 2
47K_0402_5%
VGA@ +1.25VS
1
R114 1 2 RUNON
1
@ 0_0402_5%
1 R333
1
D C269
SUSP 2 0.1U_0603_25V7K 470_0402_5%
G VGA@
1 2
Q7 S 2
3
2N7002_SOT23 D
7 7
VGA@ 2 SUSP
G
S Q23
3
2N7002_SOT23
8
Security Classification Compal Secret Data Compal Electronics, Inc. 8
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Circuit
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 35 of 47
A B C D E F G H I J
5 4 3 2 1
D
B B A B A 3 1 1
1
+5VS AO3413_SOT23
2
CMOS@ R907 Q97
G
2
2
R912
10K_0402_1% CMOS@
0_0805_5%
1 2
D CMOS1 D
Wireless / Bluetooth LED JP42
1
LED1 0_0402_5% 1
Blue 21 USB20_N3 USB20_N3 2 1 R394 2
1
R820 1 2
27 WIRELESS_LED# 2 150_0402_5% 1 2 21 USB20_P3 USB20_P3 2 1 R393 3 3
2 0_0402_5% 4
33 CMOS_OFF# 4
Q98 1 5
BTONLED R821 5
1 2 220_0402_5% 4 3 DTC124EK_SC59 6
( 1 ) 27 BTONLED
CMOS@ C880
10U_0805_10V4Z
7
GND1
GND2
3
HT-297UD/NB_BLUE/AMB_0603 2 ACES_88266-05001
Amber ME@
STATUS
AC BLUE
Chargin Blinking Blue
Low BATT Amber
+5VALW
( 2 ) BATT_CHG_LED#
Blue
LED2 +3VALW
33 CHARGE_LED0#
CHARGE_LED0# R822 1 2 150_0402_5% Left Switch BD(AUDIO DJ)
1 2
+3VALW
4 3 +5VALW
1
CHARGE_LED1# R823 1 2 220_0402_5% JP76
C 33 CHARGE_LED1# C
R904 1
HT-297UD/NB_BLUE/AMB_0603 100K_0402_5% 1
BATT_LOW_LED# Amber 2
3
2
33 KSO17 3
4
2
D38 33 KSO16 4
32,33 KSI4 5 5
32,39 51ON# 2 32,33 KSI3 6 6
1 DJ_ON 7
( 3 ) PWR_LED# R824 1 2 150_0402_5% 1
LED3
2
33 MODE# 3 33 MODE_LED#
R913 1 2 150_0402_5%8
9
7
8
33 PWR_LED# 9
DAN202U_SC70 10
29,30 INT_MIC_R 10
11
Blue : Power On, HT-191NB5-DT_BLUE_0603~D 12
11
29,30 INT_MIC_L 12
Blinking Blue : Suspend 13
14
GND
GND
MOLEX_53780-1270
+3VS
LED4
27 3G_LED# 2 1 1 2
R661 200_0402_5%
HT-191NB5-DT_BLUE_0603~D +3VS
STATUS +5VALW +5VS +VCC5_LED Right Switch BD
C830
AC BLUE 1 2 1 2
R827 0_0402_5% 100K_0402_5% 100K_0402_5%
Chargin Blinking Blue
1
+3VS 1 2
R828 0_0402_5% 1000P_0402_50V7K R830 R831
LED5 Low BATT Amber @
B @ @ B
33 TP_LOCK_LED# 1 2 1 2
Dial Wheel
2
470_0402_5% R836 ACES_87151-16071
HT-191NB5-DT_BLUE_0603~D 16 18
KSO16 16 G18
33 KSO16 15 15 G17 17
KSI1 14
32,33 KSI1 KSI0 14
32,33 KSI0 13 13
KSO17 12
33 KSO17 12
32,33 KSI2 11 11
NOVO_BTN# 10 10
Function 9 9
32 ON/OFFBTN# 8 8
7 7
KEY Matrix KO16 KO17 R887 1 2 220_0402_5% 6
33 SCROLL_LED# R832 220_0402_5% 6
NOVA_BTN# 33 NUM_LED#
R833
1 2
220_0402_5%
5 5
33 CAPS_LED# 1 2 4 4
KSI0 DW-UP DW-DOWN D34 1 2 R834 1 2 220_0402_5% 3
20 SATA_LED# 3
CH751H-40_SC76
HDD 2 2
KSI1 DW-ENTER MUTE CD-ROM D35 1 2
1 1
23 ODD_LED# JP77
CH751H-40_SC76
+3VALW
+3VALW 1 2 0.1U_0402_16V4Z
R391 0_0402_5% 1 1
2
R392 R668
1
47K_0402_5% 100K_0402_5%
VDD
R835 2 2
D26 100K_0402_5%
NOVO BTN
1
1 OUTPUT 3 1 2 LID_SWITCH# 33
C519 RB751V_SOD323 D36
2
0.1U_0402_16V4Z 1 2 NOVO_IN#
GND
A
NOVO_IN# 33 A
C521 NOVO_BTN# 1 C839, C841, C842 For EMI Solution
2 10P_0402_25V8K 51ON#
3 51ON# 32,39
U21
1
2 DAN202U_SC70
A3212ELHLT-T_SOT23W-3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
INDICATE LED
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 36 of 47
5 4 3 2 1
5 4 3 2 1
1
USB20_N4 10
21 USB20_N4 10
R894 USB20_P4 11
29 JACK_PLUG_CODEC 21 USB20_P4 11
SWDJ@ 12
2.2K_0402_5% EXT_MIC 12
30 EXT_MIC 13 13
SPDIF 14
29 SPDIF
2
JACK_PLUG_MIC 14
29 JACK_PLUG_MIC 15 15
16 16
3
E
MMBT3906_SOT23 PL 17
B 30 PL 17
2 JACK_PLUG 18
SWDJ@ PR 18
C 30 PR 19 19
20
1
@ 20
Q91
0.1U_0402_16V7K ACES_87213-2000
C517 ME@
T/P Board 1
R895
2
0_0402_5% C518
0.1U_0402_16V7K
NOSWDJ@ @
33 JACK_PLUG
JP70
1 1 +5VS
2 2
3 TP_DATA TP_DATA 33 1 2 C513 SPDIF 1 2 C878 EXT_MIC
3 TP_CLK 470P_0402_50V8J 470P_0402_50V8J
9 9 4 4 TP_CLK 33
10 10 5 5 1 2 C512 JACK_PLUG_MIC
6 470P_0402_50V8J
6
7 7 1 2 C516 PR
8 470P_0402_50V8J
8
1 2 C515 JACK_PLUG
B ACES_87151-0807G 470P_0402_50V8J B
ME@ 1 2 C514 PL
470P_0402_50V8J
+5VALW
+USB_VCCB
U15
1 GND OUT 8
C464 0.1U_0402_16V4Z 2 7
IN OUT
2 1 3 IN OUT 6
31,33 USB_ON USB_ON 4 5
EN# FLG USB_OC#2 21
G545A1P1U_SO8 USB_OC#4 21
1
C476
@ 1000P_0402_50V7K
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
INDICATE LED
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 37 of 47
5 4 3 2 1
A B C D E F G H I J
1 1
NB
2 IMVP VGATE 2
PWROK
VR_ON
EC VRMPWRGD
CK505
CK_PWRGD
ICH_POK ICH8
PWROK
3 3
4 4
FM8 FM7 FM6 FM5 FM4 FM1 FM2 FM11 FM3 FM9
1 1 1 1 1 1 1 1 1 1
1
H24 H1 H4 H7 H12 H11 H23 H5 H13 H17 H30
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1
6 6
H9 H14 H15 H16 H18 H19 H8 H31 M2
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1
7 7
8
Security Classification Compal Secret Data Compal Electronics, Inc. 8
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Hole
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom IGT30 LA-3571P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 38 of 47
A B C D E F G H I J
A B C D
2 2 1 1 2 1K_1206_5%
2
10_1206_5%
1 2
1
100P_0402_50V8J
560P_0402_50V7K
3 3
100P_0402_50V8J
PR1
560P_0402_50V7K
PQ1
1
4 PD2 PR3 TP0610K-T1-E3_SOT23
4
PC1
PC2
PC3
PC4
RLS4148_LLDS2 1K_1206_5%
VS 2 1 1 2 3 1
1 2
RLZ24B_LL34
@ JST_B4B-EH-A(LF)(SN) PR4
PD1
1K_1206_5%
1 2
100K_0402_5%
100K_0402_5%
1
1
PR8
PR6
PR7
1K_1206_5%
2
PR175 PC131 1 2
@ 10K_0402_1% @ 0.01U_0402_25V7K
1 2 1 2
2
VIN
PR5
VIN 1M_0402_1%
1 2
10K_0805_5%
100K_0402_5%
1
1
82.5K_0402_1%
1
VS
PR9
PR13
1
PR10
PR11
10K_0402_5% PQ2
1 2 DTC115EUA_SC70-3
1 2
PR12 ACIN 21,33
2
2 215K_0402_1% PU1A 2 2
+
0.068U_0603_25V7M
1 PACIN DTC115EUA_SC70-3
O PACIN 40
24.9K_0402_1%
2 - B+
1
G
0.1U_0402_16V7K
RLZ4.3B_LL34
10K_0402_1%
2
3
1
1
PR14
LM393DT_SO8
4
PC5
PC6
PR15
PD3
Vin Detector
2
2
2
3
PR16
2
2
10K_0402_1%
2 1 RTCVREF
3.3V High 18.135 17.566 17.011
Low 14.866 14.355 14.063 VL
PR17
2.2M_0402_5%
2 1
VIN
RLS4148_LLDS2
499K_0402_1%
2
1
VS
PD4
0.01U_0402_25V7K
PR18
100K_0402_1%
1
1
PR19
PC191
PD5
2
RLS4148_LLDS2
2 1 68_1206_5%
3.3V
2
BATT+
1
1
VS
68_1206_5%
PD6
8
RTCVREF
PR276
PR20
RB715F_SOT323
41,46 MAINPWON 2 5
P
3 3
PU2 PQ4 +
1 7 O
0.01U_0402_25V7K
205K_0402_1%
499K_0402_1%
PR22 G920AT24U_SOT89 PR23 TP0610K-T1-E3_SOT23 40 ACON 3 6
2
2
-
1
PR21 560_0603_5% 200_0805_5%
PC7
PR24
PR25
1000P_0402_50V7K
560_0603_5%
1 2 1 2 3 2 2 1 CHGRTCP 3 1 PR271
4
OUT IN
1
0.22U_1206_25V7K
200K_0402_1% PU1B
1
PC9
4.7U_0805_6.3V6K
0.1U_0603_25V7K
PC10
1U_0805_25V4Z
2
1
GND
0.1U_0603_25V7K
PC11
PC13
100K_0402_5%
PRG++ 2
2
1
PC8
PR26
PC12
2
1
2
2
2
2
PR27
2
22K_0402_1% PQ5
1 2 PR28 RHU002N06_SOT323 PR29
32,36 51ON#
1
10K_0402_5% D 47K_0402_5%
2 1 2 2 1
RTCVREF G PACIN 40
1
S
3
66.5K_0402_1%
PQ6
1
DTC115EUA_SC70-3
PR30
2 +5VALWP
@
3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN/DETECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 39 of 47
A B C D
A B C D E
5 5 1 2
2200P_0402_50V7K
4.7U_1206_25V6K
0.1U_0603_25V7K
4
200K_0402_1%
0.1U_0603_25V7K
4.7U_1206_25V6K
BATT+
1 PR272 1
4
1
PR48 100K_0402_1%
1
PC27
PR46
PC23
PC24
PC25
PC26
47K_0402_1% 1 2
P3 1 2
VIN
1
1
47K_0402_5%
10K_0402_1%
33 ADP_I 2 1
10K_0402_1%
PR47
PR273
2
2
PR110 PD23
A/D
PR50
PC133 10K_0402_5% 1SS355TE-17_SOD323-2
ACOFF 33,39
0_0402_5%
0.22U_0603_16V7K 1 2
2
3 2
3
PR49
PQ12 PU4
DTA144EUA_SC70 MB39A126PFV-ER_SSOP24
1
47K
1 -INC2 +INC2 24 47K
3
2
1
2 PR51 PC28 PR52 PQ13 PR336
2
47K
10K_0402_1% 4700P_0402_25V7K 100K_0402_1% AO4407_SO8 200K_0402_1% 2
47K
1
MB39A126 1 2 1 2 2 1 2 23 1 2
OUTC2 GND VIN
1
PC29 4 PQ14
0.22U_0603_16V7K DTC115EUA_SC70-3 PQ40
3 22 CS 1 2 PD34 DTC115EUA_SC70-3
1
+INE2 CS
1
DTA144EUA_SC70
PC30 2 1 21SS355TE-17_SOD323-2
1
34.8K_0402_1%
PQ41
PQ15 0.1U_0603_25V7K 2
10K_0402_1%
0.01U_0402_25V7K
DTC115EUA_SC70-3 4 21 1 2 PRECHG 39
-INE2 VCC
1
D
5
6
7
8
1
PC31
PR53
PR54
2 65W: PR54=34.8K PC243 2 PACIN 39
3
5 20 0.1U_0603_25V7K G
90W: PR54=21.0K
3
ACOK OUT
RHU002N06_SOT323-3
PC32 S
2
3
0.1U_0603_25V7K
2
PQ49
LXCHRG
6 19 1 2
3
VREF VH
1
150K_0402_1%
0.22U_0603_16V7K
PR55
1
1
D PC33 PL5
7 ACIN XACOK 18
BATT+
2 PR57 PC34 PR58 ACON 16UH_LF919AS-160M=P3_3.7A_20%
G 1K_0402_1% 2200P_0402_50V7K 56.2K_0402_1% ACON 39 1 2 1 2
2
2 MB39A1261 PR56 2
S 2 1 2 8 17 1 2
3
-INE1 RT
1
EC31QS04
EC31QS04
PQ16 0.02_2512_1%
PD10
PD11
RHU002N06_SOT323
10U_1206_25VAK
10U_1206_25VAK
10U_1206_25VAK
9 16 PR278
PR60 PR61 +INE1 -INE3 PC35 @ 0_0402_5%
1
PC36
PC37
PC38
IREF 133K_0402_1%
33 10K_0402_1% PR62 1500P_0603_50V7K
2
1 2 2 1 10 15 MB39A126
1 2 1 2
1
OUTC1 FB123
1
2
100K_0402_1%
0.01U_0402_25V7K
2 33K_0402_1%
1
PC39
G 11 14
SEL CTL
PR63
RHU002N06_SOT323 10P_0402_50V8J
2
12 -INC1 +INC1 13 1 2
2
0_0402_5%
PD25 RB751V-40TE17_SOD323-2
2
100K_0402_5%
PR65
1 2
FSTCHG 33
PR66
PR337
3K_0402_1% PD26 RB751V-40TE17_SOD323-2
1
39 PACIN 1 2 1 2
EC_ON 32,33
+3VALWP
39 ACON
47K_0402_5%
CS
1
1
PR67
PC41
1
PQ48 47P_0402_50V8J
DTC115EUA_SC70-3 PQ18 1 2
DTC115EUA_SC70-3
2
33,39 ACOFF 2
3 3
2
LI-3S :13.5V----BATT-OVP=1.5V
1
CC=2.746A
PQ19
BATT-OVP=0.1112*BATT+
3
DTC115EUA_SC70-3 (100K/(100K+133K))*2.56V=1.0985V
3
33 FSTCHG
2
BATT+
1.098/(20*0.02)=2.746A
499K_0402_1% 340K_0402_1%
1
VS
3
PR68
0.01U_0402_25V7K
CP Point=2.8A
2
1
PC42
1
5V*(10K/(34.8K+10K))=1.116V
PR69
2
1.116V/(20*0.02)=2.8A
2
8
PR277
10K_0402_1% 5
P
+
VS 33 BATT_OVP 2 1 7 0
- 6
G
105K_0402_1%
A/D
0.01U_0402_25V7K
PU12B
4
1
PR72
PU12A LM358DR_SO8
Charge voltage
8
PC43
LM358DR_SO8
+ 3 3S CC-CV MODE : 12.6V
P
2
1
2
0
4
- 2 SEL is L 4
G
4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 40 of 47
A B C D E
A B C D
B+
2
PC45 PC46
PL6 0.1U_0603_25V7K 0.1U_0603_25V7K
FBMA-L11-322513-201LMA40T_1210 1 2 BST5B BST3B 1 2
2
1
VL
1 PD13 1
1
SI4800BDY-T1-E3_SO8
CHP202UPT_SOT323-3
MAX8743_B+
2200P_0402_50V7K
8
7
6
5
10U_1206_25VAK
MAX8743_B+
D
D
D
D
1
0_0402_5%
PQ21
PC50
PC51
PR74
4.7_1206_5%
SI4800BDY-T1-E3_SO8
MAX8743_B+
0.1U_0402_16V7K
10U_1206_25VAK
4.7_1206_5%
47_0402_5%
2200P_0402_50V7K
2
5
6
7
8
S
S
S
PR76
PR77
PR75
1
PC49
PC48
PR78
D
D
D
D
1
2
3
4
PC47
PQ20
0_0402_5%
2
5HG 1 2 DH5
2
MAX8734_B++
G
S
S
S
4.7U_1206_25V6K
LX5 @
SI4810BDY-T1-E3_SO8
4
3
2
1
8
7
6
5
2
0.1U_0603_25V7K
PC52
0_0402_5%
PR79
VL 3HG
D
D
D
D
PQ29
LX3
2
2VREF_8734
4.7UH_PCMC063T-4R7MN_5.5A_20%
5
6
7
8
4.7U_0805_6.3V6K
1 PC55
SI4810BDY-T1-E3_SO8
1
G
S
S
S
499K_0402_1% 118K_0402_1%
499K_0402_1% 200K_0402_1%
D
D
D
D
1
2
1U_0603_6.3V6M
PC53
PR80
PR81
1
2
3
4
PQ30
PC54
G
S
S
S
0_0402_5%
DL5
PR82
1
4
3
2
1
2
18
20
13
17
4.7UH_PCMC063T-4R7MN_5.5A_20%
2
2
PL7
BST5A 14
V+
LD05
TON
VCC
1
BST5
PR83
PR84
2
ILIM3 5 2
16 DL3
DH5
+5VALWP
1
2
15
1
LX5
19 DL5 ILIM5 11
PL8
21 OUT5
9 PU6 28 BST3A
FB5 BST3
10.2K_0402_1%
1 26 DH3
N.C.MAX8734AEEI+_QSOP28 DH3
2
VS MAX8734_B++ 24
1
DL3
150U_V_6.3VM_R18
PR85
6 SHDN# LX3 27
@ 0_0402_5%
0_0402_5%
1 4 ON5 OUT3 22
2
3 ON3
PC56
PR86
PR324
+ 7
1
FB3
0_0402_5%
@ 12 2 +3VALWP
SKIP# PGOOD
2 2VREF_87348
PRO#
LDO3
PR88
GND
1
REF
2
2
0_0402_5%
0_0402_5%
0_0402_5% @ 3.57K_0402_1%
47K_0402_5%
PR87
PR89
PR90
1 2 1 2
150U_V_6.3VM_R18
23
25
10
@ 0.047U_0603_16V7K
PZD1 1
PR280
100K_0402_5%
RLZ5.1B_LL34 SPOK 46
1
1
2
PC58
+
PR91
PC57
0_0402_5%
2
PR92
2
1
2
4.7U_0805_6.3V6K
PC60
PR93
PR94
@ 47K_0402_5%
1
0.22U_0603_16V7K
1 2
@ 0.047U_0603_16V7K
3 3
1
1
PC59
1
PC61
2
2
VL
806K_0603_1%
1
PR323
2
PR322
0_0402_5%
39,46 MAINPWON 2 1
1
PC227
0.047U_0603_25V7M
2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+5VALWP/+3VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 41 of 47
A B C D
5 4 3 2 1
OZ813_B+
D D
PL9
FBMA-L11-322513-201LMA40T_1210
1 2 B+
10U_1206_25VAK
1
PC63
SI4800BDY-T1-E3_SO8
1.8VS2N
5
6
7
8
1.8VS2P +3VALWP
2
D
D
D
D
PQ22
PR262
@ 0_0402_5%
G
S
S
S
1 2
4
3
2
1
PR269
0_0402_5%
DH_1.8V_1 1 2 DH_1.8V_2 PL10
2.2UH_MPL73-2R2_8A_20%
220U_D2_4VM_R15
2 1
1
26,33,35 SYSON
51_0402_1%
4.7U_0805_6.3V6K
1
5
6
7
8
0.01U_0402_25V7K
PR95
SI4810BDY-T1-E3_SO8
PC65
1
1
0.1U_0603_25V7K
PC184
PC66
1000P_0402_50V7K PR97 PR98 +
D
D
D
D
2
PC228
+5VALWP 100K_0402_1% 30K_0402_1%
2
1
PQ23
1 2 1 2
2
2
2
PC67
PC68
G
S
S
S
PU7 4700P_0402_25V7K
25
24
23
22
21
20
19
2
C 1.8VS2P 1 2 C
4
3
2
1
2
2
22_0402_1%
1K_0402_1%
CS2P
GNDA
CS2N
VSET2
PGD2
LX2
HDR2
PR99
PR100
@ DL_1.8V
PD16
4700P_0402_25V7K
RB751V-40TE17_SOD323-2 1.8VS2N
PR101 1 18 BST_1.8V 1 2
1
ON/SKIP2 BST2
1
PC69
22P_0402_50V8J
PC70
0_0402_5% 2 17
VIN LDR2
2 1 3 VREF VDDP 16 +5VALWP
4 15
2
TSET GDNP
1
0.022U_0402_16V7K
0.1U_0603_25V7K
5 VDDA LDR1 14
2
24K_0402_1%
100K_0402_1%
6 13 PC71 +5VALWP
ON/SKIP1 BST1
1
1
75K_0402_1%
0.01U_0402_25V7K
PR103
PC72
PC73
PC74
1U_0603_6.3V6M
1U_0603_6.3V6M
OZ813LN_QFN24
2
0.1U_0603_25V7K
PR104
PC75
VSET1
PGD1
HDR1
CS1N
CS1P
2
LX1
1
2.2U_0603_6.3V6K
PR105
BST_1.05V1 2
1
@ PD17
7
8
9
10
11
12
1
PC76
RB751V-40TE17_SOD323-2
PC156
OZ813_B+
2
1.8VSET 1.05SET
2
DH_1.05V_1 PL11
150K_0402_1%
1UH_PCMB103E-1R0MS_20A_20%
2
LX1.05V 1 2 +1.05VSP
2
61.9K_0402_1%
PR106
51_0402_1%
0_0402_5%
PR172
1.05VS1P
4.7U_0805_6.3V6K
PR270
PR107
220U_D2_4VM_R15
220U_D2_4VM_R15
PC77 1 1
1000P_0402_50V7K 1.05VS1N
1
1
PC78
PC229
PR108 PR109 + +
1
5
6
7
8
SI4684DY-T1-E3_SO8
PC230
100K_0402_1% @ 300K_0402_1%
2
10U_1206_25VAK
1 2 1 2
D
D
D
D
2
2
1
2 2
0_0402_5%
PQ24
PC80
DH_1.05V_2
PR263
PC79
B 4700P_0402_25V7K B
1.05VS1P 2 1
2
G
S
S
S
PR179 @
1
4
3
2
1
33K_0402_1%
2 1 1.05VS1N
18,23,26,28,29,33,35,43,44 SUSP#
1U_0402_6.3V6K
+3VALWP
1
4700P_0402_25V7K
5
6
7
8
1
1
1
PC132
PC81
PC82
22P_0402_50V8J
PQ31 PR333
2
IRF7836PBF_SO8 10.5K_0402_1%
2
DL_1.05V4
3
2
1
A A
PL12
FBMA-L11-322513-201LMA40T_1210
2 1 B+
+5VALWP
1
D D
2200P_0402_50V7K
10U_1206_25VAK
PR282
PR281 10_0402_5%
PC193
1M_0402_5%
PC192
PR283
2
3K_0402_1%
2
RB751V-40TE17_SOD323-2
18,23,26,28,29,33,35,42,44 SUSP# 1 2
1
1
2
PC194 PR334
1U_0402_6.3V6K 470K_0402_1%
PD21
2
5
6
7
8
BST_1.5 PQ26
D
D
D
D
SI4800BDY-T1-E3_SO8
1
+5VALWP PC195
G
S
S
S
+1.5VSP 0.1U_0603_25V7K
16
15
14
13
2
PU13
4
3
2
1
@ 470K_0402_1%
21.5K_0402_1%
33P_0402_50V8J
PR285
EN/PSV
TON
NC
BST
1
0_0402_5% PL13
PR284
1 12 DH_1.5 1 2 DH_1.5A 3.3UH_MPL73-3R3_6A_20%
VOUT DH
1
1
PC196
PR286
2 11 LX_1.5 1 2 +1.5VSP
VCCA LX PR287
4.7U_0805_6.3V6K
3 FB ILIM 10 1 2 1
5
6
7
8
220U_D2_4VM_R15
2
1
PC88
4 9 18.2K_0402_1% PQ27 +
D
D
D
D
PGD VDDP
PGND
1000P_0402_50V7K
PC231
TPAD
VSSA
SI4810BDY-T1-E3_SO8
NC
DL
2
1
1
2
@ 0.1U_0402_16V7K
10.7K_0402_1%
1U_0603_6.3V6M
C C
1
G
S
S
S
PC197
PC198
17
8
PR288
1U_0603_6.3V6M
2
4
3
2
1
1
1
PC199
PC200
SC411MLTRT_MLPQ16_4X4
2
2
DL_1.5
VFB=0.5V
+1.8VP
B +3VS B
1
PJ9
1
+5VS JUMP_43X118
1
2
PJ10
1
JUMP_43X79
2
1
PC93 PU9
1 6 +3VALWP
2
2 GND NC 5
1
6
1
PU10 PC94 3 7 PC95
PC96 22U_1206_6.3V6M VREF NC 1U_0603_6.3V6M
5
VCNTL
2
VIN 22U_1206_6.3V6M PR120
7 4 8
2
2
PR121 TP
VOUT 3 +2.5VSP
2.2K_0402_1% G2992F1U_SO8
1
0.1U_0402_16V7K
1 2 8 EN FB 2
1
8,29,33,35,42,44 SUSP#
PC101
22U_1206_6.3V6M
PR122 PR123
GND
+0.9VSP
1
D
1K_0402_1%
PC97
RHU002N06_SOT323
9 PC99 10K_0402_1%
2
VIN
1
1
PR124
2.15K_0402_1% 2 1 2
2
1
PC100 35 SUSP G
1
1U_0402_6.3V6K S PC102
2
2
1
PQ28
APL5912-KAC-TRL_SO8 22U_1206_6.3V6M
2
1
0.01U_0402_25V7K PC103
1U_0402_6.3V6K
2
PR125
1K_0402_1%
A A
2
D D
PL17
FBMA-L11-322513-201LMA40T_1210
1 2 B+
+5VALWP
PR325
1
1M_0402_5%
PR326
2200P_0402_50V7K
10U_1206_25VAK
10_0402_5%
PC233
2
PC232
PR327
0_0402_5%
2
RB751V-40TE17_SOD323-2
18,23,26,28,29,33,35,42,43 SUSP# 1 2
2
1
PC234 PR335
PD22
@ 0.1U_0402_16V7K 470K_0402_1%
5
6
7
8
SI4800BDY-T1-E3_SO8
BST_1.25
D
D
D
D
1
PQ44
PC235
G
S
S
S
33P_0402_50V8J
+1.25VSP 0.1U_0603_25V7K
16
15
14
13
2
15.4K_0402_1%
C PU16 C
4
3
2
1
1
PR329
TON
EN/PSV
NC
BST
1
PC236
PR328
0_0402_5%
1 12 DH_1.25 1 2 DH_1.25A PL19
VOUT DH 4.7UH_PCMC063T-4R7MN_5.5A_20%
2
2 11 LX_1.25 1 2 +1.25VSP
2
VCCA LX PR331
4.7U_0805_6.3V6K
3 FB ILIM 10 1 2 1
5
6
7
8
SI4810BDY-T1-E3_SO8
220U_D2_4VM_R15
1
PC219
4 9 12.7K_0402_1% +
D
D
D
D
PGD VDDP
PGND
1000P_0402_50V7K
PQ46
PC237
TPAD
VSSA
NC
DL
2
1
10.2K_0402_1% 2
1U_0603_6.3V6M
1
G
S
S
S
PC239
17
8
PR332
1U_0603_6.3V6M
4
3
2
1
1
1
PC240
PC241
SC411MLTRT_MLPQ16_4X4
2
2 DL_1.25
VFB=0.5V
B B
PJ1 PJ2
@ PAD-OPEN 3x3m @ PAD-OPEN 3x3m
+1.5VSP 1 2 +1.5VS +1.8VP 1 2 +1.8V
PJ3 PJ4
@ PAD-OPEN 3x3m @ JUMP_43X39
+5VALWP 1 2 +5VALW +0.9VSP 1 1 2 2 +0.9VS
PJ6 PJ11
@ PAD-OPEN 3x3m @ JUMP_43X39
+3VALWP 1 2 +3VALW +2.5VSP 1 1 2 2 +2.5VS
PJ7 PJ8
@ PAD-OPEN 3x3m @ JUMP_43X39
+1.05VSP 1 2 +VCCP +VSBP 1 1 2 2 +VSB
A PR313 A
0_1206_5%
PJ19 2 1 +VCCP
@ PAD-OPEN 3x3m
1 2 PR309
+1.25VSP +1.25VS +VCCGFX
@ 0_1206_5% UMA PR313
2 1 Discrete PR309
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title
1.25VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 44 of 47
5 4 3 2 1
5 4 3 2 1
+5VS
CPU_B+ B+
PR214 PL14
5VS12 1 FBMA-L11-322513-201LMA40T_1210
2 1
0.01U_0402_25V7K
0_1206_5%
2200P_0402_50V7K
0.1U_0603_25V7K
PR215 1 1
100U_25V_M
100U_25V_M
PC157
10_0402_5%
1
10U_1206_25VAK
10U_1206_25VAK
10U_1206_25VAK
PC158
PC242
+ +
200K_0402_5%
PC159
PC160
PC161
PC162
PC163
2
2
2 PR216 1
2
D D
2
PC164 2 2
2
2.2U_0603_6.3V6K
2
13K_0402_5%
PC165
1
PR217
1U_0603_6.3V6M
5
PU11
1
NTC
100K_0402_5% V CC 19 25
PR218 Vcc VDD 0.22U_0603_16V7K PQ32
1 2 6 8 PR220 4 SI7686DP-T1-E3_SO8
THRM TON 2.2_0402_5% PC166
PR219 0_0402_5% 2 1 31 30 BST1_CPU 1 2 BSTM1_CPU 1 2
5 CPU_VID0 D0 BST1 +CPU_CORE
PR274
PR221 0_0402_5% 2 1 32 29 DH1__CPU 10_0402_5%2 PL15
5 CPU_VID1
3
2
1
D1 DH1 P_0.36H_ETQP4LR36WFC_24A_20%
PR222 0_0402_5% 2 1 33 28 LX1__CPU 2 1 +CPU_CORE
5 CPU_VID2 D2 LX1
6.8_1206_5%
5
6
7
8
5
6
7
8
1
PR223 0_0402_5% 2 1 34 26 DL1__CPU
5 CPU_VID3 D3 DL1
2
PR224
PQ33 PQ34
PR225 0_0402_5% 2 1 35 27 IRF7836PBF_SO8 IRF7836PBF_SO8 PR226
5 CPU_VID4 D4 PGND1 2.1K_0603_1%
PR227 0_0402_5% 2 1 36 18
5 CPU_VID5
2
D5 GND
1
10_0402_5%
4 4 PR230 PR231
1
470P_0603_50V7K
PR229
DL1__CPU
PR228 0_0402_5% 1 2 37 17 CSP1__CPU 3.48K_0402_1% 10KB_0603_5%_ERTJ1VR103J
5 CPU_VID6 D6 CSP1
PC167
1 2 1 2
PR2322 71.5K_0402_1%
1 7 16 CSN1_CPU 5 VCCSENSE
TIME CSN1
3
2
1
3
2
1
2
2 1 9 12 FB_CPU
470P_0402_50V7K PC168 CCV FB PC169
1 2 11 10 C CI_CPU 0.22U_0603_16V7K
C REF CCI C
1 2
PR233 499_0402_1% 1 2 PC170 0.22U_0603_16V7K 39 21 DH2_CPU
7,21 DPRSLPVR DPRSLPVR DH2
1 2
0_0402_5%
PR234 0_0402_5% 1 2 40 20 BST2_CPU
5,7,20 H_DPRSTP# DPRSTP BST2
PR235
PR237
1 2 3 22 LX2_CPU PC188 PC187 0_0402_5%
5 H_PSI# PSI LX2
PR236 0_0402_5% 180P_0402_50V8J 180P_0402_50V8J
2
+3VS 2 24 DL2__CPU PC171
1
PWRGD DL2 @ 0.022U_0402_16V7K
2.2_0402_5%
1 23 1 2 1 2 CPU_VCC_SENSE
CLKEN PGND2
10K_0402_1%
PR239
PR238
2
2
2K_0402_1%
38 14 CSP2_CPU @ 3K_0603_1%
SHDN CSP2
PR240
PR241
1 2 1 2
4700P_0402_25V7K
5 15 CSN2__CPU
1
PR244 VRHOT CSN2 PR242 PR243
PC172
0_0402_5% 4 13 3.65K_0402_1% 100_0402_5%
1
POUT GNDS
1 2 1 2 1 2
BSTM2_CPU
7,21 VGATE
1
PR247 PR245 @ PR246
4700P_0402_25V7K
10_0402_5%2 NTC @ 3K_0603_1% 3K_0603_1%
21 CLK_ENABLE# MAX8770GTL+_TQFN40
2
PR249 PC174 1 2 1 2
33 VR_ON 10_0402_5%2
PR248 PC173
1
2
CPU_B+
10K_0402_5%
0.22U_0603_16V7K
20K_0402_1% 470P_0402_50V7K
1
+3VS
PR250
PC175
1
56_0402_5%
PR251
2200P_0402_50V7K
PR252
10U_1206_25VAK
10U_1206_25VAK
10U_1206_25VAK
0.1U_0603_25V7K
100_0402_5%
1
1
PC176
PC177
@ PR253 PR314
1
PC178
PC179
PC180
B @ 0_0402_5% 0_0402_5% B
2
1 2 1 2
2
4 H_PROCHOT# 5 VSSSENSE PR275
PR254 0_0402_5% PQ35
1
@ 10K_0402_5% 1 2 4 SI7686DP-T1-E3_SO8
1 2 PR255
CPU_POUT 10_0402_5%
A/D
2
PC181
2
3
2
1
@ 0.1U_0402_16V7K 2 1
1
PL16
6.8_1206_5%
P_0.36H_ETQP4LR36WFC_24A_20%
5
6
7
8
5
6
7
8
PR256
PQ36
PQ37 IRF7836PBF_SO8
2.1K_0603_1%
IRF7836PBF_SO8
PR257
4
470P_0603_50V7K
DL2__CPU
4
2
1
PC182
PR258 PR259 NTC
3
2
1
3.48K_0402_1% 10KB_0603_5%_ERTJ1VR103J
3
2
1
2
1 2 1 2
PC183
0.22U_0603_16V7K
1 2
1 2
A A
1
PR260
PC189 PC190 0_0402_5%
180P_0402_50V8J 180P_0402_50V8J
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 45 of 47
5 4 3 2 1
A B C D
0.01U_0402_25V7K
1000P_0402_50V7K
1000P_0402_50V7K
1K_0402_1% 47K_0402_5%
2 ALI/NIMH# 1 2 1 2
Recovery at 45 degree C
2 +3VALWP
1
3 AB/I
3
1
PC14
PC15
PC16
4 TS_A
4 EC_SMDA
5
2
5
1K_0402_1%
1 6 EC_SMCA 1
2
6
PR176
7 7
100_0402_1%
100_0402_1%
VL VS
2
1
PR31
PR35
ALI/MH#
2
PR36
2
6.49K_0402_1%
1 2 +3VALWP
CPU
1
PC224
2
1K_0402_1%
PH1 0.1U_0603_25V7K
1
39,41 MAINPWON
PR38
100K_0603_1%_TH11-4H104FT
1
VL
2
A/D
2
N71
BATT_TEMP 33 PR315
470K_0402_1%
2
EC_SMB_DA1 33,34 1 2
2
PR316
PR317 470K_0402_1%
EC_SMB_CK1 33,34
0_0402_5%
PR318
1
8
215K_0603_1% PU15A
1
N72 OTPFB2 D PQ47
1 2 3
P
+ OTP RHU002N06_SOT323
2
O 1 2 2
1 2 2 G
-
G
VL PR319 OTPREF2 S
3
100K_0402_1% LM393DT_SO8
4
PR320
1
24.3K_0603_1%
2
1
PR321
PC226 100K_0402_1%
2
0.22U_0603_16V7K
2
PC225
1
1000P_0402_50V7K
PQ7
TP0610K-T1-E3_SOT23
B+ 3 1 +VSBP
0.22U_1206_25V7K
0.1U_0603_25V7K
1
100K_0402_5%
1
PR41
PC20
PC21
2
PR42
2
22K_0402_1%
VL 1 2 VS +3VALWP +3VALWP
100K_0402_5%
2
2
PR43
3 3
PR341 PR342
PR44 470K_0402_1% 470K_0402_1%
1
0_0402_5% D
1
1 2 2
41 SPOK G
BATT_IN 33
8
0.1U_0402_16V7K
S PQ8 PU15B
3
1
1
D
PC22
RHU002N06_SOT323 2 1 5 PQ50
P
33 BATT_TEMP PR338 +
7 2 RHU002N06_SOT323
470K_0402_1% O G
RTCVREF 2 1 6
2
G
PR339 S
3
30K_0402_1% LM393DT_SO8
4
1
1
PC244
2
@ 1000P_0402_50V7K PR340 PC245
2
470K_0402_1% 1000P_0402_50V7K
1
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN. / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 25, 2006 Sheet 46 of 47
A B C D
A B C D E
Delete PR59、PR64.
Decrease S5 power consumption. 40
2 ADD PD19、 PD 20.
For adjust +1.8VP, Change PR179 to 33k_0402_1% and add PC132 1u_0402_6.3v
42
For adjust +1.5VSP, Change PR283 to 3k_0402_1% and add PC194 1u_0402_6.3v
Adjust power sequence.
2 5 For adjust +2.5VSP, Change PR121 to 2.2k_0402_1% and add PC100 1u_0402_6.3v 2
43
For adjust +0.9VSP, Change PR123 to 10k_0402_1% and add PC103 1u_0402_6.3v
For improve EPA 46 Add PR338, PR339, PR340, PR341, PR342, PC244, PC245, PQ50
6
3 3
4 4
B B
A A