NuMicro Nano

PWM/Capture

NuMicro@nuvoton.com

2013/3/1
 Agenda
• What’s PWM Output
• PWM Timing Control
• What’s Capture Input
• Capture Timing Control
• Interrupt Architecture
• Sample Code

1
 What’s PWM Output?
• PWM: Pulse Width Modulation
• PWM Frequency and Duty
• How to set/change frequency and duty cycle?
• PWM Output Channels
• PWM Resolution PWM

• Complementary Paired PWM PWM period

Interrupt

(frequency)
• Needs dead-zone insertion? (CN+1)
Duty
• How to set dead-zone?
• Other Functions
(CM+1)

• Single-shot pulse
• PWM Interrupt
2
 Features of PWM Generator (I)
• Four PWM Generators, each generator supports
• One 8-bit prescale
• One clock divider
• Two PWM-timers for two outputs, each timer includes
• A 16-bit PWM down-counter
• A 16-bit PWM reload value register (CN)
• A 16-bit PWM compare register (CM)
• One dead-zone generator
• Two PWM outputs.

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 Features of PWM Generator (II)
• 8 PWM channels or 4 PWM paired channels.
• 16 bits resolution.
• PWM Interrupt synchronized with PWM period.
• Single-shot or Continuous mode PWM.

4
 PWM/Capture Clock Source

PWM01_S(CLKSEL1[29:28])

PWM01_EN(APBCLK[20])

HIRC
11 PWM01_CLK
HCLK 10
LXT
01
HXT
00

5
 Configure PWM Generator
Insert dead-zone for
paired-PWM
DZ01 Dead Zone
Generator0
CLKSEL0
CN, CM,
PWM0_ CTL
1 100 CH0_OE
1/2 000 1
PWM- 1 1
PA.12/ PWM0
1/4 001 Timer0 0
0 0
Clock 1/8 010 Logic
Divider GPIOA_ DOUT[12]
1/16 011 CH0INV
GPIOA_ MFP[12]
1 TMINT0
TMIE0
8- bit 1/2
PWM01_CLK Prescaler DZEN01
1/4
( from clock PWM0_PR
controller) ES,CP01 1/8 CN, CM,
PWM0_ CTL Select
1/16
1 100 Paired-PWM CH1_OE
1/2 000 1
PWM- 1 1
PA.13/ PWM1
1/4 001 Timer1 0
Select proper PWM 0 0
1/8 010 Logic
clock input 1/16 GPIOA_ DOUT[13]
011 CH1INV
GPIOA_ MFP[13]
CLKSEL1 TMIE1 TMINT1

Configure PWM
Set PWM frequency( CN) output channel
PWM Interrupt
Set PWM duty (CM)
Configure PWM setting (PWMx_CTL)
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 PWM Frequency & Duty Control
• PWM Frequency =
PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1);
where xy = 01 or 23, the selected PWM channels.
• Duty ratio = (CM+1)/(CN+1).
Start Update
Initialize new CM
PWM

CM+1 + PWM-Timer CM
Comparator
CN - Output CN

PWM
Ouput
CM >= CN: PWM output high.
CM < CN: PWM output low CN+1
CM+1

7
 PWM Double Buffering Illustration
• Why does need the double buffer?
• To output the whole PWM cycle without any destroying.
S/W write new period (CN)
And new duty (CM)
CN=150 CN=199 CN=99 CN=0
CM=50 CM=49 CM=0 CM=XX

Start Stop
PWM
Waveform

51 50 1

write a nonzero number to

prescaler & setup clock 151 200 100
dividor

First cycle Second cycle

New period (CN)
New duty (CM)
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 Operation of Dead Zone Generator
• Why does need the dead zone control?
• To avoid a paired-PWM outputs overlapping on duty-on
duration.
• For example, in Motor Driver application, it needs to avoid
the upper and lower power switch turn on simultaneously.
• Insert a delay time (dead zone) before duty on at
each channel of paired-PWM.
• 8-bit dead-zone timer by PWM clock.
PWM-Timer (Internal signal)
Output 0/2

PWM-Timer
Inversed Output 1/3 (Internal signal)

(Port pin signal)

Dead-Zone Generator
Output 0/2

Dead-Zone Generator
(Port pin signal)
Output 1/3

Dead zone interval

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 What’s Capture Input?
• Captured by Rising or Falling Edge Interrupt

• Measure Pulse Width

W1
• Rising to Falling (W2) Pulse width
(falling to rising)
• Falling to Rising (W1)
W2
• Rising to Rising (W1+W2)
Sampling Pulse width
• Falling to Falling (W1+W2) (rising to falling)

• Capture Input Channel

• Sampling Frequency
• Capture Function Interrupt
• Captured Pulse Width Data
• Rising/Falling Latch Registers (PWM_CRLx, PWM_CFLx)
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 Features of Capture Input
• Timing control logic shared with PWM Generators.
(therefore up to 16 bits data length)
• 8 Capture inputs shared with PWM outputs
• Each channel supports
• One rising latch register (PWM_CRLx)
• One falling latch register (PWM_CFLx)
• Capture interrupt flag (CAPIFx)

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 Operation Timing of Capture Input

PWM Counter 3 2 1 8 7 6 5 8 7 6 5 4
Reload Reload
(If CNx = 8) No reload due to
no CAPIFx
Capture Input x
• The PWM counter will be
CAPCHxEN reloaded with CNx when
a capture interrupt flag
PWMX_CFLx 1 7 (CAPIFx) is set
PWMX_CRLx 5
• The channel low pulse
width is (CNx+1 - CRLx).
CFL_IEx • The channel high pulse
width is (CNx+1 - CFLx).
CRL_IEx
Clear by S/W
CAPIFx Set by H/W

Set by H/W Clear by S/W

CFLIx
Set by H/W Clear by S/W
CRLIx

Note: X=0 or 1, x=0~3

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 Interrupt Architecture
• Two PWM/Capture Interrupt Vectors
Channel0~Channel3 share one
interrupt vector
TMINT0 PWM0CH0_INT
CAPIF0

TMINT1 PWM0CH1_INT
CAPIF1
PWM0_INT
TMINT2 PWM0CH2_INT
CAPIF2

Each PWM/
TMINT3 PWM0CH3_INT
Channel4~Channel7 share one
Capture CAPIF3
interrupt vector
channel has
its own TMINT0 PWM1CH0_INT
interrupt flag CAPIF0

TMINT1 PWM1CH1_INT
CAPIF1
PWM1_INT
TMINT2 PWM1CH2_INT
CAPIF2

TMINT3 PWM1CH3_INT
CAPIF3 13
 Conditions of Sample Code
• Capture0
• Input Channel:GPA12
• Counter unit: 1usec (((11+1)*1)/12M)
• Capture capability: 32 bits (hardware 16bits+ firmware
16bits)
• PWM2
• Output Channel:GPA14
• Period: 1365.3 usec (((1+1)*1*(8191+1))/12M)
• High level: 682usec, Low level: 682usec

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Block Diagram of Sample Code

Flash NUC130KE3BN

GPA12
Capture0
Cortex-M0
PWM2
15 GPA14

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 Sample Code (I)
void InitPWM(void)
{
/* Configure pin function */
GCR->PA_H_MFP = (GCR->PA_H_MFP & ~0x0F000000) | 0x01000000;

/* Enable PWM clock */

CLK->APBCLK |= CLK_APBCLK_PWM0_CH23_EN;

/* Select HXT for PWM clock source */

CLK->CLKSEL1 = (CLK->CLKSEL1 & ~CLK_CLKSEL1_PWM0_CH23_MASK) |
CLK_CLKSEL1_PWM0_CH23_HXT;

/* Prescaler 0~255, Setting 0 to stop output clock */

PWM0->PRES = (PWM0->PRES & ~PWM_PRES_CP23_MASK) | 0x100;

/* Clock divider->0:/2, 1:/4, 2:/8, 3:/16, 4:/1 */

PWM0->CLKSEL = (PWM0->CLKSEL & ~PWM_CLKSEL_CLKSEL2_MASK) | PWM_CLKSEL_CLKSEL2_DIV1;

/* Select PWM operation mode */

PWM0->CTL |= PWM_CTL_CH2MOD;

/* Set Reload register, CN = 0x1FFF, CM = 0x0FFF */

PWM0->DUTY2 = 0x0FFF1FFF;

/* Enable PWM down counter */

PWM0->CTL |= PWM_CTL_CH2EN;

/* Output enable */
PWM0->OE |= PWM_OE_CH2;
}
16
 Sample Code (II)
void InitCapture(void)
{
/* Configure pin function */
GCR->PA_H_MFP = (GCR->PA_H_MFP & ~0x000F0000) | 0x00010000;

/* Enable PWM clock */

CLK->APBCLK |= CLK_APBCLK_PWM0_CH01_EN;

/* Select HXT for PWM clock source */

CLK->CLKSEL1 = (CLK->CLKSEL1 & ~CLK_CLKSEL1_PWM0_CH01_MASK) |
CLK_CLKSEL1_PWM0_CH01_HXT;

/* Prescaler 0~255, Setting 0 to stop output clock */

PWM0->PRES = (PWM0->PRES & ~PWM_PRES_CP01_MASK) | 11;

/* Clock divider->0:/2, 1:/4, 2:/8, 3:/16, 4:/1 */

PWM0->CLKSEL = (PWM0->CLKSEL & ~PWM_CLKSEL_CLKSEL0_MASK) | PWM_CLKSEL_CLKSEL0_DIV1;

/* Select PWM operation mode */

PWM0->CTL |= PWM_CTL_CH0MOD;

/* Set Reload register */

PWM0->DUTY0 = 0xFFFF;

/* Enable Capture function pin, capture function, counter reload on both rising and falling edge */
PWM0->CAPCTL = PWM_CAPCTL_CAPCH0EN |
PWM_CAPCTL_CAPCH0PADEN |
PWM_CAPCTL_CAPRELOADREN0 |
PWM_CAPCTL_CAPRELOADFEN0;

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 Sample Code (III)
/* Enable Capture rising and falling edge interrupt */
PWM0->CAPINTEN = PWM_CAPINTEN_CRLIE0 | PWM_CAPINTEN_CFLIE0;

/* Enable PWM interrupt for down-counter equal zero. */

PWM0->INTEN |= PWM_INTEN_TMIE0;

/* Enable PWM intrrupt */

NVIC_EnableIRQ(PWM0_IRQn);

/* Enable PWM down counter */

PWM0->CTL |= PWM_CTL_CH0EN;

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Thank you.

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